Capacitive load driving circuit and liquid ejecting apparatus

Abstract

To provide a capacitive load drive circuit capable of improving waveform accuracy of a drive signal supplied to a piezoelectric element.SOLUTION: A modulation circuit that modulates a base driving signal and outputs a modulation signal, an amplification circuit that includes a first transistor and a second transistor and outputs an amplification modulation signal obtained by amplifying the modulation signal, a demodulation circuit that demodulates the amplification modulation signal and outputs the demodulated signal as a driving signal, a transistor driving circuit that outputs a first driving control signal for driving the first transistor and a second driving control signal for driving the second transistor, a feedback circuit that feeds back the driving signal to the modulation circuit, and a current detection circuit that outputs a current detection signal according to a change in a driving current caused by propagation of the driving signal to the transistor driving circuit, the transistor driving circuit outputs a first driving control signal for controlling the first transistor to be non-conductive and a second driving control signal for controlling the second transistor to be non-conductive according to the current detection signal.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a capacitive load drive circuit and a liquid ejection device. [Background technology]

[0002] Liquid ejection devices that eject liquid to form images or documents on a medium are known to use piezoelectric elements. In such liquid ejection devices, a piezoelectric element is provided corresponding to each of a plurality of nozzles that eject liquid, and each is driven according to a drive signal. Driving the piezoelectric element causes liquid to be ejected from the nozzle associated with that piezoelectric element. A sufficient current must be supplied to operate such a piezoelectric element. Therefore, a drive circuit that outputs a drive signal to drive the piezoelectric element includes an amplifier circuit that amplifies the base drive signal, which is the basis of the drive signal.

[0003] For example, Patent Document 1 discloses a liquid ejection device that includes a drive circuit that outputs a drive signal for driving a piezoelectric element and that includes a digital amplifier circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-117050 Summary of the Invention [Problem to be solved by the invention]

[0005] However, from the viewpoint of further improving the waveform accuracy of the drive signal supplied to the piezoelectric element, the technique described in Patent Document 1 alone is not sufficient, and there is room for further improvement. [Means for solving the problem]

[0006] One aspect of the capacitive load drive circuit according to the present invention is A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit having a first transistor pair including a first transistor and a second transistor, which amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the demodulated signal as the drive signal; a transistor drive circuit that outputs a first drive control signal that controls the drive of the first transistor and a second drive control signal that controls the drive of the second transistor; a feedback circuit that feeds back the drive signal to the modulation circuit; a current detection circuit that detects a drive current generated in association with the propagation of the drive signal and outputs a current detection signal corresponding to a change in the drive current to the transistor drive circuit; Equipped with The transistor drive circuit outputs the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive in response to the current detection signal.

[0007] One aspect of the liquid ejection device according to the present invention is a capacitive load drive circuit that outputs a drive signal; a first ejection unit including a first capacitive load driven by the drive signal, the first capacitive load being driven to eject liquid; a first switch circuit, one end of which is electrically connected to the first capacitive load and the other end of which is electrically connected to the capacitive load drive circuit, for switching a conduction state between the first capacitive load and the capacitive load drive circuit; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit having a first transistor pair including a first transistor and a second transistor, which amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the demodulated signal as the drive signal; a transistor drive circuit that outputs a first drive control signal that controls the drive of the first transistor and a second drive control signal that controls the drive of the second transistor; a feedback circuit that feeds back the drive signal to the modulation circuit; a current detection circuit that detects a drive current generated in association with the propagation of the drive signal and outputs a current detection signal corresponding to a change in the drive current to the transistor drive circuit; Equipped with The transistor drive circuit outputs the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive in response to the current detection signal. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a schematic configuration of a liquid ejection device. [Figure 2] FIG. 2 is a diagram illustrating an example of a functional configuration of the liquid ejection device. [Figure 3] FIG. 2 is a diagram showing a schematic structure of a discharge section. [Figure 4] 10 is a diagram showing an example of a signal waveform of a drive signal COM. FIG. [Figure 5] FIG. 2 is a diagram illustrating an example of a configuration of a selection control circuit and a plurality of selection circuits. [Figure 6] FIG. 10 is a diagram showing an example of the decoded content in the decoder. [Figure 7] FIG. 2 is a diagram illustrating an example of the configuration of a selection circuit. [Figure 8] FIG. 2 is a diagram illustrating a configuration of a drive signal output circuit. [Figure 9] 10A and 10B are diagrams illustrating an example of waveform distortion of the drive signal COM that can occur when the switching phases of the transistors M1 and M2 differ for each period tp. [Figure 10] 10A and 10B are diagrams for explaining an example of the operation of a drive signal output circuit having a differentiation circuit, a stop control circuit, and a load current detection circuit. [Figure 11] FIG. 10 is a diagram for explaining a voltage Vhmux. [Figure 12] 10A and 10B are diagrams for explaining an example of the operation of a drive signal output circuit having a differential circuit, a stop control circuit, and a load current detection circuit according to a modified example. [Figure 13] FIG. 10 is a diagram showing the configuration of a modified load current detection circuit 580a. [Figure 14] FIG. 10 is a diagram showing the configuration of a modified load current detection circuit 580b. [Figure 15] FIG. 10 is a diagram showing a configuration of a modified load current detection circuit 580c. [Figure 16] FIG. 10 is a diagram showing the functional configuration of a liquid ejection device according to a second embodiment. [Figure 17] FIG. 10 is a diagram showing an example of a signal waveform of a drive signal COM according to the second embodiment. [Figure 18] FIG. 10 is a diagram illustrating an example of the configuration of a selection control circuit and a plurality of selection circuits according to a second embodiment. [Figure 19] FIG. 10 is a diagram showing an example of the decoded content in the decoder of the second embodiment. [Figure 20] FIG. 10 is a diagram illustrating a configuration of a drive signal output circuit according to a second embodiment. [Figure 21] FIG. 10 is a diagram illustrating an example of the functional configuration of a drive signal output circuit 51a according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for the convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. First embodiment 1.1 Configuration of the liquid ejection device FIG. 1 is a diagram illustrating an example of a schematic configuration of a liquid ejection device 1. The liquid ejection device 1 of the first embodiment is a serial printing inkjet printer in which a carriage 21 mounted with a head unit 20 that ejects ink, an example of a liquid, moves back and forth along a scanning axis while ejecting ink onto a medium P transported along a transport direction, thereby forming a desired image on the medium P. The medium P used in this liquid ejection device 1 can be any printing target, such as printing paper, resin film, or fabric. Note that the liquid ejection device 1 is not limited to a serial printing inkjet printer, but may also be a line printing inkjet printer. Furthermore, the liquid ejection device 1 is not limited to an inkjet printer, but may also be a color material ejection device used in the manufacture of color filters for liquid crystal displays and the like, an electrode material ejection device used in the formation of electrodes for organic electroluminescence displays (EL) displays, field emission displays (FEDs), and the like, a bioorganic material ejection device used in the manufacture of biochips, a three-dimensional modeling device, a textile printing device, or the like.

[0011] As shown in FIG. 1, the liquid ejection device 1 includes an ink container 2, a control unit 10, a head unit 20, a moving unit 30, and a transport unit 40.

[0012] The ink container 2 stores multiple types of ink to be ejected onto the medium P. Colors of ink stored in the ink container 2 include black, cyan, magenta, yellow, red, gray, etc. The ink container 2 that stores such ink may be an ink cartridge, a bag-shaped ink pack made of flexible film, or an ink tank that can be refilled with ink.

[0013] The control unit 10 includes a processing circuit such as a CPU (Central Processing Unit) or FPGA (Field Programmable Gate Array) and a storage circuit such as a semiconductor memory, and controls each element of the liquid ejection device 1 including the head unit 20.

[0014] The head unit 20 is mounted on a carriage 21. The carriage 21 is fixed to an endless belt 32 included in a moving unit 30. In addition to the head unit 20, an ink container 2 may be mounted on the carriage 21.

[0015] A control signal Ctrl-H for controlling the head unit 20, output by the control unit 10, is input to the head unit 20 mounted on the carriage 21. Ink stored in the ink container 2 is supplied to the head unit 20 via a tube (not shown). The head unit 20 then ejects the ink supplied from the ink container 2 based on the input control signal Ctrl-H.

[0016] The moving unit 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 is driven based on a control signal Ctrl-C input from the control unit 10. The endless belt 32 rotates in accordance with the drive of the carriage motor 31. This causes the carriage 21 fixed to the endless belt 32 to reciprocate along the scanning axis. In other words, the head unit 20 mounted on the carriage 21 reciprocates along the scanning axis that intersects with the transport direction in which the medium P is transported.

[0017] The transport unit 40 includes a transport motor 41 and a transport roller 42. The transport motor 41 is driven based on a control signal Ctrl-T input from the control unit 10. The transport roller 42 rotates in accordance with the driving of the transport motor 41. As the transport roller 42 rotates, the medium P is transported in the transport direction.

[0018] In the liquid ejection device 1 configured as described above, the head unit 20 mounted on the carriage 21 ejects ink onto the medium P in conjunction with the transport of the medium P by the transport unit 40 and the reciprocating movement of the carriage 21 by the moving unit 30. This causes the ink ejected from the head unit 20 to land at any position on the surface of the medium P. As a result, a desired image is formed on the medium P.

[0019] A specific example of the functional configuration of the liquid ejection device 1 configured as above will be described. Fig. 2 is a diagram showing an example of the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 has a control unit 10, a head unit 20, a moving unit 30, and a transport unit 40.

[0020] The control unit 10 includes a control circuit 100 .

[0021] When an image signal is input from an external device such as a host computer, the control circuit 100 generates various control signals according to the image signal and outputs them to the corresponding components.

[0022] Specifically, the control circuit 100 generates control signals Ctrl-T and Ctrl-C when an image signal is input and printing is performed on the medium P. The control signal Ctrl-T output by the control circuit 100 is input to a transport motor 41 included in the transport unit 40. The transport motor 41 is driven in response to the control signal Ctrl-T. The driving force of this transport motor 41 transports the medium P along the transport direction. The control signal Ctrl-C output by the control circuit 100 is input to a carriage motor 31 included in the movement unit 30. The carriage motor 31 is driven in response to the control signal Ctrl-C. The driving force of this carriage motor 31 moves the carriage 21 carrying the head unit 20 back and forth along the scanning axis. Note that the transport unit 40 may include one or more transport rotors in addition to the transport motor 41. The transport unit 40 may also include a transport motor driver circuit for converting the control signal Ctrl-T into a predetermined signal that drives the transport motor 41. The moving unit 30 may also include a carriage motor driver circuit for converting the control signal Ctrl-C into a predetermined signal for driving the carriage motor 31 .

[0023] In addition, the control circuit 100 generates a clock signal SCK, a print data signal SI, a latch signal LAT, and a basic drive signal dA as control signals Ctrl-H based on an image signal input from an external device, and outputs them to the head unit 20.

[0024] The head unit 20 includes a drive circuit 50 and a plurality of ejection heads 200 .

[0025] The drive circuit 50 includes a drive signal output circuit 51. A digital base drive signal dA is input to the drive signal output circuit 51 as a control signal Ctrl-H. The drive signal output circuit 51 performs digital-to-analog conversion on the input base drive signal dA and generates and outputs a drive signal COM by class D amplifying the converted analog signal. The drive signal COM output by the drive signal output circuit 51 is input to the ejection head 200. In other words, the base drive signal dA is a signal that forms the basis of the drive signal COM and defines the waveform of the drive signal COM. Here, the base drive signal dA may be any signal that can define the waveform of the drive signal COM, and may be an analog signal.

[0026] The drive circuit 50 also includes a reference voltage output circuit 52. The reference voltage output circuit 52 generates a reference voltage signal VBS, which is a constant DC voltage with a voltage value of 5.5 V, 6 V, or the like, and outputs it to the ejection head 200. This reference voltage signal VBS functions as a reference potential for driving the piezoelectric elements 60 (described below) of the ejection head 200. The potential of such a reference voltage signal VBS is not limited to 5.5 V or 6 V, and may also be ground potential.

[0027] The ejection head 200 includes a selection control circuit 210, a plurality of selection circuits 230, and a plurality of ejection units 600. The plurality of ejection units 600 are provided corresponding to the plurality of selection circuits 230, respectively.

[0028] A clock signal SCK, a print data signal SI, and a latch signal LAT are input as control signals Ctrl-H to the selection control circuit 210. Based on the input clock signal SCK, print data signal SI, and latch signal LAT, the selection control circuit 210 generates a selection signal S corresponding to each of the multiple selection circuits 230 and outputs it to the corresponding selection circuit 230.

[0029] Each selection circuit 230 receives as input the drive signal COM and a corresponding selection signal S output by the selection control circuit 210. The selection circuit 230 selects or deselects the drive signal COM based on the input selection signal S, thereby generating a drive signal VOUT and supplying the generated drive signal VOUT to the corresponding discharge unit 600. In other words, each selection circuit 230 switches whether or not to supply the drive signal COM to the corresponding discharge unit 600 as the drive signal VOUT.

[0030] Each of the multiple ejection units 600 includes a piezoelectric element 60. One end of the piezoelectric element 60 included in each of the multiple ejection units 600 is supplied with a drive signal VOUT output by the corresponding selection circuit 230. The other end of the piezoelectric element 60 included in each of the multiple ejection units 600 is commonly supplied with a reference voltage signal VBS output by the reference voltage output circuit 52. The piezoelectric element 60 is driven in response to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the drive of this piezoelectric element 60 is ejected from the ejection unit 600.

[0031] 1.2 Discharge head 1.2.1 Discharge section structure An example of the structure of the discharge unit 600 of the discharge head 200 will be described. Fig. 3 is a diagram showing a schematic structure of one of the multiple discharge units 600 of the discharge head 200. As shown in Fig. 3, the discharge unit 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651.

[0032] The cavity 631 is filled with ink supplied from a reservoir 641. In addition, ink is introduced into the reservoir 641 from the ink container 2 via an ink tube (not shown) and a supply port 661. In other words, the cavity 631 is filled with ink stored in the corresponding ink container 2.

[0033] 3, the vibration plate 621 is displaced by driving the piezoelectric element 60 provided on the upper surface. The internal volume of the cavity 631 filled with ink expands or contracts in accordance with the displacement of the vibration plate 621. In other words, the vibration plate 621 functions as a diaphragm that changes the internal volume of the cavity 631.

[0034] The nozzle 651 is provided in the nozzle plate 632 and is an opening that communicates with the cavity 631. When the internal volume of the cavity 631 changes, an amount of ink corresponding to the change in internal volume is ejected from the nozzle 651.

[0035] Piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In piezoelectric body 601 having such a structure, the central portions of electrodes 611 and 612 bend vertically together with diaphragm 621 in response to the potential difference of signals supplied to electrodes 611 and 612.

[0036] For example, a drive signal VOUT is supplied to one of the electrodes 611 or 612 of the piezoelectric element 60, and a reference voltage signal VBS is supplied to the other of the electrodes 611 or 612 of the piezoelectric element 60. When the voltage value of the drive signal VOUT increases, the piezoelectric element 60 bends upward. As the piezoelectric element 60 bends upward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 expands. As a result, ink is drawn in from the reservoir 641. On the other hand, when the voltage value of the drive signal VOUT decreases, the piezoelectric element 60 bends downward. As the piezoelectric element 60 bends downward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 contracts. As a result, an amount of ink corresponding to the degree of contraction is ejected from the nozzle 651.

[0037] That is, the ejection section 600 includes a piezoelectric element 60 that is driven by a drive signal VOUT based on the drive signal COM, and ejects ink when the piezoelectric element 60 is driven.

[0038] 3, the piezoelectric element 60 may have any structure as long as it can eject ink from the ejection portion 600. That is, the piezoelectric element 60 is not limited to the bending vibration structure described above, and may have a structure that uses longitudinal vibration, for example. Furthermore, the piezoelectric element 60 may be configured to bend downward when the voltage value of the drive signal VOUT increases, and to bend upward when the voltage value of the drive signal VOUT decreases.

[0039] 1.2.2 Functional configuration of the drive signal selection circuit Next, the functional configuration of the selection control circuit 210 and the multiple selection circuits 230 of the ejection head 200 will be described. Before describing the functional configuration of the selection control circuit 210 and the multiple selection circuits 230, an example of a drive signal COM controlled to be selected or deselected by the selection control circuit 210 and the multiple selection circuits 230 will be described. FIG. 4 is a diagram showing an example of a signal waveform of the drive signal COM. As shown in FIG. 4, the drive signal COM includes a trapezoidal waveform Adp arranged for each cycle tp from when the latch signal LAT rises until the next rise of the latch signal LAT. The trapezoidal waveform Adp includes a period during which the voltage value is constant at voltage vb, a period during which the voltage value is constant at voltage vt, which is higher than voltage vb, and a period during which the voltage value is constant at voltage vt. That is, the drive signal COM includes a trapezoidal waveform Adp whose voltage value changes between voltage vb and voltage vt and whose voltage value starts at voltage vb and ends at voltage vb during the cycle tp.

[0040] The voltage vb is a voltage value that serves as a reference for the displacement of the piezoelectric element 60. When the voltage value of the drive signal VOUT based on the drive signal COM supplied to the piezoelectric element 60 changes from voltage vb to voltage vt, the piezoelectric element 60 is driven in the upward direction shown in FIG. 3. This causes the vibration plate 621 to be displaced in the upward direction shown in FIG. 3, and the internal volume of the cavity 631 to expand. As a result, ink is drawn from the reservoir 641 into the cavity 631. Thereafter, when the voltage value of the drive signal COM supplied to the piezoelectric element 60 changes from voltage vt to voltage vb, the piezoelectric element 60 is driven in the downward direction shown in FIG. 3. This causes the vibration plate 621 to be displaced in the downward direction shown in FIG. 3, and the internal volume of the cavity 631 to contract. As a result, the ink stored in the cavity 631 is ejected from the nozzle 651.

[0041] Here, the signal waveform of the drive signal COM shown in Figure 4 is an example and is not limited to this, and the drive signal COM may include signal waveforms of various shapes depending on the physical properties of the ink, the ink temperature, the ink ejection amount, the ink ejection period, the type of medium P, the transport speed, etc.

[0042] The selection control circuit 210 outputs a selection signal S to each of the multiple selection circuits 230, which switches whether or not to output the drive signal COM as the drive signal VOUT during the period tp, based on the clock signal SCK, the print data signal SI, and the latch signal LAT. The multiple selection circuits 230 then switch whether or not to output the drive signal COM as the drive signal VOUT based on the input selection signal S. This controls the ejection of ink from the nozzles 651 during the period tp. FIG. 5 is a diagram showing an example of the configuration of the selection control circuit 210 and the multiple selection circuits 230. In the following description, the ejection head 200 will be described as having m ejection units 600.

[0043] A clock signal SCK, a print data signal SI, and a latch signal LAT are input to the selection control circuit 210. The selection control circuit 210 also includes a set of a shift register (S / R) 212, a latch circuit 214, and a decoder 216, each of which corresponds to one of the m ejection sections 600. That is, the selection control circuit 210 includes m shift registers 212, m latch circuits 214, and m decoders 216.

[0044] The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. The print data signal SI also includes one-bit print data [SId] for selecting whether or not to eject ink, serially corresponding to each of the m ejection units 600. The print data [SId] included in the print data signal SI is held in m shift registers 212 corresponding to the m ejection units 600. Specifically, the m shift registers 212 corresponding to the piezoelectric elements 60 are cascade-connected, and the serially input print data signal SI is sequentially transferred to the subsequent shift register 212 in accordance with the clock signal SCK. Then, when the print data [SId] is held in the corresponding shift register 212, the clock signal SCK stops. As a result, the print data [SId] included in the print data signal SI is held in the corresponding shift register 212. In FIG. 5, in order to distinguish the m shift registers 212, they are denoted as 1st stage, 2nd stage, . . . , mth stage in order from the upstream side where the print data signal SI is input.

[0045] Each of the m latch circuits 214 simultaneously latches the print data [SId] held in the corresponding shift register 212 at the rising edge of the latch signal LAT. The print data [SId] latched by the latch circuit 214 is then input to the corresponding decoder 216. FIG. 6 is a diagram showing an example of the decoded content in the decoder 216. In a period tp, the decoder 216 generates a signal of a logic level determined by the input print data [SId], shifts the level to a high-amplitude logic, and outputs the signal as a selection signal S. Specifically, when print data [SId]=[1] is input to the decoder 216, the decoder 216 selects dot formation Dt, which forms dots on the medium P, and outputs an H-level selection signal S. When print data [SId]=[0] is input to the decoder 216, the decoder 216 selects dot non-formation NDt, which does not form dots on the medium P, and outputs an L-level selection signal S. The selection signal S output by this decoder 216 is output from the selection control circuit 210.

[0046] The selection signal S output by the selection control circuit 210 is input to the selection circuit 230. A selection circuit 230 is provided corresponding to each of the m ejection units 600. In other words, the ejection head 200 has m selection circuits 230, the same number as the m ejection units 600. FIG. 7 is a diagram showing an example of the configuration of the selection circuit 230. As shown in FIG. 7, the selection circuit 230 includes an inverter 232, which is a NOT circuit, and a transmission gate 234.

[0047] The selection signal S is input to a positive control terminal (not marked with a circle) of the transmission gate 234, and after its logical level is inverted by the inverter 232, is also input to a negative control terminal (marked with a circle) of the transmission gate 234. A drive signal COM is supplied to the input terminal of the transmission gate 234. When an H-level selection signal S is input, the input terminal and output terminal of the transmission gate 234 are electrically connected, and when an L-level selection signal S is input, the input terminal and output terminal are electrically disconnected. That is, when the logical level of the selection signal S is H, the transmission gate 234 outputs the drive signal COM from its output terminal, and when the logical level of the selection signal S is L, the transmission gate 234 does not output the drive signal COM from its output terminal. The signal output to the output terminal of the transmission gate 234 of this selection circuit 230 is supplied as a drive signal VOUT to the piezoelectric element 60 of the corresponding ejection unit 600.

[0048] That is, one end of the selection circuit 230 is electrically connected to the corresponding piezoelectric element 60 and the other end is electrically connected to the drive signal output circuit 51 , and switches the conduction state between the piezoelectric element 60 and the drive signal output circuit 51 .

[0049] 1.3 Drive signal output circuit Next, the configuration and operation of the drive signal output circuit 51 included in the drive circuit 50 will be described. FIG. 8 is a diagram showing the configuration of the drive signal output circuit 51. As shown in FIG. 8, the drive signal output circuit 51 includes an integrated circuit 500, an amplifier circuit 550, a demodulation circuit 560, feedback circuits 570 and 572, and multiple other circuit elements. The integrated circuit 500 generates gate signals Hgd and Lgd based on a basic drive signal dA, which is the basis of the drive signal COM, and outputs the gate signals Hgd and Lgd to the amplifier circuit 550. The amplifier circuit 550 includes transistors M1 and M2, which are driven based on the gate signals Hgd and Lgd to generate an amplified modulation signal AMs and output the amplified modulation signal AMs to the demodulation circuit 560. The demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing it. The signal demodulated by the demodulation circuit 560 is output from the drive signal output circuit 51 as the drive signal COM.

[0050] The integrated circuit 500 has a plurality of terminals including a terminal In, a terminal Bst, a terminal Hdr, a terminal Sw, a terminal Gvd, a terminal Ldr, a terminal Gnd, a terminal Ifb, a terminal Vfb, and a terminal Dic. The integrated circuit 500 is electrically connected to an external circuit via these plurality of terminals. The integrated circuit 500 also includes a DAC (Digital to Analog Converter) 511, a modulation circuit 510, and a gate drive circuit 520.

[0051] The DAC 511 converts the reference drive signal dA, which is a digital signal that defines the signal waveform of the drive signal COM, into a reference drive signal aA, which is an analog signal, and outputs it to the modulation circuit 510. The signal obtained by amplifying the reference drive signal aA output by the DAC 511 corresponds to the drive signal COM. In other words, the reference drive signal aA is a target signal for the drive signal COM before amplification, and the reference drive signal dA is a target signal for the drive signal COM before amplification and is a signal that defines the shape of the signal waveform of the drive signal COM. The voltage amplitude of the reference drive signal aA output by the DAC 511 is set to, for example, 1V to 2V.

[0052] The modulation circuit 510 generates a modulation signal Ms by modulating the basic drive signal aA and outputs it to the gate drive circuit 520. The modulation circuit 510 includes adders 512 and 513, a comparator 514, an inverter 515, an integral attenuator 516, and an attenuator 517.

[0053] The integral attenuator 516 attenuates and integrates the voltage value of the drive signal COM input via terminal Vfb, and outputs the integrated signal to the negative input terminal of the adder 512. The reference drive signal aA is input to the positive input terminal of the adder 512. The adder 512 generates a voltage signal by subtracting the voltage value of the signal input to the negative input terminal from the voltage value of the signal input to the positive input terminal, and outputs this signal to the positive input terminal of the adder 513. Here, while the maximum value of the voltage amplitude of the reference drive signal aA is about 2 V as mentioned above, the maximum voltage value of the drive signal COM can exceed 40 V. When calculating the deviation, the integral attenuator 516 attenuates the drive signal COM input via terminal Vfb to match the range of the voltage amplitude of the reference drive signal aA with the range of the voltage amplitude of the drive signal COM.

[0054] The attenuator 517 attenuates the high-frequency components of the drive signal COM input via terminal Ifb and supplies the resulting voltage to the negative input terminal of the adder 513. The signal output by the adder 512 is input to the positive input terminal of the adder 513. The adder 513 generates a voltage signal As by subtracting the voltage value of the signal input to its negative input terminal from the voltage value of the signal input to its positive input terminal, and outputs this to the comparator 514. The voltage signal As is a signal obtained by subtracting the voltage value of the signal supplied to terminal Vfb from the voltage value of the base drive signal aA, and then further subtracting the voltage value of the signal supplied to terminal Ifb. Therefore, the voltage signal As is a signal obtained by correcting the deviation, obtained by subtracting the attenuated voltage of the drive signal COM from the target voltage value of the base drive signal aA, using the high-frequency components of the drive signal COM.

[0055] The comparator 514 pulse-modulates the voltage signal As and outputs the modulated signal Ms. Specifically, the comparator 514 outputs a modulated signal Ms that goes high when the voltage value of the voltage signal As is equal to or greater than a predetermined threshold Vth1 during a period in which the voltage value of the voltage signal As is increasing, and goes low when the voltage value of the voltage signal As is lower than a predetermined threshold Vth2 during a period in which the voltage value of the voltage signal As is decreasing. Here, the thresholds Vth1 and Vth2 are set such that threshold Vth1 is greater than threshold Vth2. The frequency and duty ratio of this modulated signal Ms change in accordance with the basic drive signals dA and aA. In other words, by adjusting the modulation gain, which corresponds to the sensitivity of the attenuator 517, the amount of change in the frequency and duty ratio of the modulated signal Ms can be adjusted.

[0056] The modulation signal Ms is input to a gate driver 521 included in a gate drive circuit 520. The modulation signal Ms is also input to a gate driver 522 included in the gate drive circuit 520 after its logical level is inverted by an inverter 515. That is, signals whose logical levels are mutually exclusive are input to the gate drivers 521 and 522.

[0057] Here, the timing of the signals input to the gate drivers 521 and 522 may be controlled so that the logic levels do not become H level at the same time. In other words, the above-mentioned "mutually exclusive relationship of logic levels" means that the logic level of the signal input to the gate driver 521 and the logic level of the signal input to the gate driver 522 are not H level at the same time, and includes the case where the logic level of the signal input to the gate driver 521 and the logic level of the signal input to the gate driver 522 are L level at the same time.

[0058] The gate drive circuit 520 includes a gate driver 521 and a gate driver 522 .

[0059] The gate driver 521 generates a gate signal Hgd by level-shifting the modulation signal Ms output by the comparator 514 and outputs it from the integrated circuit 500 via the terminal Hdr. The high-potential side of the power supply voltage of the gate driver 521 is supplied via the terminal Bst, and the low-potential side is supplied via the terminal Sw. The terminal Bst is electrically connected to one end of the capacitor C5 and the cathode of the diode D1. The other end of the capacitor C5 is electrically connected to the terminal Sw. The anode of the diode D1 is electrically connected to the terminal Gvd. The terminal Gvd is also supplied with a voltage signal Vm, which is a DC voltage of, for example, 7.5 V, generated by a power supply circuit (not shown). As a result, the potential difference between the terminals Bst and Sw is the potential difference across the capacitor C5 and is approximately equal to the voltage value of the voltage signal Vm. Therefore, the gate driver 521 generates a gate signal Hgd whose H-level voltage value is greater than the voltage value of the terminal Sw by the voltage value of the voltage signal Vm and whose L-level voltage value is the voltage value of the terminal Sw according to the logical level of the input modulation signal Ms, and outputs it from the terminal Hdr.

[0060] The gate driver 522 operates at a lower potential side than the gate driver 521. The gate driver 522 generates a gate signal Lgd by level-shifting a signal in which the logical level of the modulation signal Ms output by the comparator 514 is inverted by an inverter 515, and outputs the gate signal Lgd from the integrated circuit 500 via the terminal Ldr. Of the power supply voltages of the gate driver 522, a voltage signal Vm is supplied to the high potential side, and a ground potential is supplied to the low potential side via the terminal Gnd. The gate driver 522 generates a gate signal Lgd of ground potential, whose H-level voltage value is higher than the voltage value of the voltage signal Vm relative to the terminal Gnd and whose L-level voltage value is the voltage value of the terminal Gnd, according to the logical level of the input signal, and outputs the gate signal Lgd from the terminal Ldr.

[0061] As described above, the gate signal Hgd is a signal obtained by level-shifting the voltage value of the modulation signal Ms, and the gate signal Lgd is a signal obtained by inverting the logical level of the modulation signal Ms and then level-shifting the voltage value of the inverted signal. In light of this, the gate signals Hgd and Lgd output by the gate drive circuit 520 can also be considered to be signals obtained by modulating the basic drive signals dA and aA.

[0062] The amplifier circuit 550 includes a pair of transistors M1 and M2, which are semiconductor elements such as N-type FETs (Field Effect Transistors).

[0063] A voltage signal VHV, which is a DC voltage of, for example, 42 V, is supplied to the drain terminal of the transistor M1. The gate terminal of the transistor M1 is electrically connected to one end of a resistor R1. The other end of the resistor R1 is electrically connected to a terminal Hdr of the integrated circuit 500. That is, a gate signal Hgd output by the integrated circuit 500 is input to the gate terminal of the transistor M1. The source terminal of the transistor M1 is electrically connected to a terminal Sw of the integrated circuit 500. The conduction state between the drain terminal and the source terminal of the transistor M1 is controlled by the gate signal Hgd input to the gate terminal.

[0064] The drain terminal of the transistor M2 is electrically connected to the terminal Sw of the integrated circuit 500. That is, the drain terminal of the transistor M2 and the source terminal of the transistor M1 are electrically connected to each other. The gate terminal of the transistor M2 is electrically connected to one end of the resistor R2. The other end of the resistor R2 is electrically connected to the terminal Ldr of the integrated circuit 500. That is, a gate signal Lgd output by the integrated circuit 500 is input to the gate terminal of the transistor M2. A ground potential is supplied to the source terminal of the transistor M2. The conduction state between the drain terminal and the source terminal of the transistor M2 is controlled by the gate signal Lgd input to the gate terminal.

[0065] In the following description, when the drain terminals and source terminals of transistors M1 and M2 are controlled to be conductive, this may be referred to as "on," and when the drain terminals and source terminals of transistors M1 and M2 are controlled to be non-conductive, this may be referred to as "off."

[0066] In the amplifier circuit 550 configured as described above, when the transistor M1 is controlled to be off and the transistor M2 is controlled to be on, the node to which the terminal Sw is connected is at ground potential. At this time, the voltage signal Vm is supplied to the terminal Bst. On the other hand, when the transistor M1 is controlled to be on and the transistor M2 is controlled to be off, the node to which the terminal Sw is connected is at voltage signal VHV. Therefore, a signal having a voltage value equal to the sum of the voltage values ​​of the voltage signals VHV and Vm is supplied to the terminal Bst. That is, the gate driver 521 that drives the transistor M1 uses the capacitor C5 as a floating power supply, and the potential at the other end of the capacitor C5, the terminal Sw, changes to the ground potential or the voltage value of the voltage signal VHV depending on the operation of the transistors M1 and M2, so that the gate driver 521 generates a gate signal Hgd whose L level is the voltage value of the voltage signal VHV and whose H level is the sum of the voltage values ​​of the voltage signal VHV and the voltage value of the voltage signal Vm, and supplies this to the gate terminal of the transistor M1.

[0067] On the other hand, the gate driver 522 that drives the transistor M2 generates a gate signal Lgd whose L level is the ground potential and whose H level is the voltage value of the voltage signal Vm, regardless of the operation of the transistors M1 and M2, and supplies it to the gate terminal of the transistor M2.

[0068] As described above, the amplifier circuit 550 amplifies the modulation signal Ms, which is generated by modulating the basic drive signals dA and aA, based on the voltage signal VHV by operating the transistors M1 and M2 in response to the gate signals Hgd and Lgd. The amplifier circuit 550 then outputs the amplified signal as an amplified modulation signal AMs from the connection point where the source terminal of the transistor M1 and the drain terminal of the transistor M2 are commonly connected.

[0069] The demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing it, and generates the drive signal COM. The demodulation circuit 560 then outputs the generated drive signal COM from the drive signal output circuit 51.

[0070] The demodulation circuit 560 includes a coil L1 and a capacitor C1. One end of the coil L1 is electrically connected to the source terminal of the transistor M1 and the drain terminal of the transistor M2. As a result, the amplified modulation signal AMs is input to one end of the coil L1. The other end of the coil L1 is connected to the terminal Out, which serves as the output of the drive signal output circuit 51. The other end of the coil L1 is also connected to one end of the capacitor C1. The other end of the capacitor C1 is supplied with ground potential. In other words, the coil L1 and the capacitor C1 form a low-pass filter. The amplified modulation signal AMs is smoothed by the low-pass filter formed in the demodulation circuit 560, thereby generating the drive signal COM.

[0071] The feedback circuit 570 includes resistors R3 and R4. One end of the resistor R3 is connected to the terminal Out from which the drive signal COM is output, and the other end of the resistor R3 is connected to the terminal Vfb and one end of the resistor R4. A voltage signal VHV is supplied to the other end of the resistor R4. As a result, the drive signal COM that has passed through the feedback circuit 570 from the terminal Out is fed back to the terminal Vfb in a pulled-up state.

[0072] The feedback circuit 572 includes capacitors C2, C3, and C4 and resistors R5 and R6. One end of the capacitor C2 is connected to the terminal Out from which the drive signal COM is output, and the other end of the capacitor C2 is connected to one end of the resistor R5 and one end of the resistor R6. The other end of the resistor R5 is supplied with a ground potential. This allows the capacitor C2 and the resistor R5 to function as a high-pass filter. The cutoff frequency of this high-pass filter is set to, for example, approximately 9 MHz.

[0073] The other end of the resistor R6 is connected to one end of a capacitor C4 and one end of a capacitor C3. The other end of the capacitor C3 is supplied with ground potential. This allows the resistor R6 and the capacitor C3 to function as a low-pass filter. The cutoff frequency of the low-pass filter is set to, for example, approximately 160 MHz.

[0074] As described above, the feedback circuit 572 is configured to include a high-pass filter and a low-pass filter. As a result, the feedback circuit 572 functions as a band-pass filter that passes a predetermined frequency range of the drive signal COM. The other end of the capacitor C4 included in the feedback circuit 572 is connected to the terminal Ifb of the integrated circuit 500. As a result, a signal from which the DC component has been cut out of the high-frequency components of the drive signal COM that have passed through the feedback circuit 572, which functions as a band-pass filter that passes a predetermined frequency component, is fed back to the terminal Ifb.

[0075] The drive signal COM output from the terminal Out is a signal obtained by demodulating the amplified modulation signal AMs based on the basic drive signal dA by smoothing it using the demodulation circuit 560. The drive signal COM output from the demodulation circuit 560 is then integrated and attenuated via the feedback circuit 570 and the terminal Vfb, and then fed back to the adder 512. This causes the drive signal output circuit 51 to self-oscillate at a frequency determined by the feedback delay and the feedback transfer function. However, the amount of delay is large using only the feedback path via the terminal Vfb, and therefore, feedback via the terminal Vfb alone may not be enough to increase the frequency of self-oscillation to a level sufficient to ensure the accuracy of the drive signal COM.

[0076] The drive signal output circuit 51 of this embodiment has a path that feeds back the high-frequency component of the drive signal COM via a feedback circuit 572 and terminal Ifb, in addition to the path via terminal Vfb. This reduces the delay in the drive signal output circuit 51 of this embodiment when viewed from the perspective of the entire circuit that makes up the drive signal output circuit 51, and compared to when there is no path via terminal Ifb, it is possible to increase the frequency of the voltage signal As to a level that sufficiently ensures the accuracy of the drive signal COM.

[0077] Here, the oscillation frequency of the self-oscillation in the drive signal output circuit 51 in this embodiment is preferably 1 MHz or more and 8 MHz or less from the viewpoint of reducing heat generation in the drive signal output circuit 51 while ensuring sufficient accuracy of the drive signal COM, and in particular, the oscillation frequency of the self-oscillation in the drive signal output circuit 51 is preferably 1 MHz or more and 4 MHz or less when reducing the power consumption of the liquid ejection device 1. In other words, the drive frequency of the transistors M1 and M2 is preferably 1 MHz or more and 8 MHz or less from the viewpoint of reducing heat generation in the transistors M1 and M2, and further, when reducing the power consumption of the liquid ejection device 1 by reducing losses generated in the transistors M1 and M2, the drive frequency of the transistors M1 and M2 is preferably 1 MHz or more and 4 MHz or less.

[0078] In the liquid ejection device 1 of this embodiment, the drive signal output circuit 51 smoothes the amplified modulation signal AMs to generate a drive signal COM, which is supplied to the piezoelectric element 60 of the head unit 20. Then, when the drive signal COM is supplied to the piezoelectric element 60, the piezoelectric element 60 is driven, and an amount of ink corresponding to the drive of the piezoelectric element 60 is ejected from the ejection section 600.

[0079] When frequency spectrum analysis is performed on the signal waveform of the drive signal COM that drives such a piezoelectric element 60, it is found that the drive signal COM contains frequency components of 50 kHz or higher. When generating a signal waveform of the drive signal COM containing such frequency components of 50 kHz or higher, if the frequency of the modulation signal Ms is set lower than 1 MHz, the edges of the signal waveform of the drive signal COM will become dull. Therefore, to generate the signal waveform of the drive signal COM with precision, the frequency of the modulation signal Ms, which is the drive frequency of the transistors M1 and M2, needs to be 1 MHz or higher.

[0080] On the other hand, increasing the frequency of the modulation signal Ms, which is the self-oscillation frequency of the drive signal output circuit 51, and the drive frequency of the transistors M1 and M2, increases the switching losses in the transistors M1 and M2. Such switching losses in the transistors M1 and M2 increase the power consumption and heat generation in the drive signal output circuit 51. Such switching losses in the transistors M1 and M2 undermine the power and heat generation advantages of a class-D amplifier over linear amplifiers such as a class-AB amplifier. From the perspective of reducing such switching losses in the transistors M1 and M2, it is preferable to set the frequency of the modulation signal Ms, which is the self-oscillation frequency of the drive signal output circuit 51, and the drive frequency of the transistors M1 and M2 to 8 MHz or less. In particular, from the perspective of improving the power consumption of the liquid ejection device 1, it is preferable to set the drive frequency of the transistors M1 and M2 to 4 MHz or less.

[0081] From the above, in a drive signal output circuit 51 using a Class D amplifier, when improving the accuracy of the signal waveform of the output drive signal COM while also saving power, it is preferable that the self-oscillation oscillation frequency of the drive signal output circuit 51, that is, the drive frequency of transistors M1 and M2, be 1 MHz or more and 8 MHz or less, and particularly when reducing the power consumption of the liquid ejection device 1, it is preferable that the self-oscillation oscillation frequency of the drive signal output circuit 51, that is, the drive frequency of transistors M1 and M2, be 1 MHz or more and 4 MHz or less.

[0082] As described above, in the drive signal output circuit 51 of this embodiment, the feedback circuit 572 extracts a signal of high-frequency components caused by a ripple voltage or the like included in the drive signal COM, and feeds the extracted signal back to the modulation circuit 510 via the terminal Ifb. This enables the drive signal output circuit 51 to achieve high-frequency switching of the transistors M1 and M2 included in the amplifier circuit 550, thereby improving the accuracy of the signal waveform of the drive signal COM that is output. That is, the drive signal output circuit 51 that outputs the drive signal COM that drives the piezoelectric element 60 includes a modulation circuit 510 that modulates basic drive signals dA, aA that form the basis of the drive signal COM and outputs a modulated signal Ms, an amplifier circuit 550 that has a transistor pair including transistor M1 and transistor M2 and outputs an amplified modulated signal AMs that is obtained by amplifying the modulated signal Ms, a demodulation circuit 560 that demodulates the amplified modulated signal AMs and outputs it as the drive signal COM, a gate drive circuit 520 that outputs a gate signal Hgd that controls the drive of transistor M1 and a gate signal Lgd that controls the drive of transistor M2, and feedback circuits 570, 572 that feed the drive signal COM back to the modulation circuit 510.

[0083] On the other hand, the drive signal output circuit 51 of this embodiment extracts high-frequency component signals caused by ripple signals and the like superimposed on the drive signal COM and self-oscillates based on the extracted signal. Therefore, there is no correlation between the signal waveform defined by the master drive signal dA, which is the basis of the drive signal COM, and the switching phase of the transistors M1 and M2; they are independent of each other. Therefore, the switching phase of the transistors M1 and M2 may change with each period tp of the signal waveform defined by the master drive signal dA. If the switching phase of the transistors M1 and M2 changes with each period tp of the signal waveform defined by the master drive signal dA, different waveform distortions may occur in the signal waveform of the drive signal COM for each period tp. Because this waveform distortion differs for each period tp, it is difficult to uniformly correct it, which creates a new problem: it reduces the ejection accuracy of ink ejected based on the drive signal COM.

[0084] Furthermore, to address this issue, for example, by making q times (q is an integer) the switching period of the transistors M1 and M2 equal to the period tp, which is the period of the drive signal COM, it becomes possible to uniformly control the switching phase of the transistors M1 and M2 for each period tp, and it becomes possible to reduce the risk of different waveform distortion occurring in the signal waveform of the drive signal COM for each period tp. However, in the liquid ejection device 1 of this embodiment, the voltage signal As input to the comparator 514 is a triangular wave whose frequency varies depending on the voltage value of the basic drive signal aA, and therefore the modulated signal Ms obtained by modulating the voltage signal As is a so-called pulse density modulation (PDM) signal whose frequency varies. This has the advantage that it is possible to control the duty ratio of the gate signals Hgd, Lgd output by the gate drive circuit 520 with high precision, thereby improving the waveform precision of the drive signal COM. However, because the frequencies of the gate signals Hgd, Lgd output by the gate drive circuit 520 change, it is not possible to make q times the switching period of the transistors M1, M2 equal to the period tp, which is the period of the drive signal COM.

[0085] An example of waveform distortion that may occur in such a drive signal COM, which differs for each cycle tp, will be described below. Fig. 9 is a diagram illustrating an example of waveform distortion in the drive signal COM that may occur when the switching phases of the transistors M1 and M2 differ for each cycle tp. Here, Fig. 9 illustrates, as the drive signal COM, drive signals COMa and COMb, in which the switching phases of the transistors M1 and M2 in the cycle tp differ.

[0086] 9, a ripple voltage is superimposed on the drive signals COMa and COMb. The ripple voltage superimposed on the drive signals COMa and COMb is a minute voltage change that remains in synchronization with the voltage change of the amplified modulation signal AMs when the demodulation circuit 560 smoothes the amplified modulation signal AMs, and has a voltage amplitude of, for example, about 1 V.

[0087] As described above, the amplified modulation signal AMs is generated by driving the transistors M1 and M2 included in the amplifier circuit 550. That is, the period of the ripple voltage superimposed on the drive signals COMa and COMb is synchronized with the switching period of the transistors M1 and M2. Therefore, the phase of the ripple voltage superimposed on the drive signal COMa differs from the phase of the ripple voltage superimposed on the drive signal COMb, and therefore, a voltage difference due to the superimposed ripple voltage occurs between the voltage values ​​of the drive signals COMa and COMb at any given time.

[0088] Furthermore, as mentioned above, there is no correlation between the signal waveform defined by the basic drive signal dA and the switching phase of transistors M1 and M2. Therefore, at time t1, when the voltage value of the basic drive signal aA, which is the timing when the voltage value of the signal waveform defined by the basic drive signal dA, switches from a constant state to a changing state, a voltage difference occurs between the voltage values ​​of drive signals COMa and COMb due to the voltage value of the superimposed ripple voltage. This voltage difference between drive signals COMa and COMb causes different waveform distortions to occur between drive signals COMa and COMb at time t1.

[0089] Furthermore, after time t1, the drive signal output circuit 51 controls the driving of the transistors M1 and M2 so that the signal waveforms of the output drive signals COMa and COMb are the signal waveform of the basic drive signal aA and asymptotically approach the signal waveform defined by the basic drive signal dA. In other words, the drive signal output circuit 51 performs self-oscillation so that the voltage values ​​of the output drive signals COMa and COMb are approximately equal.

[0090] However, because the voltage values ​​of drive signals COMa and COMb are different at time t1, any one of the switching phase, period, and duty of transistors M1 and M2 that generate drive signal COMa during self-oscillation differs from at least any one of the switching phase, period, and duty of transistors M1 and M2 that generate drive signal COMb during self-oscillation. As a result, at time t2, when the voltage value of the signal waveform of basic drive signal aA, defined by basic drive signal dA, switches from a varying state to a constant state, a voltage difference occurs between the voltage values ​​of drive signals COMa and COMb due to the voltage value of the superimposed ripple voltage. This voltage difference between drive signals COMa and COMb causes different waveform distortions between drive signals COMa and COMb at time t2.

[0091] After time t2, the drive signal output circuit 51 controls the driving of the transistors M1 and M2 so that the signal waveforms of the output drive signals COMa and COMb asymptotically approach the signal waveform of the basic drive signal aA defined by the basic drive signal dA. In other words, the drive signal output circuit 51 performs self-oscillation so that the voltage values ​​of the output drive signals COMa and COMb are approximately equal.

[0092] However, because the voltage values ​​of drive signals COMa and COMb are different at time t2, any one of the switching phase, period, and duty of transistors M1 and M2 that generate drive signal COMa during self-oscillation differs from at least any one of the switching phase, period, and duty of transistors M1 and M2 that generate drive signal COMb during self-oscillation. As a result, at time t3, when the voltage value of the signal waveform of basic drive signal aA, defined by basic drive signal dA, switches from a constant state to a changing state, a voltage difference occurs between the voltage values ​​of drive signals COMa and COMb due to the voltage value of the superimposed ripple voltage. This voltage difference between drive signals COMa and COMb causes different waveform distortions between drive signals COMa and COMb at time t3.

[0093] After time t3, the drive signal output circuit 51 controls the driving of the transistors M1 and M2 so that the signal waveforms of the output drive signals COMa and COMb asymptotically approach the signal waveform of the basic drive signal aA defined by the basic drive signal dA. In other words, the drive signal output circuit 51 performs self-oscillation so that the voltage values ​​of the output drive signals COMa and COMb are approximately equal.

[0094] However, because the voltage values ​​of drive signals COMa and COMb are different at time t3, any one of the switching phase, period, and duty of transistors M1 and M2 that generate drive signal COMa during self-oscillation differs from at least any one of the switching phase, period, and duty of transistors M1 and M2 that generate drive signal COMb during self-oscillation. As a result, at time t4, when the voltage value of the signal waveform of basic drive signal aA, defined by basic drive signal dA, switches from a varying state to a constant state, a voltage difference occurs between the voltage values ​​of drive signals COMa and COMb due to the voltage value of the superimposed ripple voltage. This voltage difference between drive signals COMa and COMb causes different waveform distortions between drive signals COMa and COMb at time t4.

[0095] As described above, when the switching phase of transistors M1 and M2 differs for each period tp, different waveform distortions may occur in the signal waveforms of drive signals COMa and COMb at the timing when the voltage value of the signal waveform of base drive signal aA, which is defined by base drive signal dA, switches from a constant state to a changing state, and at the timing when it switches from the changing state to a constant state.

[0096] Since the switching phases of the transistors M1 and M2 differ for each period tp, in order to reduce the risk of different waveform distortions occurring in the drive signal COM for each period tp, the drive signal output circuit 51 provided in the liquid ejection device 1 of this embodiment has a differentiation circuit 530, a stop control circuit 540, and a load current detection circuit 580 as shown in Figure 8.

[0097] The differentiating circuit 530 is included in the integrated circuit 500, along with the modulation circuit 510 and gate drive circuit 520 described above. The base drive signal dA is input to the differentiating circuit 530. The differentiating circuit 530 outputs a differentiated base drive signal DdA that goes to H level when the value of the input base drive signal dA changes, and goes to L level when the value of the input base drive signal dA does not change. In other words, the differentiating circuit 530 outputs a differentiated base drive signal DdA that goes to H level when the voltage value of the signal waveform defined by the base drive signal dA changes and the voltage value of the base drive signal aA changes, and goes to L level when the voltage value of the signal waveform defined by the base drive signal dA is constant and the voltage value of the base drive signal aA is constant. Note that the differentiating circuit 530 may be configured to receive the base drive signal aA instead of the base drive signal dA.

[0098] The load current detection circuit 580 includes a high-pass filter 582 and a comparator 584. The high-pass filter 582 also includes a capacitor C5 and a resistor R7. One end of the capacitor C5 is electrically connected to the terminal Out, which serves as the output of the drive signal output circuit 51. The other end of the capacitor C5 is electrically connected to one end of the resistor R7. The other end of the resistor R7 is supplied with ground potential. The high-pass filter 582, which is formed by the capacitor C5 and the resistor R7, outputs a load current signal DIp, whose voltage value changes depending on the amount and direction of the current generated by the propagation of the drive signal COM output via the terminal Out. Specifically, in the drive signal output circuit 51 of this embodiment, the differential value of the voltage value of the drive signal COM supplied to the piezoelectric element 60 is proportional to the value of the current flowing through the piezoelectric element 60. The high-pass filter 582 differentiates the voltage value of the drive signal COM to output a load current signal DIp whose voltage value changes depending on the amount and direction of the current generated in association with the propagation of the drive signal COM. When the current generated in association with the propagation of the drive signal COM flows from the drive signal output circuit 51 to the ejection head 200, the voltage value is positive, and when the current generated in association with the propagation of the drive signal COM flows from the ejection head 200 to the drive signal output circuit 51, the voltage value is negative.

[0099] Here, in the following description, the direction along the propagation path through which the current generated by the propagation of the drive signal COM flows from the demodulation circuit 560 of the drive signal output circuit 51 to the piezoelectric element 60 of the ejection head 200 may be referred to as the positive direction, and the direction from the piezoelectric element 60 of the ejection head 200 to the demodulation circuit 560 of the drive signal output circuit 51 may be referred to as the negative direction.

[0100] The load current signal DIp is input to the positive input terminal of the comparator 584. A ground potential is supplied to the negative input terminal of the comparator 584. The comparator 584 configured as described above outputs a current detection signal DIo that is at an H level when the voltage value of the load current signal DIp is positive and at an L level when the voltage value of the load current signal DIp is negative. In other words, the comparator 584 outputs a current detection signal DIo whose logic level switches at the timing when the load current signal DIp output by the high-pass filter 582 becomes zero and when the current generated by the propagation of the drive signal COM becomes zero.

[0101] That is, the load current detection circuit 580 includes a high-pass filter 582 and outputs a current detection signal DIo corresponding to the load current signal DIp output by the high-pass filter 582 .

[0102] The stop control circuit 540 is included in the integrated circuit 500, together with the modulation circuit 510 and gate drive circuit 520 described above. The stop control circuit 540 receives the differential base drive signal DdA output by the differentiating circuit 530 and also receives the current detection signal DIo output by the load current detection circuit 580 via the terminal Dio. The stop control circuit 540 generates an enable signal EN whose logic level changes based on the differential base drive signal DdA and the current detection signal DIo that are input, and outputs the enable signal EN to the gate drive circuit 520. The stop control circuit 540 is configured by a combination of one or more flip-flop circuits.

[0103] When the logic level of the input enable signal EN is a logic level that enables operation, the gate drive circuit 520 outputs gate signals Hgd, Lgd according to the modulation signal Ms, and when the logic level of the input enable signal EN is a logic level that disables operation, the gate drive circuit 520 outputs gate signals Hgd, Lgd at an L level regardless of the modulation signal Ms.

[0104] Here, the stop control circuit 540 of the liquid ejection device 1 of this embodiment will be described as outputting an L-level enable signal EN that disables the operation of the gate drive circuit 520 by detecting three falling edges of the current detection signal DIo after the logical level of the differential base drive signal DdA becomes L level, and outputting an H-level enable signal EN that enables the operation of the gate drive circuit 520 during the period in which the L-level enable signal EN is being outputted by the logical level of the differential base drive signal DdA becoming H level.

[0105] The relationship between the logical level of the enable signal EN output by the stop control circuit 540 and the operation of the gate drive circuit 520 is not limited to this, and for example, when the enable signal EN is at an H level, the operation of the gate drive circuit 520 may be controlled to be disabled, and when the enable signal EN is at an L level, the operation of the gate drive circuit 520 may be controlled to be enabled. Furthermore, the number of times that the stop control circuit 540 detects the falling edge of the current detection signal DIo, which is one of the conditions for outputting an L-level enable signal EN that disables the operation of the gate drive circuit 520, is not limited to three, and may be two or less, or four or more.

[0106] As described above, the differentiation circuit 530, stop control circuit 540, and load current detection circuit 580 of the drive signal output circuit 51 control the driving of the transistors M1 and M2 of the amplifier circuit 550 using the gate signals Hgd and Lgd output from the gate drive circuit 520, based on the current generated by the propagation of the drive signal COM. This control reduces the risk of the voltage value of the drive signal COM changing every period tp and reduces the risk of the switching phase of the transistors M1 and M2 differing every period tp. As a result, it is possible to reduce the risk of waveform distortion that differs every period tp occurring in the waveform of the drive signal COM output by the drive signal output circuit 51 at the timing when the voltage value of the signal waveform of the basic drive signal aA switches from a constant state to a changing state and at the timing when it switches from the changing state to a constant state.

[0107] That is, the differential circuit 530, the stop control circuit 540, and the load current detection circuit 580 included in the drive signal output circuit 51 detect the current generated as the drive signal COM propagates, and outputs a current detection signal DIo corresponding to the change in current generated as the drive signal COM propagates, and the stop control circuit 540 outputs an enable signal EN corresponding to the current detection signal DIo to the gate drive circuit 520.

[0108] A specific example of the operation of the differentiation circuit 530, stop control circuit 540, and load current detection circuit 580 configured as above will be described below, which reduces the risk of waveform distortion that varies for each period tp occurring in the signal waveform of the drive signal COM using the differentiation circuit 530, stop control circuit 540, and load current detection circuit 580. Figure 10 is a diagram for explaining an example of the operation of the drive signal output circuit 51 having the differentiation circuit 530, stop control circuit 540, and load current detection circuit 580.

[0109] 10, before time t11, the stop control circuit 540 outputs an H-level enable signal EN that enables the operation of the gate drive circuit 520. Therefore, the gate drive circuit 520 outputs gate signals Hgd and Lgd that correspond to the modulation signal Ms, and the transistors M1 and M2 are driven in accordance with the corresponding gate signals Hgd and Lgd. In other words, the drive signal output circuit 51 outputs a drive signal COM whose waveform is defined by the basic drive signal dA and whose voltage value changes in accordance with the signal waveform of the basic drive signal aA.

[0110] At this time, the voltage value of the reference drive signal aA, which is the voltage value of the signal waveform of the signal defined by the reference drive signal dA, is decreasing. That is, before time t11, the voltage value of the reference drive signal aA, which is the voltage value of the signal waveform of the signal defined by the reference drive signal dA, changes. Therefore, before time t11, the differentiating circuit 530 outputs an H-level differentiated reference drive signal DdA.

[0111] Furthermore, before time t11, the voltage value of the signal waveform of the reference drive signal aA, which is defined by the reference drive signal dA, drops, and therefore the voltage value of the drive signal COM, which is the amplified signal waveform of the reference drive signal aA, also drops. At this time, the current generated by the propagation of the drive signal COM flows in the negative direction. Therefore, before time t11, the high-pass filter 582 in the load current detection circuit 580 outputs a load current signal DIp with a negative voltage value, and the comparator 584 in the load current detection circuit 580 outputs a current detection signal DIo at an L level.

[0112] That is, before time t11, the stop control circuit 540 receives an H-level differential reference drive signal DdA and an L-level current detection signal DIo. Therefore, the stop control circuit 540 outputs an H-level enable signal EN that enables the operation of the gate drive circuit 520. As a result, the gate drive circuit 520 outputs gate signals Hgd and Lgd that correspond to the modulation signal Ms, and the transistors M1 and M2 are driven in accordance with the corresponding gate signals Hgd and Lgd. Thus, before time t11, the amplifier circuit 550 outputs an amplified modulation signal AMs obtained by amplifying the modulation signal Ms, and the demodulation circuit 560 outputs a drive signal COM obtained by demodulating the amplified modulation signal AMs and amplifying the signal waveform of the reference drive signal aA.

[0113] At a subsequent time t11, the voltage value of the reference drive signal aA, which is the voltage value of the signal waveform of the signal defined by the reference drive signal dA, becomes constant. As a result, the differentiating circuit 530 switches the logic level of the differentiated reference drive signal DdA that it outputs from H level to L level.

[0114] Furthermore, at time t11, the voltage value of the signal waveform defined by basic drive signal dA becomes constant, and so drive signal output circuit 51 operates to maintain a constant voltage value of drive signal COM that it outputs. Therefore, at time t11, the average value of the current generated in conjunction with the propagation of drive signal COM output by drive signal output circuit 51 becomes zero.

[0115] At this time, the stop control circuit 540 outputs an H-level enable signal EN that enables the operation of the gate drive circuit 520. Therefore, the gate drive circuit 520 outputs gate signals Hgd and Lgd that correspond to the modulation signal Ms. Thus, the transistors M1 and M2 are driven in accordance with the corresponding gate signals Hgd and Lgd. This driving of the transistors M1 and M2 causes a ripple current, whose value increases and decreases in synchronization with the voltage change of the amplified modulation signal AMs, to be superimposed on the current generated in conjunction with the propagation of the drive signal COM due to the switching operation of the transistors M1 and M2.

[0116] That is, at time t11, the voltage value of the signal waveform of the signal defined by the base drive signal dA becomes constant, and as the drive signal COM output by the drive signal output circuit 51 propagates, a current whose value increases and decreases around zero is generated.

[0117] At this time, high-pass filter 582 included in load current detection circuit 580 outputs load current signal DIp, the voltage value of which varies around zero in accordance with changes in the amount and direction of the current that occurs with the propagation of drive signal COM output by drive signal output circuit 51, and comparator 584 outputs current detection signal DIo, which goes to H level when the voltage value of load current signal DIp is positive and goes to L level when the voltage value of load current signal DIp is negative. In other words, comparator 584 outputs current detection signal DIo, the logic level of which changes at the timing when the voltage value of load current signal DIp becomes zero and the current value of the current that occurs with the propagation of drive signal COM becomes zero.

[0118] That is, at time t11, the voltage value of the base drive signal aA, which is the voltage value of the signal waveform of the signal defined by the base drive signal dA, becomes constant, so that the differentiation circuit 530 outputs an L-level differentiated base drive signal DdA to the stop control circuit 540, and the load current detection circuit 580 outputs a current detection signal DIo, the logic level of which changes, to the stop control circuit 540.

[0119] The stop control circuit 540 outputs a low-level enable signal EN to disable the operation of the gate drive circuit 520 at time t12, when the third falling edge of the current detection signal DIo, whose logic level changes, occurs after the low-level differential base drive signal DdA is input. That is, the stop control circuit 540 outputs a low-level enable signal EN to disable the operation of the gate drive circuit 520 at the timing when the current accompanying the propagation of the drive signal COM becomes zero after the voltage value of the signal waveform of the signal defined by the base drive signal aA, which is the voltage value of the base drive signal dA, becomes constant. As a result, at time t12, the gate drive circuit 520 outputs low-level gate signals Hgd and Lgd, turning off the transistors M1 and M2. That is, the gate drive circuit 520 turns off the transistors M1 and M2 at the timing when the current accompanying the propagation of the drive signal COM becomes zero. At this time, the voltage value of the immediately preceding drive signal COM is held at the connection point between the transistors M1 and M2 and at the terminal Out to which the drive signal output circuit 51 outputs the drive signal COM by the capacitance component of the piezoelectric element 60 of the ejection head 200. In the following explanation, the voltage value held at the terminal Out, which is the connection point between the transistors M1 and M2 at time t12, is referred to as voltage Vhmux1. Details of voltage Vhmux1 will be described later.

[0120] At a subsequent time t13, when the voltage value of the reference drive signal aA, which is the voltage value of the signal waveform of the signal defined by the reference drive signal dA, begins to rise, the logic level of the differentiated reference drive signal DdA output by the differentiation circuit 530 switches from L level to H level. As a result, the stop control circuit 540 outputs an H level enable signal EN that enables the operation of the gate drive circuit 520. As a result, the gate drive circuit 520 begins outputting gate signals Hgd and Lgd that correspond to the modulation signal Ms, and the transistors M1 and M2 are driven in accordance with the corresponding gate signals Hgd and Lgd.

[0121] Then, at time t13, transistors M1 and M2 begin driving in response to the corresponding gate signals Hgd and Lgd, causing the voltage value of drive signal COM to rise in accordance with the voltage value of the basic drive signal aA, which is the voltage value of the signal waveform defined by basic drive signal dA. At this time, the current generated by the propagation of drive signal COM flows in the positive direction. Therefore, high-pass filter 582 in load current detection circuit 580 outputs load current signal DIp with a positive voltage value, and comparator 584 in load current detection circuit 580 outputs current detection signal DIo at an H level.

[0122] Then, at time t14, the voltage value of the reference drive signal aA, which is the voltage value of the signal waveform of the signal defined by the reference drive signal dA, becomes constant. As a result, the differentiating circuit 530 switches the logic level of the differentiated reference drive signal DdA that it outputs from H level to L level.

[0123] Furthermore, at time t14, the voltage value of the signal waveform defined by basic drive signal dA becomes constant, and so drive signal output circuit 51 operates to maintain a constant voltage value of drive signal COM that it outputs. Therefore, at time t14, the average value of the current generated in conjunction with the propagation of drive signal COM output by drive signal output circuit 51 becomes zero.

[0124] At this time, the stop control circuit 540 outputs an H-level enable signal EN that enables the operation of the gate drive circuit 520. Therefore, the gate drive circuit 520 outputs gate signals Hgd and Lgd that correspond to the modulation signal Ms. Thus, the transistors M1 and M2 are driven in accordance with the corresponding gate signals Hgd and Lgd. This driving of the transistors M1 and M2 causes a ripple current, whose current value increases and decreases in synchronization with the voltage change of the amplified modulation signal AMs, to be superimposed on the current generated in conjunction with the propagation of the drive signal COM due to the switching operation of the transistors M1 and M2.

[0125] That is, at time t14, the voltage value of the signal waveform of the signal defined by the base drive signal dA becomes constant, and as the drive signal COM output by the drive signal output circuit 51 propagates, a current whose value increases and decreases around zero is generated.

[0126] At this time, high-pass filter 582 included in load current detection circuit 580 outputs load current signal DIp, the voltage value of which varies around zero in accordance with changes in the amount and direction of the current that occurs with the propagation of drive signal COM output by drive signal output circuit 51, and comparator 584 outputs current detection signal DIo, which goes to H level when the voltage value of load current signal DIp is positive and goes to L level when the voltage value of load current signal DIp is negative. In other words, comparator 584 outputs current detection signal DIo, the logic level of which changes at the timing when the voltage value of load current signal DIp becomes zero and the current value of the current that occurs with the propagation of drive signal COM becomes zero.

[0127] That is, at time t14, the voltage value of the base drive signal aA, which is the voltage value of the signal waveform of the signal defined by the base drive signal dA, becomes constant, so that the differentiation circuit 530 outputs an L-level differentiated base drive signal DdA to the stop control circuit 540, and the load current detection circuit 580 outputs a current detection signal DIo, the logic level of which changes, to the stop control circuit 540.

[0128] The stop control circuit 540 outputs a low-level enable signal EN to disable the operation of the gate drive circuit 520 at time t15, when the third falling edge of the current detection signal DIo, whose logic level changes, occurs after the low-level differential base drive signal DdA is input. That is, the stop control circuit 540 outputs a low-level enable signal EN to disable the operation of the gate drive circuit 520 at the timing when the current accompanying the propagation of the drive signal COM becomes zero after the voltage value of the base drive signal aA, which is the voltage value of the signal waveform defined by the base drive signal dA, becomes constant. As a result, at time t15, the gate drive circuit 520 outputs low-level gate signals Hgd and Lgd, turning off the transistors M1 and M2. That is, the gate drive circuit 520 turns off the transistors M1 and M2 at the timing when the current accompanying the propagation of the drive signal COM becomes zero. At this time, the voltage value of the immediately preceding drive signal COM is held at the connection point between the transistors M1 and M2 and at the terminal Out to which the drive signal output circuit 51 outputs the drive signal COM by the capacitance component of the piezoelectric element 60 of the ejection head 200. In the following explanation, the voltage value held at the terminal Out, which is the connection point between the transistors M1 and M2 at time t15, is referred to as voltage Vhmux2. Details of voltage Vhmux2 will be described later.

[0129] At a subsequent time t16, when the voltage value of the reference drive signal aA, which is the voltage value of the signal waveform of the signal defined by the reference drive signal dA, begins to decrease, the logic level of the differentiated reference drive signal DdA output by the differentiation circuit 530 switches from L level to H level. As a result, the stop control circuit 540 outputs an H level enable signal EN that enables the operation of the gate drive circuit 520. As a result, the gate drive circuit 520 begins outputting gate signals Hgd and Lgd that correspond to the modulation signal Ms, and the transistors M1 and M2 are driven in accordance with the corresponding gate signals Hgd and Lgd.

[0130] Then, at time t16, transistors M1 and M2 begin driving in response to the corresponding gate signals Hgd and Lgd, causing the voltage value of drive signal COM to decrease in accordance with the voltage value of the signal waveform of the basic drive signal aA, which is determined by basic drive signal dA. At this time, the current generated by the propagation of drive signal COM flows in the negative direction. Therefore, the high-pass filter 582 in the load current detection circuit 580 outputs a load current signal DIp with a negative voltage value, and the comparator 584 in the load current detection circuit 580 outputs a current detection signal DIo at an L level.

[0131] Then, at time t17, the voltage value of the reference drive signal aA, which is the voltage value of the signal waveform of the signal defined by the reference drive signal dA, becomes constant. As a result, the differentiating circuit 530 switches the logic level of the differentiated reference drive signal DdA that it outputs from H level to L level. This time t17 corresponds to the above-mentioned time t11. In other words, the drive signal output circuit 51, which has the differentiating circuit 530, stop control circuit 540, and load current detection circuit 580, repeatedly executes the above-mentioned operation from time t11 to time t16 for each period tp.

[0132] Here, the following describes voltage Vhmux1, which is the voltage value held at the connection point between transistors M1 and M2 and at terminal Out when transistors M1 and M2 are turned off at time t12, and which is the voltage value of the drive signal COM output from terminal Out of drive signal output circuit 51 when transistors M1 and M2 are turned off at time t12; and voltage Vhmux2, which is the voltage value held at the connection point between transistors M1 and M2 and at terminal Out when transistors M1 and M2 are turned off at time t15, and which is the voltage value of the drive signal COM output from terminal Out of drive signal output circuit 51 when transistors M1 and M2 are turned off at time t15. Note that in the following description, voltages Vhmux1 and Vhmux2 may be referred to simply as voltage Vhmux without distinction.

[0133] 11 is a diagram illustrating the voltage Vhmux. As described above, during a period in which the voltage value of the signal waveform of the signal defined by the reference drive signal aA is constant, the current value of the current generated in conjunction with the propagation of the drive signal COM varies around zero. In other words, during a period in which the voltage value of the signal waveform of the signal defined by the reference drive signal dA is constant, a ripple current whose current value varies around zero is superimposed on the current generated in conjunction with the propagation of the drive signal COM.

[0134] Just before the voltage value of the amplified modulation signal AMs reaches the voltage value of the voltage signal VHV, during the period when the voltage value of the amplified modulation signal AMs is at ground potential, the ripple current superimposed on the current generated as the drive signal COM propagates flows in the negative direction, and the amount of ripple current in this direction increases. Therefore, the voltage value of the load current signal DIp output by the high-pass filter 582 increases toward the negative direction. At this time, because the voltage value of the load current signal DIp is negative, the comparator 584 outputs the current detection signal DIo at an L level. At this time, because the ripple current superimposed on the current generated as the drive signal COM propagates flows in the negative direction, the voltage value of the ripple voltage superimposed on the drive signal COM decreases.

[0135] Subsequently, transistor M1 is turned on and transistor M2 is turned off, causing the voltage value of the amplified modulation signal AMs to change from ground potential to the voltage value of the voltage signal VHV. As a result, the ripple current superimposed on the current generated by the propagation of the drive signal COM continues to flow in the negative direction, but the amount of ripple current in that direction decreases. Therefore, the voltage value of the load current signal DIp output by the high-pass filter 582 decreases toward zero. At this time, because the voltage value of the load current signal DIp is negative, the comparator 584 continues to output the current detection signal DIo at an L level. At this time, because the ripple current superimposed on the current generated by the propagation of the drive signal COM flows in the negative direction, the voltage value of the ripple voltage superimposed on the drive signal COM decreases.

[0136] Then, after the amount of ripple current superimposed on the current generated by the propagation of the drive signal COM reaches zero, the flow direction reverses from negative to positive, and then the amount of current increases in the positive direction. Therefore, the voltage value of the load current signal DIp output by the high-pass filter 582 increases toward a positive direction, passing through zero. At this time, because the voltage value of the load current signal DIp reverses from negative to positive, the comparator 584 switches the logic level of the current detection signal DIo from L level to H level. That is, at the timing when the voltage value of the load current signal DIp reaches zero, the logic level of the current detection signal DIo output by the comparator 584 switches from L level to H level. Then, at the timing when the logic level of the current detection signal DIo switches from L level to H level, the flow direction of the ripple current superimposed on the current generated by the propagation of the drive signal COM switches from negative to positive, and the voltage value of the ripple voltage superimposed on the drive signal COM changes from decreasing to increasing.

[0137] That is, the voltage value of the ripple voltage superimposed on the drive signal COM becomes minimum when the direction of the ripple current superimposed on the current generated by the propagation of the drive signal COM switches from negative to positive and the amount of the ripple current superimposed on the current generated by the propagation of the drive signal COM becomes zero. In other words, the voltage value of the ripple voltage superimposed on the drive signal COM becomes minimum when the logic level of the current detection signal DIo switches from L level to H level.

[0138] Subsequently, transistor M1 is turned off and transistor M2 is turned on, causing the voltage value of the amplified modulation signal AMs to change from the voltage value of the voltage signal VHV to ground potential. As a result, the ripple current superimposed on the current generated by the propagation of the drive signal COM continues to flow in the positive direction, but the amount of ripple current in that direction decreases. Therefore, the voltage value of the load current signal DIp output by the high-pass filter 582 decreases toward zero. At this time, because the voltage value of the load current signal DIp is positive, the comparator 584 continues to output the current detection signal DIo at an H level. At this time, because the ripple current superimposed on the current generated by the propagation of the drive signal COM flows in the positive direction, the voltage value of the ripple voltage superimposed on the drive signal COM increases.

[0139] Then, after the amount of ripple current superimposed on the current generated by the propagation of the drive signal COM becomes zero, the flow direction reverses from positive to negative, and then the amount of current increases in the negative direction. Therefore, the voltage value of the load current signal DIp output by the high-pass filter 582 increases toward negative, passing through zero. At this time, because the voltage value of the load current signal DIp changes from positive to negative, the comparator 584 switches the logic level of the current detection signal DIo from H level to L level. That is, at the timing when the voltage value of the load current signal DIp becomes zero, the logic level of the current detection signal DIo output by the comparator 584 switches from H level to L level. Then, at the timing when the logic level of the current detection signal DIo switches from H level to L level, the flow direction of the ripple current superimposed on the current generated by the propagation of the drive signal COM switches from positive to negative, and the voltage value of the ripple voltage superimposed on the drive signal COM changes from increasing to decreasing.

[0140] That is, the voltage value of the ripple voltage superimposed on the drive signal COM reaches a maximum value when the direction of the ripple current superimposed on the current generated by the propagation of the drive signal COM switches from positive to negative and the amount of the ripple current superimposed on the current generated by the propagation of the drive signal COM becomes zero. In other words, the voltage value of the ripple voltage superimposed on the drive signal COM reaches a maximum value when the logic level of the current detection signal DIo switches from H level to L level.

[0141] As described above, the voltage value of the ripple voltage superimposed on the drive signal COM becomes a maximum or minimum value when the amount of ripple current superimposed on the current generated due to the propagation of the drive signal COM becomes zero. Specifically, the voltage value of the ripple voltage superimposed on the drive signal COM becomes a minimum value when the amount of current becomes zero as the direction of the ripple current superimposed on the current generated due to the propagation of the drive signal COM switches from negative to positive, and the voltage value of the ripple voltage superimposed on the drive signal COM becomes a maximum value when the amount of current becomes zero as the direction of the ripple current superimposed on the current generated due to the propagation of the drive signal COM switches from positive to negative.

[0142] In the liquid ejection device 1 of this embodiment, voltage Vhmux1 is maintained at the connection point between transistors M1 and M2 and at terminal Out at time t12 when the logic level of current detection signal DIo switches from H level to L level. The voltage value of voltage Vhmux1 is the maximum value of the ripple voltage superimposed on drive signal COM, regardless of the switching phase of transistors M1 and M2. Therefore, at time t12 in each cycle tp, voltage Vhmux1 of approximately the same voltage value is maintained at the connection point between transistors M1 and M2 and at terminal Out, regardless of the switching phase of transistors M1 and M2.

[0143] Then, at time t13 after time t12, when the voltage value of the signal waveform of the signal defined by the basic drive signal dA, which is the voltage value of the basic drive signal aA, begins to rise, the gate drive circuit 520 begins outputting gate signals Hgd and Lgd according to the modulation signal Ms. At this time, a voltage Vhmux1, which has a substantially equal voltage value per cycle tp, is maintained at the connection point between transistors M1 and M2 and at the terminal Out. That is, at time t13 per cycle tp, the gate drive circuit 520 controls the driving of transistors M1 and M2 using the voltage Vhmux1, which has a substantially equal voltage value, as the starting voltage value. This reduces the risk of different waveform distortions occurring in the signal waveform of the drive signal COM at time t13 per cycle tp.

[0144] Furthermore, because the gate drive circuit 520 controls the driving of the transistors M1 and M2 at time t13 in each cycle tp using a voltage Vhmux1 of approximately the same voltage value as the starting voltage value, the transistors M1 and M2 are driven with approximately the same switching phase, cycle, and duty during the period from time t13 to time t14 in each cycle tp when the voltage value of the drive signal COM changes. As a result, the voltage value of the drive signal COM at time t14, when the voltage value of the signal waveform defined by the basic drive signal aA, which is the voltage value of the basic drive signal dA, switches from a varying state to a constant state, also becomes approximately the same value in each cycle tp, reducing the risk of different waveform distortions occurring in the signal waveform of the drive signal COM at time t14 in each cycle tp.

[0145] Furthermore, at time t15 when the logic level of the current detection signal DIo switches from H level to L level, voltage Vhmux2 is maintained at the connection point between transistors M1 and M2 and at terminal Out. The voltage value of voltage Vhmux2 is the maximum value of the ripple voltage superimposed on drive signal COM, regardless of the switching phase of transistors M1 and M2. Therefore, at time t15 in each period tp, voltage Vhmux2 of approximately the same voltage value is maintained at the connection point between transistors M1 and M2 and at terminal Out, regardless of the switching phase of transistors M1 and M2.

[0146] Then, at time t16, after time t15, when the voltage value of the signal waveform of the signal defined by the basic drive signal dA, which is the voltage value of the basic drive signal aA, begins to decrease, the gate drive circuit 520 begins outputting gate signals Hgd and Lgd according to the modulation signal Ms. At this time, a voltage Vhmux2, which has a substantially equal voltage value, is maintained at the connection point between the transistors M1 and M2 and the terminal Out for each cycle tp. That is, at time t16 for each cycle tp, the gate drive circuit 520 controls the driving of the transistors M1 and M2 using the voltage Vhmux2, which has a substantially equal voltage value, as the starting voltage value. This reduces the risk of different waveform distortions occurring in the signal waveform of the drive signal COM at time t16 for each cycle tp.

[0147] Furthermore, because the gate drive circuit 520 controls the driving of the transistors M1 and M2 at time t16 in each cycle tp using voltage Vhmux2, which has a substantially equivalent voltage value as the starting voltage value, the transistors M1 and M2 are driven with substantially equivalent switching phases, cycles, and duties during the period from time t16 to time t17 in each cycle tp when the voltage value of the drive signal COM changes. As a result, the voltage value of the drive signal COM at time t17, when the voltage value of the signal waveform defined by the basic drive signal aA, which is the voltage value of the basic drive signal dA, switches from a varying state to a constant state, also becomes substantially equivalent for each cycle tp, reducing the risk of different waveform distortions occurring in the signal waveform of the drive signal COM at time t17 in each cycle tp.

[0148] As described above, in the liquid ejection device 1 of this embodiment, at time t12, a voltage Vhmux1 that is approximately the same voltage value every cycle tp is held at the connection point between transistors M1 and M2 and at terminal Out. Thereafter, at time t13, which is determined based on the reference drive signal dA output by the control circuit 100, the gate drive circuit 520 controls the driving of transistors M1 and M2 starting from the held voltage Vhmux1. This controls the phases of transistors M1 and M2 to be approximately equal from time t12 onwards. Similarly, in the liquid ejection device 1 of this embodiment, at time t15, a voltage Vhmux2 that is approximately the same voltage value every cycle tp is held at the connection point between transistors M1 and M2 and at terminal Out. Thereafter, at time t16, which is determined based on the reference drive signal dA output by the control circuit 100, the gate drive circuit 520 controls the driving of transistors M1 and M2 starting from the held voltage Vhmux2. This controls the phases of the transistors M1 and M2 to be approximately equal after time t16, thereby reducing the risk of different waveform distortions occurring in the drive signal COM for each cycle tp.

[0149] In this case, the drive signal output circuit 51 only needs to perform control so that the phases of the transistors M1 and M2 are approximately equal at least once per cycle tp. Therefore, in the cycle tp, at least one of the following operations needs to be performed: an operation to hold a voltage Vhmux1 at the junction between the transistors M1 and M2 and at the terminal Out at time t12; and an operation to hold a voltage Vhmux2 at the junction between the transistors M1 and M2 and at the terminal Out at time t15.

[0150] As described above, in the drive signal output circuit 51 of this embodiment, the gate drive circuit 520 outputs a gate signal Hgd that controls transistor M1 to be non-conductive and a gate signal Lgd that controls transistor M2 to be non-conductive in response to the enable signal EN based on the current detection signal DIo. Specifically, during a period in which the voltage value of the basic drive signal aA is constant and the voltage value of the drive signal COM is controlled to be constant, the gate drive circuit 520 outputs a gate signal Hgd that controls transistor M1 to be non-conductive and a gate signal Lgd that controls transistor M2 to be non-conductive at the timing when the direction of flow of the current generated by the propagation of the drive signal COM switches from positive to negative.

[0151] Here, the drive signal output circuit 51 corresponds to a capacitive load drive circuit, the piezoelectric element 60 is an example of a capacitive load and a first capacitive load, the discharge unit 600 including the piezoelectric element 60 is an example of a first discharge unit, and the selection circuit 230 is an example of a first switch circuit. The modulation circuit 510 included in the drive signal output circuit 51 is an example of a modulation circuit, the gate drive circuit 520 is an example of a transistor drive circuit, the amplifier circuit 550 is an example of an amplifier circuit, the demodulation circuit 560 is an example of a demodulation circuit, the feedback circuits 570 and 572 are an example of a feedback circuit, and the load current detection circuit 580, or the differentiation circuit 530, the stop control circuit 540, and the load current detection circuit 580 are examples of current detection circuits. The transistor M1 included in the amplifier circuit 550 is an example of a first transistor, the transistor M2 is an example of a second transistor, and the pair of the transistors M1 and M2 is an example of a first transistor pair. Furthermore, the high-pass filter 582 included in the load current detection circuit 580 is an example of a high-pass filter circuit. Furthermore, the drive signals COM and VOUT are examples of drive signals, the basic drive signals aA and dA are examples of basic drive signals, the gate signal Hgd is an example of a first drive control signal, the gate signal Lgd is an example of a second drive control signal, the current generated in conjunction with the propagation of the drive signal COM is an example of a drive current, and the current detection signal DIo and the enable signal EN based on the current detection signal DIo are examples of current detection signals.

[0152] 1.4 Effects As described above, in the liquid ejection device 1 and drive signal output circuit 51 of the first embodiment, the differentiation circuit 530, the stop control circuit 540, and the load current detection circuit 580 generate an enable signal EN based on the current detection signal DIo based on the amount of current generated by the propagation of the drive signal COM, and output the enable signal EN to the gate drive circuit 520. The gate drive circuit 520 outputs a gate signal Hgd that controls transistor M1 to be non-conductive and a gate signal Lgd that controls transistor M2 to be non-conductive in response to the enable signal EN based on the input current detection signal DIo. At this time, the voltage value at the connection point between transistors M1 and M2, which is the voltage value at terminal Out, is held constant by the capacitance component of the piezoelectric element 60. As a result, when transistors M1 and M2 resume driving, transistors M1 and M2 can start switching based on the voltage value held at terminal Out, which is the voltage held at the connection point between transistors M1 and M2. As a result, the phases of the transistors M1 and M2 after driving resumes become approximately equal for each period tp, and the phase of the ripple voltage superimposed on the drive signal COM can be controlled to be approximately equal for each period tp. As a result, the risk of different waveform distortions occurring in the signal waveform of the drive signal COM for each period tp is reduced, and the waveform accuracy of the drive signal VOUT corresponding to the drive signal COM supplied to the piezoelectric element 60 is improved.

[0153] In particular, in the liquid ejection device 1 of the first embodiment, the differentiation circuit 530, the stop control circuit 540, and the load current detection circuit 580 output an enable signal EN to the gate drive circuit 520 at the timing when the amount of current generated by the propagation of the drive signal COM becomes zero. The enable signal EN causes the gate drive circuit 520 to output a gate signal Hgd that controls the transistor M1 to be non-conductive and a gate signal Lgd that controls the transistor M2 to be non-conductive. This causes the energy stored in the coil L1 of the demodulation circuit 560 to become zero at the timing when the transistors M1 and M2 are turned off. As a result, after the transistors M1 and M2 are turned off, the risk of the energy stored in the coil L1 fluctuating at the voltage value at the connection point of the transistors M1 and M2 is reduced. In other words, the accuracy of the voltage value held at the connection point of the transistors M1 and M2 is improved during the period when the transistors M1 and M2 are turned off. Therefore, after driving resumes, the phases of the transistors M1 and M2 become more equal for each period tp, and the phase of the ripple voltage superimposed on the drive signal COM can be controlled to become more equal for each period tp. As a result, the risk of different waveform distortions occurring in the signal waveform of the drive signal COM for each period tp is further reduced, and the waveform accuracy of the drive signal VOUT corresponding to the drive signal COM supplied to the piezoelectric element 60 is further improved.

[0154] 1.5 Variations 1.5.1 Variation 1 In the liquid ejection device 1 and the drive signal output circuit 51 of the present embodiment described above, the stop control circuit 540 outputs an enable signal EN of L level that disables the operation of the gate drive circuit 520 by detecting three falling edges of the current detection signal DIo after the logical level of the differential base drive signal DdA becomes L level, and outputs an enable signal EN of H level that enables the operation of the gate drive circuit 520 by the logical level of the differential base drive signal DdA becoming H level during the period in which the enable signal EN of L level is being output. However, in the differential base drive signal of the modified example shown in FIG. As an example of the operation of the drive signal output circuit 51 having the circuit 530, the stop control circuit 540, and the load current detection circuit 580, the stop control circuit 540 may output an enable signal EN of L level that disables the operation of the gate drive circuit 520 by detecting three rising edges of the current detection signal DIo after the logical level of the differential base drive signal DdA becomes L level, and during the period in which the enable signal EN of L level is being output, the logical level of the differential base drive signal DdA becomes H level, thereby outputting an enable signal EN of H level that enables the operation of the gate drive circuit 520.

[0155] 11, the voltage value of the ripple voltage superimposed on the drive signal COM becomes minimal at the timing when the direction of the ripple current superimposed on the current generated as the drive signal COM propagates switches from the direction from the ejection head 200 toward the drive signal output circuit 51 to the direction from the drive signal output circuit 51 toward the ejection head 200, and the amount of the ripple current superimposed on the current generated as the drive signal COM propagates becomes zero. In other words, the voltage value of the ripple voltage superimposed on the drive signal COM becomes minimal at the timing when the logical level of the current detection signal DIo output by the comparator 584 switches from L level to H level.

[0156] In the modified liquid ejection device 1 and drive signal output circuit 51, at time t12a when the logical level of the current detection signal DIo output by the comparator 584 switches from L level to H level, the transistors M1 and M2 are controlled to be off, and the minimum value of the ripple voltage superimposed on the drive signal COM is held as voltage Vhmin1 at the connection point between the transistors M1 and M2, and at time t15a when the logical level of the current detection signal DIo output by the comparator 584 switches from L level to H level, the transistors M1 and M2 are controlled to be off, and the minimum value of the ripple voltage superimposed on the drive signal COM is held as voltage Vhmin2 at the connection point between the transistors M1 and M2. Therefore, at time t12a, a voltage Vhmin1 that is approximately the same voltage value for each period tp is maintained at the connection point between transistor M1 and transistor M2, and at time t15a, a voltage Vhmin2 that is approximately the same voltage value for each period tp is maintained.

[0157] Even in this case, at times t13 and t16, which are determined based on the basic drive signal dA output by the control circuit 100, the gate drive circuit 520 can control the driving of the transistors M1 and M2 starting from voltages Vhmin1 and Vhmin2, which have approximately equal voltage values ​​per cycle tp. Therefore, the phases of the transistors M1 and M2 from time t13 onward and from time t16 onward are controlled to be approximately equal per cycle tp. As a result, similar to the first embodiment described above, the risk of different waveform distortions occurring in the drive signal COM per cycle tp is reduced.

[0158] That is, the gate drive circuit 520 may output a gate signal Hgd that controls the transistor M1 to be non-conductive and a gate signal Lgd that controls the transistor M2 to be non-conductive at the timing when the direction of the current flowing due to the propagation of the drive signal COM switches from negative to positive during a period in which the voltage value of the basic drive signal aA is constant and the voltage value of the drive signal COM is controlled to be constant. Even in this case, the same effects can be achieved.

[0159] 1.5.2 Variation 2 In the liquid ejection device 1 and drive signal output circuit 51 of this embodiment described above, the high-pass filter 582 of the load current detection circuit 580 is used to detect the current generated in association with the propagation of the drive signal COM, but the configuration for detecting the current generated in association with the propagation of the drive signal COM is not limited to the configuration using the high-pass filter 582, and a different configuration may be used as long as it can detect the amount and direction of the current generated in association with the propagation of the drive signal COM.

[0160] Fig. 13 is a diagram showing the configuration of a load current detection circuit 580a as a modified example of the load current detection circuit 580. As shown in Fig. 13, the load current detection circuit 580a includes a resistor R7a and a comparator 584a.

[0161] One end of the resistor R7a is electrically connected to the other end of the capacitor C1 of the demodulation circuit 560. The other end of the resistor R7a is supplied with ground potential. That is, the capacitor C1 and resistor R7a of the demodulation circuit 560 form a high-pass filter. The output of the high-pass filter formed by the capacitor C1 and resistor R7a is input to the positive input terminal of the comparator 584a. The negative input terminal of the comparator 584a is supplied with ground potential. The signal output by the comparator 584a is input to the stop control circuit 540.

[0162] That is, the demodulation circuit 560 includes a coil L1 and a capacitor C1, the load current detection circuit 580a includes a resistor R7a, one end of the coil L1 is input with the amplified modulation signal AMs, the other end of the coil L1 is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to one end of the resistor R7a, the demodulation circuit 560 outputs a signal at the connection point electrically connecting the other end of the coil L1 and one end of the capacitor C1 as the drive signal COM, and the load current detection circuit 580a may output a current detection signal DIo according to the signal at one end of the resistor R7a.

[0163] The load current detection circuit 580a configured as above can also achieve the same effects as the above-described embodiment. In this case, the coil L1 is an example of an inductor element, the capacitor C1 is an example of a capacitor element, and the resistor R7a is an example of a resistive element.

[0164] Fig. 14 is a diagram showing the configuration of a load current detection circuit 580b as another modified example of the load current detection circuit 580. As shown in Fig. 14, the load current detection circuit 580b includes a resistor R8b, an amplifier circuit 586b, and a comparator 584b.

[0165] One end of the resistor R8b is electrically connected to the other end of the coil L1 and one end of the capacitor C1 of the demodulation circuit 560. The other end of the resistor R8b is connected to the terminal Out. The positive input terminal of the amplifier circuit 586b is connected to one end of the resistor R8b, and the negative input terminal of the amplifier circuit 586b is connected to the other end of the resistor R8b. That is, the amplifier circuit 586b amplifies the voltage across the resistor R8b, which is the voltage generated by the current value generated by the propagation of the drive signal COM and the resistance value of the resistor R8b. The output of the amplifier circuit 586b is input to the positive input terminal of the comparator 584b. The negative input terminal of the comparator 584b is supplied with ground potential. The signal output by the comparator 584b is input to the stop control circuit 540.

[0166] That is, the demodulation circuit 560 includes a coil L1 and a capacitor C1, the load current detection circuit 580b includes an amplifier circuit 586b and a resistor R8b, one end of the coil L1 receives an amplified modulation signal AMs, the other end of the coil L1 is electrically connected to one end of the capacitor C1 and one end of the resistor R8b, the other end of the capacitor C1 is supplied with ground potential, the demodulation circuit 560 generates a signal at the connection point where the other end of the coil L1 and one end of the capacitor C1 are electrically connected as a drive signal COM and outputs it via the resistor R8b, the amplifier circuit 586b differentially amplifies the potential difference across the resistor R8b, and the load current detection circuit 580a may output a current detection signal DIo corresponding to the signal output by the amplifier circuit 586b.

[0167] The load current detection circuit 580b configured as above also provides the same effects as those of the above-described embodiment. In this case, the coil L1 is an example of an inductor element, the capacitor C1 is an example of a capacitor element, and the resistor R8b is an example of a resistive element.

[0168] Fig. 15 is a diagram showing the configuration of a load current detection circuit 580c as another modified example of the load current detection circuit 580. As shown in Fig. 15, the load current detection circuit 580c includes a magnetic sensor 588c and a comparator 584c.

[0169] The magnetic sensor 588c detects the magnitude of the magnetic field generated in the propagation path along which the drive signal COM propagates, thereby detecting the amount and direction of the current flowing through the propagation path, i.e., the amount of current generated by the propagation of the drive signal COM, and outputs a signal corresponding to the detection result. The signal output by the magnetic sensor 588c is input to the positive input terminal of the comparator 584b. A ground potential is supplied to the negative input terminal of the comparator 584b. The signal output by the comparator 584b is then input to the stop control circuit 540.

[0170] That is, the load current detection circuit 580c may include a magnetic sensor 588c that detects the magnetic field strength generated by the current generated by the propagation of the drive signal COM, and may output a current detection signal DIo according to the output of the magnetic sensor 588c.

[0171] The load current detection circuit 580c configured as above also provides the same effects as those of the above-described embodiment. In this case, the magnetic sensor 588c is an example of a magnetic sensor circuit.

[0172] 2. Second embodiment Next, the configuration and operation of the liquid ejection device 1 of the second embodiment will be described.

[0173] As described above, in the liquid ejection device 1 of the first embodiment, the gate drive circuit 520 controls both transistors M1 and M2 to turn off at the timing when the voltage value of the drive signal COM detected based on the amount of current generated as the drive signal COM propagates reaches a predetermined value, the current generated as the drive signal COM propagates becomes zero, and therefore the ripple voltage superimposed on the drive signal COM reaches a maximum value, thereby reducing the risk of different waveform distortions occurring in the signal waveform of the drive signal COM for each period tp.

[0174] In contrast, the liquid ejection device 1 of the second embodiment differs from the liquid ejection device 1 of the first embodiment in that the gate drive circuit 520 controls a predetermined number of selection circuits 230 of the multiple selection circuits 230 possessed by the ejection head 200 to be conductive before controlling the transistors M1 and M2 to be turned off.

[0175] In the liquid ejection device 1 of the second embodiment, the gate drive circuit 520 can control the number of piezoelectric elements 60 to which the drive signal VOUT corresponding to the drive signal COM is supplied to a predetermined number at the timing when the transistors M1 and M2 are turned off, and therefore it is possible to control the load capacitance to which the drive signal VOUT corresponding to the drive signal COM is supplied to a constant value at that timing. This makes it possible to control the voltage amplitude of the ripple voltage superimposed on the drive signal COM to be approximately constant at the timing when the gate drive circuit 520 controls the transistors M1 and M2 to be turned off, further reducing the risk of different waveform distortions occurring in the signal waveform of the drive signal COM for each period tp.

[0176] In describing the liquid ejection device 1 of the second embodiment, the same components as those of the liquid ejection device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted or simplified.

[0177] Fig. 16 is a diagram showing the functional configuration of a liquid ejection device 1 of the second embodiment. As shown in Fig. 16, in the liquid ejection device 1 of the second embodiment, the control circuit 100 generates a detection trigger signal TRG as a control signal Ctrl-H in addition to a clock signal SCK, a print data signal SI, a latch signal LAT, and a basic drive signal dA. The control circuit 100 then outputs the generated detection trigger signal TRG to the drive circuit 50 and the selection control circuit 210.

[0178] 17 is a diagram showing an example of the signal waveform of the drive signal COM in the second embodiment. As shown in FIG. 17, the detection trigger signal TRG divides the period tp defined by the latch signal LAT into a period tp1 from the rising edge of the latch signal LAT to the rising edge of the detection trigger signal TRG, and a period tp2 from the rising edge of the detection trigger signal TRG to the rising edge of the latch signal LAT. At this time, the control circuit 100 outputs the detection trigger signal TRG so that the entire trapezoidal waveform Adp included in the drive signal COM is positioned in period tp1, and the voltage value of the drive signal COM is constant at voltage vb in period tp2. That is, the detection trigger signal TRG divides the period tp into a period tp1 during which the voltage value of the drive signal COM changes, and a period tp2 during which the voltage value of the drive signal COM is constant.

[0179] The selection control circuit 210 of the second embodiment generates a selection signal S that switches whether or not to output the drive signal COM as the drive signal VOUT during each of the periods tp1 and tp2, based on the clock signal SCK, the print data signal SI, the latch signal LAT, and the detection trigger signal TRG, and outputs the selection signal S to the corresponding selection circuit 230. Based on the input selection signal S, the multiple selection circuits 230 switch whether or not to output the drive signal COM as the drive signal VOUT during each of the periods tp1 and tp2.

[0180] FIG. 18 is a diagram showing an example of the configuration of the selection control circuit 210 and the plurality of selection circuits 230 according to the second embodiment.

[0181] In addition to the clock signal SCK, the print data signal SI, and the latch signal LAT, a detection trigger signal TRG is also input to the selection control circuit 210. The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. In the second embodiment, the print data signal SI is a signal of at least 2m bits, serially including 2-bit print data [SIH, SIL] corresponding to each of the m ejection units 600. The print data [SIH, SIL] included in the print data signal SI is transferred by the shift register 212 in synchronization with the clock signal SCK. Then, the print data [SIH, SIL] included in the print data signal SI is held in the m shift registers 212 corresponding to the m ejection units 600, and the clock signal SCK stops.

[0182] Each of the m latch circuits 214 simultaneously latches the print data [SIH, SIL] held in the corresponding shift register 212 at the rising edge of the latch signal LAT. The print data [SIH, SIL] latched by the latch circuit 214 is then input to the corresponding decoder 216. FIG. 19 is a diagram showing an example of the decoded content in the decoder 216 of the second embodiment. During each of periods tp1 and tp2, the decoder 216 level-shifts the signal whose logic level is defined by the input print data [SIH, SIL] to a high-amplitude logic, thereby generating and outputting the selection signal S.

[0183] Specifically, when print data [SIH,SIL]=[1,0] is input to the decoder 216, the decoder 216 outputs a high-level selection signal S during period tp1, and outputs a low-level selection signal S during period tp2. This causes the transmission gate 234 of the corresponding selection circuit 230 to be controlled to be conductive during period tp1, and non-conductive during period tp2. In other words, the corresponding selection circuit 230 outputs the trapezoidal waveform Adp as the drive signal VOUT during period tp1, and does not output the voltage vb as the drive signal VOUT during period tp2.

[0184] Here, during period tp2 when the transmission gate 234 is controlled to be non-conductive, one end of the piezoelectric element 60 included in the corresponding ejection unit 600 is held at voltage vb, which is the voltage value immediately before the transmission gate 234 was controlled to be non-conductive, due to the capacitive component of that piezoelectric element 60. In other words, when print data [SIH, SIL]=[1, 0] is input to the decoder 216, a drive signal VOUT consisting of a succession of trapezoidal waveform Adp and voltage vb is supplied to one end of the corresponding piezoelectric element 60 during period tp. As a result, ink is ejected from the corresponding ejection unit 600 during period tp, and dots are formed on the medium P.

[0185] Furthermore, when print data [SIH,SIL]=[1,1] is input to the decoder 216, the decoder 216 outputs a high-level selection signal S during period tp1, and outputs a high-level selection signal S during period tp2. As a result, the transmission gate 234 of the corresponding selection circuit 230 is controlled to be conductive during period tp1, and is controlled to be conductive during period tp2. That is, the corresponding selection circuit 230 outputs a trapezoidal waveform Adp as the drive signal VOUT during period tp1, and outputs a voltage vb as the drive signal VOUT during period tp2.

[0186] Therefore, when print data [SIH,SIL]=[1,1] is input to the decoder 216, a drive signal VOUT consisting of a series of trapezoidal waveforms Adp and voltage vb in a period tp is supplied to one end of the corresponding piezoelectric element 60. As a result, ink is ejected from the corresponding ejection section 600 in the period tp, and dots are formed on the medium P.

[0187] Furthermore, when print data [SIH,SIL]=[0,0] is input to the decoder 216, the decoder 216 outputs a low-level selection signal S during period tp1, and outputs a low-level selection signal S during period tp2. As a result, the transmission gate 234 of the corresponding selection circuit 230 is controlled to be non-conductive during period tp1, and is controlled to be non-conductive during period tp2. In other words, the corresponding selection circuit 230 does not output the trapezoidal waveform Adp as the drive signal VOUT during period tp1, and does not output the voltage vb as the drive signal VOUT during period tp2.

[0188] During periods tp1 and tp2 when the transmission gate 234 is controlled to be non-conductive, one end of the piezoelectric element 60 included in the corresponding ejection unit 600 is held at voltage vb, which is the voltage value immediately before the transmission gate 234 was controlled to be non-conductive, due to the capacitance component of the piezoelectric element 60. In other words, when print data [SIH, SIL]=[0,0] is input to the decoder 216, voltage vb is supplied as drive signal VOUT to one end of the corresponding piezoelectric element 60 during period tp. As a result, no ink is ejected from the corresponding ejection unit 600 during period tp, and no dots are formed on the medium P.

[0189] Furthermore, when print data [SIH,SIL]=[0,1] is input to the decoder 216, the decoder 216 outputs a low-level selection signal S during period tp1, and outputs a high-level selection signal S during period tp2. This causes the transmission gate 234 of the corresponding selection circuit 230 to be non-conductive during period tp1, and to be conductive during period tp2. In other words, the corresponding selection circuit 230 does not output the trapezoidal waveform Adp as the drive signal VOUT during period tp1, and outputs the voltage vb as the drive signal VOUT during period tp2.

[0190] Here, during period tp1 when the transmission gate 234 is controlled to be non-conductive, one end of the piezoelectric element 60 included in the corresponding ejection unit 600 is held at voltage vb, which is the voltage value immediately before the transmission gate 234 was controlled to be non-conductive, due to the capacitive component of that piezoelectric element 60. In other words, when print data [SIH, SIL]=[0, 1] is input to the decoder 216, voltage vb is supplied as drive signal VOUT to the corresponding piezoelectric element 60 during period tp. As a result, no ink is ejected from the corresponding ejection unit 600 during period tp, and no dots are formed on the medium P.

[0191] As described above, when print data [SIH,SIL]=[1,0] or print data [SIH,SIL]=[1,1] is input to the decoder 216, the corresponding ejection unit 600 ejects ink onto the medium P, and when print data [SIH,SIL]=[0,0] or print data [SIH,SIL]=[0,1] is input to the decoder 216, the corresponding ejection unit 600 does not eject ink onto the medium P. That is, when print data [SIH]=[1], the corresponding ejection unit 600 ejects ink onto the medium P, and when print data [SIH]=[0], the corresponding ejection unit 600 does not eject ink onto the medium P. In other words, of the print data [SIH,SIL], the print data [SIH] functions as information that controls whether the corresponding ejection unit 600 ejects ink onto the medium P.

[0192] On the other hand, when print data [SIH,SIL]=[1,1] or print data [SIH,SIL]=[0,1] is input to the decoder 216, the transmission gate 234 included in the corresponding selection circuit 230 is controlled to be conductive during period tp2, and when print data [SIH,SIL]=[1,0] or print data [SIH,SIL]=[0,0] is input to the decoder 216, the transmission gate 234 included in the corresponding selection circuit 230 is controlled to be non-conductive during period tp2. Then, whether the transmission gate 234 included in the selection circuit 230 is controlled to be conductive or non-conductive during period tp2, the voltage vb is supplied to the piezoelectric element 60 of the corresponding ejection unit 600 as the drive signal VOUT, and therefore does not contribute to the ejection of ink from the ejection unit 600.

[0193] That is, when the print data [SIL] = [1], the transmission gate 234 included in the corresponding selection circuit 230 is controlled to be conductive, thereby controlling the corresponding piezoelectric element 60 and drive signal output circuit 51 to be conductive, and when the print data [SIL] = [0], the transmission gate 234 included in the corresponding selection circuit 230 is controlled to be non-conductive, thereby controlling the corresponding piezoelectric element 60 and drive signal output circuit 51 to be non-conductive. In other words, of the print data [SIH, SIL], the print data [SIL] does not contribute to the ejection of ink onto the medium P, but rather indicates the number of piezoelectric elements 60 connected to the propagation path of the drive signal COM, and functions as information for controlling the load capacitance connected to the propagation path of the drive signal COM.

[0194] As described above, the selection control circuit 210 of the second embodiment controls the ejection of ink from each of the m ejection sections 600 based on the input clock signal SCK, print data signal SI, latch signal LAT, and detection trigger signal TRG, and also controls the number of piezoelectric elements 60 connected to the propagation path of the drive signal COM during period tp2, which is the load capacitance connected to the propagation path.

[0195] Fig. 20 is a diagram showing the configuration of a drive signal output circuit 51 of the second embodiment. As shown in Fig. 20, the drive signal output circuit 51 of the second embodiment differs from the drive signal output circuit 51 of the first embodiment in that a detection trigger signal TRG is input to a stop control circuit 540.

[0196] As described above, the stop control circuit 540 of the second embodiment receives as input the differential base drive signal DdA output by the differentiating circuit 530, the current detection signal DIo output by the load current detection circuit 580, and the detection trigger signal TRG output by the control circuit 100. The stop control circuit 540 generates an enable signal EN whose logic level changes based on the input differential base drive signal DdA, current detection signal DIo, and detection trigger signal TRG, and outputs the enable signal EN to the gate drive circuit 520.

[0197] Specifically, the stop control circuit 540 of the liquid ejection device 1 outputs an enable signal EN of an L level, which is a logical level that disables the operation of the gate drive circuit 520, when the logical level of the differential base drive signal DdA becomes L level, and then detects the rising edge of the detection trigger signal TRG and then detects the falling edge of the current detection signal DIo three times.During the period in which the enable signal EN of the L level is being output, the logical level of the differential base drive signal DdA becomes H level, and outputs an enable signal EN of an H level, which is a logical level that enables the operation of the gate drive circuit 520.

[0198] That is, the stop control circuit 540 of the second embodiment outputs an L-level enable signal EN that disables the operation of the gate drive circuit 520 at the timing when the voltage value of the drive signal COM detected based on the amount of current generated by the propagation of the drive signal COM reaches a predetermined value during the period tp2 in which the number of piezoelectric elements 60 connected to the propagation path of the drive signal COM and the load capacitance connected to the propagation path are controlled, the current generated by the propagation of the drive signal COM becomes zero, and therefore the ripple voltage superimposed on the drive signal COM reaches a maximum value.

[0199] In other words, the liquid ejection device 1 of the second embodiment includes m piezoelectric elements 60 and m selection circuits 230, each of which switches the conduction state between the m piezoelectric elements 60 and the drive signal output circuit 51, and after a predetermined number of the m selection circuits 230 are controlled to be conductive, the gate drive circuit 520 outputs a gate signal Hgd that controls transistor M1 to be non-conductive and a gate signal Lgd that controls transistor M2 to be non-conductive in accordance with an enable signal EN based on the current detection signal DIo.

[0200] In this case, by setting the number of selection circuits 230 that are controlled to be conductive to a predetermined value, when the gate drive circuit 520 outputs a gate signal Hgd that controls transistor M1 to be non-conductive and a gate signal Lgd that controls transistor M2 to be non-conductive in response to an enable signal EN based on the current detection signal DIo, the number of piezoelectric elements 60 connected to the propagation path through which the drive signal COM propagates, and the load capacitance connected to the propagation path through which the drive signal COM propagates, can be controlled to a constant value. As a result, when the transistors M1 and M2 are controlled to be non-conductive, the voltage amplitude of the ripple voltage superimposed on the drive signal COM can be controlled to a substantially uniform value for each period tp. As a result, the risk of different waveform distortions occurring in the signal waveform of the drive signal COM for each period tp is further reduced, and the waveform accuracy of the drive signal VOUT corresponding to the drive signal COM supplied to the piezoelectric elements 60 is further improved.

[0201] In this case, the number of the m selection circuits 230 that are controlled to be conductive may be all of the m selection circuits 230. In other words, the predetermined number of the m selection circuits 230 that are controlled to be conductive may be m, which is the total number of selection circuits 230 included in the ejection head 200. This simplifies processing compared to when a predetermined number of selection circuits 230 are individually controlled to be conductive, and reduces the risk of fluctuations in the load capacitance connected to the propagation path through which the drive signal COM is propagated depending on the selected piezoelectric element 60, due to variations in the capacitance components of each of the m piezoelectric elements 60. As a result, the risk of different waveform distortions occurring in the signal waveform of the drive signal COM for each period tp is further reduced, and the waveform accuracy of the drive signal VOUT corresponding to the drive signal COM supplied to the piezoelectric element 60 is further improved.

[0202] Here, the m piezoelectric elements 60 possessed by the ejection head 200 are an example of the first to n-th capacitive loads, the m selection circuits 230 corresponding to the m piezoelectric elements 60 possessed by the ejection head 200 are an example of the first to n-th switch circuits, and a predetermined number of the m selection circuits 230 that are controlled to be conductive corresponds to p. That is, the integer n is m, which is the total number of piezoelectric elements 60 possessed by the ejection head 200, and the integer p is a predetermined number of the m selection circuits 230 that are controlled to be conductive.

[0203] 3. Third embodiment Next, a liquid ejection device 1 of a third embodiment will be described. In the liquid ejection device 1 of the third embodiment, the configuration of the circuit that outputs the drive signal COM differs from the drive signal output circuit 51 of the liquid ejection devices 1 of the first and second embodiments. In the following description, the liquid ejection device 1 of the third embodiment will be described assuming that a drive signal output circuit 51a, which corresponds to the drive signal output circuit 51 of the first and second embodiments, outputs the drive signal COM. In describing the liquid ejection device 1 of the third embodiment, the same components as those of the liquid ejection devices 1 of the first and second embodiments will be assigned the same reference numerals, and their description will be omitted or simplified.

[0204] Fig. 21 is a diagram showing an example of the functional configuration of the drive signal output circuit 51a according to the third embodiment. As shown in Fig. 21, the drive signal output circuit 51a includes a DAC 711, a modulation circuit 710, inverters 715 and 815, a modulation amplifier circuit 750, a demodulation circuit 560, a feedback circuit 770, a level switching signal output circuit 810, and a level shift amplifier circuit 850.

[0205] The DAC 711 receives a reference drive signal dA, which is a digital signal, from the control circuit 100. The DAC 711 performs digital-to-analog conversion on the reference drive signal dA that is received as input, and then outputs the converted analog signal as the reference drive signal aA.

[0206] The modulation circuit 710 includes an adder 712 and a comparator 714. The basic drive signal aA is input to the positive input terminal of the adder 712. A feedback signal VFB, which is the drive signal COM fed back via a feedback circuit 770 (described later), is input to the negative input terminal of the adder 712. The adder 712 outputs a signal obtained by subtracting the feedback signal VFB from the basic drive signal aA to the comparator 714.

[0207] Comparator 714 pulse-modulates the signal output by adder 712 to generate modulated signal MS. This modulated signal MS output by comparator 714 is output from modulation circuit 710. This modulation circuit 710 generates a pulse density modulated signal (PDM signal) by modulating the signal output by adder 712 using a pulse density modulation (PDM) method, and outputs this PDM signal as modulated signal MS. Specifically, comparator 714 included in modulation circuit 710 compares the voltage of the output signal of adder 712 with a predetermined reference voltage. Then, comparator 714 generates modulated signal MS that goes to H level when the voltage of the output signal of adder 712 is greater than the reference voltage and goes to L level when the voltage of the output signal of adder 712 is less than the reference voltage, and outputs this modulated signal MS to modulation amplifier circuit 750.

[0208] The modulation amplifier circuit 750 includes a gate drive circuit 720, a diode D71, a capacitor C71, and transistors M71 and M72. The modulation amplifier circuit 750 amplifies the input modulation signal MS to generate a first amplified modulation signal AMS1 and outputs it from a first output point OP1.

[0209] The gate drive circuit 720 outputs gate signals HGD1 and LGD1 based on the modulation signal MS. Specifically, the modulation signal MS is input to a gate driver 721 included in the gate drive circuit 720. The gate driver 721 generates a gate signal HGD1 by level-shifting the input modulation signal MS and outputs it to transistor M71. The modulation signal MS has its logical level inverted by an inverter 715, and is then input to a gate driver 722 included in the gate drive circuit 720. The gate driver 722 generates a gate signal LGD1 by level-shifting a signal obtained by inverting the logical level of the input modulation signal MS and outputs it to transistor M72.

[0210] The transistors M71 and M72 are both configured as N-channel MOSFETs. The transistor M71 has a source terminal electrically connected to the first output point OP1, a drain terminal supplied with a voltage signal VD3, and an operation based on a gate signal HGD1 input to the gate terminal. The transistor M72 has a drain terminal electrically connected to the first output point OP1, a source terminal supplied with ground potential, and an operation based on a gate signal LGD1 input to the gate terminal. With the transistor M71 operating based on the gate signal HGD1 and the transistor M72 operating based on the gate signal LGD1, a first amplified modulation signal AMS1 obtained by amplifying the modulation signal MS by the voltage value of the voltage signal VD3 is generated at the first output point OP1.

[0211] Here, the operation of the gate drive circuit 720 will be described. The gate drive circuit 720 includes gate drivers 721 and 722. As described above, the gate driver 721 receives the modulation signal MS as input, and the gate driver 722 receives a signal obtained by inverting the logic level of the modulation signal MS by inverter 715. That is, the signal input to the gate driver 721 and the signal input to the gate driver 722 are exclusively at H level. Here, "exclusively at H level" includes the case where H level signals are not input to the gate driver 721 and the gate driver 722 at the same time. That is, it does not exclude the case where L level signals are input to the gate driver 721 and the gate driver 722 at the same time.

[0212] The low-potential power supply terminal of the gate driver 721 is electrically connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 generated at the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 721 as a voltage signal HVS1. The high-potential power supply terminal of the gate driver 721 is electrically connected to the cathode terminal of the diode D71 and one end of the capacitor C71. The anode terminal of the diode D71 is supplied with a voltage signal VD1, and the other end of the capacitor C71 is electrically connected to the first output point OP1. That is, the diode D71 and the capacitor C71 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 721. Therefore, the high-potential power supply terminal of the gate driver 721 is supplied with a voltage signal HVD1 whose voltage value is higher than the voltage value of the voltage signal HVS1 input to the low-potential power supply terminal of the gate driver 721 by the voltage value of the voltage signal VD1.

[0213] Therefore, when an H-level modulation signal MS is input, the gate driver 721 outputs a gate signal HGD1 based on a voltage signal HVD1 having a voltage value higher than the voltage value of the first output point OP1 by the voltage value of the voltage signal VD1, and when an L-level modulation signal MS is input, it outputs a gate signal HGD1 based on the voltage signal HVS1, which is the voltage value of the first output point OP1.

[0214] A ground potential is supplied to a low-potential power supply terminal of the gate driver 722 as a voltage signal LVS1. A voltage signal VD1 is supplied to a high-potential power supply terminal of the gate driver 722 as a voltage signal LVD1. Therefore, when an H-level signal obtained by inverting the logical level of an L-level modulation signal MS by inverter 715 is input to the gate driver 722, the gate driver 722 outputs a gate signal LGD1 with a voltage value based on the voltage signal LVD1 of the voltage signal VD1. When an L-level signal obtained by inverting the logical level of an H-level modulation signal MS by inverter 715 is input to the gate driver 722, the gate driver 722 outputs a gate signal LGD1 with a voltage value based on the voltage signal LVS1 of ground potential. Then, the transistor M71 operates based on the gate signal HGD1, and the transistor M72 operates based on the gate signal LGD1, so that a first amplified modulation signal AMS1 obtained by amplifying the modulation signal MS by the voltage value of the voltage signal VD3 is output from the first output point OP1.

[0215] The reference drive signal aA is input to the level switching signal output circuit 810. The level switching signal output circuit 810 outputs a level switching signal LS whose logical level changes based on the reference drive signal aA that is input. Specifically, the level switching signal output circuit 810 outputs an H-level level switching signal LS during a period when the value of the reference drive signal aA is greater than a predetermined threshold, and outputs an L-level level switching signal LS during a period when the value of the reference drive signal aA is smaller than the predetermined threshold. In other words, the level switching signal output circuit 810 outputs a level switching signal LS whose logical level changes based on the reference drive signal aA that is input, and which is obtained by modulating the reference drive signal aA that is input. Note that the level switching signal output circuit 810 may also receive a signal output by the feedback circuit 770 in addition to the reference drive signal dA, and may output a level switching signal LS whose logical level changes based on the reference drive signal aA and the signal output by the feedback circuit 770 during a period when the value of the reference drive signal aA changes.

[0216] The level shift amplifier circuit 850 includes a gate drive circuit 820, diodes D81 and D82, capacitors C81 and C82, transistors M81 and M82, and a boost circuit BS. The level shift amplifier circuit 850 outputs the first amplified modulated signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 from a second output point OP2 as a second amplified modulated signal AMS2 in response to an input level switching signal LS.

[0217] The gate drive circuit 820 outputs gate signals HGD2 and LGD2 based on the level switching signal LS. Specifically, the level switching signal LS is input to a gate driver 821 included in the gate drive circuit 820. The gate driver 821 generates a gate signal HGD2 by level-shifting the input level switching signal LS and outputs it to the transistor M81. The logical level of the level switching signal LS is inverted by an inverter 815, and then the level switching signal LS is input to a gate driver 822 included in the gate drive circuit 820. The gate driver 822 generates a gate signal LGD2 by level-shifting a signal obtained by inverting the logical level of the input level switching signal LS and outputs it to the transistor M82.

[0218] The transistors M81 and M82 are both configured as N-channel MOSFETs. The transistor M81 has a source terminal electrically connected to the second output point OP2, a drain terminal supplied with a voltage signal VBST, and an input gate terminal that operates based on a gate signal HGD2. The transistor M82 has a drain terminal electrically connected to the second output point OP2, a source terminal supplied with the first amplified modulation signal AMS1, and an input gate terminal that operates based on a gate signal LGD2. The transistor M81 operates based on the gate signal HGD2, and the transistor M82 operates based on the gate signal LGD2, so that the first amplified modulation signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 is output from the second output point OP2 as the second amplified modulation signal AMS2.

[0219] The boost circuit BS includes a diode D83 and a capacitor C83. One end of the capacitor C83 is electrically connected to the first output point OP1, and the first amplified modulation signal AMS1 is supplied to the one end. The other end is electrically connected to the drain terminal of the transistor M81. The voltage signal VD2 is supplied to the anode terminal of the diode D83, and the cathode terminal of the diode D83 is electrically connected to the other end of the capacitor C83 and the drain terminal of the transistor M81. Note that while FIG. 21 illustrates a case in which the boost circuit BS includes a single diode D83, the boost circuit BS may include multiple diodes D83 connected in series. Here, the drain terminal of the transistor M81 is supplied with a voltage signal VBST that is actually based on a voltage value obtained by subtracting the forward drop voltage of the diode D83 from the voltage value of the voltage signal VD2. However, the following description may assume that the forward drop voltage of the diode D83 is 0 V.

[0220] The boost circuit BS generates a voltage signal VBST, which is the voltage across the capacitor C83, by adding the voltage of the first amplified modulation signal AMS1 to the voltage of the voltage signal VD2, and outputs it to the drain terminal of the transistor M81. In other words, the boost circuit BS generates a voltage signal VBST by level-shifting the reference potential of the first amplified modulation signal AMS1 by the voltage of the voltage signal VD2, and outputs it to the drain terminal of the transistor M81.

[0221] Here, the operation of the gate drive circuit 820 will be described. The gate drive circuit 820 includes gate drivers 821 and 822. As described above, the level switching signal LS is input to the gate driver 821, and a signal obtained by inverting the logical level of the level switching signal LS by the inverter 815 is input to the gate driver 822. That is, the signal input to the gate driver 821 and the signal input to the gate driver 822 are exclusively at H level. Here, being exclusively at H level includes the case where an H level signal is not input to the gate driver 821 and the gate driver 822 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 821 and the gate driver 822 at the same time.

[0222] The low-potential power supply terminal of the gate driver 821 is electrically connected to the second output point OP2. Therefore, the signal generated at the second output point OP2 is supplied to the low-potential power supply terminal of the gate driver 821 as a voltage signal HVS2. The high-potential power supply terminal of the gate driver 821 is electrically connected to the cathode terminal of the diode D81 and one end of the capacitor C81. The anode terminal of the diode D81 is supplied with a voltage signal VD1, and the other end of the capacitor C81 is electrically connected to the second output point OP2. That is, the diode D81 and the capacitor C81 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 821. Therefore, a voltage signal HVD2 that is higher than the voltage value of the voltage signal HVS2 input to the low-potential power supply terminal of the gate driver 821 by the voltage value of the voltage signal VD1 is supplied to the high-potential power supply terminal of the gate driver 821.

[0223] Therefore, when an H-level level switching signal LS is input, the gate driver 821 outputs a gate signal HGD2 based on a voltage signal HVD2 that is higher than the voltage value of the second output point OP2 by the voltage value of the voltage signal VD1, and when an L-level level switching signal LS is input, the gate driver 821 outputs a gate signal HGD2 that is based on the voltage signal HVS2, which is the voltage value of the second output point OP2.

[0224] The low-potential power supply terminal of the gate driver 822 is connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 output from the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 822 as a voltage signal LVS2. The high-potential power supply terminal of the gate driver 822 is electrically connected to the cathode terminal of the diode D82 and one end of the capacitor C82. The anode terminal of the diode D82 is supplied with a voltage signal VD1, and the other end of the capacitor C82 is electrically connected to the first output point OP1. That is, the diode D82 and the capacitor C82 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 822. Therefore, the high-potential power supply terminal of the gate driver 822 is supplied with a voltage signal LVD2 whose voltage value is higher than the voltage value of the voltage signal LVS2 input to the low-potential power supply terminal of the gate driver 822 by the voltage value of the voltage signal VD1.

[0225] Therefore, when the gate driver 822 receives an H-level signal inverted by the inverter 815 from the logical level of the L-level level switching signal LS, it outputs a gate signal LGD2 based on the voltage signal LVD2 having a voltage value higher than the voltage value of the first output point OP1 by the voltage value of the voltage signal VD1, and when the gate driver 822 receives an L-level signal inverted by the inverter 815 from the logical level of the H-level level switching signal LS, it outputs a gate signal HGD2 based on the voltage signal LVS2 having the voltage value of the first output point OP1.

[0226] When an L-level level switching signal LS is input to the level shift amplifier circuit 850 configured as described above, the first output point OP1 of the modulation amplifier circuit 750 and the second output point OP2 of the level shift amplifier circuit 850 are electrically connected via the transistor M82. Therefore, when the input level switching signal LS is L-level, the level shift amplifier circuit 850 outputs the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2 from the second output point OP2.

[0227] On the other hand, when an H-level level switching signal LS is input to the level shift amplifier circuit 850, the first output point OP1 of the modulation amplifier circuit 750 and the second output point OP2 of the level shift amplifier circuit 850 are electrically connected via the boost circuit BS and transistor M81. Therefore, when the level switching signal LS is H, the level shift amplifier circuit 850 outputs, from the second output point OP2, the voltage signal VBST, which is a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 by the voltage value of the voltage signal VD2, as the second amplified modulation signal AMS2.

[0228] The second amplified modulated signal AMS2 output by the level shift amplifier circuit 850 is input to the demodulation circuit 560. The demodulation circuit 560 has a configuration similar to that of the drive signal output circuit 51 in the first and second embodiments, and includes a coil L1 and a capacitor C1. The demodulation circuit 560 smooths and demodulates the second amplified modulated signal AMS2 output by the level shift amplifier circuit 850 to generate a drive signal COM, which is output from a terminal Out.

[0229] The feedback circuit 770 generates a feedback signal VFB corresponding to the drive signal COM generated by the demodulation circuit 560 and feeds it back to the modulation circuit 710. The feedback signal VFB output by the feedback circuit 770 includes a signal obtained by dividing the drive signal COM, and a signal obtained by dividing the drive signal COM using a voltage divider circuit (not shown) and extracting high-frequency components of the signal obtained by dividing the drive signal COM using a high-pass filter (not shown). That is, the feedback circuit 770 includes the feedback circuits 570 and 572 included in the drive signal output circuits 51 of the first and second embodiments. In the modulation circuit 710, the adder 712 outputs a signal obtained by subtracting the feedback signal VFB from the basic drive signal aA to the comparator 714, and the comparator 714 outputs a modulated signal MS based on the feedback signal VFB in accordance with the output of the adder 712. This causes the drive signal output circuit 51a to self-oscillate, improving the waveform accuracy of the drive signal COM output by the drive signal output circuit 51a.

[0230] As described above, the drive signal output circuit 51a of the third embodiment is a so-called capacitive load drive circuit that outputs a drive signal COM that drives a capacitive load such as a piezoelectric element 60, and includes a modulation circuit 710 that modulates the basic drive signal aA according to the basic drive signal dA that is the basis of the drive signal COM and outputs a modulated signal MS, a gate drive circuit 720 that outputs gate signals HGD1, LGD1 according to the modulated signal MS, a modulation amplification circuit 750 that includes transistors M71, M72 and drives the transistors M71, M72 according to the gate signals HGD1, LGD1 to amplify the modulated signal MS and output a first amplified modulated signal AMS1, and a voltage value a level shift amplifier circuit 850 that outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 when the level switching signal LS is at the L level, and outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 when the level switching signal LS is at the H level; a demodulation circuit 560 that demodulates the second amplified modulated signal AMS2 and outputs a drive signal COM; and a feedback circuit 570 that causes the drive signal output circuit 51 to self-oscillate by outputting a feedback signal VFB corresponding to the drive signal COM.

[0231] That is, in the drive signal output circuit 51a, the transistor pair including transistor M71 and transistor M72 outputs a first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS, and the transistor pair including transistor M82 and transistor M82 outputs a second amplified modulated signal AMS2 obtained by level-shifting the reference potential of the first amplified modulated signal AMS1. In other words, the transistor pair including transistor M71 and transistor M72 and the transistor pair including transistor M82 and transistor M82 function as an amplifier circuit AP that outputs the second amplified modulated signal AMS2 by amplifying the modulated signal MS and level switching signal LS obtained by modulating the basic drive signal aA that is the basis of the drive signal COM. The gate drive circuit 720 outputs gate signals HGD1 and LGD1 that control the driving of a transistor pair including transistors M71 and M72, and the gate drive circuit 820 outputs gate signals HGD2 and LGD2 that control the driving of a transistor pair including transistors M81 and M82, so that the gate drive circuit 720 and the gate drive circuit 820 function as a gate drive circuit GD that outputs gate signals HGD1, LGD1, HGD2, and LGD2 that control the driving of the amplifier circuit AP.

[0232] Furthermore, the drive signal output circuit 51a of the liquid ejection device 1 of the third embodiment has a differential circuit 530, a stop control circuit 540, and a load current detection circuit 580, similar to the drive signal output circuit 51 of the liquid ejection device 1 of the first and second embodiments.

[0233] The base drive signal dA is input to the differentiation circuit 530. The differentiation circuit 530 outputs a differentiated base drive signal DdA that goes to H level when the voltage value of the signal waveform defined by the base drive signal dA changes and the voltage value of the base drive signal aA changes, and that goes to L level when the voltage value of the signal waveform defined by the base drive signal dA is constant and the voltage value of the base drive signal aA is constant.

[0234] The load current detection circuit 580 includes a high-pass filter 582 and a comparator 584, both of which are not shown in FIG. 21 . The high-pass filter 582 outputs a load current signal DIp, the voltage of which changes depending on the amount and direction of a current generated in association with the propagation of the drive signal COM output via the terminal Out. The load current signal DIp is input to the positive input terminal of the comparator 584, and a ground potential is supplied to the negative input terminal of the comparator 584. The comparator 584 outputs a current detection signal DIo that goes high when the voltage of the load current signal DIp is positive and goes low when the voltage of the load current signal DIp is negative. The comparator 584 switches its logic level when the load current signal DIp output by the high-pass filter 582 becomes zero and when the current generated in association with the propagation of the drive signal COM becomes zero.

[0235] The differential base drive signal DdA and the current detection signal DIo are also input to the stop control circuit 540. After the logical level of the differential base drive signal DdA becomes L level, the stop control circuit 540 detects three falling edges of the current detection signal DIo and outputs an L level enable signal EN that disables the operation of at least one of the gate drive circuits 720 and 820 included in the gate drive circuit GD, and during the period in which the L level enable signal EN is being output, the logical level of the differential base drive signal DdA becomes H level, thereby outputting an H level enable signal EN that enables the operation of the gate drive circuits 720 and 820 included in the gate drive circuit GD whose operation has been disabled.

[0236] The liquid ejection device 1 of the third embodiment configured as above also achieves the same effects as the liquid ejection device 1 of the first embodiment.

[0237] At this time, after the logical level of the differential base drive signal DdA becomes L level, the stop control circuit 540 detects three falling edges of the current detection signal DIo, thereby outputting an L level enable signal EN that disables the operation of the gate drive circuit 820 included in the gate drive circuit GD, and preferably, during the period in which the L level enable signal EN is being output, the logical level of the differential base drive signal DdA becomes H level, thereby effectively controlling the gate drive circuit 820 included in the gate drive circuit GD.

[0238] The level shift amplifier circuit 850 including the gate drive circuit 820 operates at the first output point OP1, with the propagation path of the first amplified modulation signal AMS1 propagating through the first output point OP1 being a floating ground. Therefore, from the viewpoint of improving operational stability, it is preferable that sufficient charge be stored in the capacitors C81, C82, and C83 that generate the power supply voltage for the level shift amplifier circuit 850 including the gate drive circuit 820.

[0239] With this configuration, even when the gate drive circuit 820 is disabled and both transistors M81 and M82 are turned off, the gate drive circuit 720 remains active, allowing the transistors M71 and M72 to continue driving. Therefore, even when the gate drive circuit 820 is disabled and both transistors M81 and M82 are turned off, sufficient charge is retained in the capacitors C81, C82, and C83 of the level shift amplifier circuit 850. In other words, the amount of charge released from the capacitors C81, C82, and C83 is reduced during the period when the gate drive circuit 820 is disabled and both transistors M81 and M82 are turned off. As a result, the operational stability of the drive signal output circuit 51a is improved.

[0240] Here, the amplifier circuit AP is an example of an amplifier circuit of the third embodiment, the transistor M81 included in the amplifier circuit AP is an example of a first transistor, the transistor M82 is an example of a second transistor, the transistor pair formed by the transistors M81 and M82 is an example of a first transistor pair, the transistor M71 is an example of a third transistor, the transistor M72 is an example of a fourth transistor, and the transistor pair formed by the transistors M71 and M72 is an example of a second transistor pair. A first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS and output by the transistor pair formed by the transistors M71 and M72 is an example of a base amplified modulated signal, and a second amplified modulated signal AMS2 obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 output by the transistor pair formed by the transistors M81 and M82 is an example of an amplified modulated signal.

[0241] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be combined as appropriate.

[0242] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0243] The following can be derived from the above-described embodiment.

[0244] One aspect of the capacitive load drive circuit is A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit having a first transistor pair including a first transistor and a second transistor, which amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the demodulated signal as the drive signal; a transistor drive circuit that outputs a first drive control signal that controls the drive of the first transistor and a second drive control signal that controls the drive of the second transistor; a feedback circuit that feeds back the drive signal to the modulation circuit; a current detection circuit that detects a drive current generated in association with the propagation of the drive signal and outputs a current detection signal corresponding to a change in the drive current to the transistor drive circuit; Equipped with The transistor drive circuit outputs the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive in response to the current detection signal.

[0245] In this capacitive load drive circuit, the transistor drive circuit outputs a first drive control signal that controls the first transistor, which outputs the amplified modulation signal, to be non-conductive, and a second drive control signal that controls the second transistor to be non-conductive, in response to a current detection signal. This causes the amplifier circuit to control the voltage of the amplified modulation signal to a constant value that corresponds to the current detection signal. Because the current detection signal corresponds to changes in the drive current that occur as the drive signal propagates, the transistor drive circuit can control the first and second transistors to be non-conductive when the voltage of the drive signal reaches a predetermined voltage value that takes into account factors such as ripple voltage superimposed on the drive signal. In other words, the transistor drive circuit can control the first and second transistors to be non-conductive when the voltage of the drive signal reaches a predetermined voltage value that takes into account factors such as ripple voltage superimposed on the drive signal. This allows the phases of the first transistor and the second transistor to be controlled to be approximately the same for each cycle of ejecting liquid onto the medium when the first transistor and the second transistor resume driving, thereby reducing the risk of different waveform distortions occurring in the drive signal for each cycle, and thereby improving the waveform accuracy of the drive signal supplied to the capacitive load.

[0246] In one aspect of the capacitive load drive circuit, The transistor drive circuit includes: During a period in which the voltage value of the drive signal is constant, the first drive control signal that controls the first transistor to be non-conductive and the second drive control signal that controls the second transistor to be non-conductive may be output at the timing when the direction in which the drive current flows switches from the positive direction from the demodulation circuit to the capacitive load to the negative direction from the capacitive load to the demodulation circuit.

[0247] In this capacitive load drive circuit, the transistor drive circuit holds the voltage value of the drive signal at the timing when the direction of the drive current flow switches and the drive current becomes zero, thereby keeping the ripple voltage superimposed on the drive signal constant at its maximum value and reducing the risk of the held voltage value fluctuating due to the influence of inductor elements, etc. connected to the propagation path of the drive signal at the timing when the voltage value of the drive signal is held.

[0248] In one aspect of the capacitive load drive circuit, The transistor drive circuit includes: During a period in which the voltage value of the drive signal is constant, the first drive control signal that controls the first transistor to be non-conductive and the second drive control signal that controls the second transistor to be non-conductive may be output at the timing when the direction in which the drive current flows switches from the negative direction from the capacitive load to the demodulation circuit to the positive direction from the demodulation circuit to the capacitive load.

[0249] In this capacitive load drive circuit, the transistor drive circuit holds the voltage value of the drive signal at the timing when the direction of the drive current flow switches and the drive current becomes zero, thereby keeping the ripple voltage superimposed on the drive signal constant at a minimum value and reducing the risk of the held voltage value fluctuating due to the influence of inductor elements, etc. connected to the propagation path of the drive signal at the timing when the voltage value of the drive signal is held.

[0250] In one aspect of the capacitive load drive circuit, The current detection circuit may include a high-pass filter circuit, and may output the current detection signal according to a signal output by the high-pass filter circuit.

[0251] In one aspect of the capacitive load drive circuit, the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a resistive element; The amplified modulated signal is input to one end of the inductor element, The other end of the inductor element is electrically connected to one end of the capacitor element; The other end of the capacitor element is electrically connected to one end of the resistor element, the demodulation circuit outputs, as the drive signal, a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected; The current detection circuit may output the current detection signal according to a signal at one end of the resistance element.

[0252] In one aspect of the capacitive load drive circuit, the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a differential amplifier circuit and a resistance element; The amplified modulated signal is input to one end of the inductor element, the other end of the inductor element is electrically connected to one end of the capacitor element and one end of the resistor element; The other end of the capacitor element is supplied with a ground potential, the demodulation circuit generates a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected as the drive signal, and outputs the signal via the resistor element; the differential amplifier circuit differentially amplifies the potential difference between both ends of the resistance element; The current detection circuit may output the current detection signal according to the signal output by the differential amplifier circuit.

[0253] In one aspect of the capacitive load drive circuit, The current detection circuit may include a magnetic sensor circuit that detects the intensity of a magnetic field generated by the propagation of the drive current, and may output the current detection signal according to a signal output by the magnetic sensor circuit.

[0254] In one aspect of the capacitive load drive circuit, the amplifier circuit has a second transistor pair including a third transistor and a fourth transistor; one of the first transistor pair and the second transistor pair amplifies the modulated signal and outputs an amplified modulated signal; The other of the first transistor pair and the second transistor pair may output the amplified modulated signal obtained by level-shifting a reference potential of the original amplified modulated signal.

[0255] In one aspect of the capacitive load drive circuit, the second transistor pair outputs the amplified modulated signal; The first pair of transistors may output the amplified modulated signal.

[0256] One aspect of the liquid ejection device is a capacitive load drive circuit that outputs a drive signal; a first ejection unit including a first capacitive load driven by the drive signal, the first capacitive load being driven to eject liquid; a first switch circuit, one end of which is electrically connected to the first capacitive load and the other end of which is electrically connected to the capacitive load drive circuit, for switching a conduction state between the first capacitive load and the capacitive load drive circuit; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit having a first transistor pair including a first transistor and a second transistor, which amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the demodulated signal as the drive signal; a transistor drive circuit that outputs a first drive control signal that controls the drive of the first transistor and a second drive control signal that controls the drive of the second transistor; a feedback circuit that feeds back the drive signal to the modulation circuit; a current detection circuit that detects a drive current generated in association with the propagation of the drive signal and outputs a current detection signal corresponding to a change in the drive current to the transistor drive circuit; Equipped with The transistor drive circuit outputs the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive in response to the current detection signal.

[0257] In this liquid ejection device, the transistor drive circuit outputs a first drive control signal that controls the first transistor, which outputs the amplified modulation signal, to be non-conductive, and a second drive control signal that controls the second transistor to be non-conductive, in response to the current detection signal. This causes the amplifier circuit to control the voltage value of the amplified modulation signal to a constant value that corresponds to the current detection signal. Because the current detection signal corresponds to changes in the drive current that occur as the drive signal propagates, the transistor drive circuit can control the first transistor and the second transistor to be non-conductive when the voltage value of the drive signal reaches a predetermined voltage value that takes into account factors such as ripple voltage superimposed on the drive signal. In other words, the transistor drive circuit can control the first transistor and the second transistor to be non-conductive when the voltage value of the drive signal reaches a predetermined voltage value that takes into account factors such as ripple voltage superimposed on the drive signal. This allows the phases of the first transistor and the second transistor to be controlled to be approximately the same for each cycle of ejecting liquid onto the medium when the first transistor and the second transistor resume driving, thereby reducing the risk of different waveform distortions occurring in the drive signal for each cycle, and thereby improving the waveform accuracy of the drive signal supplied to the capacitive load.

[0258] In one aspect of the liquid ejection device, The transistor drive circuit includes: During a period in which the voltage value of the drive signal is constant, the first drive control signal that controls the first transistor to be non-conductive and the second drive control signal that controls the second transistor to be non-conductive may be output at the timing when the direction in which the drive current flows switches from the positive direction from the demodulation circuit to the first capacitive load to the negative direction from the first capacitive load to the demodulation circuit.

[0259] In this liquid ejection device, the transistor drive circuit holds the voltage value of the drive signal at the timing when the direction of the drive current changes and the drive current becomes zero, thereby keeping the ripple voltage superimposed on the drive signal constant at its maximum value and reducing the risk of the held voltage value fluctuating due to the influence of inductor elements, etc. connected to the propagation path of the drive signal at the timing when the voltage value of the drive signal is held.

[0260] In one aspect of the liquid ejection device, The transistor drive circuit includes: During a period in which the voltage value of the drive signal is constant, the first drive control signal that controls the first transistor to be non-conductive and the second drive control signal that controls the second transistor to be non-conductive may be output at the timing when the direction in which the drive current flows switches from the negative direction from the first capacitive load to the demodulation circuit to the positive direction from the demodulation circuit to the first capacitive load.

[0261] In this liquid ejection device, the transistor drive circuit holds the voltage value of the drive signal at the timing when the direction of the drive current changes and the drive current becomes zero, thereby keeping the ripple voltage superimposed on the drive signal constant at its minimum value and reducing the risk of the held voltage value fluctuating due to the influence of inductor elements, etc. connected to the propagation path of the drive signal at the timing when the voltage value of the drive signal is held.

[0262] In one aspect of the liquid ejection device, The current detection circuit may include a high-pass filter circuit, and may output the current detection signal according to a signal output by the high-pass filter circuit.

[0263] In one aspect of the liquid ejection device, the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a resistive element; The amplified modulated signal is input to one end of the inductor element, The other end of the inductor element is electrically connected to one end of the capacitor element; The other end of the capacitor element is electrically connected to one end of the resistor element, the demodulation circuit outputs, as the drive signal, a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected; The current detection circuit may output the current detection signal according to a signal at one end of the resistance element.

[0264] In one aspect of the liquid ejection device, the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a differential amplifier circuit and a resistance element; The amplified modulated signal is input to one end of the inductor element, the other end of the inductor element is electrically connected to one end of the capacitor element and one end of the resistor element; The other end of the capacitor element is supplied with a ground potential, the demodulation circuit generates a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected as the drive signal, and outputs the signal via the resistor element; the differential amplifier circuit differentially amplifies the potential difference between both ends of the resistance element; The current detection circuit may output the current detection signal according to the signal output by the differential amplifier circuit.

[0265] In one aspect of the liquid ejection device, The current detection circuit may include a magnetic sensor circuit that detects the intensity of a magnetic field generated by the propagation of the drive current, and may output the current detection signal according to a signal output by the magnetic sensor circuit.

[0266] In one aspect of the liquid ejection device, the amplifier circuit has a second transistor pair including a third transistor and a fourth transistor; one of the first transistor pair and the second transistor pair amplifies the modulated signal and outputs an amplified modulated signal; The other of the first transistor pair and the second transistor pair may output the amplified modulated signal obtained by level-shifting a reference potential of the original amplified modulated signal.

[0267] In one aspect of the liquid ejection device, the second transistor pair outputs the amplified modulated signal; The first pair of transistors may output the amplified modulated signal.

[0268] In one aspect of the liquid ejection device, second to n-th capacitive loads and second to n-th switch circuits (n is an integer of 2 or more); each of the first to n-th switch circuits switches a conduction state between the first to n-th capacitive loads and the capacitive load drive circuit; The transistor drive circuit includes: After p (p is a predetermined integer between 1 and n) of the first to nth switch circuits are controlled to be conductive, the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive may be output in response to the current detection signal.

[0269] In this liquid ejection device, when the first transistor and the second transistor are controlled to be non-conductive and maintained, the voltage amplitude of the ripple voltage superimposed on the drive signal can be controlled to be approximately constant. As a result, when the first transistor and the second transistor resume driving, the phases of the first transistor and the second transistor can be controlled to be the same for each cycle of ejecting liquid onto the medium, further reducing the risk of different waveform distortions occurring in the drive signal for each cycle, and as a result, further improving the waveform accuracy of the drive signal supplied to the capacitive load.

[0270] In one aspect of the liquid ejection device, The integer p may be the integer n.

[0271] In this liquid ejection device, when the first transistor and the second transistor are controlled to be non-conductive and maintained, the voltage amplitude of the ripple voltage superimposed on the drive signal can be controlled to be approximately constant. As a result, when the first transistor and the second transistor resume driving, the phases of the first transistor and the second transistor can be controlled to be the same for each cycle of ejecting liquid onto the medium, further reducing the risk of different waveform distortions occurring in the drive signal for each cycle, and as a result, further improving the waveform accuracy of the drive signal supplied to the capacitive load. [Explanation of symbols]

[0272] 1...liquid ejection device, 2...ink container, 10...control unit, 20...head unit, 21...carriage, 30...movement unit, 31...carriage motor, 32...endless belt, 40...transport unit, 41...transport motor, 42...transport roller, 50...drive circuit, 51, 51a...drive signal output circuit, 52...reference voltage output circuit, 60...piezoelectric element, 100...control circuit, 200...ejection head, 210...selection control circuit, 212...shift register, 214...latch circuit, 216...decoder, 230...selection Selection circuit, 232... inverter, 234... transmission gate, 500... integrated circuit, 510... modulation circuit, 512, 513... adder, 514... comparator, 515... inverter, 516... integral attenuator, 517... attenuator, 520... gate drive circuit, 521, 522... gate driver, 530... differentiation circuit, 540... stop control circuit, 550... amplifier circuit, 560... demodulation circuit, 570, 572... feedback circuit, 580, 580a, 580b, 580c... load current detection circuit, 582... high pass Filter, 584, 584a, 584b, 584c... comparator, 586b... amplifier circuit, 588c... magnetic sensor, 600... discharge part, 601... piezoelectric body, 611, 612... electrode, 621... vibration plate, 631... cavity, 632... nozzle plate, 641... reservoir, 651... nozzle, 661... supply port, 710... modulation circuit, 712... adder, 714... comparator, 715... inverter, 720... gate drive circuit, 721, 722... gate driver, 750... modulation amplifier circuit, 770...feedback circuit, 810...level switching signal output circuit, 815...inverter, 820...gate drive circuit, 821, 822...gate driver, 850...level shift amplifier circuit, AP...amplifier circuit, BS...boost circuit, C1 to C5, C71, C81 to C83...capacitors, D1, D13, D71, D81 to D83...diodes, GD...gate drive circuit, L1...coil, M1, M2, M71, M72, M81, M82...transistors, P...medium, R1 to R7, R7a, R8b...resistors

Claims

1. A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit having a first transistor pair including a first transistor and a second transistor, which amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the demodulated signal as the drive signal; a transistor drive circuit that outputs a first drive control signal that controls driving of the first transistor and a second drive control signal that controls driving of the second transistor; a feedback circuit that feeds back the drive signal to the modulation circuit; a current detection circuit that detects a drive current generated in association with the propagation of the drive signal and outputs a current detection signal corresponding to a change in the drive current to the transistor drive circuit; Equipped with the transistor drive circuit outputs the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive in response to the current detection signal. A capacitive load driving circuit comprising:

2. The transistor drive circuit includes: outputting the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive at a timing when the direction of the drive current switches from the positive direction from the demodulation circuit to the capacitive load to the negative direction from the capacitive load to the demodulation circuit during a period in which the voltage value of the drive signal is constant; 2. The capacitive load driving circuit according to claim 1, wherein:

3. The transistor drive circuit includes: outputting the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive at a timing when the direction of the drive current switches from a negative direction from the capacitive load to the demodulation circuit to a positive direction from the demodulation circuit to the capacitive load during a period in which the voltage value of the drive signal is constant; 2. The capacitive load driving circuit according to claim 1, wherein:

4. the current detection circuit includes a high-pass filter circuit, and outputs the current detection signal according to a signal output from the high-pass filter circuit.

2. The capacitive load driving circuit according to claim 1, wherein:

5. the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a resistive element; The amplified modulated signal is input to one end of the inductor element, The other end of the inductor element is electrically connected to one end of the capacitor element; The other end of the capacitor element is electrically connected to one end of the resistor element, the demodulation circuit outputs, as the drive signal, a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected; the current detection circuit outputs the current detection signal according to a signal at one end of the resistance element.

2. The capacitive load driving circuit according to claim 1, wherein:

6. the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a differential amplifier circuit and a resistance element; The amplified modulated signal is input to one end of the inductor element, the other end of the inductor element is electrically connected to one end of the capacitor element and one end of the resistor element; The other end of the capacitor element is supplied with a ground potential, the demodulation circuit generates a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected as the drive signal, and outputs the signal via the resistor element; the differential amplifier circuit differentially amplifies the potential difference between both ends of the resistance element; the current detection circuit outputs the current detection signal corresponding to the signal output by the differential amplifier circuit; 2. The capacitive load driving circuit according to claim 1, wherein:

7. the current detection circuit includes a magnetic sensor circuit that detects the intensity of a magnetic field generated in association with the propagation of the drive current, and outputs the current detection signal in accordance with a signal output by the magnetic sensor circuit.

2. The capacitive load driving circuit according to claim 1, wherein:

8. the amplifier circuit has a second transistor pair including a third transistor and a fourth transistor; one of the first transistor pair and the second transistor pair amplifies the modulated signal and outputs an amplified modulated signal; the other of the first transistor pair and the second transistor pair outputs the amplified modulated signal obtained by level-shifting the reference potential of the original amplified modulated signal.

2. The capacitive load driving circuit according to claim 1, wherein:

9. the second transistor pair outputs the amplified modulated signal; the first transistor pair outputs the amplified modulated signal; 9. The capacitive load driving circuit according to claim 8.

10. a capacitive load drive circuit that outputs a drive signal; a first ejection unit including a first capacitive load driven by the drive signal, the first capacitive load being driven to eject liquid; a first switch circuit, one end of which is electrically connected to the first capacitive load and the other end of which is electrically connected to the capacitive load drive circuit, for switching a conduction state between the first capacitive load and the capacitive load drive circuit; Equipped with The capacitive load drive circuit comprises: a modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal; an amplifier circuit having a first transistor pair including a first transistor and a second transistor, which amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the demodulated signal as the drive signal; a transistor drive circuit that outputs a first drive control signal that controls driving of the first transistor and a second drive control signal that controls driving of the second transistor; a feedback circuit that feeds back the drive signal to the modulation circuit; a current detection circuit that detects a drive current generated in association with the propagation of the drive signal and outputs a current detection signal corresponding to a change in the drive current to the transistor drive circuit; Equipped with the transistor drive circuit outputs the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive in response to the current detection signal. A liquid ejection device characterized by:

11. The transistor drive circuit includes: outputting the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive at a timing when the direction of the drive current switches from the positive direction from the demodulation circuit to the first capacitive load to the negative direction from the first capacitive load to the demodulation circuit during a period in which the voltage value of the drive signal is constant; The liquid ejection device according to claim 10 .

12. The transistor drive circuit includes: outputting the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive at a timing when the direction of the drive current switches from a negative direction from the first capacitive load to the demodulation circuit to a positive direction from the demodulation circuit to the first capacitive load during a period in which the voltage value of the drive signal is constant; The liquid ejection device according to claim 10 .

13. the current detection circuit includes a high-pass filter circuit, and outputs the current detection signal according to a signal output from the high-pass filter circuit. The liquid ejection device according to claim 10 .

14. the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a resistive element; The amplified modulated signal is input to one end of the inductor element, The other end of the inductor element is electrically connected to one end of the capacitor element; The other end of the capacitor element is electrically connected to one end of the resistor element, the demodulation circuit outputs, as the drive signal, a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected; the current detection circuit outputs the current detection signal according to a signal at one end of the resistance element. The liquid ejection device according to claim 10 .

15. the demodulation circuit includes an inductor element and a capacitor element; the current detection circuit includes a differential amplifier circuit and a resistance element; The amplified modulated signal is input to one end of the inductor element, the other end of the inductor element is electrically connected to one end of the capacitor element and one end of the resistor element; The other end of the capacitor element is supplied with a ground potential, the demodulation circuit generates a signal at a connection point where the other end of the inductor element and one end of the capacitor element are electrically connected as the drive signal, and outputs the signal via the resistor element; the differential amplifier circuit differentially amplifies the potential difference between both ends of the resistance element; the current detection circuit outputs the current detection signal corresponding to the signal output by the differential amplifier circuit; The liquid ejection device according to claim 10 .

16. the current detection circuit includes a magnetic sensor circuit that detects the intensity of a magnetic field generated in association with the propagation of the drive current, and outputs the current detection signal in accordance with a signal output by the magnetic sensor circuit. The liquid ejection device according to claim 10 .

17. the amplifier circuit has a second transistor pair including a third transistor and a fourth transistor; one of the first transistor pair and the second transistor pair amplifies the modulated signal and outputs an amplified modulated signal; the other of the first transistor pair and the second transistor pair outputs the amplified modulated signal obtained by level-shifting the reference potential of the original amplified modulated signal. The liquid ejection device according to claim 10 .

18. the second transistor pair outputs the amplified modulated signal; the first transistor pair outputs the amplified modulated signal; 18. The liquid ejection device according to claim 17.

19. second to n-th capacitive loads and second to n-th switch circuits (n is an integer of 2 or more); each of the first to n-th switch circuits switches a conduction state between the first to n-th capacitive loads and the capacitive load drive circuit, The transistor drive circuit includes: After p (p is a predetermined integer from 1 to n) of the first to n-th switch circuits are controlled to be conductive, the first drive control signal for controlling the first transistor to be non-conductive and the second drive control signal for controlling the second transistor to be non-conductive are output in response to the current detection signal. The liquid ejection device according to claim 10 .

20. The integer p is the integer n, 20. The liquid ejection device according to claim 19.

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