Voltage detection circuit, display driver, and display device

Abstract

To provide a voltage detection circuit capable of suppressing current consumption and detecting whether or not each of a plurality of voltages is higher than a reference voltage, and to provide a display driver and a display device.SOLUTION: The voltage detection circuit 100 _ 1 includes a self-bias unit SB for generating a self-bias voltage based on a reference voltage vref, and first to n-th detection units U1 to Un for comparing the magnitude of each of the first to n-th voltages with the reference voltage and outputting a first to n-th voltage detection signal indicating whether or not the voltage is higher than the reference voltage, wherein the detection units include fifth and sixth transistors 11 and 12 whose drains are connected to each other and whose gates receive one of the first to n-th voltages and output a voltage generated at the drains as a voltage detection signal, and current source transistors 22 for supplying an operating current IA based on a bias voltage received by the self-bias unit and the detection unit to the fifth and sixth transistors.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a voltage detection circuit, and a display driver and a display device including the voltage detection circuit. [Background technology]

[0002] Currently, active matrix drive display devices are generally known, which are made up of a display panel using liquid crystal or organic EL, and a source driver and a gate driver that drive the display panel.

[0003] A display panel includes an insulating transparent substrate made of glass, plastic, or the like, on which a plurality of data lines each extending vertically of a two-dimensional screen and a plurality of gate lines each extending horizontally of the two-dimensional screen are arranged, intersecting each other. Furthermore, at each intersection of the plurality of data lines and the plurality of gate lines, a pixel portion connected to the data lines and the gate lines is formed. A gate driver sequentially supplies gate selection signals to each of the gate lines of the display panel. A source driver then supplies each data line with a plurality of output signals having voltage values ​​corresponding to the brightness level of each pixel based on a video signal, thereby causing the display panel to display an image based on the video signal.

[0004] In recent years, the resolution of display panels has increased, and as pixel pitches have become smaller, the wiring width and spacing between the wiring have also become smaller, increasing the risk of failure. Therefore, particularly for in-vehicle display panels, there is a growing demand for a failure detection function that quickly detects abnormalities in the display panel to prevent display freeze, or image freezing.

[0005] Therefore, a liquid crystal display device equipped with such a fault detection function has been proposed (see, for example, Figures 1 and 4 of Patent Document 1). In such a liquid crystal display device, comparators (COMP1, COMP2) serving as voltage detection circuits compare the output signal output by the source driver to the data line with a predetermined reference voltage, and the comparison result is output as a determination signal indicating whether or not a voltage abnormality has occurred.

[0006] Furthermore, a self-bias differential amplification type comparison circuit has been proposed as such a voltage detection circuit (see FIG. 1 of Patent Document 2).

[0007] FIG. 1 is a circuit diagram showing the configuration of a comparison circuit 10 shown in FIG. 1 of Patent Document 2.

[0008] As shown in FIG. 1, the comparison circuit 10 includes P-channel transistors 10a to 10c and N-channel transistors 10d to 10f.

[0009] The transistor 10a receives the power supply voltage Vcc at its source and has its drain connected to the sources of the transistors 10b and 10c via an internal node Vsp. The drains of the transistors 10b and 10d are connected to each other via an internal node Vrefb, and each receives a predetermined reference voltage Vref at its gate. The internal node Vrefb is connected to the gates of the transistors 10a and 10f. The drains of the transistors 10c and 10e are connected to each other and receive the input signal Vin at their gates. The transistor 10f receives the ground voltage Vss at its source and has its drain connected to the sources of the transistors 10d and 10e via an internal node Vsn.

[0010] The comparator circuit 10 is designed so that the transistors 10a to 10f are simultaneously turned on. With this configuration, the comparator circuit 10 outputs the voltage generated at the internal node where the drains of the transistors 10c and 10e are connected as the output signal Vout0, which indicates whether the voltage level of the input signal Vin is higher than the reference voltage Vref. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-275610 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-332793

[0012] [overview] Incidentally, the source driver contains a plurality of power supply circuits that generate, in addition to logic power supply voltages for operating digital circuits, a plurality of analog power supply voltages for generating signal voltages to be supplied to the data lines of the display panel, gate selection signals to be supplied to the gate lines, etc. In this case, if a malfunction occurs in a power supply circuit and the voltage value of each power supply voltage increases or decreases beyond a specified value, normal display will not be possible.

[0013] Therefore, it is desirable to perform voltage detection individually on multiple power supply voltages, including logic power supply voltages and various analog power supply voltages, in the same way as on multiple output signals output from a source driver, to check whether or not a voltage abnormality has occurred.

[0014] However, if a self-biased differential amplification type comparison circuit, such as that shown in FIG. 1 of Patent Document 2, is provided for detecting such voltages, the number of comparison circuits is equal to the number of voltages to be detected, which increases the circuit size and power consumption accordingly.

[0015] Furthermore, in the configuration of the comparator circuit shown in FIG. 1 of Patent Document 2, all of the transistors connected between the power supply voltage Vcc and the ground voltage Vss operate in the on state, which causes a problem in that the static current consumption increases as the amplitude of the power supply voltage (Vcc-Vss) increases.

[0016] 1 of Patent Document 2, the amplitude of the output signal Vout0 is limited to the range between the voltage of the internal node Vsp and the voltage of the internal node Vsn. In this case, this limitation can be eliminated by providing a circuit in the subsequent stage of the comparator circuit that increases the amplitude of the output signal of the comparator circuit to the amplitude of the power supply voltage (Vcc-Vss), but the additional circuitry increases power consumption and also increases the circuit area.

[0017] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a voltage detection circuit, a display driver, and a display device that are capable of detecting a plurality of voltages to be detected while reducing the circuit area and power consumption.

[0018] A voltage detection circuit according to the present invention compares the magnitude of each of first to nth voltages (n is an integer of 2 or more) with a reference voltage, and outputs first to nth voltage detection signals indicating whether the first to nth voltages are higher than the reference voltage, the voltage detection circuit including: a self-bias unit that receives the reference voltage and generates a self-bias voltage based on the reference voltage; and first to nth detection units that receive the first to nth voltages individually and output the first to nth voltage detection signals individually, the self-bias unit including first and second transistors of different conductivity types, each having its drain connected via a first node and receiving the reference voltage at its gate to generate the voltage generated at the first node as the self-bias voltage; a third transistor that receives the self-bias voltage at its gate and supplies a current corresponding to the difference between the voltage of its source and the self-bias voltage to the source of the first transistor; and a third transistor that receives the self-bias voltage at its gate and supplies a current corresponding to the voltage of its source and the self-bias voltage to the source of the second transistor. and a fourth transistor which receives the self-bias voltage at its gate and supplies a current corresponding to the difference between the voltage of its source and the self-bias voltage to the source of the sixth transistor, and a fourth transistor which receives the self-bias voltage at its gate and supplies a current corresponding to the difference between the voltage of its source and the self-bias voltage to the source of the sixth transistor, and the voltage detection circuit further includes at least one current source transistor which receives a bias voltage at its gate and generates a drain current based on the difference between the voltage of its source and the bias voltage as an operating current to be passed through the first to fourth transistors of the self-bias section and the fifth to eighth transistors of each of the first to nth detection sections.

[0019] The display driver of the present invention is a display driver for driving a display panel in which a plurality of data lines and a plurality of gate lines are arranged crossing each other, and includes: a data driver that generates a plurality of drive signals based on a video signal and supplies the plurality of data lines; a gate driver that supplies a gate selection signal to each of the plurality of gate lines; a power supply circuit that generates first to nth power supply voltages used by the data driver and the gate driver; the voltage detection circuit described above; first to nth resistor strings that individually receive the first to nth power supply voltages to be detected and generate voltages by dividing the received power supply voltages as the first to nth voltages; and a control unit that determines whether a voltage abnormality has occurred in at least one of the first to nth power supply voltages based on the first to nth voltage detection signals output from the voltage detection circuit, and stops operation of the data driver and the gate driver when it is determined that a voltage abnormality has occurred.

[0020] a control unit that determines whether or not a voltage abnormality has occurred in at least one of the first to nth power supply voltages based on the first to nth voltage detection signals output from the voltage detection circuit, and stops operation of the data driver and the gate driver when it is determined that a voltage abnormality has occurred. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a circuit diagram showing the configuration of a conventional self-bias differential amplification type comparison circuit 10. FIG. [Figure 2] It is a circuit diagram showing the configuration of the voltage detection circuit 100_1 according to the first embodiment. [Figure 3] It is a waveform diagram showing an example of waveforms of voltage detection signals Vo1 and Von output by detection units U1 and Un based on voltages Vd1 and Vdn as voltages to be detected. [Figure 4] It is a circuit diagram showing the configuration of the voltage detection circuit 100_1A as a modified example of the voltage detection circuit 100_1. [Figure 5A] It is a waveform diagram showing the waveform of the voltage detection signal Vo(k) when the reference voltage Vref has a voltage value near the power supply voltage VSS. [Figure 5B] It is a waveform diagram showing the waveform of the voltage detection signal Vo(k) when the main power supply voltage VDD is a high voltage and the reference voltage Vref is far from the power supply voltage VSS. [Figure 6] It is a circuit diagram showing the configuration of the voltage detection circuit 100_2 according to the second embodiment. [Figure 7] It is a circuit diagram showing the configuration of the voltage detection circuit 100_3 according to the third embodiment. [Figure 8A] It is a waveform diagram showing the internal waveforms of the voltage detection circuit 100_3 when detecting (high voltage detection) a state where voltages Vd1 and Vdn (Vd1 > Vdn) become higher than the reference voltage Vref as the voltage fluctuates (rises). [Figure 8B] It is a waveform diagram showing the internal waveforms of the voltage detection circuit 100_3 when detecting (low voltage detection) a state where voltages Vd1 and Vdn (Vd1 < Vdn) become lower than the reference voltage Vref as the voltage fluctuates (falls). [Figure 9] It is a circuit diagram showing the configuration of the voltage detection circuit 100_3A as a modified example of the voltage detection circuit 100_3. [Figure 10A] It is a circuit diagram showing the configuration of the voltage detection circuit 100_4 according to the fourth embodiment. [Figure 10B] It is a diagram showing a voltage detection signal (Voa, Vob) in which a logical inversion occurs with respect to a change in voltage Vd and a threshold voltage for each W / L size ratio of transistors 13A, 13a, and 13b. [Figure 10C] 10A and 10B are waveform diagrams showing simulation results of the reference voltage Vref, thresholds (Vrefa, Vrefb), and voltage detection signals Voa and Vob with respect to changes in voltage Vd in configurations where various W / L size ratios are set. [Figure 11] FIG. 10 is a circuit diagram showing a configuration of a voltage detection circuit 100_5 according to a fifth embodiment. [Figure 12] FIG. 10 is a circuit diagram showing a configuration of a voltage detection circuit 100_6 according to a sixth embodiment. [Figure 13] FIG. 12 is a block diagram showing the configuration of a display device 300 including a display driver IC 150 according to a seventh embodiment.

[0022] [Detailed explanation] Example 1

[0023] FIG. 2 is a circuit diagram showing a configuration of a voltage detection circuit 100_1 according to a first embodiment of the present invention.

[0024] The voltage detection circuit 100_1 is given a reference power supply voltage VSS (for example, 0 V) ​​and a main power supply voltage VDD, receives n (n is an integer equal to or greater than 2) voltages Vd1-Vdn as detection target voltages, and individually compares the magnitude of each of these voltages Vd1-Vdn with a predetermined reference voltage Vref. Through this comparison, the voltage detection circuit 100_1 individually detects whether each of the voltages Vd1-Vdn is higher than the reference voltage Vref, and outputs voltage detection signals Vo1-Von that represent the detection results in binary values ​​(logical values ​​L and H).

[0025] As shown in FIG. 2, the voltage detection circuit 100_1 is a modified self-bias amplifier circuit, and includes a reference voltage generation circuit 19, a self-bias unit SB, and detection units U1 to Un.

[0026] Furthermore, the voltage detection circuit 100_1 includes an N-channel transistor 22 as a current source, and a bias circuit 30.

[0027] The reference voltage generating circuit 19 is formed of, for example, a bandgap reference circuit, and generates an absolute reference voltage that is independent of the main power supply voltage VDD, ambient temperature, or manufacturing process, and supplies this as the reference voltage Vref to the self-bias unit SB.

[0028] The self-bias section SB includes P-channel transistors 11A and 13A and N-channel transistors 12A and 14A.

[0029] The gates of the transistors 11A and 12A are connected to each other and receive a reference voltage Vref. The drains of the transistors 11A and 12A are connected to the gates of the transistors 13A and 14A, respectively, via a node nd0.

[0030] The transistor 13A has its source connected to the node ng1 and its drain connected to the source of the transistor 11 A. The node ng1 is a power supply node to which the main power supply voltage VDD is supplied.

[0031] The transistor 14A has its drain connected to the source of the transistor 12A and its source connected to the node ng2.

[0032] Each of the detection units U1 to Un has the same internal configuration, that is, includes a P-channel transistor 11, an N-channel transistor 12, a P-channel transistor 13, and an N-channel transistor .

[0033] The gates of the transistors 11 and 12 are connected to each other, and the drains are connected to each other.

[0034] The transistor 13 has its drain connected to the source of the transistor 11, its gate connected to the node nd0, and its source connected to the node ng1. The source of each of the transistors 13 included in each of the detection units U1 to Un, together with the source of the transistor 13A of the self-bias unit SB, is commonly connected to the node ng1 to which the main power supply voltage VDD is supplied.

[0035] The transistor 14 has its drain connected to the source of the transistor 12, its gate connected to the node nd0, and its source connected to the node ng2. The source of each of the transistors 14 included in each of the detection units U1 to Un is commonly connected to the node ng2, together with the source of the transistor 14A of the self-bias unit SB.

[0036] Here, as shown in FIG. 2, the detection units U1 to Un individually receive voltages Vd1 to Vdn to be detected at the junctions between the gates of the transistors 11 and 12 included therein, and output voltage detection signals Vo1 to Von from the junctions between the drains of the transistors 11 and 12, respectively.

[0037] The self-bias unit SB and the detection units U1 to Un each have a common configuration in which four transistors are connected in series between nodes ng1 and ng2, and the conductivity type of each stage of the four transistors is the same.Furthermore, as a basic configuration, the W / L size of each stage of the four transistors is also the same.

[0038] The drain of the transistor 22 as a current source is connected via node ng2 to the source of the transistor 14A included in the self-bias unit SB and to the source of each of the transistors 14 included in each of the detection units U1 to Un, as shown in FIG.

[0039] Transistor 22 receives at its source a power supply voltage VSS (for example, 0 volts) and at its gate a bias voltage Vbn supplied from bias circuit 30. Transistor 22 generates a drain current of a magnitude corresponding to this bias voltage Vbn and passes this current as operating current IA to self-bias unit SB and detection units U1 to Un to operate these units.

[0040] The reference voltage Vref, the main power supply voltage VDD, and the power supply voltage VSS have the following magnitude relationships.

[0041] VDD>Vref>VSS As shown in FIG. 2, the bias circuit 30 includes P-channel transistors 31 and 32, an N-channel transistor 33, and a current source 37.

[0042] The gate and drain of transistor 31 are connected to each other. Transistors 31 and 32 have their gates connected to each other and receive the main power supply voltage VDD at their sources, forming a current mirror. A current source 37 generates a predetermined reference current Ir and supplies it to the drain of transistor 31 on the input side of the current mirror. At this time, transistor 32 on the output side of the current mirror supplies a current that is a copy of the reference current Ir to the drain of transistor 33. The drain and gate of transistor 33 are connected to each other and receive the power supply voltage VSS (e.g., 0 volts) at its source. Transistor 33 receives the current supplied from transistor 32 at its drain, and supplies the voltage generated at its drain and gate as the above-mentioned bias voltage Vbn to the gate of transistor 22.

[0043] That is, the bias circuit 30 supplies a voltage corresponding to the magnitude of the reference current Ir as the bias voltage Vbn to the gate of the transistor 22 serving as a current source.

[0044] As a result, the transistor 22 generates a drain current having a magnitude corresponding to the bias voltage Vbn, and passes this as the operating current IA to the self-bias unit SB and the detection units U1 to Un.

[0045] At this time, the reference current Ir generated by the current source 37 of the bias circuit 30 can control the operating current flowing through the self-bias unit SB and the detection units U1 to Un to any desired magnitude.

[0046] The operation of the voltage detection circuit 100_1 will be described in detail below.

[0047] First, the self-bias unit SB generates a self-bias voltage Vsb whose magnitude corresponds to the reference voltage Vref and supplies it to the gates of the transistors 13 and 14 of each of the detection units U1 to Un. This turns on the transistors 11A and 12A, and a voltage corresponding to the reference voltage Vref is generated at the node nd0. The self-bias unit SB supplies the voltage generated at the node nd0 as the self-bias voltage Vsb to the gates of the transistors 13A and 14A. This turns on both the transistors 13A and 14A, and a bias current based on the voltages at the nodes ng1 and ng2 flows through the path consisting of the transistors 13A, 11A, 12A, and 14A. As a result, the voltage generated at the node nd0 is generated as the self-bias voltage Vsb. In FIG. 2, node ng1 is a power supply node to which the main power supply voltage VDD is supplied, and node ng2 is at a voltage to which the operating current IA is supplied from the power supply voltage VSS via transistor 22. However, if the reference voltage Vref is a voltage close to the power supply voltage VSS, node ng2 will be at a voltage sufficiently close to the power supply voltage VSS.

[0048] Self-bias unit SB supplies the self-bias voltage Vsb not only to the gates of transistors 13A and 14A but also to each of detection units U1-Un. At this time, transistor 13 of each detection unit U1-Un sends a bias current of a magnitude corresponding to the self-bias voltage Vsb to the source of transistor 11. Furthermore, transistor 14 of each detection unit U1-Un draws a bias current of a magnitude corresponding to this self-bias voltage Vsb from the source of transistor 12.

[0049] Here, in each of the detection units U1 to Un, that is, detection unit U(r) (r is an integer from 1 to n), transistors 11 and 12 are turned on in response to the voltage Vd(r) received by it. At this time, if the voltage Vd(r) is higher than the reference voltage Vref, the current drawn by transistor 14 from the junction between the drains of transistors 11 and 12 is greater than the current sent by transistor 11 to this junction. As a result, the voltage at this junction drops, reaching the voltage at node ng2 that is sufficiently close to the power supply voltage VSS (e.g., 0 volts). Therefore, detection unit U(r) outputs a voltage detection signal Vo(r) with a logic value of L.

[0050] On the other hand, when voltage Vd(r) is equal to or lower than reference voltage Vref, transistor 11 outputs less current to the junction between the drains of transistors 11 and 12 than transistor 14 extracts from the junction. This causes the voltage at the junction to increase and reach the main power supply voltage VDD. Therefore, detector U(r) outputs voltage detection signal Vo(r) with a logic value of H.

[0051] Fig. 3 is a waveform diagram showing an example of waveforms of voltage detection signals Vo1 and Von output by detection units U1 and Un, respectively, based on voltages Vd1 and Vdn (Vd1>Vdn) selected from voltages Vd1 to Vdn as detection target voltages in the voltage detection circuit 100_1 of Fig. 2. For convenience of explanation, Fig. 3 will be described using an example in which voltages Vd1 and Vdn change in conjunction with each other.

[0052] Furthermore, in the following embodiments including this embodiment, for the sake of convenience, the transistors 11A, 12A, 13A and 14A included in the self-bias section SB and the transistors 11, 12, 13 and 14 included in each of the detection sections U1 to Un will be described as being arranged in the same position and having the same size.

[0053] 3, when the voltage value of voltage Vd1 is equal to or lower than reference voltage Vref, it outputs voltage detection signal Vo1 with a logical value of H. Here, as shown in FIG. 3, when the voltage value of voltage Vd1 gradually increases and becomes higher than reference voltage Vref at time t1, detection unit U1 changes voltage detection signal Vo1 from the logical value H to the logical value L.

[0054] 3, when the voltage value of voltage Vdn is equal to or lower than reference voltage Vref, detection unit Un outputs voltage detection signal Von with a logical value of H. Then, when the voltage value of voltage Vdn gradually increases and becomes higher than reference voltage Vref at time t2 shown in FIG. 3, detection unit Un changes voltage detection signal Von from the logical value H to the logical value L.

[0055] In this way, the voltage detection circuit 100_1 has first to n-th detection units U1 to Un receiving the first to n-th voltages Vd1 to Vdn as voltages to be detected, and comparing the magnitude of each of the first to n-th voltages Vd1 to Vdn with the reference voltage Vref. Then, the voltage detection circuit 100_1 outputs first to n-th voltage detection signals Vo1 to Von indicating whether or not each of the first to n-th voltages Vd1 to Vdn is higher than the reference voltage Vref.

[0056] 2, the self-bias unit SB of the voltage detection circuit 100_1 is composed of the following first to fourth transistors 11A to 14A. That is, the first transistor 11A and the second transistor 12A are of different conductivity types (P-channel type and N-channel type), their drains are connected via a first node nd0, and their gates receive a reference voltage Vref. As a result, the first transistor 11A and the second transistor 12A generate the voltage generated at the first node nd0 as a self-bias voltage Vsb. The third transistor 13A receives the self-bias voltage Vsb at its gate and supplies a current (source current) corresponding to the difference between the voltage of its own source and the self-bias voltage Vsb to the source of the first transistor 11A. The fourth transistor 14A receives the self-bias voltage Vsb at its gate, and supplies a current (sink current) corresponding to the difference between the voltage of its own source and the self-bias voltage Vsb to the source of the second transistor 12A.

[0057] The first to n-th detection units U1 to Un of the voltage detection circuit 100_1 are each composed of the following fifth to eighth transistors. That is, the fifth transistor 11 and the sixth transistor 12 are of mutually different conductivity types, their drains are connected, and their gates receive one of the first to n-th voltages Vd1 to Vdn, thereby outputting the voltage generated at each drain as one of the first to n-th voltage detection signals Vo1 to Von. The seventh transistor 13 receives the self-bias voltage Vsb at its gate and supplies a current (source current) corresponding to the difference between the voltage of its source and the self-bias voltage Vsb to the source of the fifth transistor 11. The eighth transistor 14 receives the self-bias voltage Vsb at its gate and supplies a current (sink current) corresponding to the difference between the voltage of its source and the self-bias voltage Vsb to the source of the sixth transistor 12.

[0058] As described above, in the voltage detection circuit 100_1, the number of transistors required to compare each of the n voltages Vd1 to Vdn with the reference voltage Vref is the sum of four transistors in the self-bias unit SB, 4n transistors in the detection units U1 to Un, and five transistors in the bias circuit 30 and the transistor 22 (4n+9). That is, in the voltage detection circuit 100_1, the increase in the number of transistors that increases in proportion to the number n of voltages to be detected is 4n. Therefore, according to the voltage detection circuit 100_1, it is possible to reduce the circuit area compared to the case where the comparator shown in FIG. 1 of Patent Document 2 is used, in which the increase in the number of transistors that increases in proportion to the number n of voltages to be detected is 6n.

[0059] 1 of Patent Document 2, in voltage detection circuit 100_1, transistors 13A and 14A that receive self-bias voltage Vsb at their gates and control the bias current in self-bias unit SB, and transistors 13 and 14 that receive self-bias voltage Vsb at their gates and control the bias current in each of detection units U1 to Un, are provided separately from each other. This makes it possible to widen the amplitude of voltage detection signals Vo1 to Von of each of detection units U1 to Un from the main power supply voltage VDD of node ng1 to near the power supply voltage VSS of node ng2 at maximum.

[0060] Furthermore, in the voltage detection circuit 100_1, the transistor 22 as a current source generates the operating current IA to be passed through the self-bias unit SB and the detection units U1 to Un, so that the operating current IA can be limited to any magnitude regardless of the voltage difference between the main power supply voltage VDD and the power supply voltage VSS.

[0061] Therefore, even if a high voltage main power supply voltage VDD is used, or even if transistors 13A, 14A, 13, and 14 that receive the self-bias voltage Vsb and are included in each of the self-bias section SB and the detection sections U1 to Un have low threshold voltages Vt, static current consumption can be reduced, making it possible to suppress power consumption.

[0062] In the voltage detection circuit 100_1 shown in FIG. 2, the operating current IA flowing through the self-bias unit SB and the detection units U1 to Un is generated on the low-voltage power supply voltage VSS side, but it may also be generated on the high-voltage main power supply voltage VDD side.

[0063] FIG. 4 is a circuit diagram showing a configuration of a voltage detection circuit 100_1A as a modified example of the voltage detection circuit 100_1, which has been made in consideration of the above points.

[0064] In addition, the voltage detection circuit 100_1A has the same configuration (19, SB, U1 to Un) as the voltage detection circuit 100_1 shown in Figure 2, except that it employs a bias circuit 30A instead of the bias circuit 30 and a P-channel transistor 21 instead of the transistor 22.

[0065] 2 without the transistors 32 and 33. That is, in the bias circuit 30A, when a reference current Ir generated by a current source 37 is passed through the drain of the transistor 31, the voltage generated at the gate and drain of the transistor 31 is supplied as a bias voltage Vpb to the gate of the transistor 21. In the voltage detection circuit 100_1A, the node ng2 is a power supply node to which the power supply voltage VSS is supplied, and the node ng1 is a voltage to which the operating current IA is supplied from the main power supply voltage VDD via the transistor 21. However, if the reference voltage Vref is a voltage close to the main power supply voltage VDD, the node ng1 will be a voltage sufficiently close to the main power supply voltage VDD.

[0066] The drain of transistor 21 is connected via node ng1 to the source of transistor 13A included in self-bias unit SB and the sources of transistors 13 included in each of detection units U1 to Un. Transistor 21 receives main power supply voltage VDD at its source, generates a drain current based on bias voltage Vbp supplied to its gate, and passes this as operating current IA to the source of transistor 13A in self-bias unit SB and the sources of transistor 13 in each of detection units U1 to Un.

[0067] Incidentally, the voltage detection circuit 100_1A also performs the operation shown in FIG. 3 in the same manner as the voltage detection circuit 100_1.

[0068] According to the configuration of the voltage detection circuit 100_1A shown in FIG. 4, similarly to the voltage detection circuit 100_1, it is possible to reduce the circuit area compared to the case where the comparator shown in FIG. 1 of Patent Document 2 is employed.

[0069] Furthermore, in voltage detection circuit 100_1A, transistor 21 serving as a current source generates operating current IA to be passed through self-bias unit SB and detection units U1-Un. That is, similar to voltage detection circuit 100_1, voltage detection circuit 100_1A can limit operating current IA to an arbitrary magnitude regardless of the voltage difference between main power supply voltage VDD and power supply voltage VSS. Therefore, even when a high main power supply voltage VDD is used or when transistors 13A, 14A, 13, and 14 having a low threshold voltage Vt that receive the self-bias voltage Vsb and are included in self-bias unit SB and detection units U1-Un, respectively, static current consumption can be reduced, thereby making it possible to suppress power consumption.

[0070] In each of the following embodiments, an example of a voltage detection circuit configuration will be described in which the operating current of the self-bias unit SB and the detection units U1 to Un is limited by a transistor 22 that controls the current based on the power supply voltage VSS. However, similar to the relationship between the voltage detection circuits 100_1 and 100_1A, it is possible to change the configuration of the voltage detection circuit to one in which the operating current of the self-bias unit SB and the detection units U1 to Un is limited by a transistor 21 that controls the current based on the main power supply voltage VDD.

[0071] Incidentally, in the voltage detection circuit 100_1 or 100_1A, when the reference voltage Vref has a voltage value close to the power supply voltage VSS as shown in FIG. 5A, the amplitude of the voltage detection signal Vo(k) (k is an integer from 1 to n) can be set to the amplitude of the power supply voltage (VDD-VSS).

[0072] For example, in the voltage detection circuit 100_1 of FIG. 2, when the voltage difference between the reference voltage Vref and the power supply voltage VSS is relatively small, the gate-source voltage of transistor 12A is limited, and its drain current, i.e., the current flowing through self-bias unit SB, is limited. Because the same current flows through transistors 11A, 12A, 13A, and 14A, the gate-source voltage of transistor 13A is also limited. Therefore, the self-bias voltage Vsb is close to the main power supply voltage VDD. Meanwhile, although the gate-source voltages of transistors 11A and 14A increase, the drain-source voltages are limited sufficiently small to allow the same current to flow through them as through transistors 12A and 13A. Furthermore, because the transistor 13 of each of detection units U1 to Un receives the self-bias voltage Vsb at its gate, the current flowing through each of detection units U1 to Un is limited in the same way as the current flowing through self-bias unit SB. If the total current value of the currents flowing through self-bias unit SB and detection units U1 to Un is sufficiently smaller than the maximum allowable current value limited by transistor 22, the drain-source voltage of transistor 22 will be sufficiently small, and the voltage at node ng2 will be close to the power supply voltage VSS. Therefore, the amplitude of voltage detection signal Vo(k) (k is an integer from 1 to n) will be approximately (VDD-VSS).

[0073] When the reference voltage Vref is set near the power supply voltage VSS, the current flowing through each of the self-bias unit SB and the detection units U1-Un is largely determined by the voltage difference between the reference voltage Vref and the power supply voltage VSS that exceeds the threshold voltage of transistor 12A. This allows low current consumption even without transistor 22 to limit the current. However, considering fluctuations in the threshold voltage of transistors due to manufacturing processes and temperature changes, for example, when the operating current is sufficiently reduced in a current detection circuit without transistor 22, an increase in the transistor's threshold voltage may make it impossible to maintain the operating current, or a decrease in the transistor's threshold voltage may increase the operating current, resulting in increased current consumption. By using transistor 22 to control the total current (operating current) flowing through each of the self-bias unit SB and the detection units U1-Un, a margin for the voltage difference between the reference voltage Vref and the power supply voltage VSS is secured, allowing stable operation and sufficiently low static current consumption even when the transistor's threshold voltage fluctuates.

[0074] Furthermore, when the main power supply voltage VDD is relatively high and the reference voltage Vref is far from the power supply voltage VSS, without the transistor 22, the current flowing through each of the self-bias section SB and the detection sections U1 to Un increases significantly, and distortion occurs in the waveform of the voltage detection signal Vo(k) when the voltage Vd(k) changes from a high voltage to a low voltage or from a low voltage to a high voltage relative to the reference voltage Vref, making it difficult to quickly switch the logical value.

[0075] On the other hand, in the voltage detection circuit 100_1 of FIG. 2, when the reference voltage Vref is different from the power supply voltage VSS, the operating current is controlled by the transistor 22. This maintains the current flowing through the self-bias unit SB and the detection units U1 to Un, causing the voltage at node ng2 to rise in accordance with the reference voltage Vref. For example, as shown in FIG. 5B, when the reference voltage Vref has a voltage value near the center of the power supply voltage amplitude (VDD-VSS), the amplitude of the voltage detection signal Vo(k) ranges from the main power supply voltage VDD at node ng1 to the voltage at node ng2. At this time, there is almost no waveform distortion when the voltage detection signal Vo(k) changes, and the operating current is maintained at a low level by the transistor 22. However, the low level of the voltage detection signal Vo(k) cannot be lowered to the power supply voltage VSS. In this case, if the downstream logic circuit receiving the voltage detection signal Vo(k) is, for example, an inverter circuit, the N-channel transistor of the inverter circuit may not be completely turned off even when the voltage detection signal Vo(k) is low, resulting in increased current consumption. Example 2

[0076] FIG. 6 is a circuit diagram showing a configuration of a voltage detection circuit 100_2 according to a second embodiment of the present invention, which has been made in view of the above points.

[0077] The voltage detection circuit 100_2 has the same configuration (19, 22, 30, SB, U1 to Un) as the voltage detection circuit 100_1 shown in FIG. 2 except that inverter circuits W1 to Wn are newly provided as waveform shaping units.

[0078] Each of the inverter circuits W1 to Wn has the same internal configuration, i.e., includes a P-channel transistor 15 and N-channel transistors 16 and 26. The gates of the transistors 15 and 16 are connected to each other, and the drains are connected to each other. The transistor 15 receives the main power supply voltage VDD at its source. The transistor 26 receives the power supply voltage VSS at its source, has its drain connected to the source of the transistor 16, and receives the bias voltage Vbn at its gate.

[0079] 6, the inverter circuits W1 to Wn individually receive voltage detection signals Vo1 to Von at the node between the gates of the transistors 15 and 16 included therein, and output voltage detection signals Vxo1 to Vxon from the node between the drains of the transistors 15 and 16 included therein. Furthermore, the transistor 26 controls the operating current of each of the inverter circuits W1 to Wn.

[0080] With this configuration, when the voltage value of the voltage detection signal Vo(k) received by the inverter circuit W(k) is high level (VDD), the inverter circuit W(k) outputs a voltage detection signal Vxo(k) of logic value L having the power supply voltage VSS, as shown in FIG. 5B. On the other hand, when the voltage value of the voltage detection signal Vo(k) is low level (the voltage of node ng2), the inverter circuit W(k) outputs a voltage detection signal Vxo(k) of logic value H having the main power supply voltage VDD, as shown in FIG. 5B. Note that when the voltage value of the voltage detection signal Vo(k) is low level, if the voltage of node ng2 is higher than the threshold voltage of transistor 16, transistor 16 does not turn off and current flows from the main power supply voltage VDD to the power supply voltage VSS via transistors 15 and 16, but the current flow is limited by transistor 26.

[0081] That is, in the voltage detection circuit 100_2, inverter circuits W1 to Wn are provided in the subsequent stage of each of the detection units U1 to Un, so that the waveforms of the voltage detection signals Vo1 to Von are shaped into waveforms that swing with the amplitude of the power supply voltage (VDD-VSS), and are output as voltage detection signals Vxo1 to Vxon.

[0082] Therefore, according to the voltage detection circuit 100_2, even if a high-voltage main power supply voltage VDD or a reference voltage Vref having an arbitrary voltage value is used, it is possible to obtain voltage detection signals Vxo1 to Vxon that swing with the amplitude of the power supply voltage (VDD-VSS) while reducing static current consumption.

[0083] Incidentally, by providing inverter circuits W1 to Wn in the subsequent stage of each of the detecting units U1 to Un in the voltage detecting circuit 100_1A as well, it is possible to achieve the same effect as that of the voltage detecting circuit 100_2.

[0084] Furthermore, in the voltage detection circuit 100_2, when the reference voltage Vref is a voltage away from the power supply voltage VSS, the node ng2 connected to the current-controlling transistor 22 becomes a voltage that follows the reference voltage Vref, and the amplitude of the voltage detection signal Vo(k) becomes smaller than the power supply voltage difference (VDD-VSS). For example, when the reference voltage Vref is set to the main power supply voltage VDD, the amplitude of the voltage detection signal Vo(k) may become smaller than half the power supply voltage difference (VDD-VSS). In that case, it becomes difficult for the inverter circuit W(k) to shape the signal into a waveform that swings with the power supply voltage amplitude (VDD-VSS). In view of this, when the voltage value of the reference voltage Vref is on the power supply voltage VSS side, a configuration is preferable in which the operating currents of the self-bias unit SB and the detection units U1-Un are controlled by the transistor 22 connected to the power supply voltage VSS, as in the voltage detection circuit 100_2. In this case, the amplitude of the voltage detection signal Vo(k) is always greater than half the power supply voltage difference (VDD-VSS). Similarly, when the voltage value of the reference voltage Vref is on the side of the main power supply voltage VDD, a configuration in which the operating currents of the self-bias unit SB and the detection units U1 to Un are controlled by a transistor 21 connected to the main power supply voltage VDD, such as a configuration in which an inverter circuit W(k) is added to the voltage detection circuit 100_1A. Note that the transistor 26 of the inverter circuit W(k) only needs to have a function of limiting the current, and may be configured as either an N-channel or P-channel transistor.

[0085] In the above-described voltage detection circuits 100_1, 100_1A, and 100_2, an operating current controlled by the transistor 22 or 21 based on the reference current Ir generated by the current source 37 of the bias circuit 30 always flows in the self-bias unit and each detection unit. In this case, the larger the current flowing in the self-bias unit and each detection unit, the faster the response speed of the voltage detection signals Vo1 to Von to the input of the voltages Vd1 to Vdn to be detected, but the power consumption increases accordingly.

[0086] Therefore, when the voltage values ​​of these voltages Vd1 to Vdn fluctuate and exceed the preliminary detection voltage having a voltage value just before the reference voltage Vref and approach the reference voltage Vref, the current flowing in the self-bias unit and each detection unit may be switched from a standby state of small current to an active state of normal current. Example 3

[0087] FIG. 7 is a circuit diagram showing a configuration of a voltage detection circuit 100_3 according to a third embodiment of the present invention, which has been made in view of the above points.

[0088] The voltage detection circuit 100_3 employs a bias circuit 30B instead of the bias circuit 30 shown in FIG. 2, and is configured as a current control circuit 41 including the bias circuit 30B and a transistor 22. The other configurations (19, SB, U1 to Un) are the same as those of the voltage detection circuit 100_1 shown in FIG. 2, except that a backup detection unit PD and a circuit 40 are newly added.

[0089] The preliminary detection unit PD includes P-channel transistors 11B and 13B and N-channel transistors 12B and 14B, and has the same connection configuration as each of the detection units U1 to Un.

[0090] The drains of transistors 11B and 12B are connected to each other, and the gates are connected to each other. The drain of transistor 13B is connected to the source of transistor 11B, the gate of transistor 13B is connected to node nd0, and the source of transistor 13B receives the main power supply voltage VDD. The drain of transistor 14B is connected to the source of transistor 12B, and the gate of transistor 13B is connected to node nd0. The source of transistor 14B is connected to node nd2.

[0091] Here, the preliminary detection unit PD receives a preliminary detection voltage Vsn having a voltage value just before the reference voltage Vref at the junction between the gates of transistors 11B and 12B, and outputs a preliminary voltage detection signal Vs as follows from the junction between the drains of transistors 11B and 12B:

[0092] That is, the backup detection unit PD, using the above-described configurations (11B to 14B), generates a binary backup voltage detection signal Vs that indicates a logical value H when the backup detection voltage Vsn is equal to or lower than the reference voltage Vref and a logical value L when the backup detection voltage Vsn is higher than the reference voltage Vref, and supplies this to the bias circuit 30B. When the reference voltage Vref is a voltage that is far from the power supply voltage VSS, a circuit 40 similar to the inverter circuit W(k) in FIG. 6 may be provided between the backup detection unit PD and the current control circuit 41, as shown in FIG. 7. When the amplitude of the backup detection signal Vsn output from the backup detection unit PD is smaller than the power supply voltage difference (VDD-VSS), the circuit 40 shapes the waveform of the backup detection signal Vsn to have an amplitude equal to the power supply voltage difference (VDD-VSS) and supplies the waveform to the bias circuit 30B of the current control circuit 41. When the reference voltage Vref is set near the power supply voltage VSS, the amplitude of the backup detection signal Vsn becomes the power supply voltage difference (VDD-VSS), and therefore the circuit 40 is not necessary.

[0093] Similar to the bias circuit 30, the bias circuit 30B includes a circuit made up of transistors 31 to 33. The bias circuit 30B further includes a first current source 37a that supplies a reference current smaller than that of the current source 37 included in the bias circuit 30 to the drain of the transistor 31, a newly added second current source 37b, and a switch 38.

[0094] The switch 38 receives the standby voltage detection signal Vs and is set to an ON or OFF state according to the logic value of the standby voltage detection signal Vs. When the switch 38 is set to an ON state, the switch 38 causes the constant current generated by the current source 37b to flow to the drain of the transistor 31. Therefore, a combined current, which is the combination of the reference current generated by the current source 37a and the constant current generated by the current source 37b, flows through the transistor 31. The magnitude of the constant current generated by the current source 37b is set so that the combined current is equal to or greater than the reference current Ir generated by the current source 37 included in the bias circuit 30.

[0095] That is, while the switch 38 is in the OFF state, the current source 37a generates the operating current I A that is lower than the rated current based on the bias voltage Vbn that corresponds to a reference current lower than the reference current Ir, which is the standby state.

[0096] On the other hand, while switch 38 is in the on state, the reference current generated by current source 37a is combined with the constant current generated by current source 37b. As a result, transistor 22 generates a normal operating current IA having a rated current based on bias voltage Vbn corresponding to a rated current equal to reference current Ir. This state is the active state.

[0097] The variable control of the operating current of the self-bias section and each detection section in the voltage detection circuit 100_3 will be described below.

[0098] FIG. 8A is a waveform diagram showing internal waveforms of the voltage detection circuit 100_3 when detecting (high voltage detection) a state in which voltages Vd1 and Vdn (Vd1>Vdn) as detection target voltages become higher than the reference voltage Vref due to a voltage fluctuation (rise).

[0099] In the example shown in FIG. 8A, in order to detect the point just before the voltage value of the voltage Vd1 reaches the reference voltage Vref, a preliminary detection voltage Vsn that is higher than the voltage Vd1 and whose voltage value increases at the same voltage change rate as the voltage Vd1 is supplied to the preliminary detection unit PD.

[0100] As shown in FIG. 8A, while the preliminary detection voltage Vsn, the voltages Vd1 and Vdn are below the reference voltage Vref, the preliminary detection unit PD outputs a preliminary voltage detection signal Vs of logical value H, and the detection units U1 and Un output voltage detection signals Vo1 and Von of logical value H, respectively. Further, during this period, in response to the preliminary voltage detection signal Vs of logical value H, the switch 38 is turned off, and the operating current IA sent from the transistor 22 becomes a standby state of a low current lower than the rated current.

[0101] Here, as shown in FIG. 8A, when the voltage values of the preliminary detection voltage Vsn, the voltages Vd1 and Vdn gradually increase, and at time point ts, when the voltage value of the preliminary detection voltage Vsn becomes higher than the reference voltage Vref, the preliminary detection unit PD changes the preliminary voltage detection signal Vs from the state of logical value H to logical value L. Therefore, in response to the preliminary voltage detection signal Vs of logical value L, the switch 38 is turned on, and the operating current IA sent from the transistor 22 becomes an active state of a normal current having the rated current.

[0102] Subsequently, when the voltage values of the preliminary detection voltage Vsn, the voltages Vd1 and Vdn increase, and at time point t1 as shown in FIG. 8A, when the voltage value of the voltage Vd1 becomes higher than the reference voltage Vref, the detection unit U1 changes the voltage detection signal Vo1 from the state of logical value H to logical value L.

[0103] Furthermore, when the voltage values of the preliminary detection voltage Vsn, the voltages Vd1 and Vdn increase, and at time point t2 as shown in FIG. 8A, when the voltage value of the voltage Vdn becomes higher than the reference voltage Vref, the detection unit Un changes the voltage detection signal Von from the state of logical value H to logical value L.

[0104] FIG. 8B is a waveform diagram showing the internal waveforms of the voltage detection circuit 100_5 when detecting (low voltage detection) a state where the voltages Vd1 and Vdn (Vd1 < Vdn) become lower than the reference voltage Vref as the voltage fluctuates (decreases).

[0105] In the example shown in FIG. 8B, in order to detect the point just before the voltage value of the voltage Vd1 reaches the reference voltage Vref, a preliminary detection voltage Vsn that is lower than the voltage Vd1 and whose voltage value decreases at the same voltage change rate as the voltage Vd1 is supplied to the preliminary detection unit PD.

[0106] 8B, while the preliminary detection voltage Vsn and the voltages Vd1 and Vdn are higher than the reference voltage Vref, the preliminary detection unit PD outputs a preliminary voltage detection signal Vs with a logic value L, and the detection units U1 and Un output voltage detection signals Vo1 and Von with a logic value L. Furthermore, during this period, in response to the preliminary voltage detection signal Vs with a logic value L, the switch 38 is turned off, and the operating current IA output from the transistor 22 is in a low standby state, lower than the rated current.

[0107] 8B, the voltage values ​​of the preliminary detection voltage Vsn, the voltages Vd1, and Vdn gradually decrease, and at time ts, when the voltage value of the preliminary detection voltage Vsn becomes lower than the reference voltage Vref, the preliminary detection unit PD changes the preliminary voltage detection signal Vs from logic L to logic H. Therefore, in response to the preliminary voltage detection signal Vs of logic H, the switch 38 is turned on, and the operating current IA sent from the transistor 22 becomes an active state of a normal current having a rated current.

[0108] Subsequently, the voltage values ​​of the preliminary detection voltage Vsn, the voltage Vd1, and the voltage Vdn decrease, and at time t1, as shown in FIG. 8B, the voltage value of the voltage Vd1 becomes lower than the reference voltage Vref. Then, the detection unit U1 changes the voltage detection signal Vo1 from the logical value L to the logical value H.

[0109] Furthermore, when the voltage values ​​of the preliminary detection voltage Vsn, voltages Vd1, and Vdn decrease and the voltage value of voltage Vdn becomes lower than the reference voltage Vref at time t2 as shown in FIG. 10B, the detection unit Un changes the voltage detection signal Von from the logical value L to the logical value H.

[0110] In this way, the voltage detection circuit 100_3 receives the preliminary detection voltage Vsn, which has a voltage value higher or lower than any of the voltages Vd1 to Vdn to be detected. As a result, as shown in FIG. 8A or 8B, the preliminary detection voltage Vsn reaches the reference voltage Vref before the voltages Vd1 and Vdn reach the reference voltage Vref. When the voltage value of the preliminary detection voltage Vsn exceeds the reference voltage Vref, the preliminary detection unit PD inverts the logical value of the preliminary voltage detection signal Vs. This turns on the switch 38 of the bias circuit 30B, increasing the bias voltage Vbn supplied to the gate of the transistor 22. Therefore, the transistor 22, which receives the bias voltage Vbn, increases its operating current IA.

[0111] That is, in the voltage detection circuit 100_3, when the voltages Vd1 and Vdn as the detection target voltages approach the reference voltage Vref due to voltage fluctuations, the operating current IA is increased from a low current standby state to a normal rated current active state, thereby improving the responsiveness of the detection operation.

[0112] On the other hand, when the voltages Vd1 and Vdn are far from the reference voltage Vref, that is, when the difference between the two is large, the voltage detection circuit 100_3 enters a standby state in which the operating current IA is forcibly reduced, thereby reducing the static current consumption.

[0113] In addition, the voltage detection circuit 100_3 in Figure 7 is a configuration example in which the bias voltage Vbn is switched in response to the preliminary voltage detection signal Vs, thereby switching the operating current IA flowing through the transistor 22. However, it is also possible to provide another transistor connected in parallel with the transistor 22 and control its activation / deactivation to variably control the operating current of the self-bias unit and each detection unit.

[0114] FIG. 9 is a circuit diagram showing a configuration of a voltage detection circuit 100_3A as a modified example of the voltage detection circuit 100_3, which has been made in consideration of the above points.

[0115] In the voltage detection circuit 100_3A, except that a current control circuit 41A is employed instead of the current control circuit 41, other configurations (19, SB, PD, U1 to Un, 40) are similar to those of the voltage detection circuit 100_3 shown in FIG.

[0116] The current control circuit 41A includes a transistor 22B and a switch 23B in addition to the bias circuit 30 and the transistor 22 similar to those of the voltage detection circuit 100_1. The transistor 22B has its drain connected to the node ng2 via the switch 23B, receives the power supply voltage VSS at its source, and receives the bias voltage Vbn from the bias circuit 30 at its gate.

[0117] Switch 23B receives standby voltage detection signal Vs and is set to an ON or OFF state according to the logical value of this standby voltage detection signal Vs. At this time, when switch 23B is in the OFF state, transistor 22B is inactivated, and the operating current IA of the self-bias unit and each detection unit is the current flowing through transistor 22. On the other hand, when switch 23B is in the ON state, transistor 22B is activated, and the operating current IA of the self-bias unit and each detection unit is the sum of the current flowing through transistor 22 and the current flowing through transistor 22B.

[0118] That is, while switch 23B is in the OFF state, transistor 22 generates an operating current I A that is lower than the rated current, and while switch 23B is in the ON state, transistors 22 and 22B generate a normal operating current I A that is equal to the rated current. Note that transistor 22B may be configured with any m number of parallel transistors.

[0119] Moreover, the operating currents of the self-bias section and each detection section in the voltage detection circuit 100_3A can be variably controlled as shown in FIGS. 8A and 8B, similarly to the voltage detection circuit 100_3. Example 4

[0120] FIG. 10A is a circuit diagram showing a configuration of a voltage detection circuit 100_4 according to a fourth embodiment of the present invention.

[0121] The voltage detection circuit 100_4 performs voltage detection to detect whether or not a voltage Vd of one system as a detection target voltage is higher than a first and a second threshold voltage having different voltage values, and outputs voltage detection signals Voa and Vob that individually represent each detection result.

[0122] The voltage detection circuit 100_4 has the same configuration (19, 22, 30, SB) as the voltage detection circuit 100_1 shown in FIG. 2, except that two systems of detection units U1_B and U2_B are employed instead of the detection units U1 to Un shown in FIG.

[0123] The detection unit U1_B includes a P-channel transistor 11a, an N-channel transistor 12a, a P-channel transistor 13a, and an N-channel transistor 14a.

[0124] The gates of transistors 11a and 12a are connected to each other, and the drains are connected to each other. Transistor 13a has its drain connected to the source of transistor 11a, its gate connected to node nd0, and its source receiving the main power supply voltage VDD. Transistor 14a has its drain connected to the source of transistor 12a, its gate connected to node nd0, and its source connected to node ng2. Note that detection unit U2_B has a configuration similar to that of detection unit U1_B, and includes a P-channel transistor 11b, an N-channel transistor 12b, a P-channel transistor 13b, and an N-channel transistor 14b.

[0125] The detection units U1_B and U2_B receive a common voltage Vd, which is the object of voltage detection, at the junction between the gates of the transistors 11a and 12a and the junction between the gates of the transistors 11b and 12b included in each unit, and output voltage detection signals Voa and Vob from the junction between the drains of the transistors 11a and 12a and the junction between the drains of the transistors 11b and 12b, respectively.

[0126] The drain of transistor 22 acting as a current source is connected to the source of transistor 14A included in self-bias unit SB, the source of transistor 14a included in detection unit U1_B, and the source of transistor 14b included in detection unit U2_B. Transistor 22 receives bias voltage Vbn generated by bias circuit 30 at its gate, and passes operating current IA having a magnitude corresponding to bias voltage Vbn to self-bias unit SB and detection units U1_B and U2_B.

[0127] In the voltage detection circuit 100_4, the ratio of the channel width W to the channel length L (hereinafter referred to as the W / L size ratio) of the transistor 13a included in the detection unit U1_B is set smaller than the W / L size ratio of the transistor 13A included in the self-bias unit SB. Alternatively, the W / L size ratio of the transistor 13b included in the detection unit U2_B is set larger than the W / L ratio of the transistor 13A included in the self-bias unit SB. Here, the targets for which the W / L size ratio is set variably are transistors of the same conductivity type that commonly receive the self-bias voltage Vsb.

[0128] As a result, the current values ​​controlled by transistors 13A, 13a, and 13b of self-bias unit SB and detection units U1_B and U2_B, respectively, relative to the common self-bias voltage Vsb are such that the control current for transistor 13a is smaller than the control current for transistor 13A, and the control current for transistor 13b is larger than the control current for transistor 13A. Meanwhile, the control currents for transistors 14A, 14a, and 14b are equal. By shifting the control current values ​​on the current inflow side (13A, 13a, 13b) and outflow side (14A, 14a, 14b) in this way, the threshold voltages at which the logic values ​​of voltage detection signals Voa and Vob switch with respect to voltage Vd can be shifted from reference voltage Vref.

[0129] Here, for the other transistors (11a, 12a, 14a, 11b, 12b, 14b) included in the detection units U1_B and U2_B, it is not necessary to change the W / L size ratio. As described above, as a transistor for changing the threshold voltage at which the logical value of the voltage detection signal changes by changing the W / L size ratio of the transistor, a transistor that receives the self-bias voltage Vsb at the gate is preferable.

[0130] FIG. 10B is a diagram showing voltage detection signals (Voa, Vob) that output logical values corresponding to changes in the voltage Vd and the threshold voltages at which the logical values of the voltage detection signals (Voa, Vob) invert, for each of the three W / L size ratios of the transistor 13A in the self-bias unit SB shown in FIG. 10A, the transistor 13a in the detection unit U1_B, and the transistor 13b in the detection unit U2_B.

[0131] That is, in the first W / L size ratio shown in FIG. 10B, the transistors 13A, 13a, and 13b all have a predetermined standard size, and at this time, when the voltage Vd coincides with the reference voltage Vref, both the voltage detection signals Voa and Vob logically invert.

[0132] Also, in the second W / L size ratio shown in FIG. 10B, only the W / L size ratio of the transistor 13a is smaller than that of the other transistors, and at this time, when the voltage Vd coincides with the first reference voltage Vrefa (Vrefa < Vref) which is lower than the reference voltage Vref, the voltage detection signal Voa logically inverts.

[0133] Also, in the third W / L size ratio shown in FIG. 10B, only the W / L size ratio of the transistor 13b is larger than that of the other transistors, and at this time, when the voltage Vd coincides with the second reference voltage Vrefb (Vrefb > Vref) which is higher than the reference voltage Vref, the voltage detection signal Vob logically inverts.

[0134] Thus, in the voltage detection circuit 100_4, by making the W / L size ratios of the transistors (13a, 13b) of each detection unit different from that of the transistor (13A) of the self-bias unit SB, the magnitude of one system of voltage Vd to be detected can be detected stepwise with a plurality of threshold voltages (Vrefa, Vrefb).

[0135] FIG. 10C is a waveform diagram showing simulation results of the reference voltage Vref, the threshold voltages (Vrefa, Vrefb), and the voltage detection signals Voa and Vob with respect to the change in the voltage Vd to be detected in a configuration where the W / L size ratios as shown in FIG. 10A are set.

[0136] Here, if the W / L size ratio of the transistor 13a that receives the self-bias voltage Vsb at the gate is made smaller than that of other transistors, the threshold voltage can be shifted to the first reference voltage Vrefa that is lower than the reference voltage Vref. On the other hand, if the W / L size ratio of the transistor 13b that receives the self-bias voltage Vsb at the gate is made larger than that of other transistors, the threshold voltage can be shifted to the second reference voltage Vrefb that is higher than the reference voltage Vref.

[0137] Thereby, for example, based on the logic values of the voltage detection signals Voa and Vob with respect to the change in one system of voltage Vd, it is possible to determine whether the voltage Vd is within the voltage range near the reference voltage Vref (Vrefa < Vref < Vrefb). Such determination can prevent frequent switching of the logic value due to noise when the voltage Vd includes noise. Also, for example, when the change in the voltage Vd is rising, determination can be made using the voltage detection signal Vob, and when the change in the voltage Vd is falling, determination can be made using the voltage detection signal Voa, thereby making a determination with hysteresis. In FIG. 10C, the reference voltages Vrefa and Vrefb that are deviated from the reference voltage Vref are described, but of course, one of the voltages Vrefa and Vrefb may be configured to be the reference voltage Vref.

Example 5

[0138] FIG. 11 is a circuit diagram showing a configuration of a voltage detection circuit 100_5 according to the fifth embodiment of the present invention.

[0139] The voltage detection circuit 100_5 detects an abnormal voltage drop or voltage rise of the power supply voltage VSP as the voltage to be detected in n (n is an integer of 2 or more) stages, and outputs a signal indicating the detection result for each stage as a voltage detection signal Vo1 to Von.

[0140] The voltage detection circuit 100_5 includes the voltage detection circuit 100_1 shown in Fig. 2 as a voltage detection unit SBC. Furthermore, the voltage detection circuit 100_5 includes a resistor string LD that generates voltages Vd1 to Vdn corresponding to the n threshold voltages separating the above-mentioned n stages, and supplies the voltages Vd1 to Vdn to the detection units U1 to Un individually.

[0141] The resistor string LD receives the power supply voltage VSP to be detected at one end thereof, and receives the power supply voltage VSS (for example, 0 volts) at the other end thereof.

[0142] Here, if the resistance value of the entire resistor string LD is a resistance value R0, and the resistance value in the resistor string LD from the tap for extracting the voltage Vd1 to the power supply voltage VSS is a resistance value R1, the voltage Vd1 is expressed as follows: Vd1=VSP(R1 / R0) (1) It is expressed as:

[0143] Here, if the voltage value of the power supply voltage VSP that is determined to have dropped is VSPe, and the threshold voltage that is determined to have dropped from the voltage value of the voltage Vd1 to VSPe is Vde1, then Vde1 is given by: Vde1=VSPe(R1 / R0)=Vref This means that VSPe is VSPe=Vref*(R0 / R1) (2) It is expressed as:

[0144] For example, if the power supply voltage VSP is 10 volts, the reference voltage Vref is 1 V, and VSPe is 5 V, and you want to set it so that if the power supply voltage VSP drops to 5 V as indicated by VSPe, it is detected as an abnormally low voltage, then: From equation (2), 5=(R0 / R1) (3) And According to equations (1) and (3), Vd1=10V / 5=2V Therefore, when the power supply voltage VSP=10V drops below VSPe=5V, which is the voltage value that is determined to be an abnormally low voltage, the voltage Vd1 set by the resistance value R1 drops from the initial value of 2V, and when it falls below the reference voltage Vref (threshold voltage Vde1)=1V, the logical value of the voltage detection signal Vo1 is inverted, and an abnormally low voltage is detected.

[0145] Incidentally, by providing the resistor string LD in the voltage detection circuits 100_1A, 100_2, 100_3, 100_3A or 100_4, a function similar to that of the power supply voltage detection circuit 100_5 shown in FIG. 11 may be realized. Example 6

[0146] FIG. 12 is a circuit diagram showing a configuration of a voltage detection circuit 100_6 according to the sixth embodiment of the present invention.

[0147] The voltage detection circuit 100_6 simultaneously detects abnormal voltage drops or abnormal voltage rises in n (n is an integer of 2 or more) power supply voltages as the voltages to be detected, and outputs signals indicating the detection results corresponding to the n power supply voltages as voltage detection signals Vo1 to Von.

[0148] The voltage detection circuit 100_6 includes the voltage detection circuit 100_1 shown in FIG. 2 as it is as a voltage detection unit SBC.

[0149] Furthermore, the voltage detection circuit 100_6 includes first to n-th resistor strings LD1 to LDn that individually receive the above-mentioned n power supply voltages, and supplies the received power supply voltages individually divided as voltages Vd1 to Vdn to the detection units U1 to Un. For example, in the example shown in Fig. 12, the resistor string LD1 receives a power supply voltage VSP and supplies a voltage obtained by dividing the power supply voltage VSP to the detection unit U1 as voltage Vd1. Furthermore, the resistor string LDn receives a power supply voltage VGH and supplies a voltage obtained by dividing the power supply voltage VGH to the detection unit Un as voltage Vdn.

[0150] Incidentally, by providing the resistor strings LD1 to LDn in the voltage detection circuits 100_1A, 100_2, 100_3, 100_3A or 100_4, a function similar to that of the voltage detection circuit 100_6 shown in FIG. 12 may be realized.

[0151] As described above in detail, the voltage detection circuits 100_1 to 100_6 (excluding 100_4) compare the magnitude of the reference voltage Vref with that of the first to nth (n is an integer equal to or greater than 2) voltages Vd1 to Vdn to be detected, and employ the following configuration to generate the first to nth voltage detection signals Vo1 to Von indicating whether or not each is higher than the reference voltage.

[0152] That is, the voltage detection circuit of the present invention has a self-bias section (SB, SB_A) that generates a self-bias voltage (Vsb) based on a reference voltage (Vref), and first to nth detection sections (U1 to Un, U1_A to Un_A) that individually receive first to nth voltages (Vd1 to Vdn) and individually output first to nth voltage detection signals (Vo1 to Von).

[0153] The self-bias section has the following first to fourth transistors.

[0154] The first and second transistors (11A, 12A) are of different conductivity types, and their drains are connected via a first node (nd0). Their gates receive a reference voltage (Vref), generating a voltage at the first node as a self-bias voltage (Vsb). The third transistor (13A) receives the self-bias voltage (Vsb) at its gate and supplies a current corresponding to the difference between its source voltage and the self-bias voltage to the source of the first transistor (11A). The fourth transistor (14A) receives the self-bias voltage (Vsb) at its gate and supplies a current corresponding to the difference between its source voltage and the self-bias voltage to the source of the second transistor (12A).

[0155] Each of the first to n-th detection units has the following fifth to eighth transistors.

[0156] The fifth and sixth transistors (11, 12) are of different conductivity types, have their drains connected together, and receive one of the first to n-th voltages at their gates, thereby outputting the voltage generated at their drains as one of the first to n-th voltage detection signals (Vo1 to Von). The seventh transistor (13) receives the self-bias voltage (Vsb) at its gate and supplies a current corresponding to the difference between the voltage at its source and the self-bias voltage to the source of the fifth transistor (11). The eighth transistor (14) receives the self-bias voltage (Vsb) at its gate and supplies a current corresponding to the difference between the voltage at its source and the self-bias voltage to the source of the sixth transistor (12).

[0157] Furthermore, the voltage detection circuit according to the present invention includes at least one current source transistor (21, 22) that generates an operating current (IA) that operates the self-bias units (SB, SB_A) and the first to nth detection units (U1 to Un, U1_A to Un_A).

[0158] In other words, the current source transistor receives a bias voltage (Vbn) at its gate, and generates a drain current based on the difference between the voltage of its source and the bias voltage as an operating current (IA) to be passed through the first to fourth transistors of the self-bias section and the fifth to eighth transistors of each of the first to nth detection sections.

[0159] With this configuration, in the voltage detection circuit according to the present invention, the current source transistor generates the operating current to be passed through the self-bias unit and the first to nth detection units, so that the operating current can be limited to any magnitude regardless of the voltage value of the main power supply voltage, thereby realizing a stable detection operation with low current consumption. For example, when the main power supply voltage (VDD) is high, it is possible to realize a stable detection operation with a steep transition in the logic value of the voltage detection signal in response to a change in the voltage to be detected relative to an arbitrary reference voltage (Vref) within the range of the main power supply voltage and the power supply voltage (VSS). Example 7

[0160] FIG. 13 is a block diagram showing the configuration of a display device 300 including a display driver IC 150 according to a seventh embodiment of the present invention.

[0161] The display device 300 is composed of a display panel 200, a gate driver 160, and a display driver IC 150. The display panel 200 has a GIP (Gate in Panel) structure in which the gate driver 160 is integrally formed with the gate lines, data lines, and display section.

[0162] The display panel 200 includes gate lines GL1 to GLr (r is an integer of 2 or more) wired horizontally on a display section 201 on an insulating substrate such as a glass substrate or a plastic substrate, data lines DL1 to DLm (m is an integer of 2 or more) wired vertically, and pixel cells 210 arranged at the intersections of each gate line and data line. Gate drivers 160 that output gate selection signals to each gate line are arranged at both ends of the panel and are integrally formed as thin-film semiconductor circuits with the pixel cells 210. The gate drivers 160 receive gate control signals supplied from a display driver IC 150, generate gate selection signals to be supplied to each of the gate lines GL1 to GLr, and sequentially output the gate selection signals to each gate line.

[0163] The display driver IC 150 is composed of a semiconductor IC including a control unit 151 with a built-in timing controller, a data driver 120, a gate control circuit 130, a power supply circuit 154, and a voltage detection circuit 155. The display driver IC 150 is mounted directly on the edge of the display panel 200 or mounted via a film. One or more display driver ICs 150 are mounted depending on the resolution of the display panel. Figure 7 shows an example configuration in which one display driver IC 150 is mounted.

[0164] The control unit 151 generates timing signals indicating the timing for applying gate selection signals to the gate lines GL1 to GLr based on externally input video data signals and timing control signals, and supplies these to the gate control circuit .

[0165] In addition, the control unit 151 generates various control signals including clock signals and load signals, and a video data signal including a series of pixel data pieces that represent the brightness level of each pixel as a digital value, based on an externally input video data signal and timing control signal, and supplies this to the data driver 153.

[0166] The gate control circuit 130 receives a timing signal supplied from the control unit 151, level-shifts the signal to a high level using the level shifter 131, amplifies the signal using the buffer 132, outputs it as a gate control signal from the display driver IC 150, and supplies it to the gate drivers 160 formed at both ends of the display panel 200.

[0167] The data driver 120 includes a data latch 121, a level shifter 122, a DA (digital-to-analog) converter (DAC) 123, and an amplifier 124. The data latch 121 captures each of the pixel data pieces included in the video data signal for one horizontal scan line (m pieces) at a time, and supplies the captured m pixel data pieces to the level shifter 122. The level shifter 122 level-shifts the signal levels of the m pixel data pieces to a high level, and supplies the m pixel data pieces to the DA converter 123. The DA converter 123 converts each of the m pixel data pieces into grayscale voltage signals having analog voltage values ​​corresponding to the luminance levels indicated by the respective pixel data pieces. The DA converter 123 supplies the m grayscale voltage signals obtained by this conversion to the amplifier 124. The amplifier 124 individually amplifies the m grayscale voltage signals and supplies them as drive signals to the data lines DL1 to DLm of the display panel 200.

[0168] The power supply circuit 154 receives an externally supplied main power supply voltage VDD and a power supply voltage VSS (e.g., zero volts), and generates a power supply voltage Vdd for the logic circuit based on the main power supply voltage VDD. The power supply circuit 154 also generates a positive polarity positive source power supply voltage VSP and a negative polarity negative source power supply voltage VSN as power supplies for the data driver 120. The power supply circuit 154 also generates a positive polarity positive gate power supply voltage VGP and a negative polarity negative gate power supply voltage VGN as power supplies for the gate control circuit 130, which turn on and off thin film transistors included in the pixel cells 210 of the display panel 200.

[0169] The power supply circuit 154 supplies the above-mentioned power supply voltage Vdd and power supply voltage VSS to the control unit 151 .

[0170] The power supply circuit 154 supplies the gate control circuit 130 with a positive gate power supply voltage VGP and a negative gate power supply voltage VGN, and supplies the data driver 120 with a power supply voltage VSS, a positive source power supply voltage VSP, and a negative source power supply voltage VSN.

[0171] Furthermore, the power supply circuit 154 supplies a power supply voltage Vdd, a power supply voltage VSS, a positive source power supply voltage VSP, a negative source power supply voltage VSN, a positive gate power supply voltage VGP, and a negative gate power supply voltage VGN to the voltage detection circuit 155.

[0172] The voltage detection circuit 155 includes, for example, the voltage detection circuit 100_6 shown in Fig. 12. In this case, the voltage detection circuit 155 receives the above-mentioned power supply voltage Vdd, the positive gate power supply voltage VGP, the positive source power supply voltage VSP, the negative source power supply voltage VSN, and the negative gate power supply voltage VGN individually at one end of each of resistor strings LD1 to LD5 included in the voltage detection circuit 100_9.

[0173] 11. In this case, the voltage detection circuit 155 employs the voltage detection circuit 100_5, which is provided with five resistor strings LD that individually receive the power supply voltage Vdd, the positive gate power supply voltage VGP, the positive source power supply voltage VSP, the negative source power supply voltage VSN, and the negative gate power supply voltage VGN. In this case, five sets of detection units U1 to Un are prepared corresponding to the five resistor strings LD, respectively.

[0174] As a result, the detection units U1 to U5 included in the voltage detection circuit 100_5 or 100_6 have voltage groups obtained by dividing each power supply voltage Vdd, positive gate power supply voltage VGP, positive source power supply voltage VSP, negative source power supply voltage VSN, and negative gate power supply voltage VGN at individual ratios, and output voltage detection signals Vo1 to Vo5 indicating whether the voltage value of each of the divided voltage groups is higher than the reference voltage Vref.

[0175] Here, in the voltage detection circuit 155, the voltage groups obtained by dividing the power supply voltage Vdd, the positive gate power supply voltage VGP, the positive source power supply voltage VSP, the negative source power supply voltage VSN, and the negative gate power supply voltage VGN at individual ratios are divided into a power supply voltage group that is determined to have a voltage abnormality if its voltage value is higher than the reference voltage Vref, and a power supply voltage group that is determined to have a voltage abnormality if its voltage value is equal to or lower than the reference voltage Vref.

[0176] At this time, if the voltage detection circuit 155 determines based on the voltage detection signals Vo1 to Vo5 that a voltage abnormality has occurred in at least one of the positive gate power supply voltage VGP, the positive source power supply voltage VSP, the negative source power supply voltage VSN, and the negative gate power supply voltage VGN, it supplies a voltage abnormality detection signal OUT indicating that a power supply voltage abnormality has occurred to the control unit 151.

[0177] When the control unit 151 receives the voltage abnormality detection signal OUT, it instructs the gate control circuit 130 to output a gate control signal that deactivates the gate driver 160, and also deactivates the data driver 120. This makes it possible to prevent damage and abnormal display due to a power supply voltage abnormality. Furthermore, when the control unit 151 receives the voltage abnormality detection signal OUT, it may also perform control to stop the operation of the power supply circuit 154.

[0178] In addition, the voltage detection circuit 155 may perform the above-mentioned voltage detection for various voltages generated by an internal regulator and other external power supplies in addition to the above-mentioned voltages (Vdd, VGP, VSP, VSN, VGN).

[0179] As described above in detail, the voltage detection circuit according to this embodiment includes a self-bias unit that generates a self-bias voltage based on a reference voltage, and first to nth detection units that receive the self-bias voltage and individually detect whether each of first to nth voltages to be detected is higher than the reference voltage. The voltage detection circuit includes a current source transistor that generates an operating current for operating the self-bias unit and the first to nth detection units and supplies this to the self-bias unit and the first to nth detection units. This reduces static current consumption even when the power supply voltage for operating the self-bias unit and the first to nth detection units is high, thereby making it possible to suppress power consumption. [Explanation of symbols]

[0180] 30 Bias circuit 11-14, 11A-14A, 21, 22 Transistors 100_1~100_6, 100_1A, 100_3A voltage detection circuit SB, SB_A self-bias section U1~Un, U1_A~Un_A detection unit

Claims

1. a voltage detection circuit that compares a reference voltage with a magnitude of each of first to n-th voltages (n is an integer of 2 or more), and outputs first to n-th voltage detection signals that indicate whether or not each of the first to n-th voltages is higher than the reference voltage, a self-bias unit that receives the reference voltage and generates a self-bias voltage based on the reference voltage; first to n-th detection units that receive the first to n-th voltages individually and output the first to n-th voltage detection signals individually; The self-bias unit includes: first and second transistors of different conductivity types, each having a drain connected via a first node and receiving the reference voltage at its gate, thereby generating a voltage generated at the first node as the self-bias voltage; a third transistor that receives the self-bias voltage at its gate and supplies a current corresponding to a difference between a voltage at its source and the self-bias voltage to the source of the first transistor; a fourth transistor that receives the self-bias voltage at its gate and supplies a current corresponding to a difference between a voltage at its source and the self-bias voltage to the source of the second transistor; Each of the first to nth detection units is fifth and sixth transistors of mutually different conductivity types, each having a drain connected to the other, each receiving one of first to n-th voltages at its gate, and outputting a voltage generated at the drain as one of the first to n-th voltage detection signals; a seventh transistor that receives the self-bias voltage at its gate and supplies a current corresponding to a difference between a voltage of its source and the self-bias voltage to the source of the fifth transistor; an eighth transistor that receives the self-bias voltage at its gate and supplies a current corresponding to a difference between a voltage of its source and the self-bias voltage to the source of the sixth transistor; The voltage detection circuit A voltage detection circuit characterized by further comprising at least one current source transistor that receives a bias voltage at its gate and generates a drain current based on the difference between the voltage of its source and the bias voltage as an operating current to be passed through the first to fourth transistors of the self-bias section and the fifth to eighth transistors of each of the first to nth detection sections.

2. a source of the third transistor of the self-bias unit and a source of the seventh transistor of each of the first to n-th detection units are commonly connected via a third node; a source of the fourth transistor of the self-bias unit and a source of the eighth transistor of each of the first to n-th detection units are commonly connected via a fourth node; the first current source transistor receives a first power supply voltage at its source and has its drain connected to one of the third node and the fourth node; 2. The voltage detection circuit according to claim 1, wherein the other of the third node and the fourth node is supplied with a second power supply voltage having a voltage value different from the first power supply voltage.

3. 3. The voltage detection circuit according to claim 2, wherein the reference voltage is set in a voltage range between the first power supply voltage and the second power supply voltage, and is set to a voltage closer to the first power supply voltage to which the one current source transistor is connected.

4. 2. The voltage detection circuit according to claim 1, further comprising first to nth inverter circuits that individually receive the first to nth voltage detection signals and output n voltage detection signals that invert the logical values ​​represented by the first to nth voltage detection signals, wherein each of the first to nth inverter circuits has a transistor inserted in its current path that limits an operating current.

5. a preliminary detection unit that receives a preliminary detection voltage having a voltage value higher or lower than any of the first to n-th voltages, compares the magnitude of the preliminary detection voltage with that of the reference voltage, and outputs a preliminary voltage detection signal indicating whether the preliminary detection voltage is higher than the reference voltage; a current control circuit including the one current source transistor and receiving the standby voltage detection signal; The voltage detection circuit of any one of claims 1 to 3, characterized in that the current control circuit changes the operating current flowing through the first to fourth transistors of the self-bias section and the fifth to eighth transistors of each of the first to nth detection sections when the logical value of the preliminary voltage detection signal changes.

6. The voltage detection circuit of claim 5, wherein the current control circuit changes the bias voltage supplied to the gate of the first current source transistor when the logical value of the preliminary voltage detection signal changes, thereby changing the operating current flowing to the first to fourth transistors of the self-bias section and the fifth to eighth transistors of each of the first to nth detection sections.

7. the current control circuit further comprises another current source transistor connected in parallel with the first current source transistor, and control means for controlling activation and deactivation of the other current source transistor, and when the logical value of the preliminary voltage detection signal changes, switches between activation and deactivation of the other current source transistor, and when the other current source transistor is controlled to be activated, supplies a total current obtained by adding a current flowing through the first current source transistor to a current flowing through the other current source transistor as an operating current to be flowed through the first to fourth transistors of the self-bias section and the fifth to eighth transistors of each of the first to nth detection sections.

8. The preliminary detection unit ninth and tenth transistors of different conductivity types, each having a drain connected to the other, receiving the preliminary detection voltage at its gate, and outputting a voltage generated at the drain as the preliminary voltage detection signal; an eleventh transistor that receives the self-bias voltage at its gate and supplies a current corresponding to a difference between a voltage at its source and the self-bias voltage to the source of the ninth transistor; a twelfth transistor that receives the self-bias voltage at its gate and supplies a current corresponding to a difference between a voltage at its source and the self-bias voltage to the source of the tenth transistor; 6. The voltage detection circuit according to claim 5, further comprising: a current source transistor inserted between the source of the tenth transistor and the drain of the twelfth transistor.

9. The voltage detection circuit according to claim 1 or 2, characterized in that the W / L size ratio of the seventh transistor included in each of the first to nth detection units and receiving the self-bias voltage at its gate is different from the W / L size ratio of the third transistor included in the self-bias unit and receiving the self-bias voltage at its gate.

10. A voltage detection circuit that detects the magnitude of a power supply voltage to be detected in n stages (n is an integer of 2 or more), The self-bias unit and the first to nth detection units according to claim 1, a resistor string that generates the first to n-th voltages having different voltage values ​​by dividing the power supply voltage to be detected by n; A voltage detection circuit characterized in that the logical values ​​of the first to nth voltage detection signals output from the first to nth detection units each represent the magnitude of fluctuation in the power supply voltage to be detected.

11. 2. The voltage detection circuit according to claim 1, further comprising: first to n-th resistor strings that individually receive first to n-th power supply voltages to be detected and generate voltages by dividing the received power supply voltages as the first to n-th voltages.

12. A display driver that drives a display panel in which a plurality of data lines and a plurality of gate lines are arranged crossing each other, a data driver that generates a plurality of drive signals based on a video signal and supplies the drive signals to the plurality of data lines; a gate driver that supplies a gate selection signal to each of the plurality of gate lines; a power supply circuit that generates first to n-th power supply voltages used in the data driver and the gate driver; a voltage detection circuit according to claim 11; a control unit that determines whether or not a voltage abnormality has occurred in at least one of the first to nth power supply voltages based on the first to nth voltage detection signals output from the voltage detection circuit, and stops operation of the data driver and the gate driver when it determines that a voltage abnormality has occurred.

13. a display panel in which a plurality of data lines and a plurality of gate lines are arranged crossing each other; A display device having a display driver that drives the display panel, The display driver a data driver that generates a plurality of drive signals based on a video signal and supplies the drive signals to the plurality of data lines; a gate driver that supplies a gate selection signal to each of the plurality of gate lines; a power supply circuit that generates first to n-th power supply voltages used in the data driver and the gate driver; a voltage detection circuit according to claim 11; a control unit that determines whether or not a voltage abnormality has occurred in at least one of the first to nth power supply voltages based on the first to nth voltage detection signals output from the voltage detection circuit, and stops operation of the data driver and the gate driver when it determines that a voltage abnormality has occurred.

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