Semiconductor device, insulating switch, and rectifying chip

Abstract

To stabilize an operation.SOLUTION: The semiconductor element includes first and second transformers 41A and 41B, first and second rectifier chips 50A and 50B, and a second die pad 221 on which the first and second rectifier chips 50A and 50B are mounted. Each of the first rectifying chip 50A and the second rectifying chip 50B includes the first pad 54A, the second pad 54B, the substrate 571 including the first surface, the first region 573 disposed on the first surface, the transistor 511 disposed in the first region 573 and electrically connected to the first pad 54A, and the second region 582 disposed in the first region 573 and spaced apart from the transistor 511 and electrically connected to the second pad 54B. The second semiconductor region 582 is in contact with the semiconductor substrate 571. The first rectifying chip 50A and the second rectifying chip 50B are arranged apart from each other.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices, isolation switches, and rectifier chips. [Background technology]

[0002] Signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically isolating the primary circuit system from the secondary circuit system are used in various applications such as power supply devices, motor drive devices, etc. One example of a signal transmission device is an isolated gate driver that applies a gate voltage to the gate of a switching element such as a transistor (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-78169

[0004] [overview] 2. Description of the Related Art In a semiconductor device including a primary circuit and a secondary circuit electrically isolated by a transformer, or in an isolation switch using this semiconductor device, the operation may become unstable.

[0005] A semiconductor device according to one aspect of the present disclosure includes a first transformer including a primary coil and a secondary coil, a second transformer including a primary coil and a secondary coil, a first rectifier chip including a first rectifier circuit electrically connected to the secondary coil of the first transformer and controlling a first switch circuit by rectifying an induced current flowing through the secondary coil of the first transformer, a second rectifier chip electrically connected to the secondary coil of the second transformer and including a second rectifier circuit that controls a second switch circuit by rectifying an induced current flowing through the secondary coil of the second transformer, and a semiconductor device on which the first rectifier chip and the second rectifier chip are mounted. a frame, wherein the first rectifier chip and the second rectifier chip each include a first output pad and a second output pad, a semiconductor substrate of a first conductivity type including a first surface, a first semiconductor region of a second conductivity type arranged on the first surface, a transistor provided in the first semiconductor region and electrically connected to the first output pad, and a second semiconductor region of the second conductivity type provided at a position spaced apart from the transistor in the first semiconductor region and electrically connected to the second output pad, the second semiconductor region being in contact with the semiconductor substrate, and the first rectifier chip and the second rectifier chip being arranged at a distance from each other.

[0006] An isolated switch according to one aspect of the present disclosure includes a semiconductor device including a first rectifier chip and a second rectifier chip, a first switch circuit electrically connected to the first rectifier chip, and a second switch circuit electrically connected to the second rectifier chip, wherein the semiconductor device includes a first transformer including a primary coil and a secondary coil, a second transformer including a primary coil and a secondary coil, a first rectifier chip including a first rectifier circuit electrically connected to the secondary coil of the first transformer and configured to control the first switch circuit by rectifying an induced current flowing in the secondary coil of the first transformer, and a second rectifier chip including a first rectifier circuit electrically connected to the secondary coil of the second transformer and configured to control the second switch circuit by rectifying an induced current flowing in the secondary coil of the second transformer. a second rectifier chip including a second rectifier circuit controlling a path; and a first frame on which the first rectifier chip and the second rectifier chip are mounted, wherein the first rectifier chip and the second rectifier chip each include a first output pad and a second output pad, a semiconductor substrate of a first conductivity type including a first surface, a first semiconductor region of a second conductivity type arranged on the first surface, a transistor provided in the first semiconductor region and electrically connected to the first output pad, and a second semiconductor region of the second conductivity type provided at a position spaced apart from the transistor in the first semiconductor region and electrically connected to the second output pad, wherein the second semiconductor region is in contact with the semiconductor substrate, and the first rectifier chip and the second rectifier chip are arranged spaced apart from each other. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block circuit diagram showing a schematic configuration of an isolation switch according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the isolation switch of FIG. [Figure 3] FIG. 3 is a waveform diagram showing the operation of the isolation switch of FIG. [Figure 4] FIG. 4 is a schematic plan view showing an example of the semiconductor device of FIG. [Figure 5] FIG. 5 is a schematic side view of the semiconductor device of FIG. [Figure 6] FIG. 6 is a schematic plan view showing an enlarged portion of the semiconductor device of FIG. [Figure 7] FIG. 7 is a schematic plan view showing an enlarged view of a part of the semiconductor device of FIG. [Figure 8] FIG. 8 is a schematic perspective view showing the transformer chip of FIG. [Figure 9] FIG. 9 is a schematic plan view of the transformer chip of FIG. [Figure 10] FIG. 10 is a schematic plan view showing an enlarged portion of the transformer chip of FIG. [Figure 11] FIG. 11 is a schematic plan view showing a primary coil of the transformer chip of FIG. [Figure 12] FIG. 12 is a schematic plan view showing the secondary coil of the transformer chip of FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of the transformer chip taken along line F13-F13 in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of the transformer chip taken along line F14-F14 in FIG. [Figure 15] FIG. 15 is a schematic plan view showing the rectifying chip of FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view of the rectifying chip of FIG. [Figure 17] FIG. 17 is an explanatory diagram showing the insulating switch of the first embodiment. [Figure 18] FIG. 18 is an explanatory diagram showing an insulating switch of a comparative example. [Figure 19] FIG. 19 is a block circuit diagram showing a schematic configuration of an isolation switch according to the second embodiment. [Figure 20] FIG. 20 is a schematic plan view showing an example of the semiconductor device of FIG. [Figure 21] FIG. 21 is a schematic plan view showing the rectifying chip of FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view of the rectifying chip of FIG. [Figure 23] FIG. 23 is a schematic plan view showing an enlarged portion of the semiconductor device of FIG. [Figure 24] FIG. 24 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 25] FIG. 25 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 26] FIG. 26 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 27] FIG. 27 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 28] FIG. 28 is a schematic plan view showing a semiconductor device according to the third embodiment. [Figure 29] FIG. 29 is a schematic plan view showing the rectifying chip of FIG. [Figure 30] FIG. 30 is a schematic cross-sectional view showing the rectifying chip of FIG. [Figure 31] FIG. 31 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 32] FIG. 32 is a block diagram showing a schematic configuration of an isolation switch according to the fourth embodiment. [Figure 33] FIG. 33 is an explanatory diagram showing the isolation switch of FIG. [Figure 34] FIG. 34 is a schematic plan view showing a semiconductor device according to a modified example.

[0008] [Detailed explanation] Hereinafter, several embodiments of the isolation switch of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying example embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0011] (First embodiment) An isolation switch 100 according to a first embodiment will be described with reference to FIGS. (Schematic configuration of isolation switch) Fig. 1 is a block circuit diagram showing a schematic configuration of an isolation switch 100 according to a first embodiment. Fig. 2 is a circuit diagram showing an example of the isolation switch 100 of Fig. 1. Note that Fig. 2 shows the circuit configuration of one switch circuit 60. Fig. 3 is a waveform diagram showing the operation of the isolation switch 100 of Fig. 2.

[0012] The isolation switch 100 shown in FIG. 1 may be mounted on a device such as a sequencer. The isolation switch 100 may be used as a switch that switches on and off a circuit that supplies a drive voltage VD2 to the load 80. In one example, the isolation switch 100 is connected to a power supply circuit 811. The power supply circuit 811 supplies an operating voltage VD1 to the isolation switch 100. In one example, the operating voltage VD1 is a DC voltage. The isolation switch 100 is connected to a control circuit 812. The control circuit 812 outputs a control signal S1 to the isolation switch 100 for controlling the load 80. The isolation switch 100 may be configured as a single unit. The single unit may include the isolation switch 100, the control circuit 812, and at least one of the power supply circuit 811 and the control circuit 812.

[0013] The isolation switch 100 may include a plurality of switch circuits 60 and a semiconductor device 20 to which the plurality of switch circuits 60 are connected. The plurality of switch circuits 60 may have the same configuration. In FIG. 1, a first switch circuit 60A, a second switch circuit 60B, a third switch circuit 60C, and a fourth switch circuit 60D are shown as the plurality of switch circuits 60. In the following description, when the first to fourth switch circuits 60A to 60D are not distinguished from one another, the first to fourth switch circuits 60A to 60D are simply referred to as switch circuits 60 or each switch circuit 60. Each switch circuit 60 may be configured as a bidirectional switch. The semiconductor device 20 is configured so that each switch circuit 60 can be driven individually.

[0014] The control circuit 812 outputs a plurality of control signals S1 corresponding to the plurality of switch circuits 60. The semiconductor device 20 is configured to turn on / off the corresponding switch circuits 60 in response to the plurality of control signals S1. In one example, the control circuit 812 outputs a first control signal S1A, a second control signal S1B, a third control signal S1C, and a fourth control signal S1D corresponding to the first switch circuit 60A, the second switch circuit 60B, the third switch circuit 60C, and the fourth switch circuit 60D. In the following description, when the first to fourth control signals S1A to S1D are not distinguished from one another, the first to fourth control signals S1A to S1D are simply referred to as the control signal S1 or each control signal S1. The semiconductor device 20 is configured to turn on / off the first to fourth switch circuits 60A to 60D in response to the first to fourth control signals S1A to S1D. It can be said that the semiconductor device 20 includes a drive circuit that drives the first to fourth switch circuits 60A to 60D.

[0015] 1, the first to fourth switch circuits 60A to 60D are respectively connected between a first connection terminal 101 and a second connection terminal 102. The first connection terminal 101 and the second connection terminal 102 may be provided as terminals of a device including the isolation switch 100. The second connection terminal 102 may be called a common terminal, for example.

[0016] The load 80 is connected to the first connection terminal 101 or the second connection terminal 102 depending on the usage mode of the load 80. In Fig. 1, the load 80 includes a first load 80A and a second load 80B.

[0017] In one example, the first load 80A is a load driven in a sink mode. The first load 80A is connected between a high potential terminal 801 that supplies a drive voltage VD2 to the first load 80A and the first connection terminal 101. The second connection terminal 102, which is a common terminal, is connected to a low potential terminal 802 that has a lower potential than the drive voltage VD2. The low potential terminal 802 may be a reference terminal that serves as a reference potential for the drive voltage VD2. The high potential terminal 801 and the low potential terminal 802 may be terminals or cables of a power supply that supplies power to operate the first load 80A. In one example, the low potential terminal 802 may be a ground terminal. In one example, the drive voltage VD2 is 36 V. The drive voltage VD2 may be changed as appropriate. The reference potential is, in one example, 0 V. The potential of the low potential terminal 802 may be changed arbitrarily. When the first switch circuit 60A to which the first load 80A is connected is turned on, a current flows from the first connection terminal 101 to the second connection terminal .

[0018] In one example, the second load 80B is a load driven in a source mode. The second load 80B is connected between the first connection terminal 101 and a low potential terminal 802. The second connection terminal 102, which is a common terminal, is connected to the high potential terminal 801 that supplies the drive voltage VD2. When the second switch circuit 60B to which the second load 80B is connected is turned on, a current flows from the second connection terminal 102 to the first connection terminal 101.

[0019] The semiconductor device 20 may include multiple semiconductor chips. In one example, the semiconductor device 20 may include a pulse chip 30, a transformer chip 40, and multiple rectifier chips 50.

[0020] The pulse chip 30 may include a plurality of pulse generation circuits 31. The pulse chip 30 may include a plurality of pulse generation circuits 31 corresponding to a plurality of switch circuits 60. In one example, the pulse chip 30 may include a first pulse generation circuit 31A, a second pulse generation circuit 31B, a third pulse generation circuit 31C, and a fourth pulse generation circuit 31D. In the following description, when the first to fourth pulse generation circuits 31A to 31D are not to be distinguished from one another, the first to fourth pulse generation circuits 31A to 31D will be simply referred to as pulse generation circuit 31 or each pulse generation circuit 31. The pulse generation circuit 31 generates a drive signal S2 for driving the switch circuit 60.

[0021] The pulse chip 30 may include an oscillator circuit 32. The oscillator circuit 32 outputs a clock signal CLK. The clock signal CLK is, for example, a square wave. The clock signal CLK has a predetermined frequency and a predetermined duty. The oscillator circuit 32 may be configured to change the frequency of the clock signal CLK. The oscillator circuit 32 may also be configured to start and stop outputting the clock signal CLK in response to, for example, an enable signal.

[0022] The first to fourth pulse generating circuits 31A to 31D are configured to output a pulse signal SP based on a clock signal CLK and first to fourth control signals S1A to S1D. The transformer chip 40 may include multiple transformers 41. For example, the transformer chip 40 may include a first transformer 41A, a second transformer 41B, a third transformer 41C, and a fourth transformer 41D. In the following description, when the first to fourth transformers 41A to 41D are not distinguished from one another, the first to fourth transformers 41A to 41D are simply referred to as transformers 41 or each transformer 41. Each transformer 41 includes a primary coil 42 and a secondary coil 43. The primary coils 42 of the first to fourth transformers 41A to 41D are connected to first to fourth pulse generating circuits 31A to 31D. Each transformer 41 is configured to cause an induced current to flow in the secondary coil 43 in response to a pulse signal SP supplied from the pulse generating circuit 31 to the primary coil 42.

[0023] The semiconductor device 20 includes a plurality of rectifier chips 50. For example, the plurality of rectifier chips 50 may include a first rectifier chip 50A, a second rectifier chip 50B, a third rectifier chip 50C, and a fourth rectifier chip 50D. In the following description, when the first to fourth rectifier chips 50A to 50D are not to be distinguished from one another, the first to fourth rectifier chips 50A to 50D will be simply referred to as the rectifier chip 50 or each rectifier chip 50.

[0024] The first to fourth rectifier chips 50A to 50D include first to fourth rectifier circuits 51A to 51D. In the following description, when the first to fourth rectifier circuits 51A to 51D are not distinguished from one another, the first to fourth rectifier circuits 51A to 51D are simply referred to as rectifier circuits 51 or each rectifier circuit 51. The secondary coil 43 of each transformer 41 is connected to each rectifier circuit 51. Each rectifier circuit 51 is configured to control each switch circuit 60 by rectifying the induced current flowing in the secondary coil 43 of the corresponding transformer 41.

[0025] (Electrical configuration of isolation switch) An example of the configuration of the isolation switch 100 will be described with reference to Fig. 2. Fig. 2 shows a configuration for controlling one switch circuit 60.

[0026] The pulse chip 30 includes a plurality of output pads 34. The plurality of output pads 34 may include a first output pad 34A, a second output pad 34B, and a third output pad 34C. The pulse chip 30 includes a pulse generating circuit 31. The pulse generating circuit 31 is connected to the first output pad 34A, the second output pad 34B, and the third output pad 34C.

[0027] The transformer chip 40 includes a transformer 41. The transformer chip 40 may include a plurality of first electrode pads 44 and a plurality of second electrode pads 45. The plurality of electrode pads 44 may include a first input pad 44A, a second input pad 44B, and a third input pad 44C. The plurality of second electrode pads 45 may include a first output pad 45A, a second output pad 45B, and a third output pad 45C.

[0028] The multiple first electrode pads 44 of the transformer chip 40 are electrically connected to the multiple output pads 34 of the pulse chip 30, respectively. The third input pad 44C of the transformer chip 40 is electrically connected to the third output pad 34C of the pulse chip 30. The first input pad 44A of the transformer chip 40 is electrically connected to the first output pad 34A of the pulse chip 30. The second input pad 44B of the transformer chip 40 is electrically connected to the second output pad 34B of the pulse chip 30.

[0029] The primary coil 42 of the transformer 41 includes a first coil 42A and a second coil 42B. The first coil 42A and the second coil 42B are connected to the pulse generating circuit 31. The secondary coil 43 of the transformer 41 includes a first coil 43A and a second coil 43B. The first coil 43A of the secondary coil 43 is electromagnetically coupled to the first coil 42A of the primary coil 42. The second coil 43B of the secondary coil 43 is electromagnetically coupled to the second coil 42B of the primary coil 42.

[0030] The first coil 42A of the primary coil 42 is connected between the third input pad 44C and the first input pad 44A. The second coil 42B of the primary coil 42 is connected between the third input pad 44C and the second input pad 44B.

[0031] The first coil 43A of the secondary coil 43 is connected between the third output pad 45C and the first output pad 45A. The second coil 43B of the secondary coil 43 is connected between the third output pad 45C and the second output pad 45B.

[0032] The pulse generating circuit 31 is configured to generate a first pulse signal SP1 and a second pulse signal SP2 as the pulse signals SP. The pulse generating circuit 31 supplies the first pulse signal SP1 to the first coil 42A. The pulse generating circuit 31 supplies the second pulse signal SP2 to the second coil 42B.

[0033] The pulse generating circuit 31 generates the first and second pulse signals SP1, SP2 at the rising edges of the clock signal CLK. The pulse generating circuit 31 may be configured to generate the first and second pulse signals SP1, SP2 at the falling edges of the clock signal CLK. Alternatively, the pulse generating circuit 31 may be configured to generate the first and second pulse signals SP1, SP2 at both the rising and falling edges of the clock signal CLK.

[0034] In one example, the pulse generating circuit 31 is configured to generate a first pulse signal SP1 while the first control signal S1A is at a first level. The pulse generating circuit 31 is also configured to generate a second pulse signal SP2 while the first control signal S1A is at the first level and for a predetermined period after the first control signal S1A transitions from the first level to a second level different from the first level. The first level may be a level that allows current to flow through the primary coil 42 of the transformer 41, and the second level may be a level that does not allow current to flow through the primary coil 42 of the transformer 41. In one example, the first level may be a higher potential than the second level. In this case, the first level may be referred to as a high level, and the second level may be referred to as a low level.

[0035] (rectifier chip) The rectifier chip 50 may include a plurality of input pads 53 and a plurality of output pads 54. The plurality of input pads 53 may include a first input pad 53A, a second input pad 53B, and a third input pad 53C. The third input pad 53C of the rectifier chip 50 is electrically connected to a third output pad 45C of the transformer chip 40. The third input pad 53C may be referred to as an input reference pad. The first input pad 53A of the rectifier chip 50 is electrically connected to a first output pad 45A of the transformer chip 40. The second input pad 53B of the rectifier chip 50 is electrically connected to a second output pad 45B of the transformer chip 40. The plurality of output pads 54 may include a first output pad 54A and a second output pad 54B. The first output pad 54A and the second output pad 54B are connected to a switch circuit 60.

[0036] The rectifier chip 50 includes a rectifier circuit 51. The rectifier circuit 51 may include transistors 511 to 515, transistors 521 to 527, diodes 531 to 535, capacitors 541 to 545, and resistors 551 to 557. The transistors 511 to 515 may be, for example, npn bipolar transistors. The transistors 521 to 526 may be, for example, n-channel metal oxide semiconductor field effect transistors (MOSFETs). The transistor 527 may be, for example, a p-channel MOSFET. The diode 531 may be, for example, a Zener diode. The diodes 532 to 535 may be, for example, pn junction diodes.

[0037] The base and collector terminals of transistor 511 are connected to the first input pad 53A. The emitter terminal of transistor 511 is connected to the base and collector terminals of transistor 512 and a first terminal of capacitor 541. The second terminal of capacitor 541 is connected to the second input pad 53B. The emitter terminal of transistor 512 is connected to a first terminal of capacitor 542 and a first terminal of resistor 551. The second terminal of capacitor 542 is connected to the first input pad 53A. The second terminal of resistor 551 is connected to the first output pad 54A, the cathode terminal of diode 531, and the drain terminal of transistor 521. The anode terminal of diode 531 is connected to the third input pad 53C. The anode terminal of diode 531 is connected to the second output pad 54B. The source terminal of transistor 521 is connected to the third input pad 53C. The anode terminal of the transistor 521 is connected to the second output pad 54B. The transistor 521 is connected between the first output pad 54A and the second output pad 54B. The third input pad 53C is connected to the second output pad 54B.

[0038] The base terminal and collector terminal of transistor 513 are connected to the second input pad 53B. The emitter terminal of transistor 513 is connected to a first terminal of resistor 552. The second terminal of resistor 552 is connected to a drain terminal of transistor 522, a first terminal of resistor 557, a first terminal of capacitor 545, and a gate terminal of transistor 521. The back gate terminal of transistor 521 is connected to a source terminal of transistor 521. The back gate terminal of transistor 522 is connected to a source terminal of transistor 522. The source terminal of transistor 522, a second terminal of resistor 557, and a second terminal of capacitor 545 are connected to the third input pad 53C and the second output pad 54B.

[0039] The collector terminal of transistor 514 is connected to first input pad 53A. The collector terminal of transistor 514 is connected to a first terminal of capacitor 543, and a second terminal of capacitor 543 is connected to a base terminal of transistor 514. The base terminal of transistor 514 is connected to a first terminal of resistor 553, and a second terminal of resistor 553 is connected to an emitter terminal of transistor 514. The emitter terminal of transistor 514 is connected to a first terminal of resistor 554, and a second terminal of resistor 554 is connected to a gate terminal of transistor 522 and a drain terminal of transistor 524.

[0040] The collector terminal of transistor 515 is connected to second input pad 53B. The collector terminal of transistor 515 is connected to a first terminal of capacitor 544, and a second terminal of capacitor 544 is connected to a base terminal of transistor 515. The base terminal of transistor 515 is connected to a first terminal of resistor 555, and a second terminal of resistor 555 is connected to an emitter terminal of transistor 515. The emitter terminal of transistor 515 is connected to a first terminal of resistor 556, and a second terminal of resistor 556 is connected to a drain terminal of transistor 523.

[0041] The gate terminal of the transistor 523 is connected to the drain terminal of the transistor 523 and the gate terminal of the transistor 524. The back gate terminal of the transistor 523 is connected to the source terminal of the transistor 523. The source terminal of the transistor 523 is connected to the third input pad 53C and the second output pad 54B. The back gate terminal of the transistor 524 is connected to the source terminal of the transistor 524. The source terminal of the transistor 524 is connected to the third input pad 53C and the second output pad 54B.

[0042] The anode terminal of the diode 532 is connected to the third input pad 53C, and the cathode terminal of the diode 532 is connected to the first input pad 53A. The anode terminal of the diode 533 is connected to the third input pad 53C, and the cathode terminal of the diode 533 is connected to the second input pad 53B. The anode terminal of the diode 534 is connected to the first input pad 53A, and the cathode terminal of the diode 534 is connected to the drain terminal of the transistor 525. The anode terminal of the diode 535 is connected to the second input pad 53B, and the cathode terminal of the diode 535 is connected to the drain terminal of the transistor 525. The back gate terminal of the transistor 525 is connected to the source terminal of the transistor 525. The gate terminal and the source terminal of the transistor 525 are connected to the third input pad 53C. The diodes 532 to 525 and the transistor 525 constitute a protection circuit 52A for the input pad 53.

[0043] The transistor 526 is connected between the first output pad 54A and the second output pad 54B. The transistor 527 is connected between the second output pad 54B and the semiconductor substrate 571. The drain terminal of the transistor 526 is connected to the first output pad 54A, and the source terminal of the transistor 526 is connected to the second output pad 54B. The gate terminal and the back gate terminal of the transistor 526 are connected to the source terminal of the transistor 526. The source terminal of the transistor 527 is connected to the second output pad 54B, and the drain terminal of the transistor 527 is connected to the semiconductor substrate 571. The gate terminal and the back gate terminal of the transistor 527 are connected to the source terminal of the transistor 527. The transistors 526 and 527 constitute a protection circuit 52B for the output pad 54.

[0044] (switch circuit) The switch circuit 60 includes switch elements 601 and 602. The switch circuit 60 has a configuration in which a first switch element 601 and a second switch element 602 are connected in series.

[0045] In one example, the switch elements 601 and 602 may be N-channel MOSFETs. Each of the switch elements 601 and 602 includes a source terminal, a drain terminal, a gate terminal, and a back-gate terminal. The gate terminals of the switch elements 601 and 602 are connected to the first output pad 54A of the rectifier circuit 51. The back-gate terminal of the switch element 601 is connected to the source terminal of the switch element 601. The back-gate terminal of the switch element 602 is connected to the source terminal of the switch element 602. The source terminals of the switch elements 601 and 602 are connected to the second output pad 54B of the rectifier circuit 51. The drain terminal of the switch element 601 is connected to the first connection terminal 101, and the drain terminal of the switch element 602 is connected to the second connection terminal 102. Therefore, the switch elements 601 and 602 are connected in series between the first connection terminal 101 and the second connection terminal 102.

[0046] 2 shows a load 80A connected to a first connection terminal 101 of the isolation switch 100. A drive voltage VD2 is supplied to the load 80A. A second connection terminal 102 of the isolation switch 100 is connected to a low potential terminal 802.

[0047] (Isolation switch operation) The operation of the isolation switch 100 will be described with reference to FIGS. The pulse generating circuit 31 generates a first pulse signal SP1 while the control signal S1 is at Hi level. The first pulse signal SP1 is supplied to the first coil 42A of the primary coil 42 of the transformer 41. As a result, a first induced current I21 flowing from the third output pad 45C to the first output pad 45A is generated in the first coil 43A of the secondary coil 43 of the transformer 41. The first induced current I21 generated in the first coil 43A of the transformer 41 flows from the first input pad 53A of the rectifier chip 50 to the transistor 511.

[0048] The transistors 511 and 512 are diode-connected. The transistors 511 and 512 are connected in a forward direction with respect to a first induced current I21 flowing through the first coil 43A of the secondary coil 43 of the transformer 41. The first induced current I21 is rectified by the transistors 511 and 512. The voltages at the emitter terminals of the transistors 511 and 512 are smoothed by the capacitors 541 and 542.

[0049] Furthermore, the pulse generating circuit 31 generates a second pulse signal SP2 in response to the control signal S1. The second pulse signal SP2 is supplied to the second coil 42B of the primary coil 42 of the transformer 41. As a result, a second induced current I22 flowing from the third output pad 45C to the second output pad 45B is generated in the second coil 43B of the secondary coil 43 of the transformer 41.

[0050] The second terminal of the capacitor 542 is connected to the first input pad 53A. The first induced current I21 is supplied to the second terminal of the capacitor 542. The voltage level at the second terminal of the capacitor 542 changes according to the first induced current I21. Meanwhile, the second terminal of the capacitor 541 is connected to the second input pad 53B. The second induced current I22 is supplied to the second terminal of the capacitor 541. The voltage level at the second terminal of the capacitor 541 changes according to the second induced current I22. Therefore, the voltage levels at the second terminals of the capacitors 541 and 542 alternately rise and fall in a complementary manner. Through such an operation, the transistors 511 and 512 and the capacitors 541 and 542 form a two-stage boost circuit. The number of stages of the boost circuit may be changed as appropriate. In one example, the rectifier circuit 51 may include the transistor 511 and the capacitor 541 that form a single-stage boost circuit. Furthermore, the rectifier circuit 51 may include a booster circuit with three or more stages.

[0051] The rectifier circuit 51 makes the voltage at the first terminal of the capacitor 541, i.e., the voltage at the first output pad 54A, higher than the voltages at the third input pad 53C and the second output pad 54B. The rectifier circuit 51 then maintains the voltage at the first output pad 54A at a constant voltage. For example, the constant voltage value may be determined by the reverse voltage of the diode 531. The potential difference between the second output pad 54B and the first output pad 54A is the voltage level of a drive signal S2. The drive signal S2 is supplied to the switch circuit 60. More specifically, the drive signal S2 is supplied as a source-gate voltage of a first switch element 601 and a second switch element 602 included in the switch circuit 60. The transistors 511 and 512, the capacitors 541 and 542, the resistor 551, and the diode 531 constitute a first signal generating circuit 52C that rectifies the first induced current I21 flowing through the secondary coil 43 (first coil 43A) of the transformer 41 and generates the drive signal S2.

[0052] Furthermore, the first induced current I21 is supplied to the collector terminal of the transistor 514. A capacitor 543 is connected between the collector terminal and the base terminal of the transistor 514. A resistor 553 is connected between the base terminal and the emitter terminal of the transistor 514. The capacitor 543 and the resistor 553 increase the voltage of the emitter terminal of the transistor 514 compared to when the collector terminal and the base terminal of the transistor 514 are directly connected. The emitter terminal of the transistor 514 is connected to the gate terminal of the transistor 522 via the resistor 554.

[0053] The transistor 522 is connected between the gate terminal of the transistor 521 and the source terminal of the transistor 521. The voltage at the emitter terminal of the transistor 514 turns on the transistor 522. Therefore, the voltage at the gate terminal of the transistor 521 becomes equal to the voltage at the source terminal of the transistor 521, and the transistor 521 turns off. The first induced current I21 is supplied to the gate terminal of the transistor 522 through the transistor 514 and the resistor 554. Therefore, while the first induced current I21 is generated, the transistor 522 turns on and the transistor 521 is maintained in the off state, and the voltage level Vo of the drive signal S2 is maintained.

[0054] That is, the transistor 514, the capacitor 543, the resistors 553 and 554, and the transistor 522 turn on the transistor 522 by the first induced current I21. When the transistor 522 turns on, the transistor 521 between the first output pad 54A and the second output pad 54B turns off. Therefore, the transistor 514, the capacitor 543, the resistors 553 and 554, and the transistor 522 can be said to form a holding circuit that maintains the voltage level of the drive signal S2.

[0055] The second induced current I22 is supplied to the collector terminal of the transistor 513. The gate terminal of the transistor 513 is connected to the collector terminal of the transistor 513. Therefore, the transistor 513 acts as a diode connected in the forward direction with respect to the second induced current I22. The second induced current I22 is supplied to a first electrode of a capacitor 545 through the transistor 513. The first electrode of the capacitor 545 is connected to the gate terminal of the transistor 521. The supplied second induced current I22 causes the voltage at the first end of the capacitor 545 to become the gate-source voltage of the transistor 521. When the gate-source voltage of the transistor 521 becomes higher than the threshold voltage Vth of the transistor 521, the transistor 521 turns on. Here, while the first induced current I21 is being generated, the transistor 521 is kept off by the transistor 514, the capacitor 543, and the resistors 553 and 554 turning on the transistor 522.

[0056] Then, while the first induced current I21 is not generated but the second induced current I22 is generated, that is, for a predetermined period after the control signal S1 transitions from the first level to the second level, the transistor 521 is turned on by the gate voltage due to the second induced current I22. When the transistor 521 is turned on, the voltage level of the drive signal S2 drops to the voltage level of the second output pad 54B. When the voltage level of the drive signal S2 becomes lower than the threshold voltage of the first switch element 601, the first switch element 601 is turned off, that is, the switch circuit 60 is turned off.

[0057] The second induced current is supplied to the collector terminal of transistor 515. A capacitor 544 is connected between the collector terminal and the base terminal of transistor 515. A resistor 555 is connected between the base terminal and the emitter terminal of transistor 515.

[0058] The emitter terminal of transistor 515 is connected to the drain terminal of transistor 523. The gate terminal of transistor 523 is connected to the drain terminal of transistor 523 and the gate terminal of transistor 524. The drain terminal of transistor 524 is connected to the gate terminal of transistor 522. The source terminals of transistor 523 and transistor 524 are connected to each other and to the second output pad 54B (third input pad 53C). Transistors 523 and 524 form a current mirror circuit. This current mirror circuit operates to cause a current proportional to the current flowing through transistor 523 to flow from the gate terminal of transistor 522. Therefore, when the first induced current I21 is no longer generated, the voltage of the gate terminal of transistor 522 quickly drops, and transistor 522 turns off. When transistor 522 turns off, transistor 521 turns on, and the voltage level of drive signal S2 drops. The transistors 523 and 524 form a circuit that turns off the transistor 522 to keep the transistor 521 off by the second induced current I22 after the first induced current I21 stops.

[0059] The drive signal S2 is supplied to the gate terminals of the first switch element 601 and the second switch element 602 of the switch circuit 60. The source terminals of the first switch element 601 and the second switch element 602 are connected to the second output pad 54B. Therefore, when the drive signal S2 becomes higher than the threshold voltage of the first switch element 601, the first switch element 601 is turned on. At this time, the second switch element 602 functions as a diode whose forward direction is from the first switch element 601 to the second connection terminal 102. As a result, the switch circuit 60 is made conductive. With this conductive switch circuit 60, a current flows from the load 80 through the switch circuit 60 to the low potential terminal 802, and the load 80 is driven.

[0060] (Configuration of semiconductor device) An example of the configuration of the semiconductor device 20 will be described with reference to FIGS. Fig. 4 is a schematic plan view showing an example of the semiconductor device 20. Fig. 5 is a schematic side view of the semiconductor device 20 of Fig. 4. Fig. 6 is a schematic plan view showing an enlarged view of the first lead terminal 212 and the pulse chip 30, which is a part of the semiconductor device 20 of Fig. 4. Fig. 7 is a schematic plan view showing an enlarged view of the rectifier chip 50 and the second lead terminal 222, which is a part of the semiconductor device 20 of Fig. 4.

[0061] 4 and 5, the semiconductor device 20 is a semiconductor device in which multiple semiconductor chips are packaged together. The semiconductor device 20 includes a pulse chip 30, a transformer chip 40, and multiple rectifier chips 50 as semiconductor chips.

[0062] The package format of the semiconductor device 20 is an SO (Small Outline) type, and one example is an SOP (Small Outline Package). The package format of the semiconductor device 20 can be changed as desired. The package format is not limited to an SOP, but may be a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or various similar package structures.

[0063] The semiconductor device 20 includes a first support member 210, a second support member 220, and a sealing resin 230. The pulse chip 30 is mounted on a first support member 210. In one example, the transformer chip 40 is mounted on the first support member 210. A plurality of rectifier chips 50 are mounted on a second support member 220. The sealing resin 230 seals the first support member 210, a portion of the second support member 220, the pulse chip 30, the transformer chip 40, and the rectifier chip 50. In Figures 4 and 5, the sealing resin 230 is indicated by a two-dot chain line for the convenience of explaining the internal structure of the semiconductor device 20.

[0064] The sealing resin 230 is made of an electrically insulating resin material. This resin material may be, for example, a resin containing epoxy resin. This resin material may be colored black or other colors. The sealing resin 230 is formed in the shape of a rectangular plate with its thickness direction aligned with the Z direction. The sealing resin 230 includes an upper sealing surface 231 and a lower sealing surface 232 opposite the upper sealing surface 231. The upper sealing surface 231 and the lower sealing surface 232 are spaced apart from each other in the Z direction. The sealing resin 230 also includes four resin side surfaces 233 to 236 connecting the upper sealing surface 231 and the lower sealing surface 232. The sealing resin 230 includes resin side surfaces 233 and 234 as both end surfaces in the X direction and resin side surfaces 235 and 236 as both end surfaces in the Y direction. The X direction and the Y direction are perpendicular to the Z direction. The X direction and the Y direction are perpendicular to each other. The X direction corresponds to the "second direction." The Y direction corresponds to the “first direction.” In the following description, a plan view means a view from the Z direction.

[0065] The first support member 210 and the second support member 220 are each electrically conductive. The first support member 210 and the second support member 220 are made of a material containing Cu (copper), Fe (iron), etc. The first support member 210 and the second support member 220 are provided across the inside and outside of the sealing resin 230.

[0066] The first support member 210 includes a first die pad 211 disposed within the sealing resin 230, and a plurality of first lead terminals 212 disposed across the inside and outside of the sealing resin 230. The first die pad 211 corresponds to the "second frame." The first lead terminals 212 correspond to the "second leads."

[0067] Both the pulse chip 30 and the transformer chip 40 are mounted on the first die pad 211. In plan view, the first die pad 211 is disposed so that its center in the Y direction is closer to the resin side surface 235 than the center in the Y direction of the sealing resin 230. The first die pad 211 is not exposed from the sealing resin 230. In plan view, the shape of the first die pad 211 is rectangular with the long side direction in the X direction and the short side direction in the Y direction.

[0068] The first lead terminals 212 are arranged spaced apart from one another in the X direction. A portion of each first lead terminal 212 protrudes from the resin side surface 235 toward the outside of the sealing resin 230.

[0069] 4 and 5, the second support member 220 includes a second die pad 221 disposed within the sealing resin 230, and a plurality of second lead terminals 222 disposed across the inside and outside of the sealing resin 230. The second die pad 221 corresponds to the "first frame." The second lead terminals 222 correspond to the "first leads."

[0070] A plurality of rectifier chips 50 are mounted on the second die pad 221. In a plan view, the second die pad 221 is disposed closer to the resin side surface 236 in the Y direction than the first die pad 211. The second die pad 221 is not exposed from the sealing resin 230. In a plan view, the shape of the second die pad 221 is rectangular with the long side direction in the X direction and the short side direction in the Y direction.

[0071] The first die pad 211 and the second die pad 221 are arranged apart from each other in the Y direction. Therefore, the Y direction can also be said to be the arrangement direction of both die pads 211, 221. The dimensions in the Y direction of the first die pad 211 and the second die pad 221 are set depending on the size and number of semiconductor chips to be mounted. The pulse chip 30 and the transformer chip 40 are mounted on the first die pad 211, and the multiple rectifier chips 50 are mounted on the second die pad 221. For this reason, the dimension in the Y direction of the first die pad 211 is larger than the dimension in the Y direction of the second die pad 221.

[0072] The second lead terminals 222 are arranged spaced apart from one another in the X direction. A portion of each second lead terminal 222 protrudes from the resin side surface 236 toward the outside of the sealing resin 230.

[0073] The number of second lead terminals 222 is the same as the number of first lead terminals 212. As can be seen from Fig. 4, the plurality of first lead terminals 212 and the plurality of second lead terminals 222 are arranged in a direction (X direction) perpendicular to the arrangement direction (Y direction) of the first die pad 211 and the second die pad 221. Note that the number of second lead terminals 222 and the number of first lead terminals 212 can each be changed arbitrarily.

[0074] The pulse chip 30, the multiple rectifier chips 50, and the transformer chip 40 are arranged spaced apart from one another in the Y direction. The pulse chip 30, the transformer chip 40, and the multiple rectifier chips 50 are arranged in this order from the first lead terminal 212 to the second lead terminal 222 in the Y direction.

[0075] The multiple rectifier chips 50 are arranged at intervals in the Y direction in a plan view. The multiple rectifier chips 50 can be said to be arranged in the Y direction, which intersects with the X direction in which the pulse chips 30 and the transformer chips 40 are arranged.

[0076] The pulse chip 30 includes an oscillator circuit 32 and multiple pulse generating circuits 31 shown in Fig. 1. In plan view, the pulse chip 30 has a rectangular shape with short and long sides. In plan view, the pulse chip 30 is mounted on the first die pad 211 with the long sides aligned in the X direction and the short sides aligned in the Y direction.

[0077] As shown in FIG. 5, the pulse chip 30 includes a chip top surface 301 and a chip bottom surface 302 opposite to the chip top surface 301. The chip bottom surface 302 of the pulse chip 30 is bonded to the first die pad 211 by a bonding material SD1. The bonding material SD1 may be conductive. Examples of the conductive bonding material SD1 include solder and Ag (silver) paste. The bonding material SD1 may also be insulating. As shown in FIG. 4, a plurality of input pads 33 and a plurality of output pads 34 are arranged on the chip top surface 301 of the pulse chip 30.

[0078] Each of the rectifier chips 50 includes a rectifier circuit 51 shown in FIG. 1. The shape of each of the rectifier chips 50 may be approximately square in plan view. It may be rectangular in shape having multiple short sides and multiple long sides. In plan view, the rectifier chips 50 are arranged along the Y direction.

[0079] 5, each of the multiple rectifier chips 50 includes a chip upper surface 501 and a chip lower surface 502 opposite to the chip upper surface 501. The chip lower surfaces 502 of the multiple rectifier chips 50 are bonded to the second die pad 221 by a bonding material SD3. The bonding material SD3 may be insulating. The bonding material SD3 may also be conductive.

[0080] A plurality of input pads 53 and a plurality of output pads 54 are arranged on the chip upper surface 501 of the plurality of rectifier chips 50. The plurality of input pads 53 are arranged at the ends of the chip upper surface 501 in the Y direction that are closer to the transformer chip 40. The plurality of input pads 53 are arranged in the X direction. The plurality of output pads 54 are arranged at the ends of the chip upper surface 501 in the Y direction that are farther from the transformer chip 40. In other words, the plurality of output pads 54 are arranged closer to the second lead terminals 222.

[0081] The transformer chip 40 includes multiple transformers 41 shown in Fig. 1. In plan view, the shape of the transformer chip 40 is a rectangle having short and long sides. In plan view, the transformer chip 40 is mounted on the first die pad 211 so that the long sides are aligned in the X direction and the short sides are aligned in the Y direction.

[0082] The transformer chip 40 is disposed adjacent to the pulse chip 30 in the Y direction. The transformer chip 40 is disposed closer to the multiple rectifier chips 50 than the pulse chip 30. In other words, the transformer chip 40 is disposed between the pulse chip 30 and the multiple rectifier chips 50 in the Y direction.

[0083] 5, the transformer chip 40 includes a chip upper surface 401 and a chip lower surface 402 opposite to the chip upper surface 401. The chip lower surface 402 of the transformer chip 40 is bonded to the first die pad 211 by a bonding material SD2. The bonding material SD2 may be conductive. Examples of the conductive bonding material SD2 include solder and Ag paste. The bonding material SD2 may also be insulating.

[0084] 4, the transformer chip 40 includes a plurality of first electrode pads 44 and a plurality of second electrode pads 45. The first electrode pads 44 and the plurality of second electrode pads 45 are provided on a chip upper surface 401 of the transformer chip 40.

[0085] A plurality of wires W1 to W4 are connected to each of the pulse chip 30, the transformer chip 40, and the plurality of rectifier chips 50. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor containing, for example, Au (gold), Al (aluminum), Cu, or the like.

[0086] The pulse chip 30 is electrically connected to the first lead terminal 212 by a wire W1. More specifically, the input pads 33 of the pulse chip 30 and the first lead terminals 212 are connected by the wire W1.

[0087] The rectifier chips 50 and the second lead terminals 222 of the second support member 220 are electrically connected to each other by wires W4. More specifically, the output pads 54 of the rectifier chips 50 and the second lead terminals 222 are connected to each other by wires W4.

[0088] The transformer chip 40 is connected to the pulse chip 30 by wire W2. The transformer chip 40 is also connected to the multiple rectifier chips 50 by wire W3. More specifically, the multiple first electrode pads 44 of the transformer chip 40 are connected to the multiple output pads 34 of the pulse chip 30 by wire W2. The multiple second electrode pads 45 of the transformer chip 40 are connected to the multiple input pads 53 of the multiple rectifier chips 50 by wire W3.

[0089] (Details of the first lead terminal) As shown in FIG. 6, the plurality of first lead terminals 212 include first lead terminals 212A to 212J arranged in the X direction.

[0090] The first lead terminals 212A and 212J arranged at both ends in the X direction are connected to the first die pad 211. The first lead terminals 212A and 212J are integrated with the first die pad 211. These first lead terminals 212A and 212J may be called suspension leads.

[0091] The first lead terminals 212A and 212J connected to the first die pad 211 may, for example, be external terminals for applying a predetermined first potential to the circuitry included in the pulse chip 30. The potential of the first lead terminals 212A and 212J may be, for example, 0 V and may be referred to as a first ground GND1. The pulse chip 30 includes input pads 33 connected to the first lead terminals 212A and 212J by wires W1. These input pads 33 of the pulse chip 30 may be referred to as ground pads.

[0092] For example, the first lead terminals 212D to 212G may be input terminals for supplying the control signals S1A to S1D shown in FIG. For example, the first lead terminals 212C and 212H may be input terminals for supplying a predetermined control signal to the pulse chip 30. The predetermined control signal may include an enable signal or the like.

[0093] The first lead terminals 212B and 212I may be power supply terminals for supplying an operating voltage VD1 to the circuitry included in the pulse chip 30. The pulse chip 30 includes input pads 33 connected to the first lead terminals 212B and 212I by wires W1. These input pads 33 may be referred to as power supply pads of the pulse chip 30.

[0094] 6 is an example and may be changed as appropriate. For example, at least one of the first lead terminals 212A, 212J may be spaced apart from the first die pad 211.

[0095] (Details of the connection between the rectifier chip and the second lead terminal) As shown in FIG. 7, the plurality of second lead terminals 222 include second lead terminals 222A to 222J arranged in the X direction.

[0096] The second lead terminals 222B and 222I are connected to the second die pad 221. The second lead terminals 222B and 222I are integrated with the second die pad 221. These second lead terminals 222B and 222I may be called hanging leads.

[0097] The second lead terminal 222 not connected to the second die pad 221 may be a connection terminal to be connected to the switch circuit 60 shown in FIG. The first output pad 54A of the first rectifier chip 50A is electrically connected to the second lead terminal 222A by a wire W4. The second output pad 54B of the first rectifier chip 50A is electrically connected to the second lead terminal 222C by a wire W4. The first output pad 54A of the second rectifier chip 50B is electrically connected to the second lead terminal 222D by a wire W4. The second output pad 54B of the second rectifier chip 50B is electrically connected to the second lead terminal 222E by a wire W4. The first output pad 54A of the third rectifier chip 50C is electrically connected to the second lead terminal 222F by a wire W4. The second output pad 54B of the third rectifier chip 50C is electrically connected to the second lead terminal 222G by a wire W4. The first output pad 54A of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222H by a wire W4. The second output pad 54B of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222J by a wire W4.

[0098] 7 is an example and may be changed as appropriate. For example, at least one of the second lead terminals 222B, 222I may be spaced apart from the second die pad 221.

[0099] (Transchip) An example of the transformer chip 40 will be described with reference to FIGS. In the following description, the direction from the chip lower surface 402 toward the chip upper surface 401 of the transformer chip 40 shown in FIGS. 11 and 12 is referred to as "upward," and the direction from the chip upper surface 401 toward the chip lower surface 402 is referred to as "downward."

[0100] FIG. 8 is a schematic perspective view showing the transformer chip 40 of FIG. 4. FIG. 9 is a schematic plan view of the transformer chip 40 of FIG. 8. In FIG. 9, the transformer 41 and dummy wiring 460 are indicated by dashed lines. FIG. 10 is a schematic plan view showing an enlarged portion of the transformer chip 40 of FIG. 9. FIG. 11 is a schematic plan view showing the primary coil 42 of the transformer chip 40 of FIG. 9. FIG. 11 is a cross-sectional view of the transformer chip 40 taken along the XY plane at a position in the Z direction of the primary coil 42, and shows the connection relationship of the primary coil 42.

[0101] FIG. 12 is a schematic plan view showing the secondary coil 43 of the transformer chip 40 of FIG. 9. FIG. 12 is a cross-sectional view of the transformer chip 40 taken along the XY plane at a position in the Z direction of the secondary coil 43, showing the connection relationship of the secondary coil 43. For convenience, hatching is omitted in FIGS. 11 and 12. FIG. 13 is a schematic cross-sectional view of the transformer chip 40 taken along line F13-F13 in FIG. 9. FIG. 13 shows the cross-sectional structures of the primary coil 42, the secondary coil 43, the dummy wiring 460, the first input pad 44A, and the first output pad 45A. FIG. 14 is a schematic cross-sectional view of the transformer chip 40 taken along line F14-F14 in FIG. 9. FIG. 14 shows the cross-sectional structures of the dummy wiring 460, the third input pad 44C, and the third output pad 45C. For convenience, hatching is omitted for some components in FIGS. 13 and 14.

[0102] As shown in FIGS. 8 and 9, the transformer chip 40 includes a chip top surface 401 and a chip bottom surface 402 opposite the chip top surface 401. The transformer chip 40 also includes multiple chip side surfaces 403 to 406 connecting the chip top surface 401 and the chip bottom surface 402. The chip bottom surface 402 is formed of a semiconductor substrate 410. Multiple electrode pads 44 and 45 are exposed from the chip top surface 401. The first chip side surface 403 and the second chip side surface 404 form both end surfaces of the transformer chip 40 in the X direction. The third chip side surface 405 and the fourth chip side surface 406 form both end surfaces of the transformer chip 40 in the Y direction.

[0103] 9, the transformer chip 40 includes first to fourth transformers 41A to 41D. More specifically, the transformer chip 40 is a semiconductor chip in which the first to fourth transformers 41A to 41D are integrated into a single chip. In the first to fourth transformers 41A to 41D, first coils 42A and 43A and second coils 42B and 43B are alternately arranged. More specifically, in each of the transformers 41A to 41D, the first coils 42A and 43A are arranged closer to the chip side surface 403 than the second coils 42B and 43B, and the second coils 42B and 43B are arranged closer to the chip side surface 404 than the first coils 42A and 43A.

[0104] The first to fourth transformers 41A to 41D are arranged near the center in the Y direction of the chip upper surface 401 in a plan view. The first electrode pad 44 and the second electrode pad 45 are electrically connected to the first to fourth transformers 41A to 41D. The electrode pads 44 and 45 are made of a material containing one or more appropriately selected from titanium (Ti), titanium nitride (TiN), Au, Ag, Cu, Al, and tungsten (W). The electrode pads 44 and 45 are made of a material containing, for example, Al.

[0105] The multiple first electrode pads 44 are arranged closer to the third chip side surface 405 than the first to fourth transformers 41A to 41D in a plan view. In other words, the multiple first electrode pads 44 are arranged between the first to fourth transformers 41A to 41D and the third chip side surface 405 in the Y direction in a plan view.

[0106] Each of the electrode pads 44, 45 has a shape that is long in the X direction when viewed from above, with the plurality of electrode pads 44, 45 arranged. In one example, each of the electrode pads 44, 45 has a rectangular shape with its long side in the X direction and its short side in the Y direction.

[0107] 9 to 12, the multiple first electrode pads 44 are connected to the primary coil 42 of the transformer 41. The primary coil 42 includes a first coil 42A and a second coil 42B. The multiple first electrode pads 44 include a first input pad 44A connected to the first coil 42A, a second input pad 44B connected to the second coil 42B, and a third input pad 44C connected to both the first coil 42A and the second coil 42B. The third input pad 44C is provided as a common pad for the first coil 42A and the second coil 42B.

[0108] The plurality of second electrode pads 45 are connected to the secondary coil 43 of the transformer 41. The secondary coil 43 includes a first coil 43A and a second coil 43B. The plurality of second electrode pads 45 include a first output pad 45A connected to the first coil 43A, a second output pad 45B connected to the second coil 43B, and a third output pad 45C connected to both the first coil 43A and the second coil 43B. The third output pad 45C is provided as a common pad for the first coil 43A and the second coil 43B.

[0109] As shown in FIGS. 8, 13, and 14, the transformer chip 40 includes a semiconductor substrate 410 and an insulating layer 420 formed on the semiconductor substrate 410. In one example, the semiconductor substrate 410 may be a substrate formed from a material containing Si (silicon).

[0110] The semiconductor substrate 410 includes a substrate upper surface 411 and a substrate lower surface 412 opposite to the substrate upper surface 411. The substrate lower surface 412 constitutes the chip lower surface 402 of the transformer chip 40.

[0111] As shown in FIGS. 13 and 14, the insulating layer 420 includes an upper surface 421 and a lower surface 422 facing the opposite side to the upper surface 421. The insulating layer 420 includes a plurality of insulating films 430 stacked in the Z direction from the substrate upper surface 411 of the semiconductor substrate 410. In other words, the Z direction can also be said to be the thickness direction of the insulating layer 420. The Z direction can also be said to be the stacking direction of the insulating films 430. The insulating layer 420 is formed on the substrate upper surface 411 of the semiconductor substrate 410.

[0112] The insulating film 430 includes a first insulating film 431 and a second insulating film 432 formed on the first insulating film 431. The first insulating film 431 may be made of a material including SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. The second insulating film 432 is, for example, an interlayer insulating film. The second insulating film 432 may be made of a material including SiO2 (silicon oxide). The thickness of the second insulating film 432 may be thicker than the thickness of the first insulating film 431. Both the bottom insulating film 433 in contact with the substrate top surface 411 of the semiconductor substrate 410 and the top insulating film 434 may be made of the second insulating film 432.

[0113] (primary coil) 9, the first coil 42A and the second coil 42B of the primary coil 42 are made of first coil wiring 441. The first coil wiring 441 has a ring shape in a plan view, and in one example, may be a circular spiral shape. The first coil wiring 441 may be made of a material containing one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W. In one example, the first coil wiring 441 is made of a material containing Cu.

[0114] An inner end wiring 442 is arranged inside the first coil wiring 441, and an outer end wiring 443 is arranged outside the first coil wiring 441. One end of the first coil wiring 441 is electrically connected to the inner end wiring 442, and the other end of the first coil wiring 441 is electrically connected to the outer end wiring 443.

[0115] The inner end wiring 442 and the outer end wiring 443 are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the inner end wiring 442 and the outer end wiring 443 are made of a material containing Cu. The outer end wiring 443 is configured as an end wiring common to the first coil 42A and the second coil 42B. The outer end wiring 443 may be provided for each of the first coil 42A and the second coil 42B.

[0116] 11 and 13, the inner end wiring 442 is connected to the first input pad 44A by a connection wiring 444. The connection wiring 444 is formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. As shown in Fig. 13, the connection wiring 444 may include a first wiring portion extending in the Z direction so as to penetrate the multiple insulating films 430, and a second wiring portion extending in the Y direction.

[0117] 11 and 14, the outer end wiring 443 is electrically connected to the third input pad 44C by a connection wiring 445. The connection wiring 445 is formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. As shown in Fig. 14, the connection wiring 445 may include a first wiring portion extending in the Z direction so as to penetrate the multiple insulating films 430, and a second wiring portion extending in the Y direction.

[0118] (secondary coil) 10, the first coil 43A and the second coil 43B of the secondary coil 43 include second coil wiring 451. The second coil wiring 451 has a ring shape in a plan view, and in one example, may have a circular spiral shape. The second coil wiring 451 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the second coil wiring 451 is made of a material containing Cu.

[0119] An inner end wiring 452 is arranged inside the area surrounded by the second coil wiring 451, and an outer end wiring 453 is arranged outside the second coil wiring 451. One end of the second coil wiring 451 is electrically connected to the inner end wiring 452, and the other end of the second coil wiring 451 is electrically connected to the outer end wiring 453.

[0120] The inner end wiring 452 and the outer end wiring 453 are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the inner end wiring 452 and the outer end wiring 453 are made of a material containing Cu.

[0121] The outer end wiring 453 is configured as an end wiring common to the first coil 43A and the second coil 43B. The outer end wiring 453 may be provided for each of the first coil 43A and the second coil 43B.

[0122] In plan view, the second coil wiring 451 is formed in the same winding direction as the first coil wiring 441 shown in Fig. 11. In one example, the number of turns of the second coil wiring 451 is the same as the number of turns of the first coil wiring 441. Note that the number of turns of the second coil wiring 451 and the number of turns of the first coil wiring 441 may be different.

[0123] As shown in FIG. 13 , the primary coil 42 and the secondary coil 43 of the transformer 41 are disposed opposite each other in the Z direction. The primary coil 42 and the secondary coil 43 are disposed opposite each other with multiple insulating films 430 interposed therebetween. The primary coil 42 is configured as a conductive layer embedded in one insulating film 430. In one example, the primary coil 42 is embedded in the insulating film 430. The secondary coil 43 is configured as a conductive layer embedded in one of the multiple insulating films 430, which is different from the insulating film 430 in which the primary coil 42 is embedded. In one example, the secondary coil 43 is embedded in an insulating film 430 that is spaced apart from the insulating film 430 in the Z direction. In the Z direction, the secondary coil 43 is located farther from the semiconductor substrate 410 than the primary coil 42. In other words, the secondary coil 43 is located higher than the primary coil 42. Furthermore, the primary coil 42 is located closer to the semiconductor substrate 410 than the secondary coil 43.

[0124] 9, 10, and 12, the transformer chip 40 may include dummy wiring 460. The dummy wiring 460 is provided around the secondary coil 43 of the transformer 41. The dummy wiring 460 may be omitted.

[0125] The dummy wiring 460 includes a first dummy wiring 461, a second dummy wiring 462, and a third dummy wiring 463. The first dummy wiring 461, the second dummy wiring 462, and the third dummy wiring 463 are formed from a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0126] 9 and 10, the first dummy wiring 461 is provided in a region between the first coil 43A and the second coil 43B of the secondary coil 43 in the X direction in a plan view. The first dummy wiring 461 is formed in a pattern different from that of the secondary coil 43. The first dummy wiring 461 may be electrically connected to the outer end wiring 453. The first dummy wiring 461 may be a wiring pattern formed so that no current flows. Note that the first dummy wiring 461 may be electrically connected to at least one of the four outer end wirings 453 shown in FIG. 9.

[0127] 9 and 10, the third dummy wiring 463 is formed so as to surround the secondary coil 43 (first coil 43A and second coil 43B) of the transformer 41 in a plan view. The third dummy wiring 463 is electrically connected to the first dummy wiring 461. The second dummy wiring 462 is formed so as to surround the third dummy wiring 463 in a plan view. The second dummy wiring 462 is independent from the secondary coil 43. In other words, the second dummy wiring 462 is not electrically connected to the secondary coil 43.

[0128] 14, the first dummy wiring 461 is disposed in the same position in the Z direction as the second dummy wiring 462 and the third dummy wiring 463. As shown in Fig. 13, the second dummy wiring 462 and the third dummy wiring 463 are disposed in the same position in the Z direction as the secondary coil 43. Therefore, the first dummy wiring 461, the second dummy wiring 462, and the third dummy wiring 463 are disposed in the same position in the Z direction as the secondary coil 43.

[0129] The first dummy wiring 461 has the same voltage as the secondary coil 43, thereby suppressing a voltage drop between the secondary coil 43 and the first dummy wiring 461. Therefore, electric field concentration on the secondary coil 43 can be suppressed. The third dummy wiring 463 has the same voltage as the secondary coil 43, thereby suppressing a voltage drop between the secondary coil 43 and the third dummy wiring 463. Therefore, electric field concentration on the secondary coil 43 can be suppressed. The second dummy wiring 462 can suppress an increase in electric field strength around the secondary coil 43.

[0130] As shown in FIGS. 9, 10, and 12, the transformer chip 40 may include a fourth dummy wiring 464. The fourth dummy wiring 464 may be omitted. The fourth dummy wiring 464 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The fourth dummy wiring 464 is disposed between the secondary coil 43 and the first electrode pads 44 in a plan view. The fourth dummy wiring 464 extends along the X direction. The fourth dummy wiring 464 is formed along the plurality of first electrode pads 44 in a plan view. The fourth dummy wiring 464 may include a plurality of wirings. The fourth dummy wiring 464 is electrically independent from the secondary coil 43. In other words, the fourth dummy wiring 464 is not electrically connected to the secondary coil 43. The fourth dummy wiring 464 separates the plurality of first electrode pads 44 from the secondary coil 43 .

[0131] As shown in Figures 13 and 14, the transformer chip 40 includes a passivation film 470. The passivation film 470 is formed on the upper surface 421 of the insulating layer 420. The passivation film 470 is a film that protects the insulating layer 420. The passivation film 470 is a surface protection film for the transformer chip 40. The passivation film 470 is formed from a material containing, for example, silicon oxide or silicon nitride. Examples of materials containing silicon nitride include SiN and SiCN. The passivation film 470 forms the chip upper surface 401 of the transformer chip 40.

[0132] The first electrode pad 44 and the second electrode pad 45 are covered with a passivation film 470. The passivation film 470 has openings that expose parts of the first electrode pad 44 and the second electrode pad 45. As a result, the first electrode pad 44 has an exposed surface for connecting a wire. In addition, the second electrode pad 45 has an exposed surface for connecting a wire.

[0133] The transformer chip 40 may include a resin layer 472 formed on a passivation film 470. The resin layer 472 is formed of a material containing, for example, polyimide (PI). The resin layer 472 is separated into an inner resin layer and an outer resin layer by a separation groove. The separation groove is formed so as to surround the transformer 41 in a plan view. The resin layer 472 may include a first opening exposing the first electrode pad 44 and a second opening exposing the second electrode pad 45.

[0134] (rectifier chip) The rectifier chip 50 will be described with reference to FIGS. Fig. 15 is a schematic plan view showing the rectifier chip 50. Fig. 16 is a schematic cross-sectional view of the rectifier chip 50 of Fig. 15. Note that Fig. 16 shows transistors 511 and 521 as circuit elements related to connection with the switch circuit 60 and the load 80. Note that for ease of understanding, Figs. 15 and 16 show the transistor 511 included in the rectifier circuit 51 shown in Fig. 2, and omit the transistor 512 and resistor 551 between the transistor 511 and the first output pad 54A.

[0135] The rectifier chip 50 may have a rectangular shape in a plan view. The rectifier chip 50 includes a chip top surface 501 and a chip bottom surface 502 opposite the chip top surface 501. The rectifier chip 50 includes multiple chip side surfaces 503 to 506 connecting the chip top surface 501 and the chip bottom surface 502. The chip bottom surface 502 is formed of a semiconductor substrate 571. The input pads 53 and the output pads 54 are exposed from the chip top surface 501. The first chip side surface 503 and the second chip side surface 504 form both end surfaces of the transformer chip 40 in the Y direction. The third chip side surface 505 and the fourth chip side surface 506 form both end surfaces of the transformer chip 40 in the X direction.

[0136] The rectifier chip 50 includes a plurality of input pads 53 and a plurality of output pads 54 on a chip top surface 501. The chip top surface 501 corresponds to the "first main surface" of the rectifier chip 50. The plurality of input pads 53 are arranged closer to the chip side surface 503. The plurality of input pads 53 are arranged along the chip side surface 503. It can be said that the plurality of input pads 53 are arranged in the Y direction.

[0137] The multiple input pads 53 include a first input pad 53A, a second input pad 53B, and a third input pad 53C. The third input pad 53C corresponds to the third input pad 53C shown in Figure 2. The first input pad 53A corresponds to the first input pad 53A shown in Figure 2. The second input pad 53B corresponds to the second input pad 53B shown in Figure 2.

[0138] The multiple output pads 54 include a first output pad 54A and a second output pad 54B. The first output pad 54A is arranged closer to the fourth chip side surface 506. The second output pad 54B is arranged closer to the second chip side surface 504.

[0139] 15, the rectifier chip 50 includes a circuit area 561. In Fig. 15, the circuit area 561 is indicated by a dashed line. The circuit area 561 is an area in which the elements of the rectifier circuit 51 shown in Fig. 2 are arranged.

[0140] The circuit region 561 is disposed in the central portion of the rectifier chip 50 in the Y direction. The circuit region 561 has a rectangular shape in which the length in the X direction is longer than the length in the Y direction. A portion of the circuit region 561 is recessed. For example, the circuit region 561 includes a recessed portion 562 near the corner between the third chip side surface 505 and the second chip side surface 504. The recessed portion 562 may be a portion of the circuit region 561 closer to the third chip side surface 505 and closer to the second chip side surface 504. The first output pad 54A is disposed in the recessed portion 562 of the circuit region 561. It can be said that a portion of the circuit region 561 is recessed, and the first output pad 54A is disposed in the recessed space of the circuit region 561.

[0141] As shown in Fig. 15, transistors 511 and 521 are arranged in a circuit region 561. In Fig. 15, the transistors 511 and 521 are indicated by dashed lines. The transistors 511 and 521 are elements included in the rectifier circuit 51 shown in Fig. 2. Note that the shapes and positions of the transistors 511 and 521 shown in Fig. 15 are merely examples and are not intended to specify the shapes or positions.

[0142] 15, dashed lines indicate a plurality of wirings 563 connecting the circuit area 561 to the plurality of input pads 53 and the circuit area 561 to the plurality of output pads 54. Note that the plurality of wirings 563 are merely a schematic representation of the connections between the circuit area 561, the plurality of input pads 53, and the plurality of output pads 54, and are not intended to necessarily be connected by wiring.

[0143] Fig. 16 shows an example of the cross-sectional structure of the rectifier chip 50. Fig. 16 schematically shows the cross-sectional structure of the circuit region 561 shown in Fig. 15, more specifically, the cross-sectional structures of the transistors 511 and 521. In Fig. 16, the cross-sectional structure of the transistor 511 is shown to the right of the dashed dotted line, and the cross-sectional structure of the transistor 521 is shown to the left of the dashed dotted line.

[0144] The rectifier chip 50 includes a semiconductor substrate 571. The semiconductor substrate 571 may be a substrate formed from a material containing Si. In one example, the semiconductor substrate 571 may be a Si substrate. In one example, the semiconductor substrate 571 may contain impurities of a first conductivity type (in one example, p-type). The semiconductor substrate 571 includes a substrate upper surface 5711 and a substrate lower surface 5712 opposite to the substrate upper surface 5711. The substrate upper surface 5711 corresponds to a first surface of the semiconductor substrate 571. The substrate lower surface 5712 may constitute the chip lower surface 502 of the rectifier chip 50.

[0145] The rectifier chip 50 includes a semiconductor layer 572 disposed on a semiconductor substrate 571 . For example, the semiconductor layer 572 may be an epitaxial layer. The semiconductor layer 572 may be formed of a material containing Si. The semiconductor layer 572 may contain a predetermined impurity. For example, the semiconductor layer 572 may contain an impurity of a first conductivity type (for example, p-type).

[0146] A first semiconductor region 573 is provided in the semiconductor layer 572. The first semiconductor region 573 is a region in which the transistor 511 is formed. The first semiconductor region 573 may contain impurities of a second conductivity type (n-type, for example).

[0147] The first semiconductor region 573 may include an epitaxial layer 574, a buried layer 575 disposed between the epitaxial layer 574 and the semiconductor substrate 571, a collector contact region 576 in contact with the buried layer 575, and a contact region 577 provided in the collector contact region 576. The first semiconductor region 573 may be a collector region.

[0148] A base region 578 is disposed on a surface 5731 of the first semiconductor region 573. The base region 578 may be, for example, a region containing impurities of a first conductivity type. A base contact 579 and an emitter region 580 are disposed in the base region 578. The base contact 579 may be a region containing impurities of the first conductivity type. The emitter region 580 may be, for example, a region containing impurities of a second conductivity type.

[0149] The rectifier chip 50 includes a well region 581 provided in the semiconductor layer 572. The well region 581 is a region in which the transistor 521 is formed. The well region 581 may contain impurities of a first conductivity type, for example. The rectifier chip 50 includes a source region 582 and a drain region 583. The source region 582 and the drain region 583 are provided in a surface portion of the well region 581. The source region 582 and the drain region 583 may contain impurities of a second conductivity type. The source region 582 and the drain region 583 of the second conductivity type are in contact with the well region 581. For example, the well region 581 of the first conductivity type is in contact with the semiconductor substrate 571 of the first conductivity type. It can be said that the source region 582 and the drain region 583 of the second conductivity type are in contact with the semiconductor substrate 571 of the first conductivity type. At least one of the source region 582 and the drain region 583 can be considered a second semiconductor region of a second conductivity type in contact with the semiconductor substrate 571 of the first conductivity type.

[0150] The well region 581 includes a channel region 584 between a source region 582 and a drain region 583. The rectifier chip 50 includes a gate insulating film 585 and a gate electrode 586 on the channel region 584. The gate electrode 586 faces the channel region 584 with the gate insulating film 585 sandwiched therebetween. The gate insulating film 585 is made of an insulating material such as SiO2 or SiN (silicon nitride). The gate electrode 586 is made of a material containing, for example, conductive polysilicon. The rectifier chip 50 includes a back gate region 587. The back gate region 587 is provided in a surface portion of the well region 581. For example, the back gate region 587 may contain impurities of a second conductivity type.

[0151] An emitter region 580 of the transistor 511 is electrically connected to the first output pad 54A. A base region 578 and a first semiconductor region (collector region) 573 of the transistor 511 are electrically connected to the first input pad 53A (third input pad 53C). A source region 582 of the transistor 521 is electrically connected to the third input pad 53C and the second output pad 54B.

[0152] (Operation of the first embodiment) Next, the operation of the isolation switch 100 of the first embodiment will be described. Fig. 17 is a schematic cross-sectional view showing a connection state between the isolation switch 100 of the first embodiment and loads 80A and 80B. Fig. 17 shows the first rectifier chip 50A and the second rectifier chip 50B included in the isolation switch 100, and the first switch circuit 60A and the second switch circuit 60B connected thereto. Note that Fig. 17 shows a simplified cross-sectional structure of the rectifier chips 50A and 50B in Fig. 16.

[0153] As shown in FIG. 17, the isolation switch 100 is connected to a first load 80A and a second load 80B. The first load 80A is a load driven in a sink mode. A driving voltage VD2 is supplied to a first terminal of the first load 80A, and a second terminal of the first load 80A is connected to a first connection terminal 101. The first load 80A is driven by a first switch circuit 60A that is turned on and off by a first rectifier circuit 51A of the first rectifier chip 50A. The first switch circuit 60A is connected between the first connection terminal 101 and a second connection terminal 102. The second connection terminal 102 is connected to a low potential terminal 802. In one example, the voltage of the low potential terminal 802 is 0V. In one example, the driving voltage VD2 is 36V.

[0154] The first switch circuit 60A includes a first switch element 601 and a second switch element 602. The drain terminal of the first switch element 601 is connected to the first connection terminal 101, and the drain terminal of the second switch element 602 is connected to the second connection terminal 102. The source terminal of the first switch element 601 and the source terminal of the second switch element 602 are connected to each other and to the second output pad 54B of the first rectifier chip 50A. The gate terminal of the first switch element 601 and the gate terminal of the second switch element 602 are connected to each other and to the first output pad 54A of the first rectifier chip 50A. In the first rectifier chip 50A, a first coil 43A of a first transformer 41A is connected between a first input pad 53A and a third input pad 53C.

[0155] The first rectifier chip 50A includes a semiconductor substrate 571 and a semiconductor layer 572 provided on the semiconductor substrate 571. The semiconductor layer 572 includes a first semiconductor region 573 and a second semiconductor region 582. The first semiconductor region 573 includes a transistor 511. An emitter region 580 of the transistor 511 is electrically connected to the first output pad 54A. The second semiconductor region 582 may be, for example, the source region 582 of the transistor 521 shown in FIG. 16. The second semiconductor region 582 is electrically connected to the third input pad 53C and the second output pad 54B.

[0156] The first rectifier circuit 51A of the first rectifier chip 50A generates a drive signal S2 in response to a first induced current I21 generated in the first coil 43A of the first transformer 41A. The drive signal S2 is supplied from the first output pad 54A to the gate terminal of the first switch element 601 and the gate terminal of the second switch element 602. The first switch element 601 and the second switch element 602 are turned on or off in response to the drive signal S2 supplied to their respective gate terminals.

[0157] The second load 80B is a load driven in source mode. A first terminal of the second load 80B is connected to the first connection terminal 101, and a second terminal of the second load 80B is connected to the low potential terminal 802. The second load 80B is driven by a second switch circuit 60B that is turned on and off by the second rectifier chip 50B. The second switch circuit 60B is connected between the first output pad 54A and the second output pad 54B. A drive voltage VD2 is supplied to the second output pad 54B.

[0158] The second switch circuit 60B includes a first switch element 601 and a second switch element 602. The drain terminal of the first switch element 601 is connected to the first connection terminal 101, and the drain terminal of the second switch element 602 is connected to the second connection terminal 102. The source terminal of the first switch element 601 and the source terminal of the second switch element 602 are connected to each other and to a second output pad 54B of the second rectifier chip 50B. The gate terminal of the first switch element 601 and the gate terminal of the second switch element 602 are connected to each other and to a first output pad 54A of the second rectifier chip 50B. In the second rectifier chip 50B, a first coil 43A of a second transformer 41B is connected between a first input pad 53A and a third input pad 53C.

[0159] The second rectifier chip 50B includes a semiconductor substrate 571 and a semiconductor layer 572 provided on the semiconductor substrate 571. The semiconductor layer 572 includes a first semiconductor region 573 and a second semiconductor region 582. The first semiconductor region 573 includes a transistor 511. An emitter region 580 of the transistor 511 is electrically connected to the first output pad 54A. The second semiconductor region 582 may be, for example, the source region 582 of the transistor 521 shown in FIG. 16. The second semiconductor region 582 is electrically connected to the third input pad 53C and the second output pad 54B.

[0160] The second rectifier circuit 51B of the second rectifier chip 50B generates a drive signal S2 in response to a first induced current I21 generated in a first coil 43A of the second transformer 41B. The drive signal S2 is supplied from a first output pad 54A to the gate terminal of a first switch element 601 and the gate terminal of a second switch element 602. The first switch element 601 and the second switch element 602 are turned on or off in response to the drive signal S2 supplied to their respective gate terminals.

[0161] (Comparative Example) Here, an insulating switch 100X will be described as a comparative example of the insulating switch 100 of the first embodiment. Note that the same names and symbols are used for the components of the insulating switch 100X of the comparative example that are similar to those of the insulating switch 100 of the first embodiment.

[0162] FIG. 18 shows a connection state between an isolation switch 100X of the comparative example and loads 80A and 80B. The isolation switch 100X of the comparative example includes one rectifier chip 50X. The rectifier chip 50X of the comparative example includes a first rectifier circuit 51A and a second rectifier circuit 51B.

[0163] The rectifier chip 50X of the comparative example includes a semiconductor substrate 571X and a semiconductor layer 572X provided on the semiconductor substrate 571X. The semiconductor layer 572X includes a first region 51AX in which the first rectifier circuit 51A is provided and a second region 51BX in which the second rectifier circuit 51B is provided. The semiconductor substrate 571X is provided as a common substrate for the first rectifier circuit 51A and the second rectifier circuit 51B.

[0164] Both the first region 51AX and the second region 51BX include a first semiconductor region 573 and a second semiconductor region 582. An emitter region 580 of the transistor 511 provided in the first semiconductor region 573 is electrically connected to the first output pad 54A. The second semiconductor region 582 is electrically connected to the third input pad 53C and the second output pad 54B.

[0165] The isolated switch 100X of this comparative example controls a first switch circuit 60A and a second switch circuit 60B, similarly to the isolated switch 100 of the first embodiment described above. That is, the first rectifier circuit 51A controls the first switch circuit 60A by rectifying the first induced current I21 flowing through the secondary coil 43 of the first transformer 41A. Similarly, the second rectifier circuit 51B controls the second switch circuit 60B by rectifying the first induced current I21 flowing through the secondary coil 43 of the second transformer 41B.

[0166] When the first switch circuit 60A is turned on, the first load 80A is connected between a high potential terminal 801, which is a supply source of the drive voltage VD2, and a low potential terminal 802. Then, a node 603, which is a connection point between the first switch element 601 and the second switch element 602, becomes approximately equal to the potential of the low potential terminal 802. In other words, the potential of the second connection terminal 102 of the isolation switch 100 becomes equal to the potential of the low potential terminal 802.

[0167] Similarly, when the second switch circuit 60B is turned on, the second load 80B is connected between the high potential terminal 801, which is the supply source of the drive voltage VD2, and the low potential terminal 802. Then, the potential of the node 603 between the first switch element 601 and the second switch element 602 becomes approximately equal to the potential of the drive voltage VD2. In other words, the potential of the second connection terminal 102 of the isolation switch 100 becomes equal to the potential of the drive voltage VD2.

[0168] The rectifier chip 50X of this comparative example can be connected to loads 80A and 80B of different drive types. As shown in FIG. 2, the rectifier circuit 51 is configured to rectify the induced current I21 flowing through the secondary coil 43 of the transformer 41 and output a drive signal S2. Therefore, the rectifier circuit 51 does not require an external drive voltage supply. Therefore, in the rectifier chip 50X of the comparative example, the semiconductor substrate 571X is in a floating state.

[0169] The rectifier chip 50X of this comparative example includes a parasitic transistor 516X between the first rectifier circuit 51A and the second rectifier circuit 51B. The parasitic transistor 516X is an npn-type bipolar transistor that uses a semiconductor substrate 571X of a first conductivity type (p-type) as its base and that uses the second semiconductor regions 582 of the first and second rectifier circuits 51A and 51B as its second conductivity type emitter and collector. To explain this in terms of the connection state of the loads 80A and 80B, the parasitic transistor 516X uses the second semiconductor region 582 of the second rectifier circuit 51B as its second conductivity type (n-type) collector and the second semiconductor region 582 of the first rectifier circuit 51A as its second conductivity type emitter.

[0170] In this state, if a fluctuation occurs in the drive voltage VD2, a trigger current is generated in the semiconductor substrate 571X. As described above, because the semiconductor substrate 571X is in a floating state, a current flows to the base of the parasitic transistor 516X, which is the semiconductor substrate 571X. Then, a collector current corresponding to the base current flows in the parasitic transistor 516X. As a result, a current path is formed from the second semiconductor region 582 of the second rectifier circuit 51B through the semiconductor substrate 571X to the second semiconductor region 582 of the first rectifier circuit 51A. This current flowing in the parasitic transistor 516X may continue until the supply of the drive voltage VD2 is stopped. As such, latch-up may occur in the isolated switch 100X of the comparative example.

[0171] In contrast, the isolated switch 100 of the first embodiment includes a first rectifier chip 50A and a second rectifier chip 50B. The first rectifier chip 50A and the second rectifier chip 50B are disposed apart from each other. That is, the semiconductor substrate 571 of the first rectifier chip 50A and the semiconductor substrate 571 of the second rectifier chip 50B are physically separated and not electrically connected. As such, the isolated switch 100 of the first embodiment does not include a parasitic transistor between the second semiconductor region 582 of the first rectifier circuit 51A and the second semiconductor region 582 of the second rectifier circuit 51B. Therefore, the isolated switch 100 of the first embodiment can suppress the occurrence of latch-up. Therefore, the isolated switch 100 of the first embodiment can stabilize its operation.

[0172] The first rectifier chip 50A and the second rectifier chip 50B are bonded to the second die pad 221 by the bonding material SD3. When the insulating bonding material SD3 is used, the semiconductor substrate 571 of the first rectifier chip 50A and the semiconductor substrate 571 of the second rectifier chip 50B are not electrically connected to each other. Therefore, the isolated switch 100 of the first embodiment can suppress the occurrence of latch-up. On the other hand, when the conductive bonding material SD3 is used, the semiconductor substrate 571 of the first rectifier chip 50A and the semiconductor substrate 571 of the second rectifier chip 50B are electrically connected through the bonding material SD3 and the second die pad 221. However, even if a voltage change occurs in the semiconductor substrate 571 of the second rectifier chip 50B due to a fluctuation in the drive voltage VD2, for example, the semiconductor substrate 571 of the first rectifier chip 50A is less likely to be affected. Therefore, the isolated switch 100 of the first embodiment can suppress the occurrence of latch-up. Therefore, the isolation switch 100 of the first embodiment can stabilize its operation.

[0173] (Effects of the first embodiment) The isolation switch 100 of the first embodiment provides the following advantages. (1-1) The isolation switch 100 includes a semiconductor device 20 to which a first switch circuit 60A and a second switch circuit 60B are connected. The semiconductor device 20 includes a first transformer 41A, a second transformer 41B, a first rectifier chip 50A, and a second rectifier chip 50B. The semiconductor device 20 includes a second die pad 221 on which the first rectifier chip 50A and the second rectifier chip 50B are mounted. The first transformer 41A includes a primary coil 42 and a secondary coil 43. The second transformer 41B includes a primary coil 42 and a secondary coil 43. The first rectifier chip 50A includes a first rectifier circuit 51A that is electrically connected to the secondary coil 43 of the first transformer 41A and rectifies an induced current I21 flowing through the secondary coil 43 (first coil 43A) of the first transformer 41A to control the first switch circuit 60A. The second rectifier chip 50B includes a second rectifier circuit 51B that is electrically connected to the secondary coil 43 of the second transformer 41B and controls the second switch circuit 60B by rectifying the induced current I22 flowing in the secondary coil 43 (first coil 43A) of the second transformer 41B.

[0174] The first rectifier chip 50A and the second rectifier chip 50B each include a first output pad 54A and a second output pad 54B, a semiconductor substrate 571 of a first conductivity type including a substrate upper surface 5711, a first semiconductor region 573 of a second conductivity type disposed on the substrate upper surface 5711, a transistor 511 provided in the first semiconductor region 573 and electrically connected to the first output pad 54A, and a second semiconductor region 582 of the second conductivity type provided in the first semiconductor region 573 at a position spaced apart from the transistor 511 and electrically connected to the second output pad 54B. The second semiconductor region 582 is in contact with the semiconductor substrate 571. The first rectifier chip 50A and the second rectifier chip 50B are disposed spaced apart from each other.

[0175] In the isolated switch 100 of the first embodiment, the semiconductor substrate 571 of the first rectifier chip 50A and the semiconductor substrate 571 of the second rectifier chip 50B are physically separated and not electrically connected. As such, the isolated switch 100 of the first embodiment does not include a parasitic transistor between the second semiconductor region 582 of the first rectifier circuit 51A and the second semiconductor region 582 of the second rectifier circuit 51B. Therefore, the isolated switch 100 of the first embodiment can suppress the occurrence of latch-up. Therefore, the isolated switch 100 of the first embodiment can stabilize its operation.

[0176] (1-2) The first rectifier chip 50A and the second rectifier chip 50B are bonded to the second die pad 221 by the bonding material SD3. When the insulating bonding material SD3 is used, the semiconductor substrate 571 of the first rectifier chip 50A and the semiconductor substrate 571 of the second rectifier chip 50B are not electrically connected to each other. Therefore, the isolated switch 100 of the first embodiment can suppress the occurrence of latch-up. On the other hand, when the conductive bonding material SD3 is used, the semiconductor substrate 571 of the first rectifier chip 50A and the semiconductor substrate 571 of the second rectifier chip 50B are electrically connected through the bonding material SD3 and the second die pad 221. However, even if a voltage change occurs in the semiconductor substrate 571 of the second rectifier chip 50B due to a fluctuation in the drive voltage VD2, the semiconductor substrate 571 of the first rectifier chip 50A is less likely to be affected. Therefore, the isolated switch 100 of the first embodiment can suppress the occurrence of latch-up. Therefore, the isolation switch 100 of the first embodiment can stabilize its operation.

[0177] (1-3) The isolation switch 100 includes a semiconductor device 20 to which first to fourth switch circuits 60A to 60D are connected. The semiconductor device 20 includes first to fourth rectifier chips 50A to 50D. The first to fourth rectifier chips 50A to 50D are mounted on a second die pad 221. The first to fourth rectifier chips 50A to 50D are arranged spaced apart from one another. The first to fourth rectifier chips 50A to 50D include first to fourth rectifier circuits 51A to 51D that rectify an induced current I21 flowing through the secondary coils 43 (first coils 43A) of the first to fourth transformers 41A to 41D to control the on / off of the first to fourth switch circuits 60A to 60D. The isolation switch 100 can individually control the first to fourth switch circuits 60A to 60D. This makes it possible to stabilize the operations of the first to fourth rectifier chips 50A to 50D.

[0178] (Second embodiment) An isolation switch 110 according to a second embodiment will be described with reference to FIGS. In the insulating switch 110 of the second embodiment, components common to the insulating switch 100 of the first embodiment are denoted by the same reference numerals as in the above embodiment, and description thereof will be omitted.

[0179] Fig. 19 is a block circuit diagram showing a schematic configuration of an isolation switch 110 according to a second embodiment. Fig. 20 is a schematic plan view showing an example of the semiconductor device 20 of Fig. 19. Fig. 21 is a schematic plan view showing the rectifier chip 50 of Fig. 20. Fig. 22 is a schematic cross-sectional view of the rectifier chip 50 of Fig. 21. Fig. 23 is a schematic plan view showing an enlarged portion of the semiconductor device 20 of Fig. 20.

[0180] (Schematic configuration of isolation switch) 20 , in the isolated switch 110 of the second embodiment, the first rectifier chip 50A is electrically connected to the second lead terminal 222B of the isolated switch 110. The second lead terminal 222B is electrically connected to the third connection terminal 103 shown in FIG. 19 . The third connection terminal 103 may be provided as a terminal of a device including the isolated switch 110. The device including the isolated switch 110 may include multiple third connection terminals 103.

[0181] (Rectification chip configuration) As shown in FIG. 21, the rectifier chip 50 of the second embodiment differs from the rectifier chip 50 of the first embodiment mainly in that it includes substrate connection pads 56.

[0182] Substrate connection pads 56 are provided on the chip top surface 501 which has a circuit area 561 . As shown in FIG. 22 , the substrate connection pad 56 is electrically connected to the semiconductor substrate 571 of the rectifier chip 50. The rectifier chip 50 includes a connection region 591 provided in the semiconductor layer 572. The connection region 591 may, for example, contain impurities of a first conductivity type (p-type). The connection region 591 extends from an upper surface 5721 of the semiconductor layer 572 to the semiconductor substrate 571. The connection region 591 is in contact with the semiconductor substrate 571. The connection region 591 is electrically connected to the semiconductor substrate 571. A contact region 592 is provided on an upper surface 5911 of the connection region 591. The contact region 592 may, for example, contain impurities of the first conductivity type. The contact region 592 is electrically connected to the substrate connection pad 56. Therefore, the semiconductor substrate 571 is electrically connected to the substrate connection pad 56 through the connection region 591 and the contact region 592.

[0183] 21, the rectifier chip 50 of the second embodiment includes a plurality of substrate connection pads 56. The plurality of substrate connection pads 56 may include first substrate connection pads 56A and second substrate connection pads 56B.

[0184] The first substrate connection pads 56A are arranged closer to the first chip side surface 503 of the rectifier chip 50. The second substrate connection pads 56B are arranged closer to the second chip side surface 504 of the rectifier chip 50. Therefore, it can be said that the first substrate connection pads 56A and the second substrate connection pads 56B are arranged on either side of the circuit region 561 in the Y direction.

[0185] The first substrate connection pad 56A is disposed closer to the third chip side surface 505 of the rectifier chip 50. The first substrate connection pad 56A can be said to be disposed at a corner of the rectifier chip 50 formed by the first chip side surface 503 and the third chip side surface 505. The first substrate connection pad 56A is disposed side by side in the X direction with the multiple input pads 53 of the rectifier chip 50. The second substrate connection pad 56B is disposed closer to the fourth chip side surface 506 of the rectifier chip 50. The second substrate connection pad 56B can be said to be disposed at a corner of the rectifier chip 50 formed by the second chip side surface 504 and the fourth chip side surface 506. The second substrate connection pad 56B is disposed side by side in the X direction with the second output pad 54B of the rectifier chip 50. The first substrate connection pad 56A and the second substrate connection pad 56B can be said to be disposed offset in the X direction. The first substrate connection pad 56A and the second substrate connection pad 56B can be said to be disposed at diagonal corners of the rectifier chip 50.

[0186] The multiple substrate connection pads 56 may include a third substrate connection pad 56C. The third substrate connection pad 56C is arranged closer to the second chip side surface 504 of the rectifier chip 50. Therefore, it can be said that the first substrate connection pad 56A and the third substrate connection pad 56C are arranged with the circuit region 561 sandwiched between them in the Y direction. The third substrate connection pad 56C is arranged closer to the third chip side surface 505. It can be said that the second substrate connection pad 56B and the third substrate connection pad 56C are arranged side by side in the X direction closer to the second chip side surface 504.

[0187] Third substrate connection pad 56C is arranged closer to third chip side surface 505 than second output pad 54B. Second substrate connection pad 56B is arranged closer to fourth chip side surface 506 than second output pad 54B. It can be said that second substrate connection pad 56B and third substrate connection pad 56C are arranged with second output pad 54B sandwiched between them. First output pad 54A is arranged closer to third chip side surface 505 than third substrate connection pad 56C. It can be said that third substrate connection pad 56C is arranged between first output pad 54A and second output pad 54B.

[0188] 20 and 23, the first to fourth rectifier chips 50A to 50D are bonded to a first die pad 211. The first to fourth rectifier chips 50A to 50D are arranged along the Y direction.

[0189] 23, the fourth chip side surface 506 of the first rectifier chip 50A faces the third chip side surface 505 of the second rectifier chip 50B in the Y direction. Similarly, the fourth chip side surface 506 of the second rectifier chip 50B faces the third chip side surface 505 of the third rectifier chip 50C in the Y direction. The fourth chip side surface 506 of the third rectifier chip 50C faces the third chip side surface 505 of the fourth rectifier chip 50D in the Y direction.

[0190] The second substrate connection pads 56B of the first rectifier chip 50A are electrically connected to the first substrate connection pads 56A of the second rectifier chip 50B via wires W5A. As a result, the semiconductor substrate 571 of the first rectifier chip 50A is electrically connected to the semiconductor substrate 571 of the second rectifier chip 50B via connection regions 591 shown in FIG. 22 and wires W5A shown in FIG. 23. Similarly, the second substrate connection pads 56B of the second rectifier chip 50B are electrically connected to the first substrate connection pads 56A of the fourth rectifier chip 50D via wires W5A. Furthermore, the second substrate connection pads 56B of the third rectifier chip 50C are electrically connected to the first substrate connection pads 56A of the fourth rectifier chip 50D via wires W5A. Therefore, the semiconductor substrates 571 of the first to fourth rectifier chips 50A to 50D are electrically connected to one another.

[0191] The second substrate connection pads 56B of the first rectifier chip 50A are disposed closer to the fourth chip side surface 506 of the first rectifier chip 50A. The fourth chip side surface 506 of the first rectifier chip 50A faces the third chip side surface 505 of the second rectifier chip 50B. The second substrate connection pads 56B of the first rectifier chip 50A are electrically connected to the first substrate connection pads 56A of the second rectifier chip 50B by wires W5A. The first substrate connection pads 56A of the second rectifier chip 50B are disposed closer to the third chip side surface 505 of the second rectifier chip 50B. Therefore, it can be said that the second substrate connection pads 56B of the first rectifier chip 50A are electrically connected to the first substrate connection pads 56A of the second rectifier chip 50B, which are closer to the first rectifier chip 50A. Furthermore, the first substrate connection pads 56A of the second rectifier chip 50B are electrically connected to the second substrate connection pads 56B of the first rectifier chip 50A that is closer to the second rectifier chip 50B. The same can be said for the connection between the second rectifier chip 50B and the third rectifier chip 50C, and between the third rectifier chip 50C and the fourth rectifier chip 50D.

[0192] (Board connection pad connection) The third substrate connection pad 56C of the first rectifier chip 50A is electrically connected to the second lead terminal 222B by a wire W5B. The first rectifier chip 50A corresponds to the rectifier chip arranged at the first end in the X direction. Therefore, the second lead terminal 222B is electrically connected to the semiconductor substrate 571 of each of the first to fourth rectifier chips 50A to 50D. Therefore, in the insulating switch 110 of the second embodiment, the potential of the semiconductor substrate 571 of each of the first to fourth rectifier chips 50A to 50D can be set by setting the second lead terminal 222B to a desired potential. Furthermore, the potential of the semiconductor substrate 571 of each of the first to fourth rectifier chips 50A to 50D can be stabilized. In one example, the second lead terminal 222B is connected to a low potential terminal 802 shown in FIG. 19. The connection destination of the second lead terminal 222B may be changed as desired. The second lead terminal 222B may be electrically connected to an external terminal that applies a predetermined potential.

[0193] 23, the second lead terminal 222B is integral with the second die pad 221 on which the first to fourth rectifier chips 50A to 50D are mounted. The second lead terminal 222B is electrically connected to the second die pad 221. The second die pad 221 is electrically connected to the second lead terminal 222I. Therefore, the second lead terminal 222I may be electrically connected to an external terminal that applies a predetermined potential. Furthermore, the two second lead terminals 222B and 222I may be electrically connected to external terminals that apply a predetermined potential.

[0194] (Operation of the second embodiment) The semiconductor substrates 571 of the first to fourth rectifier chips 50A to 50D are in a floating state and are physically and electrically separated from one another. By connecting the semiconductor substrates 571 of the first to fourth rectifier chips 50A to 50D to one another, voltage fluctuations on each of the semiconductor substrates 571 can be suppressed.

[0195] The third substrate connection pad 56C of the first rectifier chip 50A is electrically connected to the second lead terminal 222B by a wire W5B. By setting the second lead terminal 222B to a desired potential, the potential of the semiconductor substrate 571 of each of the first to fourth rectifier chips 50A to 50D can be set. In one example, the second lead terminal 222B is connected to the low potential terminal 802. That is, the semiconductor substrate 571 of each of the first to fourth rectifier chips 50A to 50D is set to the potential of the low potential terminal 802 (e.g., 0 V). This makes it possible to further stabilize the operation of the rectifier circuits 51 of the first to fourth rectifier chips 50A to 50D.

[0196] The potential of the semiconductor substrate 571 in a floating state may fluctuate due to the operation of the rectifier circuit 51 or external factors. Large voltage fluctuations in the semiconductor substrate 571 may cause malfunction of the rectifier circuit 51. Therefore, by suppressing the voltage fluctuations in the semiconductor substrate 571, the operation of the rectifier circuit 51 can be made more stable.

[0197] The third substrate connection pad 56C is disposed between the first output pad 54A and the second output pad 54B. The second lead terminal 222B is disposed between the second lead terminal 222A connected to the first output pad 54A and the second lead terminal 222C connected to the second output pad 54B. Therefore, the wire W5B does not intersect with the wire W4 connected to the first output pad 54A and the wire W4 connected to the second output pad 54B in a planar view. This allows for easy connection of the wires W4 and W5B. Wire intersections can increase the thickness of the sealing resin 230 from the chip top surface 501 of the first rectifier chip 50A to the sealing top surface 231 (see FIG. 5) of the sealing resin 230, which can lead to an increase in the size of the semiconductor device. Therefore, by preventing wire intersections, the size of the semiconductor device 20 can be suppressed.

[0198] (Effects of the second embodiment) In addition to the effects of the first embodiment, the insulating switch 110 of the second embodiment has the following effects.

[0199] (2-1) The semiconductor substrates 571 of the first to fourth rectifier chips 50A to 50D are in a floating state and are physically and electrically separated from one another. By connecting the semiconductor substrates 571 of the first to fourth rectifier chips 50A to 50D to one another, voltage fluctuations on each of the semiconductor substrates 571 can be suppressed.

[0200] (2-2) The third substrate connection pad 56C of the first rectifier chip 50A is electrically connected to the second lead terminal 222B by the wire W5B. By setting the second lead terminal 222B to a desired potential, the potential of the semiconductor substrate 571 of each of the first to fourth rectifier chips 50A to 50D can be set. In one example, the second lead terminal 222B is connected to the low potential terminal 802. That is, the semiconductor substrate 571 of each of the first to fourth rectifier chips 50A to 50D is set to the potential of the low potential terminal 802 (e.g., 0 V). This makes it possible to further stabilize the operation of the rectifier circuits 51 of the first to fourth rectifier chips 50A to 50D.

[0201] The potential of the semiconductor substrate 571 in a floating state may fluctuate due to the operation of the rectifier circuit 51 or external factors. Large voltage fluctuations in the semiconductor substrate 571 may cause malfunction of the rectifier circuit 51. Therefore, by suppressing the voltage fluctuations in the semiconductor substrate 571, the operation of the rectifier circuit 51 can be made more stable.

[0202] (2-3) The third substrate connection pad 56C is disposed between the first output pad 54A and the second output pad 54B. The second lead terminal 222B is disposed between the second lead terminal 222A connected to the first output pad 54A and the second lead terminal 222C connected to the second output pad 54B. Therefore, the wire W5B does not intersect with the wire W4 connected to the first output pad 54A and the wire W4 connected to the second output pad 54B in a planar view. This allows for easy connection of the wires W4 and W5B. Wire intersections can increase the thickness of the sealing resin 230 from the chip top surface 501 of the first rectifier chip 50A to the sealing top surface 231 (see FIG. 5 ) of the sealing resin 230, which can lead to an increase in the size of the semiconductor device. Therefore, by preventing wire intersections, the size of the semiconductor device 20 can be suppressed.

[0203] (2-4) The second lead terminal 222B is integral with the second die pad 221 on which the first to fourth rectifier chips 50A to 50D are mounted. The second lead terminal 222B is electrically connected to the second die pad 221. This second die pad 221 is electrically connected to the second lead terminal 222I. Therefore, it is sufficient to apply a predetermined potential to at least one of the second lead terminal 222B and the second lead terminal 222I. In other words, it is sufficient to externally connect at least one of the second lead terminal 222B and the second lead terminal 222I, which increases the degree of freedom in designing the isolation switch 110.

[0204] (Modification of the second embodiment) The second embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment and their description will be omitted.

[0205] 24 to 27 are schematic plan views showing modified semiconductor devices 20. The modified semiconductor devices 20 may be substituted for the semiconductor device 20 of the insulating switch 110 of the second embodiment.

[0206] 24 to 27 show enlarged views of a portion similar to that of FIG. 23, which shows a part of the semiconductor device 20 of the second embodiment. 24, in the semiconductor device 20 of the modified example, the fourth rectifier chip 50D is electrically connected to the second lead terminal 222I. Specifically, the second substrate connection pad 56B of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222I by the wire W5C. The fourth rectifier chip 50D corresponds to the rectifier chip arranged at the first end in the X direction. The semiconductor device 20 of this modified example has the same effects as the semiconductor device 20 of the second embodiment.

[0207] 25, in the semiconductor device 20 of the modified example, the first rectifier chip 50A is electrically connected to the second lead terminal 222B, and the fourth rectifier chip 50D is electrically connected to the second lead terminal 222I. Specifically, the third substrate connection pad 56C of the first rectifier chip 50A is electrically connected to the second lead terminal 222B by a wire W5B. The second substrate connection pad 56B of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222I by a wire W5C. The semiconductor device 20 of this modified example achieves the same effects as the semiconductor device 20 of the second embodiment.

[0208] In addition, in this modified example of the semiconductor device 20, any one of the wires W5A between the first rectifier chip 50A and the second rectifier chip 50B, the wire W5A between the second rectifier chip 50B and the third rectifier chip 50C, and the wire W5A between the third rectifier chip 50C and the fourth rectifier chip 50D may be omitted.

[0209] As shown in FIG. 26, in the semiconductor device 20 of the modified example, the first to fourth rectifier chips 50A to 50D are electrically connected to the second lead terminals, respectively. The first substrate connection pad 56A of the first rectifier chip 50A is electrically connected to the second lead terminal 222A by a wire W6. The first output pad 54A of the first rectifier chip 50A is electrically connected to this second lead terminal 222A by a wire W4. The rectifier circuit 51 of the first rectifier chip 50A is configured to output a drive signal S2 to the first output pad 54A. Therefore, in the first rectifier chip 50A, the potential of the semiconductor substrate 571 can be made equal to the potential of the first output pad 54A, i.e., the potential of the drive signal S2.

[0210] The third substrate connection pad 56C of the second rectifier chip 50B is electrically connected to the second lead terminal 222D by a wire W6. The first output pad 54A of the second rectifier chip 50B is electrically connected to the second lead terminal 222D by a wire W4. The third substrate connection pad 56C of the third rectifier chip 50C is electrically connected to the second lead terminal 222F by a wire W6. The first output pad 54A of the third rectifier chip 50C is electrically connected to the second lead terminal 222F by a wire W4. The third substrate connection pad 56C of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222H by a wire W6. The first output pad 54A of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222H by a wire W4. Therefore, in the second to fourth rectifier chips 50B to 50D, similar to the first rectifier chip 50A, the potential of the semiconductor substrate 571 can be made equal to the potential of the first output pad 54A, that is, the potential of the drive signal S2.

[0211] As shown in FIG. 27, in the semiconductor device 20 of the modified example, the first to fourth rectifier chips 50A to 50D are electrically connected to the second lead terminals, respectively. The second substrate connection pad 56B of the first rectifier chip 50A is electrically connected to the second lead terminal 222C by a wire W6. The second output pad 54B of the first rectifier chip 50A is electrically connected to this second lead terminal 222C by a wire W4. The rectifier circuit 51 of the first rectifier chip 50A is configured to output a drive signal S2 to the second output pad 54B. Therefore, in the first rectifier chip 50A, the potential of the semiconductor substrate 571 can be made equal to the potential of the second output pad 54B.

[0212] The second substrate connection pad 56B of the second rectifier chip 50B is electrically connected to the second lead terminal 222E by a wire W6. The second output pad 54B of the second rectifier chip 50B is electrically connected to the second lead terminal 222E by a wire W4. The second substrate connection pad 56B of the third rectifier chip 50C is electrically connected to the second lead terminal 222G by a wire W6. The second output pad 54B of the third rectifier chip 50C is electrically connected to the second lead terminal 222G by a wire W4. The second substrate connection pad 56B of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222J by a wire W6. The second output pad 54B of the fourth rectifier chip 50D is electrically connected to the second lead terminal 222J by a wire W4. Therefore, in the second to fourth rectifier chips 50B to 50D, the potential of the semiconductor substrate 571 can be made equal to the potential of the second output pad 54B, similar to the first rectifier chip 50A.

[0213] (Third embodiment) An isolation switch 120 according to a third embodiment will be described with reference to FIGS. In the insulating switch 120 of the third embodiment, parts common to the insulating switch 100 of the first embodiment and the insulating switch 110 of the second embodiment are given the same reference numerals as in the above embodiments, and description thereof will be omitted.

[0214] The insulating switch 120 of the third embodiment differs from the insulating switch 100 of the first embodiment in the configuration of the rectifier chip 50F included in the semiconductor device 20. For this reason, portions other than the semiconductor device 20 are omitted from the drawings.

[0215] Fig. 28 is a schematic plan view showing a semiconductor device 20 according to the third embodiment. Fig. 29 is a schematic plan view showing a rectifier chip 50F of Fig. 28. Fig. 30 is a schematic cross-sectional view showing the rectifier chip of Fig. 29.

[0216] The semiconductor device 20 of the third embodiment includes one rectifier chip 50F. In a plan view, the rectifier chip 50F of the third embodiment has a rectangular shape in which the length in the X direction is longer than the length in the Y direction. The rectifier chip 50F includes a chip upper surface 501, a chip lower surface 502, and multiple chip side surfaces 503 to 506.

[0217] The rectifier chip 50F of the third embodiment includes first to fourth chip regions 57A to 57D, a peripheral region 59, and an insulating region 58. The insulating region 58 is a region that separates the first to fourth chip regions 57A to 57D in the rectifier chip 50F. As shown in FIG. 30 , the insulating region 58 penetrates the rectifier chip 50F from the chip upper surface 501 to the chip lower surface 502 of the rectifier chip 50F. The insulating region 58 is made of an insulating material. In one example, the insulating region 58 is made of SiO2. The insulating material that makes up the insulating region 58 can be changed as desired. The insulating region 58 may be made of, for example, a material containing SiN, an insulating resin material, or the like.

[0218] 29, insulating region 58 includes first to fourth insulating regions 58A to 58D that are frame-shaped in plan view and surround first to fourth chip regions 57A to 57D, respectively. In one example, first to fourth insulating regions 58A to 58D may have a rectangular frame shape in plan view. Note that the shape of each of first to fourth insulating regions 58A to 58D in plan view is not limited to a rectangular frame shape and can be changed as desired.

[0219] As shown in FIG. 29, the first insulating region 58A and the second insulating region 58B are integrated. As a result, the insulating region 58 includes a first intermediate insulating region 58M1 that serves as both the first insulating region 58A and the second insulating region 58B. Similarly, the second insulating region 58B and the third insulating region 58C are integrated. As a result, the insulating region 58 includes a second intermediate insulating region 58M2 that serves as both the second insulating region 58B and the third insulating region 58C. Furthermore, the third insulating region 58C and the fourth insulating region 58D are integrated. As a result, the insulating region 58 includes a third intermediate insulating region 58M3 that serves as both the third insulating region 58C and the fourth insulating region 58D.

[0220] The first to fourth chip regions 57A to 57D are partitioned by first to fourth insulating regions 58A to 58D, respectively. The first chip area 57A includes a plurality of input pads 53, a plurality of output pads 54, and a plurality of substrate connection pads 56. The plurality of substrate connection pads 56 may be omitted. The first chip area 57A also includes a circuit area 561 in which a rectifier circuit is configured. That is, the first chip area 57A has a configuration similar to that of the first rectifier chip 50A of the second embodiment. Similarly, the second to fourth chip areas 57B to 57D have configurations similar to those of the second to fourth rectifier chips 50B to 50D of the second embodiment, respectively.

[0221] 30 shows a schematic cross-sectional structure of a first chip region 57A and a second chip region 57B included in a rectifier chip 50F. The first chip region 57A includes a semiconductor substrate 571 and a semiconductor layer 572 on the semiconductor substrate 571. Similarly, the second chip region 57B includes a semiconductor substrate 571 and a semiconductor layer 572 on the semiconductor substrate 571.

[0222] Therefore, the semiconductor substrate 571 of the first chip region 57A is electrically insulated from the semiconductor substrate 571 of the second chip region 57B. Although not shown in the drawings, the third and fourth chip regions 57C and 57D each include a semiconductor substrate 571, similar to the first and second chip regions 57A and 57B. The semiconductor substrates of the first to fourth chip regions 57A to 57D are electrically insulated from one another. That is, the first to fourth chip regions 57A to 57D have the same configurations as the first to fourth rectifier chips 50A to 50D of the first embodiment, respectively. Therefore, it can be said that one rectifier chip 50 of the third embodiment integrally includes the first to fourth rectifier chips 50A to 50D. Therefore, the isolated switch 120 of the third embodiment can suppress the occurrence of latch-up, similar to the isolated switch 100 of the first embodiment.

[0223] The isolation switch 120 of the third embodiment includes one rectifier chip 50. This one rectifier chip 50 includes first to fourth chip regions 57A to 57D. The first to fourth chip regions 57A to 57D include first to fourth rectifier circuits 51A to 51D, respectively. The first to fourth rectifier circuits 51A to 51D drive first to fourth switch circuits 60A to 60D, respectively. In this way, the isolation switch 120 of the third embodiment can drive the first to fourth switch circuits 60A to 60D using the one rectifier chip 50. The one rectifier chip 50 is mounted on the second die pad 221. Therefore, the isolation switch 120 of the third embodiment can easily form a semiconductor device 20 including the rectifier chip 50.

[0224] (Effects of the third embodiment) The isolation switch 120 of the third embodiment provides the following advantages. (3-1) The isolation switch 120 includes one rectifier chip 50. The rectifier chip 50 includes first to fourth chip regions 57A to 57D, a peripheral region 59, and an insulating region 58. The insulating region 58 is a region that partitions the rectifier chip 50 into the first to fourth chip regions 57A to 57D. The first chip region 57A includes a semiconductor substrate 571 and a semiconductor layer 572 on the semiconductor substrate 571. Similarly, the second chip region 57B includes a semiconductor substrate 571 and a semiconductor layer 572 on the semiconductor substrate 571. The semiconductor substrate 571 of the first chip region 57A is electrically insulated from the semiconductor substrate 571 of the second chip region 57B. Therefore, the isolation switch 120 of the third embodiment can suppress the occurrence of latch-up, similar to the isolation switch 100 of the first embodiment. Therefore, the isolation switch 120 of the third embodiment can stabilize its operation.

[0225] (Modification of the third embodiment) The third embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment and their description will be omitted.

[0226] The number of chip regions included in the rectification chip may be changed as appropriate. 31 is a schematic plan view showing a modified semiconductor device 20. The modified semiconductor device 20 includes a first rectifier chip 50F1 and a second rectifier chip 50F2.

[0227] The first rectifier chip 50F1 includes a first chip region 57A and a second chip region 57B. The first chip region 57A and the second chip region 57B are separated by a first insulating region 58A and a second insulating region 58B. The first chip region 57A and the second chip region 57B are insulated from each other by the first insulating region 58A and the second insulating region 58B. The second rectifier chip 50F2 includes a third chip region 57C and a fourth chip region 57D. The third chip region 57C and the fourth chip region 57D are separated by the third insulating region 58C and the fourth insulating region 58D. The third chip region 57C and the fourth chip region 57D are insulated from each other by the third insulating region 58C and the fourth insulating region 58D.

[0228] The insulating switch including the semiconductor device 20 of this modified example can stabilize its operation, similar to the insulating switch 120 of the third embodiment. (Fourth embodiment) An isolation switch 130 according to a fourth embodiment will be described with reference to FIGS.

[0229] Regarding the insulating switch 130 of the fourth embodiment, parts common to the insulating switch 100 of the first embodiment, the insulating switch 110 of the second embodiment, and the insulating switch 120 of the third embodiment will be assigned the same symbols as in the above embodiments, and descriptions thereof will be omitted.

[0230] Fig. 32 is a block diagram showing a schematic configuration of an insulating switch according to a fourth embodiment, and Fig. 33 is an explanatory diagram showing the insulating switch of Fig. 32. The isolation switch 130 of the fourth embodiment is configured by adding a plurality of resistors 70 to the isolation switch 100 of the first embodiment.

[0231] The plurality of resistors 70 include first to fourth resistors 70A to 70D. The first to fourth resistors 70A to 70D are connected between the semiconductor device 20 and the first to fourth switch circuits 60A to 60D, respectively.

[0232] The first resistor 70A is connected between the first rectifier circuit 51A and the first switch circuit 60A of the semiconductor device 20. The first rectifier circuit 51A is included in the first rectifier chip 50A. The first rectifier chip 50A includes a first output pad 54A and a second output pad 54B. The first resistor 70A is connected between the second output pad 54B of the first rectifier chip 50A and the first switch circuit 60A.

[0233] The second resistor 70B is connected between the second rectifier circuit 51B and the second switch circuit 60B of the semiconductor device 20. The second rectifier circuit 51B is included in the second rectifier chip 50B. The second rectifier chip 50B includes a first output pad 54A and a second output pad 54B. The second resistor 70B is connected between the second output pad 54B of the second rectifier chip 50B and the second switch circuit 60B.

[0234] The third resistor 70C is connected between the third rectifier circuit 51C and the third switch circuit 60C of the semiconductor device 20. The third rectifier circuit 51C is included in the third rectifier chip 50C. The third rectifier chip 50C includes a first output pad 54A and a second output pad 54B. The third resistor 70C is connected between the second output pad 54B of the third rectifier chip 50C and the third switch circuit 60C.

[0235] The fourth resistor 70D is connected between the fourth rectifier circuit 51D and the fourth switch circuit 60D of the semiconductor device 20. The fourth rectifier circuit 51D is included in the fourth rectifier chip 50D. The fourth rectifier chip 50D includes a first output pad 54A and a second output pad 54B. The fourth resistor 70D is connected between the second output pad 54B of the fourth rectifier chip 50D and the fourth switch circuit 60D.

[0236] The connections between the first and second switch circuits 60A and 60B and the first and second resistors 70A and 70B will be described in detail. The connections between the third and fourth resistors 70C and 70D are similar to those of the first and second resistors 70A and 70B, and therefore drawings and explanations thereof will be omitted.

[0237] 33, both the first switch circuit 60A and the second switch circuit 60B include a first switch element 601 and a second switch element 602. In one example, both the first switch element 601 and the second switch element 602 may be n-channel MOSFETs. The first switch element 601 and the second switch element 602 each include a source terminal, a drain terminal, a gate terminal, and a back gate terminal. The drain terminal of the first switch element 601 is connected to the first connection terminal 101, and the drain terminal of the second switch element 602 is connected to the second connection terminal 102.

[0238] The gate terminals of the first switch element 601 and the second switch element 602 of the first switch circuit 60A are connected to the first output pad 54A of the first rectifier chip 50A. A first terminal of the first resistor 70A is electrically connected to the second output pad 54B of the first rectifier chip 50A. A second terminal of the first resistor 70A is electrically connected to a node 603 between the source terminal of the first switch element 601 and the source terminal of the second switch element 602 of the first switch circuit 60A.

[0239] The gate terminals of the first switch element 601 and the second switch element 602 of the second switch circuit 60B are connected to the first output pad 54A of the second rectifier chip 50B. A first terminal of the second resistor 70B is electrically connected to the second output pad 54B of the second rectifier chip 50B. A second terminal of the first resistor 70A is electrically connected to a node 603 between the source terminal of the first switch element 601 and the source terminal of the second switch element 602 of the first switch circuit 60A.

[0240] The first resistor 70A may be provided as a current-limiting resistor that limits the current between the first rectifier chip 50A and the first switch circuit 60A. The resistance value of the first resistor 70A may be 100Ω or more. Similarly, the second to fourth resistors 70B to 70D may be provided as current-limiting resistors that limit the current between the second to fourth rectifier chips 50B to 50D and the second to fourth switch circuits 60B to 60D. The resistance values ​​of the second to fourth resistors 70B to 70D may be 100Ω or more.

[0241] (Operation of the fourth embodiment) As shown in FIG. 33, in the isolation switch 130 of the fourth embodiment, a first load 80A and a second load 80B are connected, similarly to the isolation switch 100 of the first embodiment.

[0242] When the first switch circuit 60A is turned on, a current flows from the high potential terminal 801 through the first load 80A and the first and second switch elements 601 and 602 of the first switch circuit 60A toward the low potential terminal 802. A node 603 between the first switch element 601 and the second switch element 602 is connected to the second terminal of the first resistor 70A, and a first terminal of the first resistor 70A is connected to the second output pad 54B of the first rectifier chip 50A. A portion of the current flowing through the first load 80A flows from the node 603 toward the first rectifier chip 50A. The first resistor 70A limits the current flowing from the node 603 toward the first rectifier chip 50A.

[0243] The second output pad 54B of the first rectifier chip 50A is connected to the second semiconductor region 582. The second semiconductor region 582 is in contact with the semiconductor substrate 571. A current flowing toward the first rectifier chip 50A can be one of the causes of voltage fluctuations on the semiconductor substrate 571. The first resistor 70A limits the current flowing toward the first rectifier chip 50A. The first resistor 70A further suppresses voltage fluctuations on the semiconductor substrate 571 of the first rectifier chip 50A. By suppressing voltage fluctuations on the semiconductor substrate 571, the operation of the first rectifier chip 50A can be more stabilized.

[0244] When the second switch circuit 60B is turned on, a current flows from the high potential terminal 801 through the first switch element 601 and the second switch element 602 of the second switch circuit 60B and the second load 80B toward the low potential terminal 802. A node 603 between the first switch element 601 and the second switch element 602 is connected to the second terminal of the second resistor 70B, and a first terminal of the second resistor 70B is connected to the second output pad 54B of the second rectifier chip 50B. A portion of the current flowing toward the second load 80B flows from the node 603 toward the second rectifier chip 50B. The second resistor 70B limits the current flowing from the node 603 toward the second rectifier chip 50B.

[0245] The second output pad 54B of the second rectifier chip 50B is connected to the second semiconductor region 582. The second semiconductor region 582 is in contact with the semiconductor substrate 571. A current flowing toward the second rectifier chip 50B can be one of the causes of voltage fluctuations on the semiconductor substrate 571. The second resistor 70B limits the current flowing toward the second rectifier chip 50B. The second resistor 70B further suppresses voltage fluctuations on the semiconductor substrate 571 of the second rectifier chip 50B. By suppressing voltage fluctuations on the semiconductor substrate 571, the operation of the second rectifier chip 50B can be more stabilized.

[0246] When the first load 80A or the second load 80B is connected to the third switch circuit 60C shown in FIG. 32 , the third resistor 70C, like the first resistor 70A and the second resistor 70B, limits the current flowing toward the third rectifier chip 50C. The third resistor 70C further suppresses voltage fluctuations on the semiconductor substrate 571 of the third rectifier chip 50C. When the first load 80A or the second load 80B is connected to the fourth switch circuit 60D, the fourth resistor 70D, like the first resistor 70A and the second resistor 70B, limits the current flowing toward the fourth rectifier chip 50D. The fourth resistor 70D further suppresses voltage fluctuations on the semiconductor substrate 571 of the fourth rectifier chip 50D. By suppressing voltage fluctuations on the semiconductor substrate 571 in this way, the operation of the third and fourth rectifier chips 50C and 50D can be more stabilized.

[0247] As described above, the first resistor 70A limits the current flowing from the first switch circuit 60A to the first rectifier chip 50A. The second resistor 70B limits the current flowing from the second switch circuit 60B to the second rectifier chip 50B. For example, in a rectifier chip in which the semiconductor substrate 571 of the first rectifier chip 50A and the semiconductor substrate 571 of the second rectifier chip 50B are formed on a single semiconductor substrate, a parasitic transistor with the single semiconductor substrate as its base electrode is generated, as described as a comparative example in the first embodiment. The first resistor 70A and the second resistor 70B function as current-limiting resistors that limit the flow of current to this parasitic transistor. As a result, in a rectifier chip including a single semiconductor substrate, the first resistor 70A and the second resistor 70B can suppress the occurrence of latch-up.

[0248] (Effects of the fourth embodiment) In addition to the effects of the isolation switch 100 of the first embodiment, the isolation switch 130 of the fourth embodiment has the following effects.

[0249] (4-1) The isolation switch 130 of the fourth embodiment includes a first resistor 70A electrically connected between the first rectifier chip 50A and the first switch circuit 60A. The first resistor 70A limits the current flowing from the first switch circuit 60A to the first rectifier chip 50A. As a result, the operation of the first rectifier chip 50A can be further stabilized.

[0250] (4-2) The isolation switch 130 of the fourth embodiment includes a second resistor 70B electrically connected between the second rectifier chip 50B and the second switch circuit 60B. The second resistor 70B limits the current flowing from the second switch circuit 60B to the second rectifier chip 50B. As a result, the operation of the second rectifier chip 50B can be further stabilized.

[0251] (4-3) The isolation switch 130 of the fourth embodiment includes a third resistor 70C electrically connected between the third rectifier chip 50C and the third switch circuit 60C. The third resistor 70C limits the current flowing from the third switch circuit 60C to the third rectifier chip 50C. As a result, the operation of the third rectifier chip 50C can be further stabilized.

[0252] (4-4) The isolation switch 130 of the fourth embodiment includes a fourth resistor 70D electrically connected between the fourth rectifier chip 50D and the fourth switch circuit 60D. The fourth resistor 70D limits the current flowing from the fourth switch circuit 60D to the fourth rectifier chip 50D. As a result, the operation of the fourth rectifier chip 50D can be further stabilized.

[0253] (Example of change) The above embodiment and modified examples can be modified, for example, as follows. The above embodiment and modified examples can be combined with the following modified examples as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0254] The configuration of the semiconductor device 20 may be changed as appropriate. In each of the above embodiments, one transformer chip 40 is mounted, but multiple transformer chips may be mounted. For example, four transformer chips each including first to fourth transformers 41A to 41D may be mounted. Also, one transformer chip including first transformer 41A and second transformer 41B, and one transformer chip including third transformer 41C and fourth transformer 41D may be mounted. Similarly, the configuration (number) of pulse chips mounted on the semiconductor device may be changed.

[0255] FIG. 34 is a schematic plan view showing a semiconductor device 20 according to a modified example. The semiconductor device 20 of this modified example includes a first transformer chip 40A and a second transformer chip 40B. The first transformer chip 40A and the second transformer chip 40B may have the same configuration as the transformer chip 40 described above. The first transformer chip 40A and the second transformer chip 40B are arranged between the pulse chip 30 and the multiple rectifier chips 50. The first transformer chip 40A is arranged closer to the pulse chip 30 than the second transformer chip 40B. The second transformer chip 40B is arranged closer to the multiple rectifier chips 50 than the first transformer chip 40A. In one example, the pulse chip 30 and the first transformer chip 40A are mounted on a first die pad 211. The second transformer chip 40B and the multiple rectifier chips 50 are mounted on a second die pad 221. The second transformer chip 40B may be mounted on the first die pad 211.

[0256] The second electrode pads 45 of the first transformer chip 40A are electrically connected to the second electrode pads 45 of the second transformer chip 40B by wires W3. The first electrode pads 44 of the second transformer chip 40B are electrically connected to the input pads 53 of the first to fourth rectifier chips 50A to 50D by wires W7. The semiconductor device 20 of this modified example can achieve the same effects as those of the first embodiment described above.

[0257] In contrast to the fourth embodiment, the resistors 70 (70A to 70D) may be provided inside the semiconductor device 20. The first switch element 601 and the second switch element 602 may be p-channel MOSFETs. In this case, the gate terminals of the first switch element 601 and the second switch element 602 are connected to the second output pad 54B, and the drain terminals of the first switch element 601 and the second switch element 602 are connected to each other and to the first output pad 54A.

[0258] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0259] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0260] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0261] (Appendix 1) a first transformer (41A) including a primary coil (42) and a secondary coil (43); a second transformer (41B) including a primary coil (42) and a secondary coil (43); a first rectifier chip (50A) electrically connected to the secondary coil (43) of the first transformer (41A) and including a first rectifier circuit that controls a first switch circuit (60A) by rectifying an induced current (I21) flowing through the secondary coil (43) of the first transformer (41A); a second rectifier chip (50B) electrically connected to the secondary coil (43) of the second transformer (41B) and including a second rectifier circuit that controls a second switch circuit (60B) by rectifying an induced current (I21) flowing through the secondary coil (43) of the second transformer (41B); a first frame (221) on which the first rectifier chip (50A) and the second rectifier chip (50B) are mounted; Including, The first rectifier chip (50A) and the second rectifier chip (50B) each include: a first output pad (54A) and a second output pad (54B); a semiconductor substrate (571) of a first conductivity type including a first surface; a first semiconductor region (573) of a second conductivity type disposed on the first surface; a first transistor (511) provided in the first semiconductor region (573) and electrically connected to the first output pad (54A); a second semiconductor region (582) of a second conductivity type provided at a position separated from the first transistor (511) in the first semiconductor region (573) and electrically connected to the second output pad (54B); Including, The second semiconductor region (582) is in contact with the semiconductor substrate (571), The first rectification chip (50A) and the second rectification chip (50B) are arranged spaced apart from each other. Semiconductor device.

[0262] (Appendix 2) The first transistor (511) a base region (578) of a first conductivity type provided on the surface of the first semiconductor region (573); an emitter region (580) of a second conductivity type provided in the base region (578); a collector region (573) of a second conductivity type provided in the first semiconductor region (573); Including, The first output pad (54A) and the emitter region (580) are electrically connected. 2. The semiconductor device according to claim 1.

[0263] (Appendix 3) a second frame (211) disposed apart from the first frame (221) in a first direction (Y) in a plan view; a transformer chip (40) mounted on the second frame (211) and including the first transformer (41A) and the second transformer (41B); Including, 10. The semiconductor device according to claim 1 or 2.

[0264] (Appendix 4) the first transformer (41A) and the second transformer (41B) are arranged apart from each other in a second direction (X) intersecting the first direction (Y) in a plan view, the first rectification chip (50A) and the second rectification chip (50B) are arranged apart from each other in the second direction (X) in a plan view; 4. The semiconductor device according to claim 3.

[0265] (Appendix 5) The first rectifier chip (50A) and the second rectifier chip (50B) each include: a first main surface (501) having a circuit region (561) in which the first transistor (511) is arranged; a plurality of substrate connection pads (56) provided on the first main surface (501) and electrically connected to the semiconductor substrate (571); Including, the plurality of substrate connection pads (56) include first substrate connection pads (56A) and second substrate connection pads (56B); The first substrate connection pads (56A) and the second substrate connection pads (56B) are arranged on either side of the circuit region (561) in the first direction (Y). 5. The semiconductor device according to claim 4.

[0266] (Appendix 6) A part of the circuit area (561) is recessed, and the first output pad (54A) is arranged in the recessed space. 6. The semiconductor device according to claim 5.

[0267] (Appendix 7) The first substrate connection pads (56A) and the second substrate connection pads (56B) are arranged to be shifted in the second direction (X). 7. The semiconductor device according to claim 5 or 6.

[0268] (Appendix 8) The first main surface (501) is rectangular in plan view, The first substrate connection pads (56A) and the second substrate connection pads (56B) are arranged diagonally on the first main surface (501). 8. The semiconductor device according to claim 5, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0269] (Appendix 9) The plurality of substrate connection pads (56) include a third substrate connection pad (56C) arranged spaced apart from the second substrate connection pad (56B) in the second direction (X). 9. The semiconductor device according to claim 5, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0270] (Appendix 10) the second output pad (54B) of the first rectifier chip (50A) is disposed between the third substrate connection pad (56C) and the second substrate connection pad (56B); 10. The semiconductor device according to claim 9.

[0271] (Appendix 11) The third substrate connection pad (56C) and the first output pad (54A) are arranged to be offset in the first direction (Y). 11. The semiconductor device according to claim 9 or 10.

[0272] (Appendix 12) each of the first rectifier chip (50A) and the second rectifier chip (50B) includes a plurality of input pads (53) connected to the secondary coil (43); the plurality of input pads (53) are arranged on the opposite side of the circuit region (561) from the first output pad (54A) and the second output pad (54B); The first substrate connection pads (56A) are arranged in the second direction (X) with respect to the plurality of input pads (53). 12. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0273] (Appendix 13) The plurality of input pads (53) includes an input pad (53C) electrically connected to the second output pad (54B). 13. The semiconductor device according to claim 12.

[0274] (Appendix 14) The plurality of input pads (53) include first to third input pads (53A to 53C), The secondary coil (43) a first coil (43A) connected between the first input pad (53A) and the third input pad (53C); a second coil (43B) connected between the second input pad (53B) and the third input pad (53C); Including, 13. The semiconductor device according to claim 12.

[0275] (Appendix 15) The third input pad (53C) is electrically connected to the second output pad (54B). 15. The semiconductor device according to claim 14.

[0276] (Appendix 16) and a wire (W5A) connecting the second substrate connection pad (56B) of the first rectifier chip (50A) to the first substrate connection pad (56A) of the second rectifier chip (50B). 16. The semiconductor device according to any one of claims 9 to 15.

[0277] (Appendix 17) a plurality of first leads (222) arranged along the second direction (X) on the opposite side of the transformer chip (40) with respect to the first rectifier chip (50A) and the second rectifier chip (50B); 17. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0278] (Appendix 18) the first output pad (54A) and the second output pad (54B) of the first rectifier chip (50A), and the first output pad (54A) and the second output pad (54B) of the second rectifier chip (50B) are connected to the first leads (222) different from each other by wires (W4), respectively; 18. The semiconductor device according to claim 17.

[0279] (Appendix 19) a plurality of rectifier chips (50) including the first rectifier chip (50A) and the second rectifier chip (50B) are arranged in the second direction (X), and the first rectifier chip (50A, 50D) is disposed at a first end of the plurality of rectifier chips; the third substrate connection pad (56C) of the first rectifier chip (50A, 50D) is connected to a first lead (222B, 222I) of the plurality of first leads (222) that is different from the first leads to which the first output pad (54A) and the second output pad (54B) are respectively connected; 19. The semiconductor device according to claim 18.

[0280] (Appendix 20) Any one of the first substrate connection pad (56A) to the third substrate connection pad (56C) is connected to the first lead to which the first output pad (54A) is connected. 20. The semiconductor device according to claim 19.

[0281] (Appendix 21) Any one of the first substrate connection pad (56A) to the third substrate connection pad (56C) is connected to the first lead to which the second output pad (54B) is connected. 20. The semiconductor device according to claim 19.

[0282] (Appendix 22) a capacitor (541) connected to the emitter region (580) of the first transistor (511); 22. The semiconductor device according to claim 3, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0283] (Appendix 23) The first transistors (511, 512) and capacitors (541, 542) are provided in plurality and connected in series. 23. The semiconductor device according to claim 3, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0284] (Appendix 24) a first transformer (41A) including a primary coil (42) and a secondary coil (43); a second transformer (41B) including a primary coil (42) and a secondary coil (43); a rectifier chip connected to the secondary coil (43) of the first transformer (41A) and the secondary coil (43) of the second transformer (41B); a first frame (221) on which the rectifier chip (50) is mounted; Including, The rectifying chip (50) is a first rectification area including a first rectification circuit electrically connected to the secondary coil (43) of the first transformer (41A) and configured to control a first switch circuit (60A) by rectifying an induced current (I21) flowing through the secondary coil (43) of the first transformer (41A); a second rectification region including a second rectification circuit electrically connected to the secondary coil (43) of the second transformer (41B) and configured to control a second switch circuit (60B) by rectifying an induced current (I21) flowing through the secondary coil (43) of the second transformer (41B); Including, The first rectification region and the second rectification region each include: a first output pad (54A) and a second output pad (54B); a semiconductor substrate (571) of a first conductivity type including a first surface; a first semiconductor region (573) of a second conductivity type disposed on the first surface; a first transistor (511) provided in the first semiconductor region (573) and electrically connected to the first output pad (54A); a second semiconductor region (582) of a second conductivity type provided at a position separated from the first transistor (511) in the first semiconductor region (573) and electrically connected to the second output pad (54B); Including, The second semiconductor region (582) is in contact with the semiconductor substrate (571), The rectification chip includes an insulating region that insulates the semiconductor substrate (571) of the first rectification region from the semiconductor substrate (571) of the second rectification region. Semiconductor device.

[0285] (Appendix 25) a semiconductor device including a first rectifier chip (50A) and a second rectifier chip (50B); a first switch circuit (60A) electrically connected to the first rectifier chip (50A); a second switch circuit (60B) electrically connected to the second rectifier chip (50B); Including, The semiconductor device includes: a first transformer (41A) including a primary coil (42) and a secondary coil (43); a second transformer (41B) including a primary coil (42) and a secondary coil (43); a first rectifier chip (50A) electrically connected to the secondary coil (43) of the first transformer (41A) and including a first rectifier circuit that controls the first switch circuit (60A) by rectifying an induced current (I21) flowing through the secondary coil (43) of the first transformer (41A); a second rectifier chip (50B) electrically connected to the secondary coil (43) of the second transformer (41B) and including a second rectifier circuit that controls the second switch circuit (60B) by rectifying an induced current (I21) flowing through the secondary coil (43) of the second transformer (41B); a first frame (221) on which the first rectifier chip (50A) and the second rectifier chip (50B) are mounted; Including, The first rectifier chip (50A) and the second rectifier chip (50B) each include: a first output pad (54A) and a second output pad (54B); a semiconductor substrate (571) of a first conductivity type including a first surface; a first semiconductor region (573) of a second conductivity type disposed on the first surface; a first transistor (511) provided in the first semiconductor region (573) and electrically connected to the first output pad (54A); a second semiconductor region (582) of a second conductivity type provided at a position separated from the first transistor (511) in the first semiconductor region (573) and electrically connected to the second output pad (54B); Including, The second semiconductor region (582) is in contact with the semiconductor substrate (571), The first rectification chip (50A) and the second rectification chip (50B) are arranged spaced apart from each other. Isolation switch.

[0286] (Appendix 26) Each of the first switch circuit (60A) and the second switch circuit (60B) includes a first switch element (601) and a second switch element (602) connected in series. 26. An isolating switch as described in Clause 25.

[0287] (Appendix 27) The first switch element (601) and the second switch element (602) are n-channel MOSFETs. 27. The isolating switch of claim 26.

[0288] (Appendix 28) The first switch element (601) and the second switch element (602) are p-channel MOSFETs. 27. The isolating switch of claim 26.

[0289] (Appendix 29) a first resistor (70A) electrically connected between the first rectifier chip (50A) and the first switch circuit (60A); a second resistor (70B) electrically connected between the second rectifier chip (50B) and the second switch circuit (60B); Including, 29. The isolation switch of any one of claims 26 to 28.

[0290] (Appendix 30) the first resistor (70A) is connected between a connection point (603) between the first switch element (601) and the second switch element (602) and the second output pad (54B); the second resistor (70B) is connected between a connection point (603) between the first switch element (601) and the second switch element (602) and the second output pad (54B); 29. The isolating switch of claim 29.

[0291] (Appendix 31) a second frame (211) disposed apart from the first frame (221) in a first direction (Y) in a plan view; a transformer chip (40) mounted on the second frame (211) and including the first transformer (41A) and the second transformer (41B); Including, 31. The isolating switch of any one of clauses 25 to 30.

[0292] (Appendix 32) a pulse chip (30) disposed on the opposite side of the transformer chip (40) from the first rectifier chip (50A) and the second rectifier chip (50B), The pulse chip (30) a first pulse generating circuit (31A) connected to the primary coil (42) of the first transformer (41A); a second pulse generating circuit (31B) connected to the primary coil (42) of the second transformer (41B); Including, 32. The isolating switch of claim 31.

[0293] (Appendix 33) The pulse chip (30) is mounted on the second frame (211). 33. The isolating switch of claim 32.

[0294] (Appendix 34) A rectifier chip (50) including a rectifier circuit used to control a switch circuit (60) by rectifying an inductive current flowing in a transformer (41), a first output pad (54A) and a second output pad (54B); a semiconductor substrate (571) of a first conductivity type including a first surface; a first semiconductor region (573) of a second conductivity type disposed on the first surface; a first transistor (511) provided in the first semiconductor region (573) and electrically connected to the first output pad (54A); a second semiconductor region (582) of a second conductivity type provided at a position separated from the first transistor (511) in the first semiconductor region (573), electrically connected to the second output pad (54B), and in contact with the semiconductor substrate (571); a first main surface (501) including a circuit region (561) in which the first transistor (511) is arranged; a plurality of substrate connection pads (56) provided on the first main surface (501) and electrically connected to the semiconductor substrate (571); Including, The plurality of substrate connection pads (56) include a first substrate connection pad (56A) and a second substrate connection pad (56B) provided on both sides of the circuit region (561) in a first direction (Y) in a plan view. Rectification chip.

[0295] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0296] 20 Semiconductor Devices 30 Pulse Chips 31 Pulse generation circuit 31A to 31D 1st to 4th pulse generating circuits 32 Oscillator Circuit 33 Input Pad 34 Output Pad 34A~34C 1st~3rd output pads 40 Transformer Chip 40A, 40B 1st and 2nd transformer chips 41 Transformer 41A~41D 1st to 4th transformers 42 Primary coil 42A, 42B 1st and 2nd coils 43 Secondary coil 43A, 43B First and second coils 44 First electrode pad 44A~44C 1st~3rd input pads 45 Second electrode pad 45A~45C 1st~3rd output pads 50 rectifier chip 50A~50D 1st~4th rectifier chips 50F rectifier chip 50F1, 50F2 1st and 2nd rectifier chips 50X Rectifier Chips 51 Rectifier circuit 51A~51D 1st~4th rectifier circuit 52A,52B protection circuit 52C 1st signal generation circuit 53 Input Pad 53A~53C 1st~3rd input pads 54 Output Pad 54A, 54B 1st and 2nd output pads 56 PCB connection pads 56A~56C 1st~3rd board connection pads 57A to 57D 1st to 4th chip areas 58 Insulation Area 58A~58D 1st to 4th insulating areas 58M1~58M3 1st~3rd intermediate insulation areas 59 Outer area 60 Switch Circuit 60A~60D 1st~4th switch circuits 70 Resistance 70A~70D 1st~4th resistor 80 load 80A, 80B 1st, 2nd load 100,110,120,130 Isolation Switch 101~103 1st~3rd connection terminals 210 First support member 211 First die pad 212, 212A~212J First lead terminal 220 second support member 221 Second die pad 222, 222A~212J Second lead terminal 230 Sealing resin 231 Sealing top surface 232 Bottom sealing surface 233~236 Resin side 301 Chip top surface 302 Tip bottom 401 Chip top surface 402 Tip bottom 403~406 Chip side 410 Semiconductor substrate 411 Top surface of board 412 Bottom surface of board 420 Insulation Layer 421 Top surface 422 Bottom surface 430 Insulating film 431, 432 First and second insulating films 433,434 Insulating film 441 First coil wiring 442 Inner end wiring 443 Outer end wiring 444,445 Connection wiring 451 Second coil wiring 452 Inner end wiring 453 Outer end wiring 460 Dummy wiring 461~464 1st~4th dummy wiring 470 Passivation Film 472 Resin layer 501 Chip top surface 502 Tip bottom 503~506 Chip side 511~515 Transistors 521~527 Transistor 531~535 ​​Diodes 541~545 Capacitor 551~557 Resistance 561 Circuit area 562 recess 563 Wiring 571 Semiconductor Substrates 5711 Top surface of board 5712 Bottom side of board 572 Semiconductor layer 5721 Top surface 5731 Surface 573 First Semiconductor Region 574 Epitaxial Layer 575 Embedding Layer 576 Collector contact area 577 Contact Area 578 Base Area 579 Base Contact 580 emitter area 581 well area 582 Source region (second semiconductor region) 583 Drain Region 584 channel region 585 Gate insulating film 586 Gate electrode 587 Backgate Area 591 Connection Area 5911 Top side 592 Contact Area 601, 602 First and second switch elements 603 nodes 801 High potential terminal 802 Low potential terminal 811 Power supply circuit 812 control circuit CLK Clock signal I21,I22 1st, 2nd induced current S1 control signal S1A to S1D 1st to 4th control signals S2 drive signal SD1~SD3 Bonding material SP1, SP2 1st and 2nd pulse signals SPA pulse signal VD1 operating voltage VD2 drive voltage W1~W4 wires W5A~W5C, W6, W7 wire

Claims

1. a first transformer including a primary coil and a secondary coil; a second transformer including a primary coil and a secondary coil; a first rectifier chip including a first rectifier circuit electrically connected to the secondary coil of the first transformer and configured to control a first switch circuit by rectifying an induced current flowing through the secondary coil of the first transformer; a second rectifier chip including a second rectifier circuit electrically connected to the secondary coil of the second transformer and configured to control a second switch circuit by rectifying an induced current flowing through the secondary coil of the second transformer; a first frame on which the first rectifier chip and the second rectifier chip are mounted; Including, The first rectification chip and the second rectification chip each include: a first output pad and a second output pad; a semiconductor substrate of a first conductivity type including a first surface; a first semiconductor region of a second conductivity type disposed on the first surface; a first transistor provided in the first semiconductor region and electrically connected to the first output pad; a second semiconductor region of a second conductivity type provided at a position separated from the first transistor in the first semiconductor region and electrically connected to the second output pad; Including, the second semiconductor region is in contact with the semiconductor substrate; the first rectification chip and the second rectification chip are spaced apart from each other; Semiconductor device.

2. The first transistor is a first conductivity type base region provided on a surface of the first semiconductor region; an emitter region of a second conductivity type provided in the base region; a collector region of a second conductivity type provided in the first semiconductor region; Including, the first output pad and the emitter region are electrically connected; The semiconductor device according to claim 1 .

3. a second frame disposed apart from the first frame in a first direction in a plan view; a transformer chip mounted on the second frame and including the first transformer and the second transformer; Including, The semiconductor device according to claim 1 .

4. the first transformer and the second transformer are arranged apart from each other in a second direction intersecting the first direction in a plan view, the first rectification chip and the second rectification chip are arranged to be spaced apart from each other in the second direction in a plan view; The semiconductor device according to claim 3 .

5. The first rectification chip and the second rectification chip each include: a first main surface having a circuit region in which the first transistor is disposed; a plurality of substrate connection pads provided on the first main surface and electrically connected to the semiconductor substrate; Including, the plurality of substrate bond pads include first substrate bond pads and second substrate bond pads; the first substrate connection pads and the second substrate connection pads are arranged on either side of the circuit region in the first direction; The semiconductor device according to claim 4 .

6. a part of the circuit region is recessed, and the first output pad is disposed in the recessed space; The semiconductor device according to claim 5 .

7. the first substrate connection pads and the second substrate connection pads are arranged to be shifted in the second direction; The semiconductor device according to claim 5 .

8. The first main surface is rectangular in plan view, the first substrate connection pads and the second substrate connection pads are diagonally arranged on the first main surface; The semiconductor device according to claim 5 .

9. the plurality of substrate connection pads include a third substrate connection pad arranged spaced apart from the second substrate connection pad in the second direction; The semiconductor device according to claim 5 .

10. the second output pad of the first rectifier chip is disposed between the third substrate connection pad and the second substrate connection pad; The semiconductor device according to claim 9 .

11. the third substrate connection pad and the first output pad are arranged to be offset from each other in the first direction; The semiconductor device according to claim 9 .

12. each of the first rectifier chip and the second rectifier chip includes a plurality of input pads connected to the secondary coil; the plurality of input pads are arranged on the opposite side of the circuit area from the first output pad and the second output pad, the first substrate connection pads are arranged in the second direction relative to the plurality of input pads; The semiconductor device according to claim 9 .

13. the plurality of input pads includes an input pad electrically connected to the second output pad; The semiconductor device according to claim 12.

14. the plurality of input pads include first to third input pads, The secondary coil is a first coil connected between the first input pad and the third input pad; a second coil connected between the second input pad and the third input pad; Including, The semiconductor device according to claim 12.

15. the third input pad is electrically connected to the second output pad; The semiconductor device according to claim 14.

16. a wire connecting the second substrate connection pad of the first rectifier chip to the first substrate connection pad of the second rectifier chip; The semiconductor device according to claim 9 .

17. a plurality of first leads arranged along the second direction on an opposite side of the transformer chip with respect to the first rectifier chip and the second rectifier chip; The semiconductor device according to claim 9 .

18. the first output pad and the second output pad of the first rectifier chip, and the first output pad and the second output pad of the second rectifier chip are connected to the first leads by wires different from each other; The semiconductor device according to claim 17.

19. a plurality of rectifying chips including the first rectifying chip and the second rectifying chip are arranged in the second direction, and the first rectifying chip is disposed at a first end of the plurality of rectifying chips; the third substrate connection pad of the first rectifier chip is connected to a first lead among the plurality of first leads that is different from the first leads to which the first output pad and the second output pad are respectively connected; 19. The semiconductor device according to claim 18.

20. a semiconductor device including a first rectifier chip and a second rectifier chip; a first switch circuit electrically connected to the first rectifier chip; a second switch circuit electrically connected to the second rectifier chip; Including, The semiconductor device includes: a first transformer including a primary coil and a secondary coil; a second transformer including a primary coil and a secondary coil; a first rectifier chip including a first rectifier circuit electrically connected to the secondary coil of the first transformer and configured to control the first switch circuit by rectifying an induced current flowing through the secondary coil of the first transformer; a second rectifier chip including a second rectifier circuit electrically connected to the secondary coil of the second transformer and configured to control the second switch circuit by rectifying an induced current flowing through the secondary coil of the second transformer; a first frame on which the first rectifier chip and the second rectifier chip are mounted; Including, The first rectification chip and the second rectification chip each include: a first output pad and a second output pad; a semiconductor substrate of a first conductivity type including a first surface; a first semiconductor region of a second conductivity type disposed on the first surface; a first transistor provided in the first semiconductor region and electrically connected to the first output pad; a second semiconductor region of a second conductivity type provided at a position separated from the first transistor in the first semiconductor region and electrically connected to the second output pad; Including, the second semiconductor region is in contact with the semiconductor substrate; the first rectification chip and the second rectification chip are spaced apart from each other; Isolation switch.

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