Semiconductor device and method of manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: An n-type source region NS1 and an n-type drain region ND1 are formed in the substrate SUB. On a portion of the semiconductor substrate SUB located between the source region NS1 and the drain region ND1, a gate electrode GE1 is formed via a gate insulating film GI1. In the portions of the substrate SUB which are located under the drain regions ND1, the gate electrodes GE1, and the source regions NS1, the p-type impurity regions HPW are formed. The impurity concentration of the impurity region HPW is higher than that of the semiconductor substrate SUB. The impurity region HPW is apart from the upper surface TS of the semiconductor substrate SUB.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Laterally Diffused Metal Oxide Semiconductor (LDMOS) is a type of metal insulator semiconductor field effect transistor (MISFET). LDMOS has a low-concentration drift region between a high-concentration drain region and a gate electrode in plan view.

[0003] For example, Patent Document 1 discloses a semiconductor device equipped with an LDMOS, in which a p-type semiconductor region is formed below a gate electrode to improve the breakdown voltage of the LDMOS, and deep insulating regions are formed in an interlayer insulating film and a semiconductor substrate to electrically isolate the LDMOS from other semiconductor elements. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-152559 Summary of the Invention [Problem to be solved by the invention]

[0005] In addition to LDMOS, various MISFETs are formed in semiconductor devices depending on various circuit applications. Examples of the various MISFETs include n-type MISFETs having a p-type well region formed in a semiconductor substrate and n-type MISFETs without a p-type well region. An n-type MISFET without a p-type well region uses a p-type semiconductor substrate with a relatively low impurity concentration as its channel region. Therefore, compared to n-type MISFETs with a p-type well region, n-type MISFETs without a p-type well region are more susceptible to punch-through, leakage current during off-state operation, and reduced breakdown voltage during off-state operation. This may result in reduced reliability of the semiconductor device.

[0006] Increasing the gate length of the gate electrode is one way to prevent punch-through, but this increases the plane area of ​​the MISFET, which increases the size of the semiconductor device. It also makes it difficult to shrink the MISFET and miniaturize the semiconductor device.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] In one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a first source region of a second conductivity type formed in the semiconductor substrate, a first drain region of the second conductivity type formed in the semiconductor substrate, and a first gate electrode formed on a portion of the semiconductor substrate located between the first source region and the first drain region, with a first gate insulating film interposed therebetween. A first impurity region of the first conductivity type is formed in portions of the semiconductor substrate located below the first drain region, below the first gate electrode, and below the first source region. The first impurity region is spaced apart from the top surface of the semiconductor substrate. The impurity concentration of the first impurity region is higher than the impurity concentration of the semiconductor substrate. No impurity region of the first conductivity type other than the semiconductor substrate and the first impurity region is formed in portions of the semiconductor substrate located between the first drain region, the first gate electrode, and the first source region and the first impurity region.

[0009] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate of a first conductivity type; forming a first impurity region of the first conductivity type in the semiconductor substrate; forming a first gate insulating film on an upper surface of the semiconductor substrate; forming a first gate electrode on the first gate insulating film; and forming a first source region of a second conductivity type opposite to the first conductivity type and a first drain region of the second conductivity type in the semiconductor substrate. The first impurity region is formed in portions of the semiconductor substrate located below the first drain region, below the first gate electrode, and below the first source region. The first impurity region is spaced from the upper surface of the semiconductor substrate. The impurity concentration of the first impurity region is higher than the impurity concentration of the semiconductor substrate. No impurity region of the first conductivity type other than the semiconductor substrate and the first impurity region is formed in portions of the semiconductor substrate located between the first drain region, the first gate electrode, and the first source region and the first impurity region. [Effects of the Invention]

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the potential distribution obtained by simulation in Study Example 1. In FIG. [Figure 3] FIG. 3 is a diagram showing a potential distribution obtained by simulation in the first embodiment. [Figure 4] FIG. 4 is a diagram showing the potential distribution obtained by simulation in the second study example. [Figure 5] FIG. 5 is a diagram showing the potential distribution obtained by simulation in Study Example 3. In FIG. [Figure 6] FIG. 6 is a graph showing the simulation results. [Figure 7] FIG. 7 is a graph showing the simulation results. [Figure 8] FIG. 8 is a graph showing the impurity concentration profile of the impurity region in the first embodiment. [Figure 9] FIG. 9 is a diagram showing a potential distribution obtained by simulation in the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 12] 12A to 12C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to that shown in FIG. [Figure 13] 13A to 13C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 14] 14A to 14C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 15] FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 16]16 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 18] FIG. 18 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 19] FIG. 19 is a plan view showing a semiconductor device according to the second embodiment. [Figure 20] FIG. 20 is a graph showing a simulation result in the second embodiment. [Figure 21] FIG. 21 is a diagram showing the potential distribution obtained by simulation in Study Example 4. In FIG. [Figure 22] FIG. 22 is a diagram showing a potential distribution obtained by a simulation in the second embodiment. [Figure 23] FIG. 23 is a diagram showing the potential distribution obtained by simulation in Study Example 5. In FIG. [Figure 24] FIG. 24 is a diagram showing the potential distribution obtained by simulation in Study Example 6. In FIG. [Figure 25] FIG. 25 is a graph showing the simulation results. [Figure 26] FIG. 26 is a graph showing the simulation results. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] Furthermore, the X, Y, and Z directions described in this application intersect and are perpendicular to each other. In this application, the Z direction is the vertical, depth, or thickness direction of a structure. Furthermore, expressions such as "plan view" or "plan view" used in this application mean that a surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) <Structure of semiconductor device> The semiconductor device according to the first embodiment will be described below with reference to Fig. 1. The semiconductor device comprises a region 1A having a MISFET 1Q and a region 2A having a MISFET 2Q as an LDMOS.

[0015] As shown in FIG. 1, the semiconductor device includes a p-type semiconductor substrate SUB having an upper surface TS and a lower surface BS, an n-type buried region (impurity region) NBL, and an element isolation portion STI. In the first embodiment, the semiconductor substrate SUB includes, for example, a support substrate SS and a semiconductor layer EP formed on the support substrate SS. The support substrate SS is, for example, a p-type silicon substrate. The semiconductor layer EP is, for example, a p-type silicon layer. An n-type buried region NBL is formed in the semiconductor substrate SUB. In the following description, various impurity regions formed in the semiconductor substrate SUB may specifically be formed in the semiconductor layer EP. Note that the semiconductor substrate SUB may be a single-layer p-type silicon substrate.

[0016] An element isolation portion STI is formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The element isolation portion STI includes a trench formed in the semiconductor substrate SUB and an insulating film buried inside the trench. The insulating film is, for example, a silicon oxide film. The depth of the element isolation portion STI is, for example, not less than 0.2 μm and not more than 0.5 μm.

[0017] <Structure of MISFET1Q in region 1A> The MISFET 1Q has an n-type source region NS1, an n-type drain region ND1, a gate insulating film GI1, a gate electrode GE1, a sidewall spacer SW, a semiconductor layer EP, and a p-type impurity region HPW.

[0018] In region 1A, a source region NS1 and a drain region ND1 are formed in the semiconductor substrate SUB so as to reach a predetermined depth from an upper surface TS of the semiconductor substrate SUB. The depths of the source region NS1 and the drain region ND1 are shallower than the depths of the element isolation parts STI. The source region NS1 and the drain region ND1 include an n-type lightly doped diffusion region (impurity region) LDD1 and an n-type heavily doped diffusion region (impurity region) NR, respectively. The impurity concentration of the heavily doped diffusion region NR is higher than the impurity concentration of the lightly doped diffusion region LDD1.

[0019] In the region 1A, a gate insulating film GI1 is formed on an upper surface TS of the semiconductor substrate SUB. The gate insulating film GI1 is made of, for example, a silicon oxide film. A gate electrode GE1 is formed on the gate insulating film GI1. The gate electrode GE1 is made of, for example, an n-type polycrystalline silicon film. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE1. The sidewall spacers SW include, for example, a silicon oxide film and a silicon nitride film formed on the silicon oxide film.

[0020] The gate electrode GE1 is formed on a portion of the semiconductor substrate SUB located between the source region NS1 and the drain region ND1 via a gate insulating film GI1. The portion of the semiconductor substrate SUB (semiconductor layer EP) located between the source region NS1 and the drain region ND1 and below the gate electrode GE1 functions as a channel region of the MISFET 1Q.

[0021] The impurity region HPW is formed in the semiconductor substrate SUB and is located above the buried region NBL. The impurity concentration of the impurity region HPW is higher than the impurity concentration of the semiconductor substrate SUB (semiconductor layer EP).

[0022] The impurity region HPW is formed in a portion of the semiconductor substrate SUB located below the drain region ND1, the gate electrode GE1, and the source region NS1. The impurity region HPW is spaced apart from the upper surface TS of the semiconductor substrate SUB and the buried region NBL. No p-type impurity region other than the semiconductor substrate SUB and the impurity region HPW is formed in a portion of the semiconductor substrate SUB located between the drain region ND1, the gate electrode GE1, the source region NS1, and the impurity region HPW.

[0023] In other words, the impurity concentration of the portion of the semiconductor substrate SUB located above the impurity region HPW is the same as the impurity concentration of the portion of the semiconductor substrate SUB located below the impurity region HPW.

[0024] The main feature of the first embodiment is that the MISFET 1Q has an impurity region HPW, which will be described in detail later.

[0025] <Structure of MISFET2Q in region 2A> MISFET2Q has a gate insulating film GI2, a gate electrode GE2, a sidewall spacer SW, an n-type drift region (impurity region) NLD, a p-type well region (impurity region) PW, an n-type source region NS2, an n-type drain region ND2, a high-concentration diffusion region (impurity region) PR, and a p-type resurf region PRF.

[0026] In the region 2A, the drift region NLD and the well region PW are formed in the semiconductor substrate SUB to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB and are located above the buried region NBL. The depths of the drift region NLD and the well region PW are deeper than the depths of the element isolation parts STI. The impurity concentration of the well region PW is higher than the impurity concentration of the semiconductor layer EP.

[0027] A source region NS2 and a heavily doped diffusion region PR are formed in the well region PW. The source region NS2 includes an n-type lightly doped diffusion region (impurity region) LDD2 and an n-type heavily doped diffusion region NR formed in the semiconductor substrate SUB.

[0028] A drain region (impurity region) ND2 is formed in the drift region NLD. The impurity concentrations of the drain region ND2, the lightly doped diffusion region LDD2, and the heavily doped diffusion region NR are each higher than the impurity concentration of the drift region NLD. The impurity concentration of the heavily doped diffusion region NR is higher than the impurity concentration of the lightly doped diffusion region LDD2. The impurity concentration of the heavily doped diffusion region PR is higher than the impurity concentration of the well region PW.

[0029] In the region 2A, a gate insulating film GI2 is formed on the upper surface TS of the semiconductor substrate SUB. The gate insulating film GI2 is made of, for example, a silicon oxide film. Furthermore, an element isolation part STI is formed in the drift region NLD. A gate electrode GE2 is formed on the gate insulating film GI2 and on a part of the element isolation part STI located in the drift region NLD. The gate electrode GE2 is made of, for example, an n-type polycrystalline silicon film. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE2.

[0030] Of the semiconductor substrate SUB (semiconductor layer EP, well region PW), a portion located between the source region NS1 and the drift region NLD and located below the gate electrode GE2 functions as a channel region of the MISFET 2Q.

[0031] The resurf region (impurity region) PRF is formed in the semiconductor substrate SUB. The resurf region PRF is located above the buried region NBL, and is formed in a portion of the semiconductor substrate SUB located below the drift region NLD and the well region PW. The impurity concentration of the resurf region PRF is higher than the impurity concentration of the semiconductor substrate SUB (semiconductor layer EP).

[0032] As will be described later, the step of forming the resurf region PRF and the step of forming the impurity region HPW are performed as the same step, so the impurity profile of the resurf region PRF is the same as the impurity profile of the impurity region HPW.

[0033] The semiconductor device includes an interlayer insulating film IL, multiple plugs PG, multiple wirings M1, and an element isolation portion DTI. In regions 1A and 2A, the interlayer insulating film IL is formed on an upper surface TS of a semiconductor substrate SUB so as to cover MISFET1Q and MISFET2Q. The interlayer insulating film IL is made of, for example, a silicon oxide film. Multiple holes are formed in the interlayer insulating film IL. Plugs PG are formed inside each of the multiple holes. Each of the multiple plugs PG includes, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film includes, for example, a titanium film and a titanium nitride film, and the conductive film is, for example, a tungsten film. Although not shown here, a plug PG connected to the gate electrode GE1 or the gate electrode GE2 is also formed in the interlayer insulating film IL.

[0034] A plurality of wirings M1 are formed on the interlayer insulating film IL. The plurality of wirings M1 are electrically connected to the drain region ND1, the source region NS1, the drain region ND2, the source region NS2, the heavily doped diffusion region PR, and the gate electrode GE1 or GE2 via plugs PG, respectively.

[0035] Each of the multiple wirings M1 has a lower barrier metal film, a conductive film formed on the lower barrier metal film, and an upper barrier metal film formed on the conductive film. The lower barrier metal film includes a titanium film and a titanium nitride film formed on the titanium film. The conductive film includes an aluminum alloy film in which copper or silicon is added to an aluminum film. The upper barrier metal film includes a titanium nitride film.

[0036] In the region 2A, an element isolation portion DTI is formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The element isolation portion DTI is also formed in the interlayer insulating film IL and penetrates the interlayer insulating film IL. The element isolation portion DTI includes a trench formed in the interlayer insulating film IL and the semiconductor substrate SUB, and an insulating film buried inside the trench. The insulating film is, for example, a silicon oxide film.

[0037] The depth of the element isolation portion DTI is deeper than the depth of the element isolation portion STI. The element isolation portion DTI is in contact with the resurf region PRF and the buried region NBL. The element isolation portion DTI electrically isolates the MISFET2Q from other semiconductor elements such as the MISFET1Q.

[0038] <Comparison between the study example and the first embodiment> The effect of the impurity region HPW included in MISFET 1Q will be explained below with reference to Figures 2 to 7. Figures 2 to 5 show potential distributions based on a simulation conducted by the present inventors to investigate the occurrence of leakage current (Ioff characteristics) during the off operation of MISFET 1Q. Here, the case is illustrated in which the voltage Vg applied to the gate electrode GE1 is set to -1 V, the voltage Vd applied to the drain region ND1 is set to 3.3 V, and the voltage Vs applied to the source region NS1 and the voltage Vb applied to the semiconductor layer EP are set to 0 V.

[0039] As shown in FIG. 2, in Study Example 1, unlike Embodiment 1, an impurity region HPW is not formed. Furthermore, an impurity region having a higher impurity concentration than the semiconductor layer EP, such as a well region PW, is not formed in the semiconductor layer EP. Therefore, in Study Example 1, equipotential lines extending from the drain region ND1 are likely to reach the source region NS1, which makes punch-through likely to occur. Therefore, leakage current is likely to occur in MISFET 1Q, potentially reducing the reliability of the semiconductor device.

[0040] As shown in FIG. 3, in the first embodiment, the formation of the impurity region HPW prevents the equipotential lines from reaching the source region NS1. Therefore, as shown in FIG. 6, punch-through is less likely to occur. Furthermore, as shown in FIG. 7, in the first embodiment, compared to the first study example, the occurrence of leakage current during off operation can be suppressed, and the breakdown voltage of the MISFET 1Q during off operation can be improved. Therefore, the reliability of the semiconductor device can be improved.

[0041] Furthermore, in the first embodiment, punch-through is unlikely to occur, which facilitates shrinking of the MISFET 1Q and miniaturization of the semiconductor device. Furthermore, the impurity region HPW can be formed in the same process as the process for forming the resurf region PRF. Therefore, an increase in manufacturing costs can be suppressed.

[0042] As shown in FIGS. 4 and 5, impurity regions HPW are also formed in Study Examples 2 and 3. However, the positions where the impurity regions HPW are formed in Study Examples 2 and 3 are different from the positions where the impurity regions HPW are formed in Embodiment 1. Note that boron (B) is used in the ion implantation process for forming the impurity regions HPW. The ion implantation energy is 800 keV in Embodiment 1, 250 keV in Study Example 2, and 2500 keV in Study Example 3.

[0043] As shown in FIG. 4, the position of the impurity region HPW in Study Example 2 is shallower than that in Embodiment 1, so the impurities contained in the impurity region HPW diffuse into the channel region of MISFET 1Q. Therefore, although punch-through can be suppressed in Study Example 2, the characteristics of MISFET 1Q vary significantly compared to Embodiment 1. For example, as shown in FIG. 6, the threshold voltage of MISFET 1Q in Study Example 2 is higher and the drive timing of MISFET 1Q is delayed compared to Embodiment 1.

[0044] 5, the position of the impurity region HPW in Study Example 3 is deeper than the position of the impurity region HPW in Embodiment 1, and therefore the extension of the equipotential lines cannot be suppressed. Therefore, in Study Example 3, the occurrence of punch-through cannot be suppressed, and as shown in FIG. 6, the characteristics of Study Example 3 are almost the same as the characteristics of Study Example 1. In other words, if the position of the impurity region HPW is too deep, the effect of the impurity region HPW cannot be exhibited.

[0045] If the impurity region HPW is spaced apart from the upper surface TS of the semiconductor substrate SUB to a certain extent, the impurity region HPW has almost no effect on the fluctuation of the characteristics of the MISFET 1Q and can suppress the occurrence of punch-through. In order to further enhance the effect of suppressing the occurrence of punch-through, the following lower and upper limit conditions may be set.

[0046] The position of the impurity concentration peak of the impurity region HPW will be described below with reference to Figures 8 and 9. The lower limit condition for the position of the impurity concentration peak of the impurity region HPW will be described with reference to Figure 8, and the upper limit condition for the position of the impurity concentration peak of the impurity region HPW will be described with reference to Figure 9.

[0047] As shown in FIG. 8, the impurity profile of the impurity region HPW has a half-width at half maximum of approximately 0.4 μm from the position of the impurity concentration peak of the impurity region HPW. As explained in Study Example 2 of FIG. 4, if the position of the impurity region HPW is too shallow, there is a problem in that the characteristics of the MISFET 1Q fluctuate significantly. If the impurity concentration peak of the impurity region HPW is located at a position that is at least the half-width at half maximum from the upper surface TS of the semiconductor substrate SUB, the impurity region HPW has almost no effect on the fluctuation of the characteristics of the MISFET 1Q. Therefore, it is preferable that the impurity concentration peak of the impurity region HPW be located at a position that is at least 0.4 μm from the upper surface TS of the semiconductor substrate SUB.

[0048] In addition, since the half width at half maximum of the impurity region HPW is approximately the same as the depth of the element isolation part STI, it can also be said that the impurity concentration peak of the impurity region HPW is located at a position deeper than the depth of the element isolation part STI.

[0049] 9 is the length of the gate electrode GE1 in the direction from the drain region ND1 to the source region NS1 (X direction). The distance Ld is the depth of the drain region ND1. The distance La is the extent of the equipotential lines extending from the drain region ND1 in the X direction. The distance Lb is the extent of the equipotential lines extending from the drain region ND1 in the Z direction.

[0050] The distance Lb is approximately half of the distance La. When punch-through occurs, the distance La becomes approximately equal to the gate length Lg. Therefore, in order to prevent punch-through from occurring, it is preferable that the impurity concentration peak of the impurity region HPW be located at a position shallower from the upper surface TS of the semiconductor substrate SUB than the sum of the depth Ld of the drain region ND1 and twice the gate length Lg.

[0051] In the first embodiment, the distance Ld is, for example, 0.3 μm, and the gate length Lg is, for example, 1.0 μm. Therefore, it is preferable that the impurity concentration peak of the impurity region HPW is located at a position 2.3 μm or less from the upper surface TS of the semiconductor substrate SUB.

[0052] By setting the position of the impurity concentration peak of the impurity region HPW as described above, the occurrence of leakage current in the MISFET 1Q during off operation can be suppressed, the breakdown voltage during off operation can be improved, and fluctuations in the characteristics of the MISFET 1Q can be suppressed.

[0053] <Method of manufacturing a semiconductor device> Each manufacturing step included in the method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.

[0054] As shown in Figure 10, a semiconductor substrate SUB is prepared. As described above, the semiconductor substrate SUB may be a single-layer p-type silicon substrate, but in the first embodiment, the semiconductor substrate SUB includes a support substrate SS and a semiconductor layer EP. First, a support substrate SS made of p-type silicon is prepared. Next, the semiconductor layer EP, which is a p-type silicon layer, is formed on the support substrate SS by epitaxial growth.

[0055] Next, a buried region NBL is formed in the semiconductor substrate SUB by photolithography and ion implantation. Note that after the buried region NBL is formed in the support substrate SS, the semiconductor layer EP may be formed on the support substrate SS.

[0056] As shown in FIG. 11, an element isolation part STI is formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB.

[0057] First, a silicon nitride film, for example, is formed on the upper surface TS of the semiconductor substrate SUB by a film formation process using, for example, a CVD method. Next, the silicon nitride film is patterned to form a hard mask. Next, a trench is formed in the semiconductor substrate SUB by performing an anisotropic etching process using the hard mask as a mask.

[0058] Next, an insulating film, such as a silicon oxide film, is formed on the upper surface TS of the semiconductor substrate SUB so as to fill the inside of the trench. Next, the insulating film located outside the trench is removed by a polishing process using a CMP method so that the insulating film remains inside the trench. In this way, an element isolation portion STI including the trench and the insulating film is formed. Thereafter, the hard mask is selectively removed by, for example, an isotropic etching process, to expose the upper surface TS of the semiconductor substrate SUB.

[0059] 12, by photolithography and ion implantation, an impurity region HPW is formed in the semiconductor substrate SUB in region 1A, and a resurf region PRF is formed in the semiconductor substrate SUB in region 2A. Note that the impurity region HPW and the resurf region PRF are formed by the same ion implantation process, and as described in FIG. 3, boron (B) is used in this ion implantation process, with a dose of, for example, 2.0×10 11 cm -2 Above 1.0×10 13 cm -2 The ion implantation energy is preferably 500 keV or more and 1200 keV or less, and more preferably 800 keV.

[0060] 13, a drift region NLD and a well region PW are sequentially formed in the semiconductor substrate SUB in region 2A by photolithography and ion implantation. The drift region NLD and the well region PW are each formed to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB.

[0061] 14, gate insulating films GI1 and GI2 are formed on the upper surface TS of the semiconductor substrate SUB. Next, a gate electrode GE1 is formed on the gate insulating film GI1, and a gate electrode GE2 is formed on the gate insulating film GI2.

[0062] First, in region 1A, a gate insulating film GI1 is formed on the upper surface TS of the semiconductor substrate SUB, for example, by thermal oxidation, and in region 2A, a gate insulating film GI2 is formed on the drift region NLD and the well region PW. Next, a conductive film is formed on the gate insulating film GI1, the gate insulating film GI2, and the element isolation portion STI, for example, by film formation using a CVD method. The conductive film is, for example, a polycrystalline silicon film doped with n-type impurities.

[0063] Next, by patterning the conductive film, a gate electrode GE1 made of the conductive film is formed on the gate insulating film GI1 in region 1A, and a gate electrode GE2 made of the conductive film is formed on the gate insulating film GI2 and on a part of the element isolation part STI in region 2A. Thereafter, the gate insulating film GI1 and the gate insulating film GI2 exposed from the gate electrode GE1 and the gate electrode GE2 are removed by an isotropic etching process.

[0064] As shown in FIG. 15, a lightly doped diffusion region LDD1 is formed in the semiconductor substrate SUB in the region 1A by photolithography and ion implantation, and a lightly doped diffusion region LDD2 is formed in the well region PW in the region 2A.

[0065] As shown in FIG. 16, sidewall spacers SW, heavily doped diffusion regions NR, drain regions ND2 and heavily doped diffusion regions PR are formed.

[0066] First, a stacked film including, for example, a silicon oxide film and a silicon nitride film is formed on the upper surface TS of the semiconductor substrate SUB by a film formation process using, for example, a CVD method so as to cover the gate electrodes GE1 and GE2. Next, the stacked film is anisotropically etched to form sidewall spacers SW from the stacked film remaining on the side surfaces of the gate electrodes GE1 and GE2.

[0067] Next, using photolithography and ion implantation, a heavily doped diffusion region NR is formed in the semiconductor substrate SUB in region 1A, and a heavily doped diffusion region NR is formed in the well region PW in region 2A, and a drain region ND2 is formed in the drift region NLD. Thus, a drain region ND1 and a source region NS1, each including a lightly doped diffusion region LDD1 and a heavily doped diffusion region NR, are formed in region 1A. Furthermore, a source region NS2, each including a lightly doped diffusion region LDD2 and a heavily doped diffusion region NR, is formed in region 2A. Next, using photolithography and ion implantation, a heavily doped diffusion region PR is formed in the well region PW in region 2A.

[0068] As a result of the above, MISFET 1Q is formed in region 1A, and MISFET 2Q is formed in region 2A.

[0069] 17, an interlayer insulating film IL and an element isolation portion DTI are formed. In the first embodiment, the element isolation portion DTI is formed in the region 2A, but the element isolation portion DTI is not formed in the region 1A.

[0070] First, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB and on the element isolation parts STI by a film formation process using, for example, a CVD method so as to cover the MISFET 1Q and the MISFET 2Q. Next, the interlayer insulating film IL is subjected to a planarization process using a CMP method.

[0071] Next, a resist pattern (not shown) is formed on the interlayer insulating film IL. Next, using the resist pattern as a mask, anisotropic etching and isotropic etching are performed to form trenches in the semiconductor substrate SUB so as to penetrate the interlayer insulating film IL and the element isolation portions STI and reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB.

[0072] Next, an insulating film such as a silicon oxide film is formed on the interlayer insulating film IL so as to fill the inside of the trench. Next, the insulating film located outside the trench is removed by a polishing process using a CMP method so that the insulating film remains inside the trench. In this way, an element isolation part DTI including the trench and the insulating film is formed.

[0073] 1 is obtained through the following manufacturing steps. First, a plurality of holes are formed in the interlayer insulating film IL by photolithography and anisotropic etching. Next, plugs PG are formed in the plurality of holes.

[0074] To form the plug PG, first, a titanium film, for example, is formed inside the hole and on the interlayer insulating film IL by a film formation process using, for example, a sputtering method. Next, a titanium nitride film, for example, is formed on the titanium film by a film formation process using, for example, a CVD method. The titanium film and the titanium nitride film become a barrier metal film. Next, a conductive film, for example, a tungsten film, is formed on the barrier metal film by a film formation process using, for example, a CVD method so as to fill the inside of the hole. Next, the conductive film and the barrier metal film formed outside the hole are removed by a polishing process using, for example, a CMP method. In this way, a plug PG including the conductive film and the barrier metal film is formed inside the hole.

[0075] Next, a lower barrier metal film is formed on the interlayer insulating film IL. The lower barrier metal film includes a titanium film formed by, for example, a sputtering method and a titanium nitride film formed on the titanium film by, for example, a CVD method. Next, a conductive film such as an aluminum alloy film is formed on the lower barrier metal film by, for example, a sputtering method. Next, an upper barrier metal film such as a titanium nitride film is formed on the conductive film by, for example, a sputtering method. Next, the upper barrier metal film, the conductive film, and the lower barrier metal film are patterned to form multiple wirings M1.

[0076] (Embodiment 2) The semiconductor device according to the second embodiment will be described below with reference to Figures 18 and 19. In the following description, differences from the first embodiment will be mainly described, and explanation of points that overlap with the first embodiment will be omitted. Figure 18 shows a cross-sectional view of MISFET1Q and a cross-sectional view of MISFET2Q taken along line AA shown in Figure 19.

[0077] 18 and 19, in the second embodiment, an element isolation portion DTI is also formed in the region 1A. In order to more reliably electrically isolate the MISFET 1Q from other semiconductor elements, the element isolation portion DTI may be disposed in the vicinity of the MISFET 1Q in a plan view. In such a case, the inventors have found through their studies that the side surface of the element isolation portion DTI may exhibit n-type conductivity, which may cause fluctuations in the characteristics of the MISFET 1Q.

[0078] 20 shows the relationship between the distance D1 between the element isolation part DTI and the drain region ND1 in a plan view and the fluctuation (ΔVth) of the threshold voltage of MISFET 1Q. As shown in FIG. 20, when the distance D1 is 1 μm or less, the threshold voltage of MISFET 1Q fluctuates.

[0079] The reason for this variation in the threshold voltage of MISFET1Q is presumably the anisotropic etching process and isotropic etching process performed when forming the trench for the element isolation region DTI. The element isolation region DTI is formed deeper than the buried region NBL and is in contact with the buried region NBL. It is presumed that the etching gas used in the anisotropic etching process or the chemical solution used in the isotropic etching process causes the n-type impurities contained in the buried region NBL to diffuse along the trench for the element isolation region DTI. As a result, an n-type impurity region is ultimately formed along the side surface of the element isolation region DTI.

[0080] In order to suppress the characteristic fluctuation of MISFET 1Q, distance D1 should be increased. However, the larger distance D1 is, the larger the plane area of ​​MISFET 1Q becomes, and the larger the size of the semiconductor device becomes. Furthermore, the larger distance D1 is, the more difficult it becomes to shrink MISFET 1Q, and the more difficult it becomes to miniaturize the semiconductor device. The impurity region HPW can solve these problems without increasing distance D1.

[0081] The effect of the impurity region HPW in the second embodiment will be described below with reference to Figures 21 to 26. Figures 21 to 24 show potential distributions based on a simulation performed by the inventors to examine the occurrence of leakage current (Ioff characteristics) during the off operation of MISFET 1Q. The voltages applied to gate electrode GE1, drain region ND1, source region NS1, and semiconductor layer EP are the same as those in Figures 2 to 5.

[0082] In addition, in Figures 21 to 24, the simulations are performed by regarding the area where the element isolation part DTI is originally formed and the n-type impurity region formed along the side of the element isolation part DTI as a virtual n-type impurity region DTIn.

[0083] 21 , in Study Example 4, like Study Example 1 of the first embodiment, the impurity region HPW is not formed. In Study Example 4, the equipotential lines extend not only from the drain region ND1 but also from the virtual n-type impurity region DTIn and reach the source region NS1. That is, due to the influence of the virtual n-type impurity region DTIn, punch-through is more likely to occur in Study Example 4 than in Study Example 1.

[0084] As shown in FIG. 22, in the second embodiment, the formation of the impurity region HPW prevents the equipotential lines from reaching the source region NS1. Therefore, as shown in FIG. 25, punch-through is less likely to occur. Furthermore, as shown in FIG. 26, in the second embodiment, compared with the first and fourth study examples, the generation of leakage current during off operation can be suppressed, and the breakdown voltage of the MISFET 1Q during off operation can be improved. Therefore, the reliability of the semiconductor device can also be improved in the second embodiment.

[0085] Furthermore, in the second embodiment, punch-through is unlikely to occur even when the element isolation part DTI is formed, which makes it easier to shrink the MISFET 1Q. For example, even when the distance D1 is 1 μm or less, punch-through can be suppressed by forming the impurity region HPW.

[0086] 23 and 24, in Study Examples 5 and 6, the impurity region HPW is formed with the same ion implantation energy as in Study Examples 2 and 3. Therefore, in Study Example 5, the impurities contained in the impurity region HPW diffuse into the channel region of MISFET 1Q, as in Study Example 2. Therefore, in Study Example 5, the characteristics of MISFET 1Q vary significantly compared to the second embodiment, as shown in FIG.

[0087] Furthermore, in Study Example 6, similarly to Study Example 3, the position of the impurity region HPW is deeper than the position of the impurity region HPW in Embodiment 1, and therefore the extension of the equipotential lines cannot be suppressed. Therefore, in Study Example 6, as shown in FIG. 25 , the occurrence of punch-through cannot be suppressed, and the characteristics of Study Example 6 are almost the same as those of Study Example 4.

[0088] The position of the impurity concentration peak of the impurity region HPW is the same as that described in the first embodiment with reference to FIGS.

[0089] Moreover, in order to form the element isolation part DTI in the region 1A, in the manufacturing process of FIG. 17, trenches for the element isolation part DTI may be formed not only in the region 2A but also in the region 1A.

[0090] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0091] 1A, 2A area 1Q, 2Q MISFET BS Bottom surface of semiconductor substrate DTI isolation section DTIn Virtual n-type impurity region EP p-type semiconductor layer GE1, GE2 gate electrodes GI1, GI2 gate insulating film HPW p-type impurity region IL Interlayer insulating film M1 wiring NBL n-type buried region ND1, ND2 n-type drain region LDD1, LDD2 n-type lightly doped diffusion regions NLD n-type drift region NR n-type heavily doped diffusion region NS1, NS2 n-type source regions PG plug PRF p-type resurf region PR p-type high concentration diffusion region PW p-type well region SS support board STI element isolation section SUB Semiconductor substrate SW Sidewall Spacer TS Top surface of semiconductor substrate

Claims

1. a semiconductor substrate of a first conductivity type having an upper surface; a first source region formed in the semiconductor substrate, the first source region having a first depth from the top surface of the semiconductor substrate, and having a second conductivity type opposite to the first conductivity type; a first drain region of the second conductivity type formed in the semiconductor substrate and having a second depth from the upper surface of the semiconductor substrate; a first gate electrode formed on a portion of the semiconductor substrate located between the first source region and the first drain region via a first gate insulating film; Equipped with a first impurity region of the first conductivity type is formed in a portion of the semiconductor substrate located below the first drain region, below the first gate electrode, and below the first source region; the first impurity region is spaced from the upper surface of the semiconductor substrate; an impurity concentration of the first impurity region is higher than an impurity concentration of the semiconductor substrate; a first impurity region of the first conductivity type other than the semiconductor substrate and the first impurity region is not formed in a portion of the semiconductor substrate that is located between the first drain region, the first gate electrode, and the first source region and the first impurity region.

2. 2. The semiconductor device according to claim 1, a semiconductor device, wherein the impurity concentration of a portion of the semiconductor substrate located above the first impurity region is the same as the impurity concentration of a portion of the semiconductor substrate located below the first impurity region.

3. 2. The semiconductor device according to claim 1, the semiconductor substrate includes a support substrate of the first conductivity type and a semiconductor layer of the first conductivity type formed on the support substrate; The semiconductor device, wherein the first source region, the first drain region, and the first impurity region are formed in the semiconductor layer.

4. 2. The semiconductor device according to claim 1, an impurity profile of the first impurity region having a predetermined half width at half maximum from an impurity concentration peak of the first impurity region; the impurity concentration peak of the first impurity region is located at a position equal to or greater than the half width at half maximum from the top surface of the semiconductor substrate.

5. 5. The semiconductor device according to claim 4, the impurity concentration peak of the first impurity region is located at a position shallower than the sum of the second depth of the first drain region and twice the length of the first gate electrode in a direction from the first drain region to the first source region from the top surface of the semiconductor substrate.

6. 2. The semiconductor device according to claim 1, a first isolation portion having a third depth from the top surface of the semiconductor substrate and formed in the semiconductor substrate; the second depth of the first drain region and the first depth of the first source region are shallower than the third depth of the first element isolation part, the impurity concentration peak of the first impurity region is located at a position deeper than the third depth of the first element isolation part.

7. 7. The semiconductor device according to claim 6, an impurity concentration peak of the first impurity region is located at a position shallower than the sum of the second depth of the first drain region and twice the length of the first gate electrode in a direction from the first drain region to the first source region from the top surface of the semiconductor substrate.

8. 8. The semiconductor device according to claim 7, a second impurity region of the second conductivity type formed in the semiconductor substrate; a second isolation portion having a fourth depth from the top surface of the semiconductor substrate and formed in the semiconductor substrate; Further provided with the second impurity region is located below the first impurity region, the fourth depth of the second element isolation portion is deeper than the third depth of the first element isolation portion; the second element isolation portion is in contact with the first impurity region and the second impurity region.

9. 9. The semiconductor device according to claim 8, a distance between the second element isolation portion and the first drain region in a plan view is 1 μm or less.

10. 2. The semiconductor device according to claim 1, a drift region of the second conductivity type formed in the semiconductor substrate; a well region of the first conductivity type formed in the semiconductor substrate; a second drain region of the second conductivity type formed in the drift region; a second source region of the second conductivity type formed in the well region; a third isolation portion formed in the drift region so as to reach a predetermined depth from the upper surface of the semiconductor substrate; a second gate insulating film formed on the drift region and the well region; a second gate electrode formed on the second gate insulating film and on a part of the third element isolation portion; a resurf region of the first conductivity type formed in a portion of the semiconductor substrate located below the drift region and below the well region; Further provided with a depth of the first impurity region is the same as a depth of the resurf region.

11. (a) providing a semiconductor substrate of a first conductivity type having an upper surface; (b) forming a first impurity region of the first conductivity type in the semiconductor substrate; (c) forming a first gate insulating film on the top surface of the semiconductor substrate; (d) forming a first gate electrode on the first gate insulating film; (e) forming in the semiconductor substrate a first source region of a second conductivity type opposite to the first conductivity type and a first drain region of the second conductivity type; Equipped with the first source region has a first depth from the top surface of the semiconductor substrate; the first drain region has a second depth from the top surface of the semiconductor substrate; the first gate electrode is formed on a portion of the semiconductor substrate located between the first source region and the first drain region, with the first gate insulating film interposed therebetween; the first impurity region is formed in a portion of the semiconductor substrate located below the first drain region, below the first gate electrode, and below the first source region; an impurity concentration of the first impurity region is higher than an impurity concentration of the semiconductor substrate; the first impurity region is spaced from the upper surface of the semiconductor substrate; an impurity concentration of the first impurity region is higher than an impurity concentration of the semiconductor substrate; a first impurity region of the first conductivity type other than the semiconductor substrate and the first impurity region is not formed in a portion of the semiconductor substrate located between the first drain region, the first gate electrode, and the first source region and the first impurity region.

12. 12. The method for manufacturing a semiconductor device according to claim 11, a semiconductor substrate having a first impurity region and a second impurity region, the first impurity region being formed on the semiconductor substrate; a second impurity region and a third impurity region being formed on the semiconductor substrate;

13. 12. The method for manufacturing a semiconductor device according to claim 11, the semiconductor substrate includes a support substrate of the first conductivity type and a semiconductor layer of the first conductivity type formed on the support substrate by an epitaxial growth method; The method for manufacturing a semiconductor device, wherein the first source region, the first drain region, and the first impurity region are formed in the semiconductor layer.

14. 12. The method for manufacturing a semiconductor device according to claim 11, an impurity profile of the first impurity region having a predetermined half width at half maximum from an impurity concentration peak of the first impurity region; The method for manufacturing a semiconductor device, wherein the impurity concentration peak of the first impurity region is located at a position equal to or greater than the half width at half maximum from the upper surface of the semiconductor substrate.

15. 15. The method for manufacturing a semiconductor device according to claim 14, a first impurity region having an impurity concentration peak located at a position shallower than a sum of the first depth of the first drain region and twice the length of the first gate electrode in a direction from the first drain region to the first source region from the top surface of the semiconductor substrate.

16. 12. The method for manufacturing a semiconductor device according to claim 11, (f) forming a first isolation portion in the semiconductor substrate; Further provided with the first isolation portion has a third depth from the top surface of the semiconductor substrate; the first depth of the first drain region and the second depth of the first source region are shallower than the third depth of the first element isolation part, a peak of the impurity concentration of the first impurity region is located at a position deeper than the third depth of the first element isolation part;

17. 17. The method for manufacturing a semiconductor device according to claim 16, an impurity concentration peak of the first impurity region is located at a position shallower than the sum of the first depth of the first drain region and twice the length of the first gate electrode in a direction from the first drain region to the first source region from the top surface of the semiconductor substrate.

18. 18. The method for manufacturing a semiconductor device according to claim 17, (g) forming a second impurity region of the second conductivity type in the semiconductor substrate; (h) forming a second isolation portion in the semiconductor substrate; Further provided with the second isolation portion has a fourth depth from the top surface of the semiconductor substrate; the second impurity region is located below the first impurity region, the fourth depth of the second element isolation portion is deeper than the third depth of the first element isolation portion; the second element isolation portion is in contact with the first impurity region and the second impurity region.

19. 20. The method of manufacturing a semiconductor device according to claim 18, a distance between the second element isolation portion and the first drain region in a plan view is 1 μm or less.

20. 12. The method for manufacturing a semiconductor device according to claim 11, (i) forming a third element isolation portion in the semiconductor substrate; (j) forming a resurf region of the first conductivity type in the semiconductor substrate; (k) forming a drift region of the second conductivity type in the semiconductor substrate; (l) forming a well region of the first conductivity type in the semiconductor substrate; (m) forming a second gate insulating film on the drift region and the well region; (n) forming a second gate electrode on the second gate insulating film and on a part of the third element isolation part; (o) forming a second drain region of the second conductivity type in the drift region; (p) forming a second source region of the second conductivity type in the well region; Further provided with the third isolation portion is located in the drift region, the resurf region is formed in a portion of the semiconductor substrate located below the drift region and the well region, The method for manufacturing a semiconductor device, wherein the step (b) and the step (i) are performed as the same step.

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