Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a leakage current.SOLUTION: A semiconductor device according to the present disclosure includes a first semiconductor layer of a first conductivity type having a first impurity concentration C111, an epitaxial semiconductor layer disposed on the first semiconductor layer, a first device region formed in a first region of the epitaxial semiconductor layer in plan view, a second device region formed in a second region of the epitaxial semiconductor layer in plan view and to which a voltage higher than a voltage applied to the first device region is applied, and a second semiconductor layer formed on the first semiconductor layer in the first region and not formed on the first semiconductor layer in the second region, and a second layer of the first conductivity type having a second impurity concentration C12, wherein C11 <C12, 2 * 1014 (cm-3) ≤ C12 ≤ 1 * 1016 (cm-3).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a plurality of types of device regions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent No. 9812565 [Summary]

[0004] The present disclosure provides a semiconductor device capable of reducing leakage current.

[0005] The semiconductor device of the present disclosure has a first impurity concentration C 11 an epitaxial semiconductor layer disposed on the first semiconductor layer; a first device region formed in a first region of the epitaxial semiconductor layer in a plan view; a second device region formed in a second region of the epitaxial semiconductor layer in a plan view, the second device region being applied with a higher voltage than the first device region; and a second impurity concentration C 12 and a second semiconductor layer of the first conductivity type having the following relationship: C 11 <C 12 , 2 × 10 14 (cm -3 )≦C 12 ≦1×10 16 (cm -3 ) is satisfied. [Brief explanation of the drawings]

[0006] [Figure 1] 1A is a plan view of the semiconductor device, and FIG. 1B is a vertical cross-sectional view taken along the line AA in FIG. 1A. [Figure 2] FIG. 2 is a diagram showing a vertical cross-sectional configuration within a region of a first example of a semiconductor device. [Figure 3] FIG. 3 is a diagram showing a vertical cross-sectional configuration within a region of a second example of a semiconductor device. [Figure 4] FIG. 4 is a diagram showing a vertical cross-sectional configuration within a region of a third example of a semiconductor device. [Figure 5] FIG. 5 is a diagram showing a vertical cross-sectional configuration within a region of a fourth example of a semiconductor device. [Figure 6] 6A and 6B are a diagram showing the vertical cross-sectional configuration of the first device region 16A (FIG. 6A) and a diagram showing the vertical cross-sectional configuration of the other device region 16B (FIG. 6B). [Figure 7] FIG. 7 is a diagram showing a vertical cross-sectional configuration within a region of a fifth example of a semiconductor device. [Figure 8] FIG. 8 is a plan view of a region in a fifth example of a semiconductor device. [Figure 9] FIG. 9 is a diagram showing a vertical cross-sectional configuration within a region of a sixth example of a semiconductor device. [Figure 10] FIG. 10 is a diagram showing the relationship between impurity concentration, leakage current, and breakdown voltage. [Figure 11] 11A and 11B are a graph showing the relationship between impurity concentration and leakage current (FIG. 11A) and a graph showing the relationship between impurity concentration and breakdown voltage (FIG. 11B).

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in each drawing are designated by the same reference numerals, and redundant explanations will be omitted.

[0008] 1A is a plan view of the semiconductor device, and FIG. 1B is a vertical cross-sectional view taken along the line AA in FIG. 1A.

[0009] The semiconductor device (semiconductor chip 100) includes a low-voltage region RL, a medium-voltage region RM, and a high-voltage region RH. Transistors and other components corresponding to the respective breakdown voltages are arranged within each region. For example, in a BCD (BIPOLAR-CMOS-DMOS) chip, the region where a DMOS (double-diffused metal-oxide semiconductor) FET (field-effect transistor) is formed can be designated as the high-voltage region RH, and the regions where the remaining transistors are formed can be designated as the low-voltage region RL or the medium-voltage region RM. This configuration is an example of a semiconductor chip having multiple regions with different breakdown voltages, and semiconductor chips with other structures are also known. Different voltages are used to drive devices within each region: a relatively high voltage is applied to devices within the high-voltage region RH, a relatively low voltage is applied to devices within the low-voltage region RL, and a voltage somewhere in between these two is applied to devices within the medium-voltage region RM.

[0010] The semiconductor device includes a first semiconductor layer 11 and a second semiconductor layer 12 formed on a low-breakdown voltage region RL and a medium-breakdown voltage region RM on the first semiconductor layer 11. In other words, the second semiconductor layer 12 is formed on a region of the first semiconductor layer 11 excluding the high-breakdown voltage region RH. The first semiconductor layer 11 is a semiconductor substrate or a semiconductor layer formed on a semiconductor substrate. For the sake of clarity, the region where the second semiconductor layer 12 is formed is shaded in FIG. 1(A).

[0011] In an XYZ three-dimensional Cartesian coordinate system, the thickness direction (depth direction) of the first semiconductor layer 11 is defined as the Z-axis direction. The axis perpendicular to the Z-axis is defined as the X-axis, and the axis perpendicular to both the Z-axis and the X-axis is defined as the Y-axis. The main surface in a plan view of the semiconductor chip 100 is the XY plane. Referring to FIG. 1(B) showing the XZ cross-sectional structure, an epitaxial semiconductor layer 14 is formed on the first semiconductor layer 11 in the high-breakdown voltage region RH. The epitaxial semiconductor layer 14 is formed on the second semiconductor layer 12 in the low-breakdown voltage region RL and the medium-breakdown voltage region RM. A buried semiconductor layer 13 is formed on the second semiconductor layer 12. The epitaxial semiconductor layer 14 is located on the buried semiconductor layer 13. The P-type second semiconductor layer 12 and the N-type buried semiconductor layer 13 are in contact with each other to form a PN junction, which can be represented as a parasitic diode D1. When a voltage exceeding the reverse breakdown voltage of the parasitic diode D1 is applied to the parasitic diode D1, a breakdown phenomenon occurs.

[0012] In this example, in the low-breakdown voltage region RL, a first device region 16A is formed on the buried semiconductor layer 13. In the medium-breakdown voltage region RM, a first device region 16A is also formed on the buried semiconductor layer 13. The first device region 16A is formed on the buried semiconductor layer 13 and is surrounded by a first isolation region 15 that is annular in plan view. The second device region 16C is formed on the epitaxial semiconductor layer 14 and is surrounded by a second isolation region 19 that is annular in plan view.

[0013] The conductivity type of the first semiconductor layer 11 is P-type, and the first semiconductor layer 11 has a first impurity concentration C 11In this example, P type is the first conductivity type and N type is the second conductivity type, but these conductivity types can be interchanged to function as an element. The conductivity type of the epitaxial semiconductor layer 14 is N type. The first device region 16A is formed in a first region (low-breakdown voltage region RL or medium-breakdown voltage region RM) of the epitaxial semiconductor layer 14 in a planar view. The second device region 16C is formed in a second region (high-breakdown voltage region RH) of the epitaxial semiconductor layer 14 in a planar view. A higher voltage is applied to the second device region 16C than to the first device region 16A.

[0014] The second semiconductor layer 12 is formed on the first semiconductor layer 11 in the first region (low-breakdown voltage region RL or medium-breakdown voltage region RM), but is not formed on the first semiconductor layer 11 in the second region (high-breakdown voltage region RH). The conductivity type of the second semiconductor layer 12 is P-type, and the second semiconductor layer 12 has a second impurity concentration C 12 The first impurity concentration C 11 and the second impurity concentration C 12 is C 11 <C 12 The second impurity concentration C 12 is 2 x 10 14 (cm -3 )≦C 12 ≦1×10 16 (cm -3 ) is satisfied. Within this range, the breakdown voltage can be maintained while suppressing leakage current in the low withstand voltage region RL and the medium withstand voltage region RM. Increasing the impurity concentration of the second semiconductor layer 12 tends to decrease the breakdown voltage. Therefore, the high withstand voltage region RH does not include the second semiconductor layer 12.

[0015] Second impurity concentration C 12 is C 12 ≦6×10 15 (cm -3 In this case, the breakdown voltage can be further increased in the first region (low withstand voltage region RL or medium withstand voltage region RM).

[0016] Second impurity concentration C12 is C 12 ≦4×10 15 (cm -3 In this case, the breakdown voltage can be further increased in the first region (low withstand voltage region RL or medium withstand voltage region RM).

[0017] The conductivity type of the buried semiconductor layer 13 is N-type, and in the first region (low-breakdown voltage region RL or medium-breakdown voltage region RM), the buried semiconductor layer 13 is formed on the second semiconductor layer 12, and has a third impurity concentration C 13 The second impurity concentration C 12 and the third impurity concentration C 13 is C 12 <C 13 The third impurity concentration C 13 is 1.0 x 10 18 (cm -3 )≦C 13 ≦1.0×10 19 (cm -3 ) is preferably satisfied. 13 However, if the value is below the lower limit, the parasitic NPN bipolar transistor becomes more likely to operate, and if the value is above the upper limit, the breakdown voltage of elements in the low and medium breakdown voltage regions will decrease.

[0018] An exemplary value for the thickness t(L) of the second semiconductor layer 12 is 10 μm, and an exemplary value for the thickness t(H) of the buried semiconductor layer 13 is 6 μm. These values ​​satisfy the relationship 8 μm≦t(L)≦12 μm, and may also satisfy the relationship 5 μm≦t(H)≦7 μm. This is because if the thickness is below the lower limit, the effect of reducing leakage current weakens, and if the thickness exceeds the upper limit, it becomes difficult to form an element.

[0019] The upper end position (Z 12H ) is the upper end position (Z 13H ) and bottom position (Z 13L ) is located between the bottom end position (Z 12L ) is the bottom end position (Z 13L ) is closer to the first semiconductor layer 11.

[0020] The first region (low-breakdown voltage region RL or medium-breakdown voltage region RM) surrounds the first device region 16A in a planar view from the Z-axis direction, has a second conductivity type (N-type), and includes a first isolation region 15 extending from the buried semiconductor layer 13 toward the substrate surface.

[0021] The second region (high-withstand voltage region RH) surrounds the second device region 16C in plan view, has the first conductivity type (P type), and includes a second isolation region 19 extending from the first semiconductor layer 11 toward the substrate surface.

[0022] FIG. 2 is a diagram showing a vertical cross-sectional configuration within a region of a first example of a semiconductor device.

[0023] The region 10A of the first example is an element region in the first region (the low-breakdown voltage region RL or the medium-breakdown voltage region RM). The first device region 16A in the first region includes, for example, a first field-effect transistor (see FIG. 6A) having a channel of a second conductivity type (N-type). A second semiconductor layer 12 is formed on a first semiconductor layer 11. A buried semiconductor layer 13 is formed on a portion of the second semiconductor layer 12. A lower first isolation region 15A extends upward from the peripheral region of the buried semiconductor layer 13. An upper first isolation region 15B is formed on the lower first isolation region 15A. The lower first isolation region 15A and the upper first isolation region 15B constitute the first isolation region 15. The upper first isolation region 15B can be a surface contact region to which a bias potential can be applied, as necessary. The conductivity type of the lower first isolation region 15A and the upper first isolation region 15B is the second conductivity type (N type). The impurity concentration of the upper first isolation region 15B can be set higher than the impurity concentration of the lower first isolation region 15A.

[0024] The surface of the substrate is covered with an insulating region 18. The insulating region 18 is made of a field oxide film or STI (shallow trench isolation), or the like.

[0025] FIG. 3 is a diagram showing a vertical cross-sectional configuration within a region of a second example of a semiconductor device.

[0026] The region 10B of the second example is an element region in the first region (low-breakdown voltage region RL or medium-breakdown voltage region RM) described above. A separate device region 16B different from the first device region 16A can be provided in the first region. The separate device region 16B includes, for example, a second field-effect transistor (see FIG. 6B) having a channel of the first conductivity type (P-type). A second semiconductor layer 12 is formed on the first semiconductor layer 11. A buried semiconductor layer 13 is formed on a partial region of the second semiconductor layer 12. A lower isolation region 17A extends upward from the first semiconductor layer 11 so as to surround the buried semiconductor layer 13 in a plan view. An upper isolation region 17B is formed on the lower isolation region 17A. The lower isolation region 17A and the upper isolation region 17B form an isolation region 17. The upper isolation region 17B can be a surface contact region to which a bias potential can be applied if necessary, but in this example, no bias potential is applied. The conductivity types of the lower isolation region 17A and the upper isolation region 17B are both the first conductivity type (P type).

[0027] FIG. 4 is a diagram showing a vertical cross-sectional configuration within a region of a third example of a semiconductor device.

[0028] The region of the third example is an element region in the first region (low-breakdown voltage region RL or medium-breakdown voltage region RM) described above, and has a structure in which the region 10A and region 10B described above are adjacent to each other.

[0029] A first device region 16A formed in region 10A may be a first field effect transistor having an N-type channel, and another device region 16B formed in region 10B may be a second field effect transistor having a P-type channel.

[0030] In a plan view, the first device region 16A is surrounded by an N-type first isolation region 15. The first isolation region 15 is connected to the periphery of the buried semiconductor layer 13. In a plan view, the other device region 16B is surrounded by a P-type isolation region 17. The isolation region 17 is connected to the periphery of the first semiconductor layer 11 and extends from the first semiconductor layer 11 toward the substrate surface.

[0031] FIG. 5 is a diagram showing a vertical cross-sectional configuration within a region of a fourth example of a semiconductor device.

[0032] The region of the fourth example is an element region within the first region (low-breakdown voltage region RL or medium-breakdown voltage region RM) described above, and has a structure in which regions 10a and 10b, which are modified isolation regions in the above-mentioned regions 10A and 10B, are adjacent to each other.

[0033] A first device region 16A formed in region 10a may be a first field effect transistor having an N-type channel, and another device region 16B formed in region 10b may be a second field effect transistor having a P-type channel.

[0034] The first device region 16A and the other device region 16B are surrounded by an N-type first isolation region 15 in plan view. The first isolation region 15 is connected to the periphery of the buried semiconductor layer 13.

[0035] 6A and 6B are a diagram showing the vertical cross-sectional configuration of the first device region 16A (FIG. 6A) and a diagram showing the vertical cross-sectional configuration of the other device region 16B (FIG. 6B).

[0036] 6(A) shows an N-channel field effect transistor as the first device region 16A. The first device region 16A includes a first P-type semiconductor layer 161 and a second P-type semiconductor layer 162 formed on the first P-type semiconductor layer 161. An N-type source region SR and an N-type drain region DR are formed on the surface side of the second P-type semiconductor layer 162. A P-type contact region 164 is formed on the surface side of the second P-type semiconductor layer 162. A gate electrode GE is formed on the region between the source region SR and the drain region DR via a gate insulating film GX.

[0037] A source terminal S is electrically connected to the source region SR, a drain terminal D is electrically connected to the drain region DR, and a gate terminal G is electrically connected to the gate electrode GE. The surface of the substrate where no electrodes or contacts need to be formed is covered with an insulating region 18.

[0038] The P-type impurity concentration in the first P-type semiconductor layer 161 is lower than the P-type impurity concentration in the second P-type semiconductor layer 162. The P-type impurity concentration in the P-type contact region 164 is higher than the P-type impurity concentration in the second P-type semiconductor layer 162.

[0039] 6(B) shows a P-channel field effect transistor as the separate device region 16B. The separate device region 16B includes an N-type semiconductor layer 165. A P-type source region SR and a P-type drain region DR are formed on the surface side of the N-type semiconductor layer 165. An N-type contact region 166 is formed on the surface side of the N-type semiconductor layer 165. A gate electrode GE is formed on the region between the source region SR and the drain region DR via a gate insulating film GX.

[0040] In the P-channel field effect transistor, the source region SR is electrically connected to a source terminal S, the drain region DR is electrically connected to a drain terminal D, and the gate electrode GE is electrically connected to a gate terminal G. The surface of the substrate where no electrodes or contacts need to be formed is covered with an insulating region 18.

[0041] Fig. 7 is a diagram showing a vertical cross-sectional configuration within a region of a fifth example of a semiconductor device. Fig. 8 is a plan view of the region of the fifth example of a semiconductor device. In Fig. 8, the N-type well region 168, terminals, etc. are omitted. Fig. 7 also shows a vertical cross-sectional configuration taken along the arrow AA in Fig. 8.

[0042] This example discloses an example of a transistor included in a second device region 16C formed in a high-voltage region. An epitaxial semiconductor layer 14 is formed on a first semiconductor layer 11. A second device region 16C including a transistor is formed in the epitaxial semiconductor layer 14. This transistor is a field-effect transistor.

[0043] The field-effect transistor formed in the high-breakdown voltage region (second region) includes a source region SR, a drain region DR, and a drift region 167 disposed between the source region SR and the drain region DR. The drift region 167 is formed on the epitaxial semiconductor layer 14.

[0044] The second isolation region 19 is formed to surround the device region in a plan view. The second isolation region 19 includes a first P-type semiconductor layer 19A extending upward from the first semiconductor layer 11, a second P-type semiconductor layer 19B (well region) formed on the first P-type semiconductor layer 19A, and a surface contact layer 19C formed on the second P-type semiconductor layer 19B. The conductivity type of the first P-type semiconductor layer 19A, the second P-type semiconductor layer 19B, and the surface contact layer 19C is P-type. A back gate potential BK of ground level is applied to the surface contact layer 19C of the second isolation region 19.

[0045] An N-type source region SR is formed in the second P-type semiconductor layer 19B as a P-type well region. A part of the second P-type semiconductor layer 19B is interposed between the source region SR and the epitaxial semiconductor layer 14, and a gate electrode GE is formed thereon with a gate insulating film GX interposed therebetween.

[0046] An N-type well region 168 is formed in the region between the drift region 167 and the drain region DR and in the region below the drain region DR. The depth of the N-type well region 168 is greater than the depth of the drift region 167. An insulating film GX1 is formed on the drift region 167 and the N-type well region 168, except for the region directly above the drain region DR. A field plate FP is disposed on the insulating film GX1. The field plate FP is made of a metal material having a spiral shape in a plan view, and can gradually change the potential in the X-axis direction in the drift region 167, thereby improving the breakdown voltage.

[0047] One end of the field plate FP on the drain side is connected to the drain terminal D together with the drain region DR, and a drain potential is applied. A ground-level back gate potential BK is applied to one end of the field plate FP on the source side. When a source-drain voltage is applied between the source terminal S connected to the source region SR and the drain terminal D connected to the drain region DR, and a positive potential is applied to the gate electrode GE via the gate terminal G, an N-type channel is formed between the source region SR and the drift region 167. Electrons from the source region SR flow through the drift region 167 and reach the drain region DR via the N-type well region 168. Note that the structure of this example is symmetrical with respect to the YZ plane passing through the drain region DR. Electrons generated in the left source region SR travel to the right, and electrons generated in the right source region SR travel to the left and reach the central drain region DR.

[0048] As shown in FIG. 8, the drift region 167 has an impurity concentration (C 167H ) is relatively high, and the first drift region 167H has a low impurity concentration (C 167L The first drift region 167H and the second drift region 167L are arranged alternately along the Y-axis direction. In other words, the impurity concentration (C 167) fluctuates periodically in a direction (Y-axis direction) perpendicular to the carrier travel direction (X-axis direction) in the channel of this field-effect transistor in a plan view. Carriers tend to flow through areas with low resistance. In the so-called superjunction structure, there are performance-improving effects such as reducing on-resistance and increasing breakdown voltage, but the stripe structure with impurity concentration differences as in this example also has the effect of improving transistor performance.

[0049] FIG. 9 is a diagram showing a vertical cross-sectional configuration within a region of a sixth example of a semiconductor device.

[0050] This example discloses an example of a transistor included in a first device region 16A formed in a low-breakdown-voltage region or a medium-breakdown-voltage region. The transistor in this example is an NPN bipolar transistor. A second semiconductor layer 12 is formed on a first semiconductor layer 11, and an epitaxial semiconductor layer 14 is formed on the second semiconductor layer 12. A buried semiconductor layer 13 is formed on a partial region of the second semiconductor layer 12. A P-type well region PW is formed in the epitaxial semiconductor layer 14 on the buried semiconductor layer 13. An N-type emitter region ER and a P-type base region BR are formed in the P-type well region PW.

[0051] An N-type lower first isolation region 15A extends upward from the peripheral region of the buried semiconductor layer 13. A collector region CR is formed on the lower first isolation region 15A. An emitter terminal E, a base terminal B, and a collector terminal C are connected to the emitter region ER, the base region BR, and the collector region CR, respectively.

[0052] FIG. 10 is a diagram showing the relationship between impurity concentration, leakage current, and breakdown voltage.

[0053] In the case of the structure of the region including the first device region 16A shown in FIG. 1, the second impurity concentration C 12 (cm -3), leakage current I from the first device region 16A to the first semiconductor layer 11 side LEAK (A), the reference leakage current (1.8 × 10 ―10 Leakage current I normalized to 100% (A) LEAK (%), the breakdown voltage V LIMIT (V) is shown.

[0054] Second impurity concentration C 12 (cm -3 ) is 6×10 13 (cm -3 ) ~ 2.5 × 10 16 (cm -3 The second impurity concentration C 12 (cm -3 ) increases, the leakage current decreases, and therefore the second semiconductor layer 12 functions as a leakage current suppressing layer. 12 (cm -3 ) but 1×10 15 (cm -3 ) exceeds the breakdown voltage V LIMIT (V) began to drop sharply, reaching 1.2×10 16 (cm -3 ) in the breakdown voltage V LIMIT (V) drops to 70(V).

[0055] From the viewpoint of slightly suppressing the leakage current, the second impurity concentration C 12 (cm -3 ) is 1×10 where the leakage current is reduced to 61.1(%). 14 (cm -3 ) or more. From the viewpoint of sufficiently suppressing the leakage current, the second impurity concentration C 12 (cm -3 ) shows that the leakage current has decreased to 31.1% (2 × 10 14 (cm -3 ) or more. From the viewpoint that a breakdown voltage of about 70 (V) is sufficient, the second impurity concentration C 12 (cm -3 ) is 1.2 × 10 16 (cm -3) or less. From the viewpoint that a breakdown voltage of 250 (V) is quite good, the second impurity concentration C 12 (cm -3 ) is 5.7 × 10 15 (cm -3 ) or less is sufficient.

[0056] Figure 11 shows the impurity concentration (C 12 (cm -3 )) and leakage current (I LEAK (A)) and the impurity concentration (C 12 (cm -3 )) and breakdown voltage (V LIMIT 11(B) and 11(C) are graphs showing the relationship between the temperature (V) and the temperature (C). These graphs are plots of the data shown in FIG. 10.

[0057] Second impurity concentration C 12 (cm -3 ) increases, the leakage current I LEAK From the viewpoint of sufficiently reducing the leakage current, the second impurity concentration C 12 (cm -3 ) is C MIN (=2×10 14 (cm -3 From the viewpoint of maintaining a sufficient breakdown voltage (100 V or more), the second impurity concentration C 12 (cm -3 ) is C MAX (=1×10 16 (cm -3 )) or less is preferable.

[0058] To further increase the breakdown voltage, C MAX =6×10 15 (cm -3 ) can also be used. That is, C 12 ≦6×10 15 (cm -3 In this case, the breakdown voltage V LIMIT (V) can exceed at least 200V. To further increase the breakdown voltage, C MAX =4×10 15 (cm-3 ) can also be used. That is, C 12 ≦4×10 15 (cm -3 In this case, the breakdown voltage V LIMIT (V) can exceed at least 1000V.

[0059] Next, the materials and impurity concentrations of the above-mentioned semiconductor regions will be described.

[0060] The semiconductor material constituting the semiconductor chip described above is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor chip. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Si-containing semiconductors such as SiC and SiGe can be used as IV-IV compound semiconductors. In addition, impurities can be added to the semiconductor region by ion implantation, but diffusion methods can also be used.

[0061] More specifically, the material of the first semiconductor layer 11 or the semiconductor substrate is silicon (Si). The material of the first semiconductor layer 11 can be, for example, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). The conductivity type of the first semiconductor layer 11 is P-type (first conductivity type), and its first impurity concentration (C 11 ) is, for example, 1×10 14 cm -3 ≦C 11 ≦5×10 18 cm -3 When the first semiconductor layer 11 is a semiconductor substrate, the thickness is, for example, 250 μm to 800 μm.

[0062] The material of the second semiconductor layer 12 can be the same as the semiconductor material of the first semiconductor layer 11. The conductivity type of the second semiconductor layer 12 is P type (first conductivity type), and the second impurity concentration (C 12 ) is C 11 <C12 The second impurity concentration C 12 and the range of the thickness t(L) of the second semiconductor layer 12 are as described above. The second semiconductor layer 12 can be formed by a technique of implanting a P-type impurity (such as boron) into the first semiconductor layer 11 and thermally diffusing the impurity, or by implanting ions of a P-type impurity (such as boron) into the epitaxial semiconductor layer 14 during its manufacture and then growing the epitaxial semiconductor layer 14 thereon.

[0063] The material of the buried semiconductor layer 13 can be the same as the semiconductor material of the first semiconductor layer 11. The conductivity type of the buried semiconductor layer 13 is N-type (second conductivity type), and the third impurity concentration (C 13 ) is C 11 <C 13 , C 12 <C 13 The third impurity concentration C 13 and the range of the thickness t(H) of the buried semiconductor layer 13 are as described above. The buried semiconductor layer 13 can be formed by implanting ions of an N-type impurity (such as As) into the second semiconductor layer 12 and then growing an epitaxial semiconductor layer 14 thereon.

[0064] The material of the epitaxial semiconductor layer 14 can be the same as the semiconductor material of the first semiconductor layer 11. The conductivity type of the epitaxial semiconductor layer 14 is N-type (second conductivity type), and the fourth impurity concentration (C 14 ) is, for example, 5×10 14 cm -3 ≦C 14 ≦1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 14 can be set to, for example, 3 μm to 20 μm. In this example, the impurity concentration is 14 <C 11 <C 13 The relationship is fulfilled.

[0065] It is also possible to make the conductivity type of the epitaxial semiconductor layer 14 P-type in order to reduce the drain capacitance of the transistor or for other purposes.

[0066] The materials of the first P-type semiconductor layer 161 and the second P-type semiconductor layer 162 in the transistor (FIG. 6) can be the same as the semiconductor material of the first semiconductor layer 11. The impurity concentration (C 161 ) is the impurity concentration (C 162 ) can be set lower than (C 161 <C 162 The thickness of these layers can be, for example, 0.5 μm to 4 μm.

[0067] The material of the contact region 164 in the transistor (FIG. 6) can be the same as the semiconductor material of the first semiconductor layer 11. The impurity concentration (C 164 ) is the impurity concentration (C 162 ) can be set higher than (C 162 <C 164 The thickness of the contact region 164 can be set to, for example, 0.2 μm to 1 μm, but a structure with an even shallower depth or a structure with an even deeper depth is also possible.

[0068] The material of the source region SR and the drain region DR can be the same as the semiconductor material of the first semiconductor layer 11. The conductivity type of the source region SR and the drain region DR is N-type (second conductivity type), and the impurity concentration of each region (C SR , C DR ) is, for example, 1×10 19 cm -3 ≦C SR ≦5×10 21 cm -3 , 1×10 19 cm -3 ≦C DR ≦5×10 21 cm -3 The thickness of the source region SR and the drain region DR can be set to, for example, 0.2 μm to 1 μm, but a structure in which these depths are made shallower or deeper is also possible.

[0069] The material of the contact region 166 in the transistor (FIG. 6) can be the same as the semiconductor material of the first semiconductor layer 11. The impurity concentration (C 166 ) is the impurity concentration (C 165 ) can be set higher than (C 165 <C 166 The thickness of the contact region 166 can be set to, for example, 0.2 μm to 1 μm, but a structure with an even shallower depth or a structure with an even deeper depth is also possible.

[0070] The material of the first drift region 167H in the transistor (FIG. 7) can be the same as the semiconductor material of the first semiconductor layer 11. The impurity concentration (C 167H ) is the impurity concentration (C 14 ) can be set higher than (C 14 <C 167H ) The impurity concentration (C 167H ) is, for example, 3×10 15 cm -3 ≦C 167H ≦5×10 17 cm -3 can be set to.

[0071] The material of the second drift region 167L in the transistor (FIGS. 7 and 8) can be the same as the semiconductor material of the first semiconductor layer 11. The impurity concentration (C 167L ) is the impurity concentration (C 14 ) or more, and the impurity concentration (C 167H ) can be set lower than (C 14 ≦C 167L <C 167H ) The impurity concentration (C 167L ) is, for example, 5×10 14 cm -3 ≦C 167L ≦2×10 16 cm-3 can be set to.

[0072] In addition, in the range of various parameters, the range of an arbitrary parameter P is P min ≦P≦P max If given by (P min +ΔP)≦P≦(P max -ΔP), ΔP=(P max -P min )×R%, R may be set to 10, or R may be set to 20, R may be set to 30, or R may be set to 40.

[0073] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0074] [A1] First impurity concentration C 11 an epitaxial semiconductor layer 14 disposed on the first semiconductor layer 11; a first device region formed in a first region (e.g., low-breakdown voltage region RL) of the epitaxial semiconductor layer 14 in a plan view; a second device region formed in a second region (e.g., high-breakdown voltage region RH) of the epitaxial semiconductor layer 14 in a plan view and to which a higher voltage is applied than the first device region; and a second impurity region formed on the first semiconductor layer 11 in the first region (e.g., low-breakdown voltage region RL) and not formed on the first semiconductor layer 11 in the second region (e.g., high-breakdown voltage region RH), and having a second impurity concentration C 12 and a second semiconductor layer 12 of the first conductivity type having the following relationship: C 11 <C 12 , 2 × 10 14 (cm -3 )≦C 12 ≦1×10 16 (cm -3 ) a semiconductor device that satisfies the requirements.

[0075] [A2] The following relationship: C 12 ≦6×10 15 (cm -3 ) The semiconductor device according to [A1],

[0076] [A3] The following relationship: C 12 ≦4×10 15 (cm -3 ) The semiconductor device according to [A1],

[0077] [A4] In the first region (for example, low-breakdown voltage region RL), a third impurity concentration C 13 and a buried semiconductor layer 13 of a second conductivity type having the following relationship: C 12 <C 13 The semiconductor device according to [A1] satisfies the above.

[0078] [A5] The semiconductor device according to [A4], wherein the thickness t(L) of the second semiconductor layer 12 and the thickness t(H) of the buried semiconductor layer 13 satisfy the following relationship: 8 μm≦t(L)≦12 μm, 5 μm≦t(H)≦7 μm.

[0079] [A6] The semiconductor device according to [A4], wherein the upper end position of the second semiconductor layer is located between the upper end position and the lower end position of the buried semiconductor layer, and the lower end position of the second semiconductor layer is closer to the first semiconductor layer than the lower end position of the buried semiconductor layer.

[0080] [A7] The semiconductor device according to claim 4, wherein the first region (low-withstand voltage region, medium-withstand voltage region) comprises: a first field-effect transistor (FIGS. 4, 6(A)) having a channel of the second conductivity type; a first isolation region (15) surrounding the first field-effect transistor in a planar view, having the second conductivity type, and extending from the buried semiconductor layer (13) toward the substrate surface; a second field-effect transistor (FIGS. 4, 6(B)) having a channel of the first conductivity type; and a second isolation region (17) surrounding the second field-effect transistor in a planar view, having the first conductivity type, and extending from the first semiconductor layer (11) toward the substrate surface.

[0081] [A8] The semiconductor device according to [A4], wherein the first region (low withstand voltage region, medium withstand voltage region) comprises: a first field effect transistor (Figures 5 and 6(A)) having a channel of a second conductivity type; a second field effect transistor (Figures 5 and 6(B)) having a channel of the first conductivity type; and an isolation region (15) having the second conductivity type, surrounding the first field effect transistor (first device region 16A) and the second field effect transistor (another device region 16B) in a planar view, and extending from the buried semiconductor layer 13 toward the substrate surface.

[0082] [A9] The second region (high-breakdown voltage region) includes a field-effect transistor (FIGS. 7 and 8) including a source region SR, a drain region DR, and a drift region 167 disposed between the source region SR and the drain region DR, and the drift region 167 is formed on the epitaxial semiconductor layer 14, and the impurity concentration (C 167H , C 167L 2. The semiconductor device according to claim 1, wherein, in plan view, the .lambda. dc.sub.1 / dc.sub.2 periodically fluctuates along a direction perpendicular to a carrier traveling direction in a channel of the field effect transistor.

[0083] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0084] 10A,10a,10B,10b…area 11...First semiconductor layer 12...Second semiconductor layer 13...Buried semiconductor layer 14...Epitaxial semiconductor layer 15...First isolation area 15A...Lower first isolation area 15B...Upper first isolation region 16A...First device area 16B...Another device area 16C...Second device area 17A...Lower isolation area 17B...Upper isolation region 18...Isolation area 19A...First P-type semiconductor layer 19B...Second P-type semiconductor layer 19C...Surface contact layer 19...Second isolation area 161...First P-type semiconductor layer 162...Second P-type semiconductor layer 164...Contact area 165...N-type semiconductor layer 166...Contact area 167H...First drift region 167L...Second drift area 167...Drift area 168...N-type well region B: Base terminal BR...base area C: Collector terminal CR: Collector region D: Drain terminal DR...Drain region D1: Parasitic diode E: Emitter terminal ER: Emitter region FP...Field Plate G...Gate terminal GE: gate electrode GX...Gate insulating film GX1...insulating film PW: P-type well region RL: Low voltage region RM: Medium voltage range RH: High voltage region SR...Source region S: Source terminal

Claims

1. First impurity concentration C １１ a first semiconductor layer of a first conductivity type having an epitaxial semiconductor layer disposed on the first semiconductor layer; a first device region formed in a first region of the epitaxial semiconductor layer in a plan view; a second device region formed in a second region of the epitaxial semiconductor layer in a plan view, the second device region being supplied with a higher voltage than the first device region; formed on the first semiconductor layer in the first region and not formed on the first semiconductor layer in the second region, and having a second impurity concentration C １２ a second semiconductor layer of the first conductivity type having with the following relationships: C １１ <C １２ 、 2×10 １４ (cm －３ )≦C １２ ≦1×10 １６ (cm －３ )、 Semiconductor device that satisfies the above requirements.

2. The following relationship: C １２ ≦6×10 １５ (cm －３ )、 fulfill, The semiconductor device according to claim 1 .

3. The following relationship: C １２ ≦4×10 １５ (cm －３ )、 fulfill, The semiconductor device according to claim 1 .

4. In the first region, a third impurity concentration C １３ a buried semiconductor layer of a second conductivity type having The following relationship: C １２ <C １３ 、 fulfill, The semiconductor device according to claim 1 .

5. The thickness t(L) of the second semiconductor layer and the thickness t(H) of the buried semiconductor layer have the following relationship: 8μm≦t(L)≦12μm 5μm≦t(H)≦7μm Satisfying The semiconductor device according to claim 4 .

6. an upper end position of the second semiconductor layer is located between an upper end position and a lower end position of the buried semiconductor layer; a lower end position of the second semiconductor layer is closer to the first semiconductor layer than a lower end position of the buried semiconductor layer; The semiconductor device according to claim 4 .

7. The first region is a first field effect transistor having a channel of a second conductivity type; a first isolation region that surrounds the first field effect transistor in a plan view, has a second conductivity type, and extends from the buried semiconductor layer toward a substrate surface; a second field effect transistor having a channel of the first conductivity type; a second isolation region that surrounds the second field effect transistor in a plan view, has a first conductivity type, and extends from the first semiconductor layer toward a substrate surface; Equipped with The semiconductor device according to claim 4 .

8. The first region is a first field effect transistor having a channel of a second conductivity type; a second field effect transistor having a channel of the first conductivity type; an isolation region that surrounds the first field effect transistor and the second field effect transistor in a plan view, has a second conductivity type, and extends from the buried semiconductor layer toward a substrate surface; Equipped with The semiconductor device according to claim 4 .

9. The second region is A source region; a drain region; a drift region disposed between the source region and the drain region; a field effect transistor comprising: the drift region is formed on the epitaxial semiconductor layer; the impurity concentration of the drift region varies periodically in a direction perpendicular to a carrier traveling direction in a channel of the field effect transistor in a plan view; The semiconductor device according to claim 1 .

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