Semiconductor device

Abstract

To provide a semiconductor device which reduces on-resistance.SOLUTION: The semiconductor device 1 includes a first electrode 11 (drain electrode) and a second electrode 12 (source electrode) respectively provided on a lower surface 2a and an upper surface 2b of a semiconductor layer 2, a first semiconductor region (drift region 21, drain region) of a first conductivity type provided in the semiconductor layer, an upper region 24 having a higher impurity concentration than the first semiconductor region and extending from the first electrode toward the second electrode, a lower region 23 including a region narrower than the upper region, a third electrode 13 (gate electrode) provided in the semiconductor layer via an insulating region 51 and aligned with the lower region along a second direction Y orthogonal to a first direction Z from the first electrode toward the second electrode, and a second semiconductor region 20 facing the third electrode with the second semiconductor region interposed therebetween and electrically connected to the second electrode. The semiconductor device includes a first conductive part 41 in Schottky contact with the lower region, and a second conductive part 31 electrically connected to the second electrode and in ohmic contact with the upper region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices having switching functions, such as metal oxide semiconductor field effect transistors (MOSFETs), are known. In such semiconductor devices, it is preferable that the on-resistance is low. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-134149 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a semiconductor layer, a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first conductive portion, and a second conductive portion. The semiconductor layer has a first main surface and a second main surface. The first electrode is provided on the first main surface. The second electrode is provided on the second main surface. The first semiconductor region is a semiconductor region of a first conductivity type provided in the semiconductor layer and electrically connected to the first electrode. The second semiconductor region is a semiconductor region of a first conductivity type provided in the semiconductor layer and extending from the first semiconductor region toward the second electrode. The second semiconductor region has an upper region that includes an upper end of the second semiconductor region and has a higher impurity concentration than the first semiconductor region, and a lower region that is sandwiched between the upper region and the first semiconductor region and includes a region narrower in width than the upper region. The third electrode is provided in the semiconductor layer via an insulating region and is aligned with the lower region of the second semiconductor region along a second direction perpendicular to a first direction from the first electrode to the second electrode. The first conductive portion faces the third electrode across the second semiconductor region, is electrically connected to the second electrode, and makes Schottky contact with the lower region of the second semiconductor region. The second conductive portion is electrically connected to the second electrode and makes ohmic contact with the upper region of the second semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is an enlarged view of an area A1 in FIG. [Figure 3A] 1A to 1C are cross-sectional views for explaining an example of a manufacturing process of a semiconductor device according to an embodiment. [Figure 3B] 3B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, following FIG. 3A. FIG. [Figure 3C] 3B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 3D] 3D is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, following FIG. 3C. [Figure 3E] 3D, a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 3F] 3E and 3F are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a first modified example of the embodiment. [Figure 5] FIG. 5 is an enlarged view of an area A2 in FIG. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification of the embodiment. [Figure 7] FIG. 7 is an enlarged view of an area A3 in FIG. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor device according to a third modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] For ease of explanation, an XYZ Cartesian coordinate system is adopted, as shown in FIG. 1 etc. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. In addition, in the Z-axis direction, the source electrode side is also referred to as "upper" and the drain electrode side is also referred to as "lower." However, these expressions are for convenience and are unrelated to the direction of gravity. The Z-axis direction is the first direction in the claims. The Y-axis direction is the second direction in the claims. The X-axis direction is the third direction in the claims.

[0009] In the following description, n is used to indicate the relative level of impurity concentration in each conductivity type. + , n, n - , and ,p + , p, p- In some cases, the notation n + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than p. When both p-type and n-type impurities are contained in each region, these notations represent the relative high and low net impurity concentrations after the impurities compensate for each other. n-type, n + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The n-type is an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. In other words, the first conductivity type may be the p-type.

[0010] The impurity concentration of a semiconductor region can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS), and the relative level of the impurity concentration can be determined from the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM).

[0011] Furthermore, dimensions such as the width of the conductive portion can be measured by surface and / or cross-sectional analysis using, for example, a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or a scanning electron microscope (SEM).

[0012] The composition of the conductive portion can be analyzed by energy dispersive X-ray spectroscopy.

[0013] A semiconductor device 1 according to the embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view of the semiconductor device 1 according to the embodiment.

[0014] The semiconductor device 1 according to this embodiment is a vertical transistor. More specifically, the semiconductor device 1 is a vertical MOSFET that switches between an on state and an off state by controlling the potential of a gate electrode (a gate electrode 13 described later) to control the thickness of a Schottky barrier.

[0015] 1, the semiconductor device 1 includes a semiconductor layer 2 having a lower surface 2a and an upper surface 2b, a drain electrode 11 provided on the lower surface 2a, and a source electrode 12 provided on the upper surface 2b. The lower surface 2a and the upper surface 2b are examples of the first main surface and the second main surface, respectively, in the claims.

[0016] The semiconductor layer 2 is provided with various semiconductor regions, which will be described later. The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) is used as the n-type impurity, and for example, boron (B) is used as the p-type impurity. The semiconductor layer 2 may also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0017] The drain electrode 11 functions as a drain electrode of the semiconductor device 1. In this embodiment, the drain electrode 11 is in ohmic contact with a drain region 22 provided in the semiconductor layer 2. The drain electrode 11 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), or the like. The drain electrode 11 is an example of a first electrode in the claims.

[0018] The source electrode 12 functions as a source electrode of the semiconductor device 1. In this embodiment, the source electrode 12 is electrically connected to the drift region 21 via the conductive portion 31 and the conductive portion 32, and is electrically connected to the lower region 23 of the semiconductor layer 2 via the conductive portion 31, the conductive portion 32, and the conductive portion 41. The source electrode 12 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), or the like. The source electrode 12 is an example of a second electrode in the claims.

[0019] The following describes the details of the semiconductor layer 2. As shown in Fig. 1, the semiconductor layer 2 includes a gate electrode 13, an FP electrode 14, a thinned region 20, a drift region 21, a drain region 22, a conductive portion 31, a conductive portion 32, a conductive portion 41, and insulating regions 51 and 52.

[0020] The drift region 21 functions as the drift region of the semiconductor device 1. The drift region 21 is disposed above the drain region 22 (above the drain electrode 11). The drift region 21 is, for example, an n - The n-type impurity concentration of the drift region 21 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The following is the result.

[0021] The drain region 22 functions as the drain region of the semiconductor device 1. The drain region 22 is disposed between the drift region 21 and the drain electrode 11 and is electrically connected to the drain electrode 11. The drain region 22 is, for example, an n + The n-type impurity concentration of the drain region 22 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0022] Both the drift region 21 and the drain region 22 are examples of the first semiconductor region in the claims. The drain region 22 does not have to be provided. In this case, the drift region 21 is provided directly on the drain electrode 11, and the drain electrode 11 is electrically connected to the drift region 21. Alternatively, the drift region 21 does not have to be provided. In this case, for example, the drain region 22 is also provided at the position of the drift region 21.

[0023] The thinned region 20 is a semiconductor region of the first conductivity type that extends from the drift region 21 toward the source electrode 12. The thinned region 20 is an example of a second semiconductor region in the claims. The thinned region 20 has a lower region 23 and an upper region 24. The lower region 23 of the thinned region 20 is sandwiched between the upper region 24 and the drift region 21 in the Z-axis direction, and is sandwiched between the insulating region 51 and the conductive portion 41 in the Y-axis direction. The lower region 23 is, for example, an n-type semiconductor region having an impurity concentration similar to that of the drift region 21. - In this case, lower region 23 can be said to be a portion of drift region 21 that is provided between insulating region 51 and conductive portion 41. However, this is not limiting, and lower region 23 may have a higher impurity concentration than drift region 21, or may have a lower impurity concentration than drift region 21.

[0024] The upper region 24 of the thinned region 20 is a semiconductor region located above the lower region 23 and including an upper end 24a of the thinned region 20. The upper end 24a of the thinned region 20 is also the upper end of the upper region 24. The upper region 24 has a higher impurity concentration than the drift region 21. In this embodiment, the upper region 24 has a higher impurity concentration than the lower region 23. The upper region 24 is, for example, an n + The upper region 24 has an n-type impurity concentration of, for example, 8×10 19 cm -3 5x10 or more 20 cm -3 The following is the result.

[0025] The gate electrode 13 functions as the gate electrode of the semiconductor device 1. The gate electrode 13 is provided in the semiconductor layer 2 via an insulating region 51, and is aligned with the lower region 23 along the Y-axis direction perpendicular to the thickness direction (Z-axis direction) of the semiconductor layer 2. The gate electrode 13 is an example of a third electrode in the claims. In this embodiment, the gate electrode 13 extends in the X-axis direction in FIG. 1. The gate electrode 13 is made of, for example, polysilicon containing p-type or n-type impurities. The insulating region 51 is, for example, an insulating film containing silicon oxide or silicon nitride.

[0026] An insulating region 52 is provided on the gate electrode 13. The insulating region 52 is an interlayer insulating film that electrically insulates the gate electrode 13 from the source electrode 12. The insulating region 52 contains, for example, silicon oxide or silicon nitride. The shapes of the insulating region 51 and the insulating region 52 are not limited to those shown in FIG. 1 . For example, the insulating region 51 may also be provided on the gate electrode 13, and the insulating region 52 may be provided thereon.

[0027] The conductive portion 41 faces the gate electrode 13 along the Y-axis direction, with the thinned region 20 and the insulating region 51 sandwiched therebetween. In this embodiment, the conductive portion 41 faces the gate electrode 13 along the Y-axis direction, with the lower region 23 and the insulating region 51 sandwiched therebetween. The conductive portion 41 is electrically connected to the source electrode 12, and is in Schottky contact with the lower region 23 of the thinned region 20. In this embodiment, the conductive portion 41 is not directly connected to the source electrode 12, but is electrically connected to the source electrode 12 via the conductive portions 31 and 32. The conductive portion 41 is an example of a first conductive portion in the claims.

[0028] In this embodiment, the first conductivity type is n-type, and the conductive portion 41 includes a first metal element. The first metal element is at least one of Co, Ni, Se, Rh, Pd, Te, Re, Ir, Pt, and Au. The conductive portion 41 may include a compound (silicide) of the first metal element and silicon.

[0029] A Schottky junction between the conductive portion 41 and the lower region 23 forms a Schottky barrier on the semiconductor side of the interface between the conductive portion 41 and the lower region 23. If this Schottky barrier is thick, substantially no current flows from the drain electrode 11 to the source electrode 12, and the semiconductor device 1 is in the off state. Conversely, if this Schottky barrier is thin, current flows from the drain electrode 11 to the source electrode 12, and the semiconductor device 1 is in the on state. By controlling the potential of the gate electrode 13, the thickness of this Schottky barrier can be controlled, and the semiconductor device 1 can be switched between the on state and the off state.

[0030] The conductive portion 31 is located on the upper region 24. The conductive portion 31 is electrically connected to the source electrode 12 and is in ohmic contact with the upper region 24 of the thinned region 20. More specifically, the conductive portion 31 is in ohmic contact with the upper end of the upper region 24. The conductive portion 31 is an example of a second conductive portion in the claims.

[0031] In this embodiment, the conductive portion 31 has a work function different from that of the conductive portion 41. Furthermore, in this embodiment, the first conductivity type is n-type, and the work function of the conductive portion 31 is lower than that of the conductive portion 41. The conductive portion 31 includes a second metal element. The second metal element is at least one of Al, Mg, Ti, Se, V, Cr, Mn, Fe, Cu, Zn, Rb, Sr, Y, Zr, Nb, Mo, Ru, Ag, In, Sn, Sb, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, and Bi. The conductive portion 31 may include a compound (silicide) of the second metal element and silicon. Note that, when the first conductivity type is p-type, the work function of the conductive portion 31 is higher than that of the conductive portion 41. Furthermore, if an ohmic junction can be formed between the conductive portion 31 and the upper region 24, for example, because the impurity concentration in the upper region 24 is high, the work function of the conductive portion 31 may be the same as the work function of the conductive portion 41. Furthermore, if the first conductivity type is n-type, the work function of the conductive portion 31 may be higher than the work function of the conductive portion 41, and if the first conductivity type is p-type, the work function of the conductive portion 31 may be lower than the work function of the conductive portion 41.

[0032] The conductive portion 32 sandwiches the conductive portion 41 with the thinned region 20 along the Y-axis direction. In this embodiment, the conductive portion 32 sandwiches the conductive portion 41 with the lower region 23 along the Y-axis direction. The conductive portion 32 is electrically connected to the source electrode 12 via the conductive portion 31. The lower end of the conductive portion 32 makes Schottky contact with the drift region 21. In this embodiment, the first conductivity type is n-type, and the work function of the conductive portion 32 is lower than the work function of the conductive portion 41. Therefore, the Schottky barrier height between the conductive portion 32 and the drift region 21 is lower than the Schottky barrier height between the conductive portion 41 and the lower region 23 of the thinned region 20. The conductive portion 32 is an example of a third conductive portion in the claims. In this embodiment, the conductive portion 32 is made of the same material as the conductive portion 31. Note that the conductive portion 32 may be made of a different material from the conductive portion 31. In this case, the conductive portion 32 may include, for example, the second metal element or a compound (silicide) of the second metal element and silicon.

[0033] In this embodiment, the conductive portion 32 is in ohmic contact with at least a portion of the side surface of the upper region 24. The conductive portion 31 may extend to the side surface of the upper region 24, and the conductive portion 31 may be in ohmic contact with at least a portion of the side surface of the upper region 24. Alternatively, a conductive portion made of a material different from both the conductive portions 31 and 32 may be provided, and the conductive portion may be in ohmic contact with at least a portion of the side surface of the upper region 24.

[0034] 1 and 2, the conductive portion 32 and the conductive portion 41 are provided in the same trench. This trench is a contact trench that extends from the upper surface 2b of the semiconductor layer 2 to the drift region 21. In this embodiment, the shape of the contact trench in which the conductive portion 32 and the conductive portion 41 are provided is elliptical.

[0035] In this embodiment, the drift region 21, the drain region 22, the lower region 23, the upper region 24, the conductive portion 31, the conductive portion 32, and the conductive portion 41 extend along the X-axis direction. In this embodiment, the drift region 21, the drain region 22, the lower region 23, the upper region 24, the conductive portion 31, the conductive portion 32, and the conductive portion 41 extend to the end portion in the X-axis direction of the semiconductor layer 2, i.e., the terminal end (not shown). However, at the end portion in the X-axis direction, the impurity concentration of the upper region 24 may be lower than the impurity concentration other than the end portion.

[0036] As shown in FIG. 1 , the semiconductor device 1 according to this embodiment includes a field plate electrode (FP electrode) 14 provided in the semiconductor layer 2 via an insulating region 51. In the example of FIG. 1 , the FP electrode 14 is provided below the gate electrode 13 and extends in the X-axis direction. The FP electrode 14 is made of, for example, polysilicon containing p-type or n-type impurities. The FP electrode 14 is electrically connected to the source electrode 12 while being electrically insulated from the semiconductor layer 2 by the insulating region 51. By providing such an FP electrode 14, when the semiconductor device 1 is in an off state, a depletion layer extends from the FP electrode 14 to the surrounding drift region 21 due to a reverse voltage applied between the drain electrode 11 and the source electrode 12. This depletion layer connects to the depletion layer of the adjacent FP electrode 14, thereby improving the breakdown voltage of the semiconductor device 1. The semiconductor device 1 may also include an FP electrode provided in the semiconductor layer 2 via an insulating region (not shown) separate from the insulating region 51. The FP electrode 14 may also be provided to extend in a direction other than the X-axis direction (e.g., the Y-axis direction). Moreover, the FP electrode 14 does not necessarily have to be provided.

[0037] Next, the structure around the thinned region 20 in this embodiment, that is, the lower region 23, the upper region 24, and the conductive portion 41, will be described in more detail with reference to Fig. 2. Fig. 2 is an enlarged view of region A1 in Fig. 1.

[0038] 2, when the lower region 23 in the thinned region 20 is viewed along the Z-axis direction, the lower region 23 has a narrow region NR1 that is narrower than the upper region 24. In this embodiment, the length of the narrow region NR1 in the Y-axis direction is shorter than the length e1 of the upper end 24a of the upper region 24 in the Y-axis direction. Here, as shown in FIG. 2, the lower end 23a of the lower region 23 is at the same height as the lower end of the conductive portion 41.

[0039] The narrow region NR1 is at least a part of the lower region 23. In this embodiment, the entire lower region 23 is configured as the narrow region NR1. The narrow region NR1 also includes the narrowest part of the narrow region NR1 (hereinafter also referred to as the "narrowest part"). In the example of FIG. 2, the narrowest part has a length d1 in the Y-axis direction. For example, when the semiconductor device 1 is in the off state, the length d1 is equal to or less than the length necessary to prevent leakage current by a Schottky barrier formed near the boundary between the conductive portion 41 and the lower region 23. The length d1 may be equal to or less than the width of a depletion layer formed in the thinned region 20.

[0040] The upper region 24 is wider than the narrow region NR1 of the lower region 23. That is, the upper region 24 has a longer length in the Y-axis direction than the narrow region NR1 and the narrowest portion of the lower region 23. More specifically, the upper end 24a of the upper region 24 has a length e1 in the Y-axis direction. The length e1 is longer than the length d1 of the narrowest portion in the Y-axis direction. Furthermore, the upper region 24 has a length f1 in the Z-axis direction on the side surface that contacts the conductive portion 32. That is, the length f1 is the distance between the upper end 24a of the upper region 24 and the upper end of the conductive portion 41.

[0041] The conductive portion 41 is embedded in a recess in the narrow region NR1. That is, a recess is formed in the narrow region NR1 with its narrowest portion as the bottom in the Y-axis direction, and the conductive portion 41 is embedded in this recess. In other words, the side surface of the conductive portion 41 on the lower region 23 side (the left side surface in FIG. 2) is in Schottky contact with the narrow region NR1, and the side surface of the conductive portion 41 on the conductive portion 32 side (the right side surface in FIG. 2) is approximately flat from the height of the upper end to the height of the lower end of the conductive portion 41 and is approximately parallel to the Z-axis direction.

[0042] In this embodiment, the narrow region NR1 has a shape in which its width increases upward and downward from the narrowest portion of the narrow region NR1. In other words, the conductive portion 41 in this embodiment has a shape in which its width increases from the upper end to the height of the narrowest portion and decreases from the height of the narrowest portion to the lower end. More specifically, in this embodiment, the thinned region 20 (upper region 24 and lower region 23) has a shape in which its width remains approximately constant from the upper end 24a of the upper region 24 to the lower portion of the upper region 24 over the length f1, narrows from the lower portion of the upper region 24 to the narrowest portion of the lower region 23, and widens from the narrowest portion to the lower end 23a of the lower region 23.

[0043] In this embodiment, the narrowest portion of the narrow region NR1 is located at the center of the narrow region NR1 in the Z-axis direction. In other words, the narrowest portion is located at the height of the center of the conductive portion 41 in the Z-axis direction. In other words, the widest portion of the conductive portion 41 is located at the center of the conductive portion 41 in the Z-axis direction.

[0044] 2, the upper region 24 is illustrated as a region different from the lower region 23, and the boundary between the upper region 24 and the lower region 23 is lower than the position of the upper end of the conductive portion 41. However, this is not limited thereto, and for example, the boundary between the upper region 24 and the lower region 23 may be at the same height as the upper end of the conductive portion 41, or may be higher than the position of the upper end of the conductive portion 41. In reality, the impurity concentration changes continuously along the Z-axis direction, so the boundary between the upper region 24 and the lower region 23 may be unclear. However, no second semiconductor-type semiconductor region, such as a base region, is provided between the upper region 24 and the lower region 23.

[0045] As described above, the semiconductor device 1 according to the first embodiment includes the thinned region 20 of a first conductivity type provided in the semiconductor layer 2 and extending from the drift region 21 toward the source electrode 12, the thinned region 20 including: an upper region 24 including an upper end 24 a of the thinned region 20 and having a higher impurity concentration than the drift region 21; and a lower region 23 sandwiched between the upper region 24 and the drift region 21 and including a narrow region NR1 that is narrower than the upper region 24; the gate electrode 13 provided in the semiconductor layer 2 via the insulating region 51 and aligned with the lower region 23 of the thinned region 20 along the Y-axis direction; the conductive portion 41 facing the gate electrode 13 across the thinned region 20 along the Y-axis direction, electrically connected to the source electrode 12, and making Schottky contact with the lower region 23 of the thinned region 20; and the conductive portion 31 electrically connected to the source electrode 12 and making ohmic contact with the upper region 24 of the thinned region 20.

[0046] According to this embodiment, the upper region 24 is configured to be wider than the narrow region NR1 of the lower region 23, thereby increasing the contact area between the upper region 24 and the conductive portion 31. More specifically, the length e1 in the Y-axis direction at the upper end 24a of the upper region 24 is longer than the length d1 in the Y-axis direction of the narrowest portion of the narrow region NR1, thereby increasing the contact area between the upper end 24a of the upper region 24 and the conductive portion 31. This reduces the contact resistance between the conductive portion 31 and the upper region 24. This reduces the on-resistance of the semiconductor device 1.

[0047] Furthermore, in this embodiment, the conductive portion 32 is in ohmic contact with at least a part of the side surface of the upper region 24. This allows the on-resistance of the semiconductor device 1 to be further reduced.

[0048] In this embodiment, the conductive portion 32, which has a work function lower than that of the conductive portion 41, has a Schottky contact at its bottom end with the drift region 21. This allows the forward voltage of the semiconductor device 1 to be reduced.

[0049] Furthermore, in this embodiment, the conductive portion 31 and the upper region 24 extend in the X-axis direction. This increases the area where the conductive portion 31 and the upper region 24 make ohmic contact, thereby further reducing the on-resistance of the semiconductor device 1. Furthermore, in this embodiment, the conductive portion 31 and the upper region 24 extend to the end, i.e., the terminal end, of the semiconductor layer 2 in the X-axis direction. This further increases the area where the conductive portion 31 and the upper region 24 make ohmic contact, thereby further reducing the on-resistance of the semiconductor device 1.

[0050] Furthermore, in this embodiment, the conductive portion 32 and the drift region 21 extend in the X-axis direction. This increases the area where the conductive portion 32 and the drift region 21 make Schottky contact, thereby further reducing the forward voltage of the semiconductor device 1. Furthermore, in this embodiment, the conductive portion 32 and the drift region 21 extend to the end of the semiconductor layer 2 in the X-axis direction. This further increases the area where the conductive portion 32 and the drift region 21 make Schottky contact, thereby further reducing the forward voltage of the semiconductor device 1.

[0051] <Method of Manufacturing Semiconductor Device 1> Next, an example of a method for manufacturing the semiconductor device 1 according to the embodiment will be described with reference to Figures 3A to 3F. Figures 3A to 3F are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 1 according to the embodiment.

[0052] First, a semiconductor layer shown in FIG. 3A is prepared. Such a semiconductor layer can be obtained, for example, as follows. First, n + A drain region 22 made of a semiconductor substrate having a shaped structure, and an n-type semiconductor layer formed on the drain region 22. -A semiconductor layer is prepared, including a drift region 21 made of an epitaxial layer with a gate electrode 13 and a field plate electrode (FP electrode) 14. A trench is then formed on the upper surface of the drift region 21 by reactive ion etching (RIE) or the like. This trench is a trench for disposing a gate electrode 13 and a field plate electrode (FP electrode) 14 therein. An insulating region 51 is then formed on the inner wall of the trench by thermal oxidation or the like. A conductive material such as polysilicon is then deposited in the trench by chemical vapor deposition (CVD) or the like, and the excess conductive material is etched back to form the FP electrode 14. An insulating material is then deposited so as to bury the FP electrode 14. A conductive material such as polysilicon is then deposited on the insulating material by CVD or the like, and the excess conductive material is etched back to form the gate electrode 13. An n-type impurity is then ion-implanted on the upper surface of the drift region 21 to form an n-type impurity. + A high-concentration region 124, which is a semiconductor region having a shape similar to that of a gate electrode 13, is formed. Then, an insulating material is deposited so as to bury the gate electrode 13 and cover the upper surface of the high-concentration region 124. Then, a through-hole H1 is formed in the insulating material by RIE or the like, thereby forming an insulating region 152. The high-concentration region 124 is exposed at the bottom of the through-hole H1.

[0053] Next, as shown in FIG. 3B , the high-concentration region 124 exposed at the bottom of the through-hole H1 and a portion of the underlying drift region 21 are removed by RIE or the like using the insulating region 152 as a mask. Then, RIE or the like is performed under different etching conditions, such as the type of etching gas and power, to remove the drift region 21 toward the gate electrode 13. This forms a trench H2 whose width is widened in its lower portion. The trench H2 is a trench (contact trench) for disposing the conductive portion 32 and the conductive portion 41 therein. At least a portion of the trench H2 has a shape whose width widens as it extends downward from the upper surface 2b of the semiconductor layer 2. This process forms the thinned region 20. More specifically, a lower region 23 is formed in the drift region 21 between the insulating region 51 and the trench H2, and the high-concentration region 124 is divided to form an upper region 24. Instead of performing RIE under changed conditions, wet etching or the like may be performed to remove the drift region 21 facing the gate electrode 13 along the Y-axis direction, thereby widening the width of the lower portion of the contact trench.

[0054] 3C, a portion of the insulating region 152 is removed by chemical dry etching (CDE), wet etching, or the like. More specifically, the insulating region 152 located above the upper region 24 is removed. The thickness of the insulating region 152 located above the gate electrode 13 is also reduced. The remaining portion of the insulating region 152 corresponds to the insulating region 52.

[0055] Next, as shown in Fig. 3D, the inside of trench H2 is filled with a conductive material of a first metal element by CVD or the like, and a conductive material is also deposited on the upper surface of the semiconductor layer, thereby forming conductive portion 141. Note that, as shown in Fig. 3D, voids V may be formed within conductive portion 141.

[0056] Next, as shown in FIG. 3E, a portion of the conductive portion 141 is removed by RIE or the like. More specifically, of the conductive portion 141, the portion deposited on the insulating region 52, the portion deposited on the upper region 24, the portion sandwiched between the left and right upper regions 24 in the trench H2, and the portion located below these are removed. This forms the trench H3 and the conductive portion 41. The conductive portion 41 is a portion of the conductive portion 141 remaining in the recess in the lower region 23. Note that a portion of the conductive portion 141 may remain at the bottom of the trench H3.

[0057] Next, as shown in FIG. 3F, trench H3 is filled with a conductive material of a second metal element by CVD or the like, and a conductive material is also deposited on the upper surface of the semiconductor layer. This forms conductive portion 31 and conductive portion 32. More specifically, conductive portion 32 is formed to fill trench H3, and conductive portion 31 is formed on upper region 24 and insulating region 52. Then, conductive portion 31 is removed from above insulating region 52 by CDE or the like.

[0058] Thereafter, although not shown, a drain electrode 11 is formed on the lower surface of the semiconductor layer, and a source electrode 12 is formed on the upper surface of the semiconductor layer.

[0059] Through the above steps, the semiconductor device 1 is manufactured.

[0060] According to the manufacturing method of this embodiment, it is possible to reduce the width of the narrow region NR1 and the narrowest portion of the lower region 23 while maintaining the width of the upper region 24. Therefore, it is possible to maintain a high impurity concentration in the portion of the upper region 24 that contacts the conductive portion 31, and to reduce the contact resistance between the conductive portion 31 and the upper region 24.

[0061] Furthermore, according to the manufacturing method of this embodiment, even if voids V are formed in the conductive portion 141, they are removed in the subsequent process, and therefore the semiconductor device 1 can be manufactured stably.

[0062] Furthermore, in the manufacturing method of this embodiment, the conductive portion 32 is made of the same material as the conductive portion 31. This allows the manufacturing process of the semiconductor device 1 to be simplified.

[0063] As shown in FIG. 3F, in the manufacturing method of this embodiment, the portion of the side surface of the conductive portion 32 that contacts the upper region 24 (the portion with length f1 in FIG. 2) is parallel to the Z-axis direction. This is not limited to this, and the portion may be inclined so as to widen upward (toward the source electrode 12). This relaxes the conditions for RIE and the like for forming the trench H2 shown in FIG. 3B, making it easier to form the trench H2. However, since the inclination shortens the length e1 in the Y-axis direction at the upper end 24a of the upper region 24 shown in FIG. 2, the degree of inclination is within a range in which an increase in contact resistance between the upper region 24 and the conductive portion 31 does not become a problem.

[0064] The shapes of the contact trenches in which the conductive portions 32 and 41 are provided are not limited to those described above. Modifications 1 to 3 in which the shapes of the contact trenches are changed will be described below. Each of the modifications described below can also reduce the on-resistance of the semiconductor device, as in the above embodiment.

[0065] (Variation 1) A semiconductor device 1A according to a first modification of the embodiment will be described with reference to Figures 4 and 5. Figure 4 is a cross-sectional view of the semiconductor device 1A according to this modification. Figure 5 is an enlarged view of region A2 in Figure 4. In this modification, the shape of the contact trench in which the conductive portion 32A and the conductive portion 41A are provided is a so-called bottle shape.

[0066] As shown in FIG. 5, the thinned region 20A of this modified example has a lower region 23A and an upper region 24. The lower region 23A has a narrow region NR2 that is narrower than the upper end 24a of the upper region 24. The narrow region NR2 includes a narrowest portion that is the narrowest part of the narrow region NR2. The narrowest portion has a length d2 in the Y-axis direction. In this modified example, the narrowest portion is a region that extends along the Z-axis direction. The conductive portion 41A is embedded in a recess in the narrow region NR2.

[0067] The upper region 24 is wider than the narrow region NR2 of the lower region 23A. More specifically, the upper end 24a of the upper region 24 has a length e2 in the Y-axis direction. The length e2 is longer than the length d2 of the narrowest portion in the Y-axis direction. Furthermore, the upper region 24 has a length f2 in the Z-axis direction on the side surface that contacts the conductive portion 32A. In other words, the length f2 is the distance between the upper end 24a of the upper region 24 and the lower end of the upper region 24.

[0068] In this modified example, the narrow region NR2 of the lower region 23A has a shape in which its width increases upward and downward from the narrowest portion of the narrow region NR2. However, the narrowest portion of this modified example has a predetermined length along the Z-axis direction. In other words, the conductive portion 41A of this modified example has a shape in which its width increases from its upper end to the height of the narrowest portion, then maintains the same width over a predetermined length along the Z-axis direction of the conductive portion 41A, and then narrows toward its lower end. More specifically, the lower region 23A and the upper region 24 of this modified example have a shape in which their widths remain approximately constant over a predetermined length from the upper end 24a of the upper region 24 to the upper portion of the lower region 23A, then narrow from the upper portion of the lower region 23A to the narrowest portion, then maintain the same width over a predetermined length along the Z-axis direction, and then widen toward the lower end 23a of the lower region 23A. 5, the narrow region NR2 of the lower region 23A maintains the same length d2 in the Y-axis direction over at least half the length of the narrow region NR2 in the Z-axis direction. In other words, the conductive portion 41A maintains the same width over at least half the length of the lower region 23A in the Z-axis direction. In the example of FIG. 5, the bottom surface of the conductive portion 32A is approximately flat along the Y-axis direction.

[0069] The lower region 23A and the conductive portions 32A and 41A of this modified example can be manufactured by, for example, changing the RIE conditions for forming the trench H2 from the conditions in the above-described embodiment.

[0070] (Variation 2) Next, a semiconductor device 1B according to a second modification of the embodiment will be described with reference to Fig. 6 and Fig. 7. Fig. 6 is a cross-sectional view of the semiconductor device 1B according to this modification. Fig. 7 is an enlarged view of an area A3 in Fig. 6. In this modification, the shape of the contact trench in which the conductive portion 32B and the conductive portion 41B are provided is a so-called carrot shape.

[0071] As shown in FIG. 7, the thinned region 20B of this modification has a lower region 23B and an upper region 24. The lower region 23B has a narrow region NR3 that is narrower than the upper end 24a of the upper region 24. The narrow region NR3 includes a narrowest portion that is the narrowest part of the narrow region NR3. The narrowest portion has a length d3 in the Y-axis direction. The conductive portion 41B is embedded in the recess of the narrow region NR3.

[0072] The upper region 24 is wider than the narrow region NR3 of the lower region 23B. More specifically, the upper end 24a of the upper region 24 has a length e3 in the Y-axis direction. The length e3 is longer than the length d3 of the narrowest portion in the Y-axis direction. Furthermore, the upper region 24 has a length f3 in the Z-axis direction on the side surface that contacts the conductive portion 32B. In other words, the length f3 is the distance between the upper end 24a of the upper region 24 and the lower end of the upper region 24.

[0073] In this modification, the narrow region NR3 of the lower region 23B has a shape that widens upward and downward from the narrowest portion of the narrow region NR3. In other words, the conductive portion 41B of this modification has a shape that widens from the upper end to the height of the narrowest portion and narrows from the height of the narrowest portion to the lower end. More specifically, the lower region 23B and the upper region 24 of this modification maintain a substantially constant width over a predetermined length from the upper end 24a of the upper region 24 to the upper portion of the lower region 23B, then narrows from the upper portion of the lower region 23B to the narrowest portion, and widens from the narrowest portion to the lower end 23a of the lower region 23B. In the example of FIG. 7, the conductive portion 32B has a substantially flat slope from the height of the narrowest portion to the bottom surface.

[0074] In this modification, the narrowest portion of the lower region 23B is located at the top of the narrow region NR3 in the Z-axis direction. In other words, the narrowest portion is located at a height above the center of the conductive portion 41B in the Z-axis direction. In other words, the widest portion of the conductive portion 41B is located above the center of the conductive portion 41B in the Z-axis direction.

[0075] The lower region 23B and the conductive portions 32B and 41B of this modified example can be manufactured by changing the conditions for forming the trench H2 from those in the embodiment, for example.

[0076] (Variation 3) Next, a semiconductor device 1C according to a third modification of the embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view of the semiconductor device 1C according to this modification, and corresponds to an enlarged view of region A1 in Fig. 1. In this modification, the conductive portion 41 in the embodiment is also provided between the conductive portion 32 and the drift region 21.

[0077] When manufacturing semiconductor device 1C, in the step of removing conductive portion 141 shown in FIG. 3D, which was referred to in the description of the manufacturing method of semiconductor device 1, conductive portion 141 is left inside the recess in lower region 23 and at the bottom of trench H3. Conductive portion 41C in this modification corresponds to the portion of conductive portion 141 that remains in the recess in lower region 23 and at the bottom of trench H3. Conductive portion 32C in this modification is not electrically connected to drift region 21.

[0078] As shown in FIG. 8, the thinned region 20C of this modification has a lower region 23C and an upper region 24. In addition to a portion embedded in the recess of the lower region 23C, the conductive portion 41C has a portion embedded in the bottom of the contact trench (between the conductive portion 32 and the drift region 21). Meanwhile, the lower region 23C of this modification is identical to the lower region 23 of the embodiment except for the position of the lower end 23a. Also, as in the embodiment, the lower region 23C has a narrow region NR4 that is narrower than the upper end 24a of the upper region 24. The narrow region NR4 includes a narrowest portion that is the narrowest of the narrow region NR4. The narrowest portion has a length d4 in the Y-axis direction. The upper end 24a of the upper region 24 has a length e4 in the Y-axis direction. The length f4 is the distance between the upper end 24a of the upper region 24 and the upper end of the conductive portion 41C.

[0079] In the above-described embodiment and modified examples, several shapes of the contact trench, i.e., several shapes of the narrow region in the lower region, have been described. However, the shape of the narrow region is not limited to these. For example, the narrow region may have a shape in which the width increases upward and downward from the narrowest part of the narrow region, and the narrowest part may be located at the bottom of the narrow region in the Z-axis direction. Also, in the above-described embodiment and modified examples, the lower region has one narrow region. However, this is not limited to this, and the lower region may have multiple narrow regions.

[0080] Although the embodiments of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These embodiments and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. [Explanation of symbols]

[0081] 1, 1A, 1B, 1C Semiconductor device 11 Drain electrode 12 Source electrode 13 Gate electrode 14 FP electrode 2. Semiconductor layer 20,20A,20B,20C thinning area 21 Drift Region 22 Drain region 23,23A,23B,23C Lower area 24 Upper area 31 Conductive part 32,32A,32B,32C Conductive part 41,41A,41B,41C Conductive part 51,52 Insulation area NR1,NR2,NR3,NR4 Narrow area

Claims

1. a semiconductor layer having a first major surface and a second major surface; a first electrode provided on the first main surface; a second electrode provided on the second main surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer and electrically connected to the first electrode; a second semiconductor region of the first conductivity type provided in the semiconductor layer and extending from the first semiconductor region toward the second electrode, the second semiconductor region having an upper region that includes an upper end of the second semiconductor region and has a higher impurity concentration than the first semiconductor region, and a lower region that is sandwiched between the upper region and the first semiconductor region and includes a region that is narrower in width than the upper region; a third electrode provided in the semiconductor layer via an insulating region, and aligned with the lower region of the second semiconductor region along a second direction perpendicular to a first direction from the first electrode toward the second electrode; a first conductive portion that faces the third electrode across the second semiconductor region, is electrically connected to the second electrode, and is in Schottky contact with the lower region of the second semiconductor region; a second conductive portion electrically connected to the second electrode and in ohmic contact with the upper region of the second semiconductor region; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the first conductive portion is embedded in a recess in the second semiconductor region.

3. 2. The semiconductor device according to claim 1, wherein said second semiconductor region has a shape whose width increases upward and downward from a narrowest portion of said region.

4. The semiconductor device according to claim 3 , wherein the portion is located at a height equal to a central portion of the first conductive portion in the first direction.

5. The semiconductor device according to claim 3 , wherein the portion has a predetermined length along the first direction.

6. The semiconductor device according to claim 3 , wherein the portion is located at a height above a center of the first conductive part in the first direction.

7. The semiconductor device according to claim 1 , further comprising a third conductive portion that sandwiches the first conductive portion together with the second semiconductor region along the second direction and is electrically connected to the second conductive portion.

8. 8. The semiconductor device according to claim 7, wherein a lower end of the third conductive portion is in Schottky contact with the first semiconductor region, and a Schottky barrier height between the third conductive portion and the first semiconductor region is lower than a Schottky barrier height between the first conductive portion and the lower region.

9. The semiconductor device according to claim 8 , wherein said third conductive portion is made of the same material as said second conductive portion.

10. The semiconductor device according to claim 8 , wherein said third conductive portion and said first semiconductor region extend along a third direction perpendicular to said first direction and said second direction.

11. The semiconductor device according to claim 1 , wherein said second conductive portion and said upper region of said second semiconductor region extend along a third direction perpendicular to said first direction and said second direction.

12. 12. The semiconductor device according to claim 1, wherein the first conductivity type is n-type, and the work function of the second conductive portion is lower than the work function of the first conductive portion.

13. the first conductive portion includes a first metal element, and the first metal element is at least one of Co, Ni, Se, Rh, Pd, Te, Re, Ir, Pt, and Au; 13. The semiconductor device according to claim 12, wherein the second conductive portion includes a second metal element, and the second metal element is at least one of Al, Mg, Ti, Se, V, Cr, Mn, Fe, Cu, Zn, Rb, Sr, Y, Zr, Nb, Mo, Ru, Ag, In, Sn, Sb, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, and Bi.

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