Display device

Abstract

To provide a high-definition display device having a deformed display area and having a high occupancy rate of the display area.SOLUTION: The display device includes a substrate, a gate line drive circuit, a signal line drive circuit, a plurality of gate lines, and a plurality of video signal lines. The substrate has a polygonal shape having n vertices, and includes a display region in which a plurality of pixels are arranged and a frame region surrounding the display region. The gate line drive circuit and the signal line drive circuit are located on the frame region. The plurality of gate lines extend from the gate line drive circuit to the display region. The plurality of video signal lines extend from the signal line drive circuit to the display region and intersect the plurality of gate lines. Each of the plurality of pixels includes a transistor including a first gate electrode, a semiconductor film over the first gate electrode, and a second gate electrode over the semiconductor film. Other features are described in detail in the description.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. For example, one embodiment of the present invention relates to a display device that can be applied to a high-resolution small display device used in VR (virtual reality) goggles and the like. [Background technology]

[0002] With the recent technological advances in liquid crystal display devices and electroluminescent display devices, extremely high-definition display devices have been released onto the market. One application of high-definition display devices is VR goggles worn on the user's head. Unlike display devices with rectangular display areas used in smartphones and television monitors, display devices used in VR goggles often have display areas with a shape close to circular in order to simulate the human field of vision. For example, Patent Documents 1 and 2 disclose display devices with display areas whose outlines are partially curved or octagonal. Display areas that are not rectangular are also called irregular-shaped display areas. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-7220 [Patent Document 2] Patent No. 6639866 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a display device having a novel structure, or to provide a high-definition display device having an irregular-shaped display area and a high occupancy rate of the display area. [Means for solving the problem]

[0005] One embodiment of the present invention is a display device. The display device includes a substrate, a gate line driving circuit, a signal line driving circuit, a plurality of gate lines, and a plurality of video signal lines. The substrate has a polygonal shape with n vertices, a display area in which a plurality of pixels are arranged, and a frame area surrounding the display area. The gate line driving circuit and the signal line driving circuit are located on the frame area. A plurality of gate lines extend from the gate line driving circuit to the display area. A plurality of video signal lines extend from the signal line driving circuit to the display area and intersect with the plurality of gate lines. Each of the plurality of pixels includes a transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film. A portion of the signal line driving circuit is sandwiched between the gate line driving circuit and the display area in the direction in which the plurality of gate lines extend. Each of the plurality of gate lines overlaps with each other, exists in the same layer as the first gate electrode and the second gate electrode, and has a lower gate line and an upper gate line electrically connected to the first gate electrode and the second gate electrode, respectively. A lower-layer gate line and an upper-layer gate line of at least one gate line selected from the plurality of gate lines are electrically connected to each other between the display area and a part of the signal line driving circuit, where n is a natural number of 5 or more.

[0006] One embodiment of the present invention is a display device. The display device includes a substrate, a first gate line driving circuit, a second gate line driving circuit, a signal line driving circuit, a plurality of gate lines, and a plurality of video signal lines. The substrate has a polygonal shape with n vertices, a display area in which a plurality of pixels are arranged, and a frame area surrounding the display area. The first gate line driving circuit and the second gate line driving circuit are located on the frame area, sandwiching the display area. The signal line driving circuit is also located on the frame area. The plurality of gate lines extend from the first gate line driving circuit across the display area to the second gate line driving circuit. The plurality of video signal lines extend from the signal line driving circuit to the display area and intersect with the plurality of gate lines. Each of the plurality of pixels includes a transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film. The first portion of the signal line driving circuit is sandwiched between the first gate line driving circuit and the display area in the direction in which the plurality of gate lines extend. The second portion of the signal line driving circuit is sandwiched between the second gate line driving circuit and the display area in the direction in which the multiple gate lines extend. Each of the multiple gate lines overlaps with the other, exists in the same layer as the first gate electrode and the second gate electrode, and has a lower gate line and an upper gate line electrically connected to the first gate electrode and the second gate electrode, respectively. The lower gate line and the upper gate line of at least one gate line selected from the multiple gate lines are electrically connected to each other between the display area and the first portion and between the display area and the second portion. n is a natural number of 5 or more. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 2] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; [Figure 3] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; [Figure 4] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; [Figure 5]1 is a schematic top view of a portion of a display device according to an embodiment of the present invention; [Figure 6] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; [Figure 7] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; [Figure 8] 1 is a schematic top view of a portion of a display device according to an embodiment of the present invention; [Figure 9] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; [Figure 10] 1 is a schematic top view of a portion of a display device according to an embodiment of the present invention; [Figure 11] 1 is a schematic top view of a portion of a display device according to an embodiment of the present invention; [Figure 12] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; [Figure 13] 1 is a schematic top view of a portion of a display device according to an embodiment of the present invention; [Figure 14] 1 is a schematic end view of a portion of a display device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below.

[0009] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described in the previous drawings may be given the same reference numerals, and duplicated explanations may be omitted. This reference numeral is used to collectively represent multiple identical or similar structures, and when these are individually represented, a hyphen and a natural number are added after the reference numeral.

[0010] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0011] In this specification and claims, the expression "a structure exposed from another structure" means a state in which a part of a structure is not covered by another structure, and includes a state in which the part not covered by another structure is covered by yet another structure. The state expressed by this expression also includes a state in which a structure is not in contact with another structure.

[0012] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from films formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0013] A display device according to one embodiment of the present invention will be described below.

[0014] 1. Overall configuration of the display device FIG. 1 shows a schematic top view of a display device 100 according to one embodiment of the present invention. The display device 100 includes a substrate 102 and a counter substrate (not shown in FIG. 1). The substrate 102 is partitioned into a display area 110 for displaying an image and a frame area surrounding the display area 110. Various conductive films, semiconductor films, and insulating films are patterned and formed using a photolithography process between the substrate 102 and the counter substrate. By appropriately combining these conductive films, semiconductor films, and insulating films, a plurality of pixels (described below), each including a display element, are formed in the display area 110. Additionally, various scanning lines and signal lines (not shown in FIG. 1) are also formed, in addition to a drive circuit for driving the pixels, a plurality of gate lines 124 and a plurality of video signal lines 208 for supplying various signals from each drive circuit to the pixels.

[0015] The drive circuit includes a gate line drive circuit 170 and a signal line drive circuit 200. In the example shown in FIG. 1, two gate line drive circuits 170 are provided on either side of the display area 110, but a single gate line drive circuit 170 may be provided on one side of the display area 110. Meanwhile, the signal line drive circuit 200 includes an analog switch 204 and a drive integrated circuit (hereinafter referred to as a drive IC) 202 connected to the analog switch 204 by a lead wiring 206. The drive IC 202 may be configured by combining various conductive films, semiconductor films, and insulating films formed on the substrate 102, or an integrated circuit formed on a semiconductor substrate may be formed as the drive IC 202 and mounted on the substrate 102. Power and various signals supplied from an external circuit (not shown) are supplied to the gate line drive circuit 170 and the signal line drive circuit 200, and the gate line drive circuit 170 and the signal line drive circuit 200 generate various control signals for controlling pixels based on these signals. Each gate line 124 extends from the gate line drive circuit 170 to the display area 110 and controls each pixel by supplying a control signal to the pixel. Each gate line 124 may be electrically connected to one gate line drive circuit 170, or may be electrically connected to two gate line drive circuits 170 that sandwich the display area 110. A plurality of video signal lines 208 extending from the signal line drive circuit 200 also extend to the display area 110 and intersect with the plurality of gate lines 124. Control signals are supplied from the signal line drive circuit 200 via the video signal lines 208, and thereby video signals and the like required to display an image are supplied to each pixel.

[0016] As can be seen from FIG. 1 , the display area 110 is not rectangular but has an n-polygon with five or more vertices. n is a natural number greater than or equal to four. There is no restriction on the maximum value of n, but the maximum value of n may be selected, for example, from the range of 8 to 12. The shape of the display area 110 does not necessarily have to be a regular n-polygon; the length of at least one side may be different from the length of any of the other sides. By including such an irregularly shaped display area 110 in the display area 110, a display closer to a circle can be achieved, making the display device 100 suitable for use in head-mounted VR goggles and the like. The substrate 102 may be rectangular, or, like the display area 110, may be an m-polygon with five or more vertices. m is a natural number greater than or equal to five, and its maximum value may be selected, for example, from the range of 8 to 12. The vertices of the display area 110 do not necessarily have to be formed by the intersection of two straight lines; they may be rounded. Similarly, the vertices of the substrate 102 may also be chamfered. By making the substrate 102 irregularly shaped, the entire display device 100 can be made smaller, making the display device 100 suitable for use in head-mounted VR goggles and the like. Furthermore, by making the substrate 102 irregularly shaped to fit the display area 110, the area (occupancy rate) that the display area 110 occupies with respect to the entire area of ​​the display device 100 can be increased, making it possible to realize large images while making the VR goggles smaller. As a result, it is possible to provide VR goggles that can reproduce a field of view that is closer to reality.

[0017] Because the display region 110 has an irregular shape, the gate line driving circuit 170 bends along the contour of the display region 110. In the example shown in FIG. 1, each gate line driving circuit 170 is arranged so as to have two bending points. Similarly, the signal line driving circuit 200 is also bent along the contour of the display region 110. In the example shown in FIG. 1, a part of the signal line driving circuit 200, for example, the analog switch 204, is arranged so as to have two bending points. Furthermore, a part of the signal line driving circuit 200 is located between the gate line driving circuit 170 and the display region 110 in the direction in which the gate lines 124 extend. In the example shown in FIG. 1, a part of the signal line driving circuit 200 is located between the display region 110 and one of the gate line driving circuits 170, another part is located between the display region 110 and one of the gate line driving circuits 170, and the remaining part is located in a position not sandwiched between the two gate line driving circuits 170. Each of the above-mentioned configurations will be described in detail below.

[0018] (1) Substrate and opposing substrate Fig. 2 shows a schematic end view taken along the dashed line AA' in Fig. 1. Fig. 2 shows a schematic end view of a gate line driving circuit 170 and one pixel provided in the display area 110, each having a liquid crystal element as a display element. When a liquid crystal element is used as the display element, a backlight (not shown) is provided. As a backlight, a known light source (for example, a cold cathode fluorescent lamp or a light emitting diode) can be used as appropriate, and therefore a description thereof will be omitted.

[0019] The substrate 102 and the counter substrate 104 face each other, provide physical strength to the display device 100, and are configured to transmit visible light emitted from a backlight (not shown). For example, the substrate 102 and the counter substrate 104 may be made of a light-transmitting substrate such as a glass substrate or a quartz substrate. The substrate 102 and the counter substrate 104 may contain a light-transmitting polymer such as polyimide, polyamide, polycarbonate, acrylic resin, or polysiloxane. At least one of the substrate 102 and the counter substrate 104 may be plastic.

[0020] (2) Drive circuit At least a portion of the gate line driver circuit 170 and the signal line driver circuit 200 is formed by appropriately combining various patterned conductive films, semiconductor films, and insulating films provided on the substrate 102. There are no restrictions on the configuration of these driver circuits, and the gate line driver circuit 170 and the signal line driver circuit 200 may be configured using a plurality of transistors, capacitor elements, etc. In the example shown in FIG. 1, two transistors 172 and 174 connected to each other are shown as some of the elements that configure the gate line driver circuit 170.

[0021] Specifically, the transistors 172 and 174 are provided in the frame region 112 directly on the substrate 102 or on an undercoat 106 having any desired configuration. There are no limitations on the configuration of the transistors 172 and 174; any known structure may be used as appropriate. In the example shown in FIG. 2 , the transistors 172 and 174 each include a semiconductor film 176, a first insulating film 178 on the semiconductor film 176, a gate electrode 180 located on the first insulating film 178 and overlapping the semiconductor film 176, a second insulating film 182 and a third insulating film 184 covering the gate electrode 180, and terminals 188 and 190 electrically connected to the semiconductor film 176 through openings in the second insulating film 182 and the third insulating film 184. Wiring 192 is connected to the terminals 188 and 190 to supply signals from an external circuit to the transistors 172 and 174. The first insulating film 178 functions as a gate insulating film for the transistors 172 and 174. Terminal 190 of transistor 172 and terminal 188 of transistor 174 are integrated, thereby electrically connecting transistors 172 and 174. There are no restrictions on the material that makes up semiconductor film 176, and it may be a Group 14 element such as silicon, or it may contain an oxide of a Group 13 element such as gallium or indium. When semiconductor film 176 contains silicon, there are no restrictions on its crystallinity, and semiconductor film 176 may be amorphous or polycrystalline. For example, by forming semiconductor film 176 from polysilicon, a driver circuit capable of high-speed operation can be formed.

[0022] (3) Pixels Each pixel is composed of a display element 150 and a pixel circuit for operating the display element 150 based on control signals supplied from the gate line driving circuit 170 and the signal line driving circuit 200. There are no restrictions on the configuration of the pixel circuit, and it is sufficient to form the pixel circuit by appropriately combining one or more transistors and one or more capacitive elements. There are also no restrictions on the configuration or display mechanism of the display element 150. Therefore, the display element 150 may be a liquid crystal element or an electroluminescent element. The example shown in FIG. 2 shows a driving transistor 122 electrically connected to the display element 150 and a liquid crystal element that functions as the display element 150.

[0023] The driving transistor 122 includes a first gate electrode 124-1a provided on the first insulating film 178, a second insulating film 182 covering the first gate electrode 124-1a, a semiconductor film 126 located on the second insulating film 182 and overlapping with the first gate electrode 124-1a, a third insulating film 184 on the semiconductor film 126, a second gate electrode 124-2a located on the third insulating film 184 and overlapping with the first gate electrode 124-1a and the semiconductor film 126, a fourth insulating film 186 covering the second gate electrode 124-2a, a terminal 128 electrically connected to the semiconductor film 126 via an opening provided in the fourth insulating film 186, a fifth insulating film 132 on the terminal 128 and the fourth insulating film 186, and a terminal 130 electrically connected to the semiconductor film 126 via an opening provided in the fourth insulating film 186 and the fifth insulating film 132. The first gate electrode 124-1a is present in the same layer as the gate electrode 180, and the second gate electrode 124-2a is present in the same layer as the terminals 188 and 190. The first gate electrode 124-1a and the second gate electrode 124-2a form part of the gate line 124. As will be described later, the first gate electrode 124-1a and the second gate electrode 124-2a are electrically connected and have the same potential. The second insulating film 182 and the third insulating film 184 are shared with transistors 172 and 174 of the gate line driving circuit 170, and both function as gate insulating films for the driving transistor 122. The terminal 130 is electrically connected to the display element 150. Therefore, a video signal input to the terminal 128 from the signal line driving circuit 200 via the video signal line 208 is input to the display element 150 via the semiconductor film 126 and the terminal 130 when the driving transistor 122 is on.

[0024] There is no limitation on the material contained in the semiconductor film 126, and examples thereof include group 14 elements such as silicon. In this case, there is no limitation on the crystallinity of the semiconductor film 126, and the semiconductor film 126 may be amorphous or polycrystalline.

[0025] Alternatively, the semiconductor film 126 may include an oxide semiconductor of a Group 13 element such as gallium or indium. The oxide semiconductor may contain multiple different Group 13 elements, such as indium-gallium oxide (IGO). The oxide semiconductor may further include a Group 12 element. A typical oxide semiconductor containing a Group 12 element is indium-gallium-zinc oxide (IGZO). The semiconductor film 126 may also include other elements, such as a Group 14 element such as tin, or a Group 4 element such as titanium or zirconium.

[0026] A planarization film 142 is provided on the pixel circuits including the gate line driving circuit 170 and the driving transistors 122. At this time, a sixth insulating film 134 may be provided under the planarization film 142. By providing the planarization film 142, irregularities caused by the transistors 172, 174, and the driving transistors 122 can be absorbed, and a flat surface can be formed. The display region 110 shown in FIG. 2 has a structure called a color filter on array, in which a color filter 140 is provided between the display element 150 and the substrate 102 (specifically, between the planarization film 142 and the fifth insulating film 132 (or between the planarization film 142 and the sixth insulating film 134)).

[0027] The above-described components forming the drive circuit and pixel circuit can be formed using known materials, and therefore detailed description will be omitted. Briefly, the undercoat 106, first insulating film 178, second insulating film 182, third insulating film 184, fourth insulating film 186, fifth insulating film 132, and sixth insulating film 134 may each be formed of one or more films containing a silicon-containing inorganic compound such as silicon oxide or silicon nitride. The gate electrode 180, terminals 188 and 190, first gate electrode 124-1a, second gate electrode 124-2a, and terminal 128 may be formed of a metal such as titanium, molybdenum, tungsten, or copper, or an alloy containing one or more of these metals. The terminal 130, pixel electrode 152 (described later), and common electrode 158 are formed of a transparent conductive film such as indium tin oxide (ITO). The planarization film 142 may be formed of a polymer such as acrylic resin, epoxy resin, silicone resin, or polyimide resin. The color filter 140 may be made of the above-mentioned polymer and pigment.

[0028] 2, when the display element 150 is a liquid crystal element, it is composed of a pixel electrode 152 electrically connected to the drive transistor 122, a common electrode 158 on the pixel electrode 152, an inter-electrode insulating film 154 located between the pixel electrode 152 and the common electrode 158 and insulating the pixel electrode 152 from the common electrode 158, a first alignment film 160 and a second alignment film 164 on the pixel electrode 152, and a liquid crystal layer 162 between the first alignment film 160 and the second alignment film 164. As an optional configuration, an auxiliary wiring 156 for preventing a voltage drop in the common electrode 158 may be provided below or above the common electrode 158.

[0029] The substrate 102 and the counter substrate 104 are fixed to each other with a sealant 146, and a liquid crystal layer 162 is filled in a space formed by the sealant 146, the substrate 102, and the counter substrate 104. The liquid crystal layer 162 may be provided with spacers 144 to maintain the thickness of the liquid crystal layer 162. The spacers 144 may be formed in a columnar shape as shown in FIG. 2, or, although not shown, spherical spacers may be dispersed in the liquid crystal layer 162. As an optional configuration, an overcoat 108 may be provided in contact with the counter substrate 104. The overcoat 108 may also be formed of one or more films containing a silicon-containing inorganic compound.

[0030] 2 is a so-called IPS (In Plane Switching) type liquid crystal element, but there are no restrictions on the driving format of the display element, and the liquid crystal element may be a TN (Twisted Nematic) type liquid crystal element or a VA (Vertical Alignment) type liquid crystal element. Since the various components forming the liquid crystal element are well-known, a description thereof will be omitted.

[0031] 3, the color filter 140 may be provided in contact with the counter substrate 104, and an overcoat 108 may be formed to cover the color filter 140.

[0032] Alternatively, the display element 150 may be an electroluminescent element. In this case, as shown in FIG. 4 , an insulating partition wall 136 is provided to cover the end of the pixel electrode 152 and an opening provided in the planarization film 142 or the like for connecting the pixel electrode 152 to the terminal 130, and an electroluminescent layer 168 is formed between the pixel electrode 152 and the common electrode 158. The configuration of the electroluminescent layer 168 may be determined arbitrarily, and the electroluminescent layer 168 may be formed by appropriately combining functional layers such as a charge injection layer, a charge transport layer, a charge blocking layer, a light-emitting layer, and an exciton blocking layer. The electroluminescent element may be either a bottom-emission type or a top-emission type. A sealant 146, which also functions as a protective film, is provided between the common electrode 158 and the opposing substrate 104. Examples of the sealant 146 include a layer containing a silicon-containing inorganic compound such as silicon nitride, a layer containing a resin such as an acrylic resin or an epoxy resin, or a laminate thereof.

[0033] 2. Gate line structure FIG. 5 is a schematic top view of a portion of the display device 100. FIG. 5 shows a pair of gate line drive circuits 170 provided in the frame region 112, along with a plurality of pixels 120 electrically connected thereto. The pixels 120 are arranged to form a plurality of rows and columns. The example shown in FIG. 5 employs a power supply method known as a one-sided power supply method, in which each of the plurality of gate lines 124 extends in the row direction from one of the pair of gate line drive circuits 170 and is arranged to cross the display region 110, but is not connected to the other gate line drive circuit. The power supply direction switches for each row. Therefore, when one gate line 124 is connected to one gate line drive circuit 170 and receives a gate signal, which is one of the control signals, from that gate line drive circuit 170, the gate lines 124 adjacent to this gate line 124 in the column direction are both connected to the other gate line drive circuit 170 and receive the gate signal.

[0034] Here, each gate line 124 exists in a different layer and is composed of a lower-layer gate line and an upper-layer gate line located in two layers that overlap each other in the normal direction of the substrate 102. Specifically, as shown in FIG. 6, which includes a schematic end view along dashed lines BB' and CC' in FIG. 5, each gate line 124 is composed of a lower-layer gate line 124-1 and an upper-layer gate line 124-2. The lower-layer gate line 124-1 and the upper-layer gate line 124-2 both cross the display region 110 and are electrically connected to a first gate electrode 124-1a and a second gate electrode 124-2a, respectively. In other words, the first gate electrode 124-1a and the lower-layer gate line 124-1 exist in the same layer, and the first gate electrode 124-1a forms part of the lower-layer gate line 124-1. Similarly, the second gate electrode 124-2a and the upper gate line 124-2 are present in the same layer, and the second gate electrode 124-2a forms a part of the upper gate line 124-2.

[0035] Furthermore, the lower-layer gate line 124-1 and the upper-layer gate line 124-2 are electrically connected to each other in the frame region 112. More specifically, the lower-layer gate line 124-1 and the upper-layer gate line 124-2 are electrically connected to each other in the frame region 112 on the side where the gate line driving circuit 170 to which the gate line 124 is connected is located, and in the frame region 112 on the opposite side of the display region 110 from the gate line driving circuit 170. Therefore, the first gate electrode 124-1a and the second gate electrode 124-2a are electrically connected to each other and have the same potential. The lower-layer gate line 124-1 and the upper-layer gate line 124-2 are electrically connected to each other through openings provided in insulating films (the second insulating film 182 and the third insulating film 184 in the example shown in FIG. 6) formed between them. 6 employs a one-sided power supply system, and therefore, focusing on two gate lines 124 adjacent in the column direction, one of the gate lines 124 receives a gate signal from one of the gate line drive circuits 170, and is electrically connected to a lower-layer gate line 124-1 and an upper-layer gate line 124-2 in the frame regions 112 on both sides of the display region 110. On the other hand, as shown in FIG. 7 including a schematic diagram of the end surface along the dashed lines DD' and EE' in FIG. 5, the other gate line 124 receives a gate signal from the other of the gate line drive circuits 170, and is electrically connected to a lower-layer gate line 124-1 and an upper-layer gate line 124-2 in the frame regions 112 on both sides of the display region 110.

[0036] Furthermore, in the frame region 112, the lower-layer gate line 124-1 does not continue from the display region 110 to the gate-line driving circuit 170, but is divided into two fraction wirings (see the BB' end face in FIG. 6 and the EE' end face in FIG. 7). One fraction wiring (the left lower-layer gate line 124-1 appearing in the BB' end face in FIG. 6) is connected to the gate-line driving circuit 170, and the other fraction wiring (the lower-layer gate line 124-1 appearing in the end-face view in FIG. 6) crosses the display region 110. The two fraction wirings are electrically connected via the upper-layer gate line 124-2. The electrical connection between the two fraction wirings and the upper-layer gate line 124-2 is also made via openings provided in the insulating films formed between them (the second insulating film 182 and the third insulating film 184 in the examples shown in FIGS. 6 and 7).

[0037] In this manner, in the display device 100, the gate line 124 is branched into a lower-layer gate line 124-1 and an upper-layer gate line 124-2 in the frame region 112, and gate signals are supplied using the branched lower-layer gate line 124-1 and upper-layer gate line 124-2. Furthermore, the lower-layer gate line 124-1 and the upper-layer gate line 124-2 are connected at two locations on either side of the display region 110. By adopting this configuration, a large cross-sectional area of ​​the gate line 124 can be secured within the display region 110. This reduces the electrical resistance of the gate line 124, preventing an increase in the time constant. As a result, gate signal delays can be prevented. Furthermore, by dividing the lower-layer gate line 124-1 into two fractional lines, pixel circuits and the gate line driving circuit 170 provided in the display region 110 can be insulated from each other until the upper-layer gate line 124-2 is formed. Therefore, when the display device 100 is charged up during manufacturing, the charge is discharged to the gate line driving circuit 170, and the probability of electrostatic breakdown of the pixel circuit can be significantly reduced.

[0038] The display device 100 may employ a double-sided power supply system instead of the single-sided power supply system. In this case, as shown in FIG. 8, each of the gate lines 124 is connected to a pair of gate line drive circuits 170 arranged on either side of the display area 110, and receives gate signals from the pair of gate line drive circuits 170. In this system, the gate line 124 is also composed of a lower-layer gate line 124-1 and an upper-layer gate line 124-2, which are electrically connected to each other in the frame area 112. More specifically, as shown in FIG. 9, which includes a schematic diagram of an end surface along dashed lines FF' and GG' in FIG. 8, the gate line 124 branches into a lower-layer gate line 124-1 and an upper-layer gate line 124-2 at two locations on either side of the display area 110 in the frame area 112, and both the lower-layer gate line 124-1 and the upper-layer gate line 124-2 cross the display area 110. The lower-layer gate line 124-1 and the upper-layer gate line 124-2 are electrically connected via openings provided in the insulating films (second insulating film 182 and third insulating film 184 in the example shown in FIG. 9) formed between them.

[0039] The lower-layer gate line 124-1 is divided in the frame region 112. That is, it is divided into a first fraction wiring (the lower-layer gate line 124-1 appearing in the end view of both ends in FIG. 9) that crosses the display region 110, a second fraction wiring (the left lower-layer gate line 124-1 appearing in the end view FF' in FIG. 9) that is located between the first fraction wiring and one of the gate-line driving circuits 170 and connected to one of the gate-line driving circuits 170, and a third fraction wiring (the right lower-layer gate line 124-1 appearing in the end view GG' in FIG. 9) that is located between the first fraction wiring and the other gate-line driving circuit 170 and connected to the other gate-line driving circuit 170. The first fraction wiring and the second fraction wiring are electrically connected by the upper-layer gate line 124-2, and similarly, the first fraction wiring and the third fraction wiring are electrically connected by the upper-layer gate line 124-2. The electrical connection between the first fraction wiring and the second fraction wiring, and the electrical connection between the first fraction wiring and the third fraction wiring are also made through openings provided in the insulating films formed between them (in the example shown in Figure 9, the second insulating film 182 and the third insulating film 184).

[0040] 3. Gate wiring connection and its relationship with video signal lines As described above, in the display device 100, the shapes of the substrate 102 and the counter substrate 104 can be set to fit the shape of the display region 110. Therefore, for example, by cutting off the corners of the substrate 102 and the counter substrate 104 on the side where the signal line driving circuit 200 is provided, it is possible to provide not only a display device with a shape closer to a circle but also a display device with a high occupancy rate of the display region 110. However, when such a shape is adopted, it becomes difficult to arrange the gate line driving circuit 170 in a straight line, and the gate line driving circuit 170 is arranged with a partially bent portion, as shown in FIG. 1 . Furthermore, a portion of the signal line driving circuit 200, for example, the analog switch 204, is also arranged with a partially bent portion to fit the shape of the substrate 102 and the display region 110. Therefore, by arranging a portion of the signal line driving circuit 200, for example, the analog switch 204, between the display region 110 and the gate line driving circuit 170 in the direction in which the gate lines 124 extend, the display device 100 can be made smaller.

[0041] 10 , in the frame region 112-1 where a portion of the signal line driving circuit 200 is not present between the display region 110 and the gate line driving circuit 170, the connection portions of the lower-layer gate lines 124-1 and the upper-layer gate lines 124-2, including fractional wiring, can be arbitrarily arranged without considering the arrangement of the video signal lines 208 formed above the gate lines 124. On the other hand, in the frame region 112-2 where a portion of the signal line driving circuit 200 is present between the display region 110 and the gate line driving circuit 170, the lower-layer gate lines 124-1 and the upper-layer gate lines 124-2 are connected in the region where the video signal lines 208 are arranged. For this reason, when the video signal lines 208 are arranged at a small pitch and at a high density, misalignment or the like occurs in the photolithography process for manufacturing the display device 100, the video signal lines 208 may short-circuit or break.

[0042] For this reason, in the frame region 112-1, as shown in the schematic top view of FIG. 11 and the schematic end view along the dashed line HH' (FIG. 12), the lower-layer gate line 124-1 and the upper-layer gate line 124-2 are connected at locations that overlap with the video signal line 208. In other words, the opening 114, in which a plurality of insulating films (e.g., the second insulating film 182 and the third insulating film 184) are provided for the electrical connection between the lower-layer gate line 124-1 and the upper-layer gate line 124-2, is formed so that the entire opening 114 overlaps with one video signal line 208. Alternatively, when the lower-layer gate line 124-1 and the upper-layer gate line 124-2 are in direct contact with each other in this opening 114, the lower-layer gate line 124-1 and the upper-layer gate line 124-2 are electrically connected so that the entire contact surface thereof overlaps with one video signal line 208. Therefore, the opening 114 does not overlap with the region between adjacent video signal lines. By adopting this arrangement, even if the openings 114 are misaligned, the video signal lines 208 that do not overlap the openings 114 are not affected, thereby preventing short circuits between adjacent video signal lines 208. For example, if an opening 114 is formed near a video signal line 208 adjacent to a video signal line 208 that overlaps with the opening 114 due to misalignment or variations in the processed shape, an abnormality may occur in the shape of the resist when the video signal lines 208 are formed. Such an abnormality may make it difficult to achieve the intended patterning, and the adjacent video signal lines 208 may short circuit. Furthermore, if the video signal lines 208 are not formed to cover the entire openings 114, the video signal lines 208 that partially overlap the openings 114 may not be formed with sufficient width, or the openings 114 may cause a break in the video signal lines 208. However, by forming each opening 114 so that its entire length overlaps one video signal line 208, such defects can be prevented even when the video signal lines 208 are arranged at high density.

[0043] In addition, when the pitch of the video signal lines 208 is large and the arrangement density is not high, openings 114 may be formed between adjacent video signal lines 208 to electrically connect the lower-layer gate line 124-1 and the upper-layer gate line 124-2. Specifically, as shown in FIG. 13 and the schematic diagram of the end surface along the dashed line JJ' in FIG. 14, the openings 114 are formed so as to be exposed from the plurality of video signal lines 208. In other words, the lower-layer gate line 124-1 and the upper-layer gate line 124-2 are electrically connected so that the openings 114 or the entire contact surfaces between the lower-layer gate line 124-1 and the upper-layer gate line 124-2 do not overlap with any of the video signal lines 208. By adopting such an arrangement, it is possible to prevent the video signal lines 208 from being disconnected even if the openings 114 are misaligned.

[0044] As described above, in the display device 100 according to one embodiment of the present invention, the gate line driving circuit 170 and the signal line driving circuit 200 can be bent to fit the irregularly shaped display region 110, and a portion of the signal line driving circuit 200 can be disposed between the gate line driving circuit 170 and the display region 110. This allows the substrate 102 and the counter substrate 104 to be miniaturized, thereby providing a display device that is compact and has a high occupancy rate of the display region 110. Furthermore, the gate lines 124 are branched into lower-layer gate lines 124-1 and upper-layer gate lines 124-2 in the frame region 112, and the lower-layer gate lines 124-1 and upper-layer gate lines 124-2 both cross the display region 110 and are electrically connected to each other in the frame region 112 on both sides of the display region. This prevents an increase in the wiring resistance of the gate lines 124, and prevents an increase in the resistance of the gate lines 124 and a resulting increase in the time constant even when the number of pixels 120 in each row is increased. Because of these characteristics, by applying the embodiments of the present invention, it is possible to provide a small display device with a large number of pixels, i.e., high resolution. Furthermore, each of the openings 114 for electrically connecting the lower-layer gate line 124-1 and the upper-layer gate line 124-2 is formed so that it entirely overlaps with one video signal line 208, or so that it is entirely exposed from the adjacent video signal line 208. This reduces the impact on the video signal lines 208 due to misalignment when forming the openings 114, and prevents short circuits and breaks of the video signal lines 208 even when the video signal lines 208 are arranged at high density. It can be said that these characteristics also contribute to higher resolution and improved yield of display devices.

[0045] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0046] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0047] 100: display device, 102: substrate, 104: opposing substrate, 106: undercoat, 108: overcoat, 110: display region, 112: frame region, 112-1: frame region, 112-2: frame region, 114: opening, 120: pixel, 122: driving transistor, 124: gate line, 124-1: lower layer gate line, 124-1a: first gate electrode, 124-2: upper layer gate line, 124-2a: second gate electrode, 126: semiconductor film, 128: terminal, 130: terminal, 132: fifth insulating film, 134: sixth insulating film, 136: partition wall, 140: color filter, 142: planarizing film, 144: spacer, 1 46: sealing material, 150: display element, 152: pixel electrode, 154: inter-electrode insulating film, 156: auxiliary wiring, 158: common electrode, 160: first alignment film, 162: liquid crystal layer, 164: second alignment film, 168: electroluminescent layer, 170: gate line driving circuit, 172: transistor, 174: transistor, 176: semiconductor film, 178: first insulating film, 180: gate electrode, 182: second insulating film, 184: third insulating film, 186: fourth insulating film, 188: terminal, 190: terminal, 192: wiring, 200: signal line driving circuit, 202: driving IC, 204: analog switch, 206: routing wiring, 208: video signal line

Claims

1. a substrate having a display area having a polygonal shape with n vertices and in which a plurality of pixels are arranged, and a frame area surrounding the display area; a gate line driving circuit and a signal line driving circuit on the frame region; a plurality of gate lines extending from the gate line driving circuit to the display area; and a plurality of video signal lines extending from the signal line driving circuit to the display area and intersecting the plurality of gate lines; each of the plurality of pixels includes a transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film; a portion of the signal line driving circuit is sandwiched between the gate line driving circuit and the display area in a direction in which the plurality of gate lines extend; each of the plurality of gate lines overlaps with each other, is present in the same layer as the first gate electrode and the second gate electrode, and includes a lower gate line and an upper gate line electrically connected to the first gate electrode and the second gate electrode, the lower layer gate line and the upper layer gate line of at least one gate line selected from the plurality of gate lines are electrically connected to each other between the display area and the part of the signal line driving circuit, A display device, wherein n is a natural number greater than or equal to 5.

2. The display device according to claim 1 , wherein a contact surface between the lower-layer gate line and the upper-layer gate line overlaps one of the plurality of video signal lines.

3. The display device according to claim 1 , wherein a contact surface between the lower layer gate line and the upper layer gate line is exposed from the plurality of video signal lines.

4. the lower layer gate line of the at least one gate line is divided into two fractional lines between the display area and the part of the signal line driving circuit; 2. The display device according to claim 1, wherein the two fraction wirings are electrically connected to each other via the upper layer gate line between the display region and the part of the signal line driving circuit.

5. The display device according to claim 4 , wherein a contact surface between the fraction wiring and the upper layer gate line overlaps one of the plurality of video signal lines.

6. The display device according to claim 4 , wherein a contact surface between the fraction wiring and the upper layer gate line is exposed from the plurality of video signal lines.

7. 2. The display device according to claim 1, wherein the lower-layer gate line and the upper-layer gate line of the at least one gate line are further electrically connected to each other between the display area and the part of the signal line driving circuit on the frame area opposite the gate line driving circuit.

8. The display device according to claim 1 , wherein the part of the signal line driving circuit includes an analog switch.

9. The display device according to claim 1 , wherein the gate line driving circuit is bent along the contour of the display area.

10. the substrate has a polygonal shape with m vertices, The display device according to claim 1 , wherein m is a natural number of 5 or more.

11. a substrate having a display area having a polygonal shape with n vertices and in which a plurality of pixels are arranged, and a frame area surrounding the display area; a first gate line driving circuit and a second gate line driving circuit positioned on the frame region and sandwiching the display region therebetween; a signal line driving circuit on the frame region; a plurality of gate lines extending from the first gate line drive circuit across the display area to the second gate line drive circuit; and a plurality of video signal lines extending from the signal line driving circuit to the display area and intersecting the plurality of gate lines; each of the plurality of pixels includes a transistor having a first gate electrode, a semiconductor film on the first gate electrode, and a second gate electrode on the semiconductor film; the first portion of the signal line driving circuit is sandwiched between the first gate line driving circuit and the display area in a direction in which the plurality of gate lines extend; the second portion of the signal line driving circuit is sandwiched between the second gate line driving circuit and the display area in a direction in which the plurality of gate lines extend; each of the plurality of gate lines overlaps with each other, is present in the same layer as the first gate electrode and the second gate electrode, and includes a lower gate line and an upper gate line electrically connected to the first gate electrode and the second gate electrode, the lower-layer gate line and the upper-layer gate line of at least one gate line selected from the plurality of gate lines are electrically connected to each other between the display area and the first portion and between the display area and the second portion; A display device, wherein n is a natural number greater than or equal to 5.

12. The display device according to claim 11 , wherein a contact surface between the lower-layer gate line and the upper-layer gate line overlaps one of the plurality of video signal lines.

13. The display device according to claim 11 , wherein a contact surface between the lower-layer gate line and the upper-layer gate line is exposed from the plurality of video signal lines.

14. the lower layer gate line of the at least one gate line is divided into a first fraction wiring that crosses the display area, a second fraction wiring between the first fraction wiring and the first gate line driving circuit, and a third fraction wiring between the first fraction wiring and the second gate line driving circuit; 12. The display device according to claim 11, wherein the second fraction wiring and the third fraction wiring are electrically connected to the first fraction wiring via the upper layer gate line in the display region, the first portion, and the display region, and the second portion, respectively.

15. The display device according to claim 14 , wherein a contact surface between the second fraction wiring and the upper layer gate line overlaps one of the plurality of video signal lines.

16. The display device according to claim 14 , wherein a contact surface between the second fraction wiring and the upper layer gate line is exposed from the plurality of video signal lines.

17. The display device according to claim 14 , wherein a contact surface between the third fraction wiring and the upper layer gate line overlaps one of the plurality of video signal lines.

18. The display device according to claim 14 , wherein a contact surface between the third fraction wiring and the upper layer gate line is exposed from the plurality of video signal lines.

19. The display device of claim 11 , wherein the first portion and the second portion include analog switches.

20. The display device according to claim 11 , wherein the first gate line driving circuit and the second gate line driving circuit are curved along the contour of the display area.

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