Current detection device

Abstract

To provide a highly accurate current detection device even if a shunt resistor is formed by a printing technique when the shunt resistor and a circuit chip are vertically stacked for miniaturization.SOLUTION: A trimming circuit chip having a shunt resistor made of a printed resistor on its rear surface and an amplifier circuit chip are vertically stacked, and an amplifier circuit is formed by the trimming resistor formed in the trimming circuit chip and an amplifier formed in the amplifier circuit chip. A current flowing through the shunt resistor is detected by the amplifier circuit, and the gain of the amplifier circuit can be adjusted by the trimming resistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a current detection device, and more particularly to miniaturization and high accuracy of a current detection device. [Background technology]

[0002] Current detection devices are used to detect motor drive currents, and the higher the current detection accuracy, the more precisely the motor's rotation speed can be controlled. By controlling the motor's rotation speed precisely, the motor itself can be operated without unnecessary movement, leading to energy savings. This is why there is a demand for current detection devices with higher accuracy. In addition, there is a demand for products equipped with motors to be more compact, so there is also a demand for more compact current detection devices. Figure 13 shows the circuit diagram of a conventional current detector. This current detector consists of a shunt resistor Rs and an amplifier circuit AMP. One end of the shunt resistor Rs is connected to GND, and the other end is connected to the load LO. Therefore, when a current Is flows from the load LO to GND, a voltage drop occurs across the shunt resistor Rs, and a potential of Vin is generated at the connection node between the shunt resistor Rs and the load LO. The amplifier circuit AMP has a first input terminal IN1, a second input terminal IN2, and an output terminal OUT. The first input terminal IN1 is connected to the connection node between the shunt resistor Rs and GND, and the second input terminal IN2 is connected to the connection node between the shunt resistor Rs and the load LO. Here, if the gain of the amplifier circuit AMP is set to A, the output voltage Vout generated at the output terminal OUT of the amplifier circuit is A × Vin. This amplifier circuit AMP can be an operational amplifier or an instrumentation amplifier.

[0003] Figure 14 shows a component diagram of the current detection device in Figure 13. This diagram shows a schematic overview of the state in which each component is mounted on a mounting board (not shown). As shown in the figure, the shunt resistor Rs is located on the left and the amplifier circuit AMP is located on the right. The shunt resistor Rs is a chip resistor, and the amplifier circuit AMP is formed on a circuit chip built into the semiconductor device SOP. The circuit topology is the same as the circuit diagram in Figure 13. As described above, in the conventional technology, the shunt resistor Rs and amplifier circuit AMP are located side by side, which causes the problem of a large mounting area.

[0004] The technology disclosed in Patent Document 1 attempts to solve this problem. Figure 15 shows part of the mounting structure described in Patent Document 1. As shown in the figure, Patent Document 1 saves space by forming a shunt resistor 102 on a metal substrate 103 and then vertically stacking an amplifier circuit 101 on top of that. Here, Patent Document 1 is characterized in that the shunt resistor 102 is a printed resistor made by printing carbon paste or silver paste on the metal substrate. The amplifier circuit 101 is mounted so as to be electrically connected to this shunt resistor. Interpreting Patent Document 1, it can be inferred that the current detection device can be miniaturized, as shown in the component diagram in Figure 16. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2007-180267 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 proposes miniaturization by stacking a shunt resistor and an amplifier circuit vertically. The shunt resistor used here is realized as a printed resistor obtained by firing a carbon paste or silver paste. However, because these printed resistors are made by printing a gel paste using a mask and squeegee, there are limitations to the accuracy of the external dimensions and thickness. If the dimensional error in the manufacturing of the shunt resistor is large, the error in the resistance value of the finished shunt resistor will also increase, resulting in a problem of reduced accuracy of the current detection device.

[0007] In view of the above problems, one object of the present invention is to provide a highly accurate current detection device even when a shunt resistor and a circuit chip are stacked vertically for miniaturization, and a resistance value error occurs due to a dimensional error of the shunt resistor. [Means for solving the problem]

[0008] According to one aspect of the present invention, a trimming circuit chip having a shunt resistor formed of a printed resistor attached to its backside and an amplifier circuit chip are stacked vertically, and an amplifier circuit is formed by the trimming resistor formed in the trimming circuit chip and the amplifier formed in the amplifier circuit chip. This amplifier circuit detects the current flowing through the shunt resistor, and the amplifier circuit gain can be adjusted by the trimming resistor. The shunt resistor may be a plated resistor instead of a printed resistor. The amplifier formed on the amplifier circuit chip may be incorporated into the trimming circuit chip to form a single chip. The amplifier circuit may be an instrumentation amplifier and may include an operational amplifier. The amplifier circuit may be for high-side current detection. [Effects of the Invention]

[0009] According to one aspect of the present invention, a trimming circuit for correcting an error in a shunt resistor is provided in a vertically stacked structure, so that a small-sized, highly accurate current detection device can be provided. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a current detection device according to a first embodiment of the present invention. [Figure 2] 1 is a top view of a current detection device according to a first embodiment of the present invention. [Figure 3] 2 is a diagram showing the bottom surface of the inside of the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 4] 1 is a diagram showing a circuit inside a semiconductor device according to a first embodiment of the present invention. [Figure 5] FIG. 5 is a cross-sectional view of a current detection device according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a diagram showing a top view of the inside of a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a cross-sectional view of a current detection device according to a third embodiment of the present invention. [Figure 8] FIG. 10 is a diagram showing a top view of the inside of a semiconductor device according to a third embodiment of the present invention. [Figure 9] FIG. 10 is a circuit diagram of a current detection device according to a fourth embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram of a current detection device according to a fifth embodiment of the present invention. [Figure 11] FIG. 4 is a cross-sectional view showing a modified example of the current detecting device according to the first embodiment of the present invention. [Figure 12] FIG. 10 is a cross-sectional view showing a modified example of the current detecting device according to the second embodiment of the present invention. [Figure 13] FIG. 1 is a circuit diagram of a conventional current detection device. [Figure 14] FIG. 1 is a component diagram of a conventional current detection device. [Figure 15] FIG. 1 is a diagram showing a part of the mounting structure described in Patent Document 1. [Figure 16] FIG. 1 is a diagram of components that can be imagined when the technology of Patent Document 1 is used. DETAILED DESCRIPTION OF THE INVENTION

[0011] First to fifth embodiments of the present invention will be described below with reference to FIGS. 1 to 12. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals. These embodiments have in common the inclusion of a trimming circuit. This trimming circuit trims the feedback resistor of the amplifier circuit and compensates for variations in the resistance value of the shunt resistor.

[0012] (First embodiment) About the structure A current detection device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4. As shown in the cross-sectional view of FIG. 1, an insulating film 2 is formed on the backside of the main surface of a trimming circuit chip 1, and a shunt resistor 3 is further formed on the surface of the insulating film 2 by printing. A plurality of electrode pads 1a are formed on the main surface of the trimming circuit chip 1, some of which are used for electrical connection to the amplifier circuit chip 4 and others for electrical connection to a lead frame 5. The trimming circuit chip 1 also has electrode pads for zapping the trimming resistors (described later), but these are not shown. The amplifier circuit chip 4 is flip-chip bonded to the main surface of the trimming circuit chip 1, and bumps 4b on the electrode pads 4a are bonded to the electrode pads 1a. The electrode pads 1a and the leads 5a are electrically connected by bonding wires 6, and the shunt resistor 3 is electrically connected to the leads 5a of the lead frame 5. The entire lead frame 5, except for its backside, is covered with a mold resin 7. That is, in this embodiment, the shunt resistor 3, the trimming circuit chip 1, and the amplifier circuit chip 4 are vertically stacked.

[0013] FIG. 2 is a top view of the current detection device shown in FIG. 1, shown through the molding resin 7. As shown, several electrode pads 1a on the main surface of the trimming circuit chip 1 are connected to leads 5a of the lead frame 5 by bonding wires 6. FIG. 3 is a bottom view of the current detection device shown in FIGS. 1 and 2, shown through the molding resin 7. As shown, four leads 5a are connected to the shunt resistor 3, and the remaining leads 5a and 5b are connected to lands (not shown) formed on the insulating film 2. In this way, the lead 5a electrically connects to the shunt resistor 3 while supporting the vertical stack structure of the shunt resistor 3, trimming circuit chip 1, and amplifier circuit chip 4. The lead 5b is solely responsible for supporting this vertical stack structure.

[0014] About the circuit Next, the electrical connections between the trimming circuit chip 1, shunt resistor 3, and amplifier circuit chip 4 of this embodiment will be described with reference to the circuit diagram of Fig. 4. In this circuit diagram, the shunt resistor is denoted by the symbol Rs. (Overall composition) One end (low voltage terminal) of shunt resistor Rs is connected to the GND terminal, and the other end (high voltage terminal) is connected to the LO terminal, which is connected to the load. Therefore, when current Is flows from the LO terminal to the GND terminal, a voltage drop occurs across shunt resistor Rs, and a potential of Vin appears at the connection node between shunt resistor Rs and the LO terminal. The amplifier circuit chip 4 includes a first operational amplifier OP1 and a second operational amplifier OP2. The non-inverting input terminal of the first operational amplifier OP1 is connected to the connection node between the shunt resistor Rs and the GND terminal via the IN1 terminal, while the non-inverting input terminal of the second operational amplifier OP2 is connected to the connection node between the shunt resistor Rs and the LO terminal via the IN2 terminal. Therefore, a ground potential (low-voltage terminal voltage) is applied to the non-inverting input terminal of the first operational amplifier OP1, and a Vin (high-voltage terminal voltage) is applied to the non-inverting input terminal of the second operational amplifier OP2. The trimming circuit chip 1 includes a resistor network that provides a reference voltage and a feedback voltage to the first and second operational amplifiers OP1 and OP2. The resistor network is formed by resistors R1A, R2A, R2B, and R1B and a trimming resistor RG.

[0015] The inverting input terminal of the first operational amplifier OP1 is connected to one end of resistor R1A, and the other end of resistor R1A is connected to ground via the REF terminal, which serves as the reference voltage input terminal. Therefore, a reference voltage equivalent to the voltage drop across resistor R1A is applied to the inverting input terminal of the first operational amplifier OP1. Furthermore, a series circuit consisting of resistors R2A and R2B and trimming resistor RG is connected between the inverting input terminal and output terminal of the first operational amplifier OP1. Therefore, voltage feedback is performed from the output terminal of the first operational amplifier OP1 to the inverting input terminal via the output negative feedback circuit composed of resistors R2A and R2B and trimming resistor RG. The inverting input terminal of the second operational amplifier OP2 is connected to the output of the first operational amplifier OP1 via R2B, and is also connected to one end of a trimming resistor RG. The other end of the trimming resistor RG is connected to the connection node between resistors R1A and R2A. Therefore, a reference voltage equivalent to the voltage drop caused by the combined resistance of resistors R1A, R2A, R2B, and trimming resistor RG is applied to the inverting input terminal of the second operational amplifier OP2. In addition, resistor R1B is connected between the inverting input terminal and the output terminal of the second operational amplifier OP2, and negative feedback is established using this resistor R1B as a feedback resistor.

[0016] (Circuit operation) Since the circuit of this embodiment has the above-described configuration, the gain can be changed by adjusting the trimming resistor RG. Although the output appearing at the output terminal OUT varies depending on the resistance value of the shunt resistor Rs, it is possible to set the output to a predetermined level by changing the circuit gain by adjusting the trimming resistor RG. Various trimming methods can be used to adjust the gain. When a current Is flows through the shunt resistor Rs in this embodiment, the voltage Vout output from the output terminal OUT is expressed by equation (1).

[0017]

number

[0018] 《Manufacturing method》 A method for manufacturing the current detection device according to this embodiment will be described. First, a lead frame 5 without a die pad is prepared. The die pad's suspension lead is left as lead 5b, and the other leads are designated as lead 5a. Meanwhile, a trimming circuit chip 1 is prepared. A resistor network consisting of resistors R1A, R2A, R2B, and R1B and a trimming resistor RG is formed on the main surface of the trimming circuit chip 1 by wafer processing. The trimming resistor RG is then configured as a series connection of multiple resistors, with Zener diodes connected in parallel to each resistor. Both ends of each Zener diode are electrically connected to electrode pads (not shown). After wafer processing, an epoxy resin or similar is applied to the back surface of the trimming circuit chip 1 to form an insulating film 2. Then, a resistor pattern and a land pattern are formed on the surface of the insulating film 2 by screen printing with a carbon paste or silver paste, and then heat treatment is performed. After heat treatment, the resistor pattern becomes a shunt resistor Rs, and the land pattern becomes a land. These lands become the junctions with the leads 5b.

[0019] Next, the trimming circuit chip 1 is die-bonded onto the lead frame 5. Die-bonding is performed by applying a conductive adhesive to the inner end surfaces of all of the leads 5a and 5b, and then aligning and joining the shunt resistor Rs and lands of the trimming circuit chip 1. Next, the amplifier circuit chip 4 is mounted on the main surface of the trimming circuit chip 1 by an ultrasonic flip-chip mounter, thereby bonding the bumps 4b and the electrode pads 1a. Next, the trimming circuit chip 1 and the lead frame 5 are connected by bonding wires 6. At this time, a wire bonder is used to set the electrode pad 1a of the trimming circuit chip 1 as the first bonding point, and the space between the inner end and outer end of the lead 5a (connection node) as the second bonding point.

[0020] Next, the tie bars of the lead frame 5 are cut, and the leads are severed so that only lead 5b and lead 5a (GND terminal and REF terminal), which are at ground potential, remain connected to the frame. This forms an assembly in which multiple stacks of trimming circuit chips 1 and amplifier circuit chips are connected to the lead frame. This assembly is then placed on a prober, the GND terminal and REF terminal are grounded, and the voltage of the OUT terminal is monitored while applying predetermined voltages to the LO terminal, VDD terminal, and VSS terminal. The trimming resistor RG is then trimmed so that the voltage of the OUT terminal reaches a predetermined voltage value. This trimming is performed using Zener zapping. Next, the above assembly is set in the mold of a resin molding machine, and resin is injected to perform transfer molding to form molded resin 7. At this time, in order to expose the back surfaces of leads 5a and 5b from molded resin 7, the back surfaces of these leads are butted against the lower mold. Finally, the gates and burrs are removed, and the leads 5a and 5b are cut off to separate the semiconductor devices. Note that since the illustrated example is a leadless package, the leads 5a and 5b can be cut off along the outline of the molding resin 7 using a cutting die.

[0021] As described above, in the first embodiment, a trimming circuit that corrects errors in the shunt resistors is provided in the vertical stack structure, thereby realizing a small, highly accurate current detection device. In particular, after forming the vertical stack structure and completing the circuit, the trimming resistor RG can be adjusted by batch processing while the vertical stack structure is connected to a frame, thereby improving productivity. Note that the trimming resistor RG can also be adjusted after the device is singulated into individual current detection devices.

[0022] (Second embodiment) A current detection device according to a second embodiment of the present invention will be described with reference to FIGS. 5 and 6. FIG. 5 is a cross-sectional view of the current detection device, and FIG. 6 is a top view of the same. The bottom view of the current detection device is similar to FIG. 3. As shown in these figures, the trimming circuit chip 1 and the amplifier circuit chip 4 are electrically connected by bonding wires 6. In the first embodiment, bump connections were used, which limited the combinations of the amplifier circuit chip 4 and the trimming circuit chip 1. In other words, it was necessary to prepare a trimming circuit chip 1 that corresponded to the pad arrangement of the amplifier circuit chip 4. In this embodiment, the amplifier circuit chip 4 and the trimming circuit chip 1 are connected by bonding, which increases the degree of freedom in the pad arrangement of the amplifier circuit chip 4 and the trimming circuit chip 1. In other words, this embodiment has the advantage of increasing the degree of freedom in the combinations of the amplifier circuit chip 4 and the trimming circuit chip 1 compared to the first embodiment. The circuit is the same as that of the first embodiment, and the relationship between the output voltage Vout of the current detection device and the detected current Is follows equation (1). The manufacturing method is also the same as that of the first embodiment, except that flip-chip bonding is replaced by wire bonding.

[0023] (Third embodiment) A current detection device according to a third embodiment of the present invention will be described with reference to Fig. 7 and Fig. 8. Fig. 7 is a cross-sectional view of the current detection device, and Fig. 8 is a top view of the same. The view of the current detection device seen from below is the same as Fig. 3. The feature of this embodiment is that the amplifier circuit chip 4, which was a separate chip in the previous embodiments, is integrated into the trimming circuit chip 1 to form a single chip. By making it a single chip, this embodiment has the advantage of simplifying assembly. The circuit is the same as that of the first embodiment, and the relationship between the output voltage Vout of the current detection device and the detected current Is follows equation (1). The manufacturing method of this embodiment is the same as that of the first embodiment, except that a process for forming an operational amplifier is added to the wafer process for the trimming circuit chip 1, and flip-chip bonding is omitted.

[0024] (Fourth embodiment) A current detection device according to a fourth embodiment of the present invention will be described with reference to FIG. 9. This embodiment differs from the previous embodiments in that the circuit of FIG. 9 is used instead of the circuit of FIG. 4. In this embodiment, the circuit of FIG. 9 is realized in a vertical stacking structure such as that shown in FIG. 1 (described in the first embodiment), FIG. 5 (described in the second embodiment), or FIG. 7 (described in the third embodiment). By using the circuit of FIG. 9 in this embodiment, the common-mode signal rejection ratio is improved compared to the current detection devices used in the previous embodiments, which has the advantage of enabling higher current detection accuracy. The circuit configuration of Figure 9 will be explained. The circuit in Figure 9 has an instrumentation amplifier with two non-inverting amplifiers arranged symmetrically above and below in the front stage and a differential amplifier in the rear stage. One end (low-voltage terminal) of shunt resistor Rs is connected to the GND terminal, and the other end (high-voltage terminal) is connected to the LO terminal, which is connected to the load. Therefore, when current Is flows from the LO terminal to the GND terminal, a voltage drop occurs across shunt resistor Rs, and a potential of Vin is generated at the connection node between shunt resistor Rs and the LO terminal.

[0025] The amplifier circuit chip 4 includes a first operational amplifier OP1, a second operational amplifier OP2, and a third operational amplifier OP3. The non-inverting input terminal of the first operational amplifier OP1 is connected to the connection node between the shunt resistor Rs and the LO terminal via the IN1 terminal, while the non-inverting input terminal of the second operational amplifier OP2 is connected to the connection node between the shunt resistor Rs and the GND terminal via the IN2 terminal. Therefore, Vin is applied to the non-inverting input terminal of the first operational amplifier OP1, and ground potential is applied to the non-inverting input terminal of the second operational amplifier OP2. The trimming circuit chip 1 includes a resistor network that provides a reference voltage and a feedback voltage to the first to third operational amplifiers OP1 to OP3, and the resistor network is formed by resistors R2, R3, R4A, R5A, R4B, and R5B and a trimming resistor RG. The inverting input terminal of the first operational amplifier OP1 is connected to the output terminal of the first operational amplifier OP1 via resistor R2. Meanwhile, the inverting input terminal of the second operational amplifier OP2 is connected to the output terminal of the second operational amplifier OP2 via resistor R3. One end of trimming resistor RG is connected to the inverting input terminal of the first operational amplifier OP1, and the other end is connected to the inverting input terminal of the second operational amplifier OP2. The inverting input terminal of the third operational amplifier OP3 is connected to the output terminal of the first operational amplifier OP1 via resistor R4A. The non-inverting input terminal of the third operational amplifier OP3 is connected to the output terminal of the second operational amplifier OP2 via resistor R4B, and is also connected to the REF terminal via resistor R5B, which is connected to ground. The output terminal of the third operational amplifier OP3 is connected to the inverting input terminal of the third operational amplifier OP3 via resistor R5A, and is also connected to the output terminal OUT of the current detection device. This completes the circuit configuration of this embodiment. In the circuit of FIG. 9, when a current Is flows through the shunt resistor Rs, the voltage Vout output from the output terminal OUT is expressed by the following equation:

[0026]

number

[0027] (Fifth embodiment) Next, a fifth embodiment of the present invention is shown in Fig. 10. This embodiment differs from the previous embodiments in that the circuit of Fig. 10 is used instead of the circuit of Fig. 4 or Fig. 9. In this embodiment, the circuit of Fig. 10 is realized in a vertical stacking structure as in Fig. 1, Fig. 5 or Fig. 7. By using the circuit of Fig. 10, high-side current detection, which was not possible in the previous embodiments, is possible. The circuit configuration of Figure 10 will be described. The circuit of this embodiment also comprises a shunt resistor Rs, an amplifier circuit chip 4, and a trimming circuit chip 1. The shunt resistor Rs is inserted, for example, in the high-side arm of the gate driver, with one end (high-voltage terminal) connected to the SUP terminal connected to the power supply and the other end (low-voltage terminal) connected to the LO terminal connected to the load. Therefore, when a current Is flows from the SUP terminal to the LO terminal, a voltage obtained by subtracting the voltage drop across the shunt resistor Rs from the SUP terminal voltage is generated at the connection node between the shunt resistor Rs and the LO terminal. The amplifier circuit chip 4 includes an operational amplifier OP1, the inverting input terminal of which is connected to the connection node between the shunt resistor Rs and the LO terminal. The trimming circuit chip 1 is composed of a series circuit of a resistor R1, a transistor FET, and a trimming resistor RG, and is placed between the SUP terminal and the GND terminal. The output terminal OUT of the current detection device is connected to the connection node between one main electrode (source) of the transistor FET and the trimming resistor RG. The non-inverting input terminal of the operational amplifier OP1 is connected to the connection node between the shunt resistor Rs and the SUP terminal via a resistor R1, and is also connected to the other main electrode (drain) of the transistor FET. The output terminal of the operational amplifier OP1 is connected to the control electrode (gate) of the transistor FET. This completes the circuit configuration of this embodiment. With this configuration, the voltage between the main electrodes (Vds) of the transistor FET changes based on the difference between the voltage generated across resistor R1 and the voltage generated across shunt resistor Rs, and a voltage that follows this is output to the OUT terminal. In the current detection device of FIG. 10, when a current Is flows through the shunt resistor Rs, the voltage Vout output from the output terminal OUT is expressed by the following equation.

[0028]

number

[0029] Although the embodiments of the present invention have been described above, various modifications are possible without departing from the spirit of the present invention. For example, in the first embodiment, the amplifier circuit chip 4 is disposed on the trimming circuit chip 1 as shown in FIG. 1. Alternatively, the trimming circuit chip 1 may be disposed on the amplifier circuit chip 4 (FIG. 11). In the second embodiment, the amplifier circuit chip 4 is disposed on the trimming circuit chip 1 as shown in FIG. 5, but the trimming circuit chip 1 may be disposed on the amplifier circuit chip 4 (FIG. 12). In the above embodiment, the shunt resistor is a printed resistor, but it may be a plated resistor instead. In the above embodiment, an insulating film is formed on the back surface of the trimming circuit chip, but a ceramic substrate may be bonded instead of the insulating film. However, if a material with high insulation properties from the outside, such as an SOI wafer, is used, forming an insulating film or bonding a ceramic substrate is not necessary. In the above embodiment, Zener zapping is used to adjust the trimming resistor, but other adjustment methods such as laser trimming, digital trimming, or electronic trimmer can also be used. Furthermore, in the above embodiment, a leadless package has been described as an example, but the present invention is not limited to this, and may be a package in which both the front and back surfaces of the outer lead ends are exposed to the outside, such as an inline type lead or a gull-wing type lead. In the above embodiment, a lead frame is used as a fan-out member to ensure sufficient distance between the external terminals of the current detection device and improve mounting reliability. However, other fan-out members can also be used. For example, when using an interposer or chip carrier made of an organic substrate, a metal pattern may be used instead of leads. In this case, the metal pattern on the back surface of the fan-out member that connects to the shunt resistor and the metal pattern on the front surface of the fan-out member that connects to the trimming circuit chip via bonding wires may be connected by via holes that penetrate the inside of the fan-out member. The external connection terminals may be peripheral electrodes obtained by dividing through holes, or lands, bumps, pins, etc. formed on the back surface of the fan-out member. However, using a lead frame as the fan-out member provides better flatness and productivity. [Explanation of symbols]

[0030] 1 trimming circuit chip 1a, 4a Electrode pads 2. Insulating film 3,102,Rs shunt resistor 4 Amplification circuit chip 5 Lead Frame 5a,5b lead 6 Bonding Wire 7 Molding resin 101 Amplifier circuit 103 Metal Substrate GND Ground terminal IN1, IN2 input terminals LO load connection terminal OP1~OP3 operational amplifiers R1~R5B Resistors RG trimming resistor FET transistor

Claims

1. a trimming circuit chip having a plurality of electrodes formed on a main surface, a resistor network electrically connected to the plurality of electrodes, and a shunt resistor made of a printed resistor attached to a back surface of the main surface; an amplifier circuit chip having at least one amplifier formed thereon and mounted on the main surface of the trimming circuit chip; a lead frame having a plurality of leads, inner end surfaces of the leads abutting against the back surface of the trimming circuit chip, at least two of the leads being connected to the shunt resistor, and supporting the trimming circuit chip; a resin that covers the trimming circuit chip, the shunt resistor, and the amplifier circuit chip so as to expose a portion of the lead of the lead frame, a part of the plurality of electrodes of the trimming circuit chip is electrically connected to the amplifier circuit chip, and another part of the electrodes is electrically connected to the leads of the lead frame; an amplifier circuit is formed by the resistor network formed on the trimming circuit chip and the amplifier of the amplifier circuit chip; The current detection device is characterized in that a part of the resistor network includes a trimming resistor, and the gain of the amplifier circuit is adjustable by the trimming resistor.

2. 2. The current detection device according to claim 1, wherein the shunt resistor is a plated resistor instead of the printed resistor.

3. The amplifier circuit includes a first operational amplifier that outputs a difference between a low-voltage terminal voltage of the shunt resistor and a reference voltage; a second operational amplifier that outputs a difference between a high-voltage terminal voltage of the shunt resistor and an output of the first operational amplifier, 2. The current detection device according to claim 1, wherein the first operational amplifier has an output negative feedback circuit formed of a part of the resistor network, and the output negative feedback circuit is provided with the trimming resistor.

4. The amplifier circuit is an instrumentation amplifier in which two non-inverting amplifiers arranged vertically symmetrically in a front stage and a differential amplifier arranged in a rear stage for outputting a difference between the outputs of the two non-inverting amplifiers, a non-inverting input terminal of one of the two non-inverting amplifiers is connected to the high-voltage terminal of the shunt resistor, and a non-inverting input terminal of the other non-inverting amplifier is connected to the low-voltage terminal of the shunt resistor; 2. The current detection device according to claim 1, wherein one end of the trimming resistor is connected to the inverting input terminal of the one non-inverting amplifier, and the other end is connected to the inverting input terminal of the other non-inverting amplifier.

5. The amplifier circuit includes an operational amplifier that outputs a difference between a low-voltage side terminal voltage and a high-voltage side terminal voltage of the shunt resistor; a transistor having one main electrode connected to a power supply, the other main electrode connected to a ground potential via the trimming resistor, and a control electrode connected to an output terminal of the operational amplifier, the voltage between the main electrodes of which changes in response to the output; 2. The current detection device according to claim 1, wherein a connection node between the other main electrode of the transistor and the trimming resistor is connected to an output terminal of the amplifier circuit.

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