Wiring substrate, semiconductor module, aggregate substrate, and method for manufacturing aggregate substrate

Abstract

To provide a technique capable of manufacturing a semiconductor module excellent in heat dissipation.SOLUTION: In a wiring board in which a conductor layer and an insulating resin layer are formed on both surfaces of a core insulating layer, the core insulating layer includes, in a peripheral region thereof, a region having a thickness smaller than that of the other region, and a heat-conductive material is disposed above the region of the core insulating layer having a small thickness.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board, a semiconductor module, an aggregate substrate, and a method for manufacturing the aggregate substrate. [Background technology]

[0002] Semiconductor integrated circuits are prone to malfunction when exposed to high temperatures. Therefore, in order to cool a semiconductor chip containing a semiconductor integrated circuit, for example, a heat sink may be placed in contact with the top surface of the semiconductor chip mounted on a wiring substrate. With this cooling method, heat generated in the semiconductor chip is transferred from the semiconductor chip to the heat sink, and then dissipated from the heat sink into the atmosphere.

[0003] Furthermore, Patent Document 1 discloses a multilayer wiring board and a semiconductor device as follows, which aims to provide a highly reliable multilayer wiring board and semiconductor device that can improve heat dissipation from semiconductor elements and can accommodate semiconductor elements that generate a large amount of heat. "In a multilayer wiring board formed by laminating wiring layers 26 on a core substrate 12 made of metal, thermal vias 16 are provided in the inner layer of the area where a heat sink 40 is bonded and attached to the outer surface of the board, connecting in a columnar manner from the core substrate 12 and thermally connecting the heat sink 40 and the core substrate 12. In addition, thermal vias 18 are provided to thermally connect the core substrate 12 and the semiconductor element."

[0004] Furthermore, there is also another cooling method in which the wiring board on which the semiconductor chip is mounted is immersed in an insulating liquid. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-101243 Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductor integrated circuits become faster, their power consumption increases. As a result, semiconductor chips that include semiconductor integrated circuits generate a great deal of heat. Therefore, it is becoming difficult to achieve sufficient cooling using the cooling method disclosed in Patent Document 1. Furthermore, the cooling method of immersing the wiring board in an insulating liquid requires that the entire wiring board on which the semiconductor chip is mounted be sealed to prevent the liquid from leaking out, which results in the problem of the device configuration being large.

[0007] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a wiring board that has a compact device configuration and excellent heat dissipation properties. [Means for solving the problem]

[0008] To solve the above problems, one representative wiring board of the present invention has a core insulating layer on both sides of which a conductor layer and an insulating resin layer are formed, and the core insulating layer of the wiring board has a peripheral region that is thinner than other regions, and a heat transfer material is disposed above the thinner region of the core insulating layer.

[0009] A typical semiconductor module of the present invention includes a semiconductor element mounted on the wiring board via connection terminals, and a heat sink joined to an end face of the wiring board.

[0010] Furthermore, one representative method for manufacturing a wiring board assembly of the present invention includes a first step of forming recesses in a region that will become the peripheral region of the wiring board on a core insulating layer base material using a router or laser processing, a second step of injecting adhesive into the protrusions, and a third step of placing a molded heat transfer material in the recesses into which the adhesive has been injected and pushing the heat transfer material into the recesses from above, so that the height of the core insulating base material other than the recesses is approximately the same as the height of the molded heat transfer material. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a wiring board that has a compact device configuration and excellent heat dissipation properties. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments of the invention. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a cross-sectional view schematically illustrating a wiring board according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a top view schematically showing a core insulating layer in the wiring board shown in FIG. [Figure 3] FIG. 3 is a top view schematically showing the heat transfer material in the wiring board shown in FIG. [Figure 4] 4A to 4C are cross-sectional views schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 5] 5A to 5C are cross-sectional views schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 6] 6A to 6C are cross-sectional views and a top view schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 7] 7A to 7C are cross-sectional views schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 8] 8A to 8C are cross-sectional views and a top view schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 9] 9A to 9C are cross-sectional views schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 10] 10A to 10C are cross-sectional views schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 11] 11A to 11C are cross-sectional views schematically showing a manufacturing process for the wiring board shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view illustrating an example of the semiconductor package according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view illustrating an example of the semiconductor module according to the first embodiment. [Figure 14]FIG. 14 is a cross-sectional view schematically showing a semiconductor module according to a comparative example. [Figure 15] FIG. 15 is a heat dissipation equivalent circuit diagram of a semiconductor module according to a comparative example. [Figure 16] FIG. 16 is a heat dissipation equivalent circuit diagram of the semiconductor module of the first embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing an example of a semiconductor module according to the second embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing an example of a semiconductor module according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below are examples that embody the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not limited to the materials, shapes, structures, arrangements, etc. of the components described below.

[0014] In the drawings referred to in the following description, components having the same or similar functions are denoted by the same reference numerals. It should be noted that the drawings are schematic, and the relationship between the dimension in the thickness direction and the dimension in the direction perpendicular to the thickness direction, i.e., the in-plane direction, and the relationship between the dimensions of multiple layers in the thickness direction may differ from the actual dimensions. Therefore, specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationship between two or more components may differ between multiple drawings.

[0015] In this disclosure, the terms "top surface" and "bottom surface" refer to the two main surfaces of a plate-like member or a layer contained therein, i.e., the surface that is approximately perpendicular to the thickness direction and has the largest area, and the back surface thereof, respectively, the surface shown at the top and the surface shown at the bottom in the drawings. Furthermore, the term "end surface" refers to the surface of a plate-like member or a layer contained therein that is located on the periphery when viewed from a direction approximately parallel to the thickness direction. Furthermore, the term "side surface" refers to a surface that is approximately perpendicular to or inclined with respect to the top or bottom surface.

[0016] In addition, in the present disclosure, the "peripheral region" refers to a region other than the center of a plate-like member, but the peripheral region does not necessarily have to be a region that includes the end face.

[0017] Furthermore, in this disclosure, the expression "AA on BB" is used regardless of the direction of gravity. The state specified by the expression "AA on BB" includes a state in which AA is in contact with BB. The expression "AA on BB" does not exclude the presence of one or more other components between AA and BB.

[0018] [First embodiment] <Wiring board> First, the wiring board of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view that schematically shows a wiring board according to one embodiment of the present invention. Note that the z-axis direction in Fig. 1 is the thickness direction of the wiring board 10. Fig. 1 depicts a portion of the wiring board 10 near one end face thereof.

[0019] 1 is a multilayer wiring board. Here, as an example, it is assumed that wiring board 10 has a substantially square shape when viewed from above along the z-axis.

[0020] The wiring board 10 includes a core insulating layer 101, a conductor layer 102, a hole filling resin 103 provided in the through hole of the core insulating layer 101, an insulating layer 104, a conductor layer 105A, a conductor layer 105B, a heat transfer material 106, an adhesive layer 200, an insulating layer 107, and a joining conductor 108.

[0021] The core insulating layer 101 is an organic insulating layer. For example, the core insulating layer 101 is a composite material containing glass fiber and a cured resin. The core insulating layer 101 has a plurality of through holes extending in the thickness direction thereof.

[0022] The conductor layer 102 is a layer made of a metal material. The conductor layer 102 may have a single-layer structure or a multi-layer structure. Here, the conductor layer 102 constitutes a through electrode that covers the side wall of a through hole provided in the core insulating layer 101. The conductor layer 102 may fill the through hole provided in the core insulating layer 101.

[0023] The filling resin 103 is an insulator made of a cured resin. The filling resin 103 fills the through holes of the core insulating layer 101 whose side walls are covered with the conductor layer 102. When the conductor layer 102 fills the through holes provided in the core insulating layer 101, the filling resin 103 can be omitted.

[0024] The insulating layer 104 is an organic insulating layer. The insulating layer 104 is made of, for example, a cured resin. Each insulating layer 104 may have a single-layer structure or a multi-layer structure. Each insulating layer 104 has a plurality of through holes extending in its thickness direction. In FIG. 1, two insulating layers 104 are stacked on the upper and lower main surfaces of the core insulating layer 101. The number of insulating layers 104 provided on each main surface of the core insulating layer 101 may be one, or may be three or more. Furthermore, as long as one or more insulating layers 104 are provided on one main surface, it is not necessary that an insulating layer 104 is provided on the other main surface.

[0025] Each of the conductor layers 105A and 105B is a wiring layer including a main conductor layer. Here, the "main conductor layer" is the thickest conductive layer included in the wiring layer. The main conductor layer is made of a metal material such as copper. As described below, each of the conductor layers 105A and 105B may further include one or more other layers, such as an adhesion layer and a seed layer.

[0026] Each of the conductor layers 105A is provided between the core insulating layer 101 and the insulating layer 104. Each of the conductor layers 105A is a conductor pattern including a pad portion and a wiring portion. The pad portions include those arranged at the positions of the through holes provided in the core insulating layer 101 and those arranged at positions away from the through holes provided in the core insulating layer 101. The wiring portion connects the former pad portion to the latter pad portion.

[0027] The conductor layer 105B includes one provided between two stacked insulating layers 104. Each of these conductor layers 105B includes a pad portion, a wiring portion, and a via portion. In each of these conductor layers 105B, the pad portions include one located at the position of a through hole provided in the insulating layer 104 interposed between the conductor layer 105B and the core insulating layer 101, and one located at a position away from the through hole. The wiring portion connects the former pad portion to the latter pad portion. The via portion fills the through hole provided in the insulating layer 104 interposed between the above conductor layer 105B and the core insulating layer 101, and electrically connects the former pad portion to the pad portion included in the conductor layer 105A.

[0028] The conductor layers 105B further include one provided between the insulating layer 104 and the insulating layer 107. Each of these conductor layers 105B includes a pad portion and a via portion. In each of these conductor layers 105B, the pad portion is located at the position of a through hole provided in the insulating layer 104 that is in contact with the insulating layer 107. The via portion fills the through hole provided in the insulating layer 104 that is in contact with the insulating layer 107, and electrically connects the pad portion included in this conductor layer 105B to the pad portion included in the conductor layer 105B that is provided between the two stacked insulating layers 107. In addition to the pad portion and via portion described above, this conductor layer 105B may further include a pad portion located away from the through hole provided in the insulating layer 104 that is in contact with the insulating layer 107, and a wiring portion that connects the former pad portion to the latter pad portion.

[0029] <Core insulation layer> Next, the shape of the core insulating layer 101 when viewed from above the z-axis will be described with reference to Figure 2. Figures 2(a) and (b) are top views that schematically show the core insulating layer in the wiring board shown in Figure 1. In Figures 2(a) and (b), the conductor layer 105A is not shown, and the core insulating layer 101 has a first region 201 and a second region 202. The second region 202 is a region provided in the peripheral region of the core insulating layer 101, and is thinner than the first region 201. 2(a), the first region 201 is surrounded by the second region 202, but the second region does not necessarily have to surround the first region 201. As shown in FIG. 2(b), the second region 202 may be disposed only in a portion of the periphery of the first region 201. The position at which the second region 202 is disposed can be selected from an appropriate region surrounding the first region 201 depending on the relationship with the arrangement of the heat sink, which will be described later, and the like.

[0030] When viewed in the thickness direction, the first region 201 is thicker than the second region 202. The thickness of the first region is approximately 800 μm to 2000 μm, while the thickness of the second region 202 is preferably 50 μm to 200 μm. If it is 50 μm or less, the strength for holding the heat transfer material 106 is insufficient, and if it is 200 μm or more, the heat dissipation effect decreases.

[0031] <Heat transfer materials> Next, the shape of the heat transfer material when viewed from above the z-axis will be described with reference to Fig. 3. Figs. 3(a) and 3(b) are top views schematically showing the core insulating layer in the wiring board shown in Fig. 1. As described above, the heat transfer material 106 is formed in the second region 202 of the core insulating layer 101. As shown in FIG. 3(a), when the second region 202 of the core insulating layer 101 has a rectangular shape as shown in FIG. 2(a), the heat transfer material 106 is desirably rectangular and has an opening 203 and is frame-shaped when viewed in the thickness direction. The thickness of the heat transfer material 106 is smaller than the difference in thickness between the first region 201 and the second region 202. The thickness of the heat transfer material 106 is preferably in the range of 600 to 2000 μm, and more preferably in the range of 700 to 1900 μm. From the viewpoint of heat dissipation effect, it is preferable that the area of ​​the heat conductive material 106 is large. However, when the second region 202 of the core insulating layer 101 is disposed only in a part of the periphery of the first region 201 as shown in Fig. 2(b), the heat conductive material 106 will also be disposed in accordance with the second region 202 as shown in Fig. 3(b). The thickness of the heat conductive material 106 is as described above.

[0032] Next, the heat transfer material will be described again with reference to FIG. 1. The heat transfer material 106 is bonded to the core insulating layer 101 via an adhesive layer 200. In FIG. 1, the adhesive layer 200 is not disposed on the upper surface of the heat transfer material 106, and the heat transfer material 106 is not exposed at the edge surface of the wiring board 10. However, the adhesive layer 200 may or may not be formed on the upper surface of the heat transfer material 106. Furthermore, the heat transfer material 106 may or may not be exposed at the edge surface of the wiring board 10.

[0033] The top surface of the heat transfer material 106 may be lower than the top surface of the core insulating layer 101, may be the same height as the top surface of the core insulating layer 101, or may be higher than the top surface of the core insulating layer 101. When the top surface of the heat transfer material 106 is higher than the top surface of the core insulating layer 101, the difference in height is preferably smaller than the thickness of the organic insulating layer covering the heat transfer material 106, in this case the insulating layer 104 in contact with the core insulating layer 101, and the heat transfer material 106 is completely covered by the insulating layer 104 in contact with the core insulating layer 101. If the height of the top surface of the heat transfer material 106 is excessively high, there is a risk of poor filling when the insulating layer 104 is formed.

[0034] The heat transfer material 106 is made of a material having a higher thermal conductivity than the organic insulating layers that sandwich it, here, the core insulating layer 101 and the insulating layer 104 .

[0035] The thermal conductivity of the heat transfer material 106 is preferably in the range of 100 to 400 W / m·K. The materials constituting the core insulating layer 101 and the insulating layers 104 and 107 have a thermal conductivity in the range of, for example, 0.58 to 0.65 W / m·K. On the other hand, the thermal conductivity of copper is approximately 400 W / m·K, and the thermal conductivity of pure aluminum and aluminum alloys is approximately 200 W / m·K for pure aluminum and approximately 100 W / m·K for 5000 series aluminum alloys.

[0036] Next, the adhesive layer, insulating layer, and bonding conductor will be described with reference to FIG. <Adhesive layer> The adhesive layer 200 is made of insulating resin. The insulating resin is, for example, a cured product of thermosetting resin. The adhesive layer 200 may also contain organic filler or inorganic filler.

[0037] <Insulating layer> The insulating layer 107 is an organic insulating layer. The insulating layer 107 is made of, for example, solder resist. Each of the insulating layers 107 shown in FIG. 1 covers the uppermost insulating layer 104 and the uppermost conductor layer 105B. Each of the insulating layers 107 has a through-hole at the position of the pad portion of the conductor layer 105B that it covers.

[0038] <Conductor for joining> The bonding conductors 108 cover the pad portions of the conductor layer 105B covered by the insulating layer 107 at the positions of the through holes formed in the insulating layer 107. Each of the bonding conductors 108 includes a portion located within the through hole formed in the insulating layer 107 and a portion protruding from the insulating layer 107. The bonding conductors 108 are, for example, solder bumps. The arrangement pitch of the bonding conductors 108 on the lower surface of the wiring board 10 is larger than the arrangement pitch of the bonding conductors 108 on the upper surface of the wiring board 10.

[0039] <Method of manufacturing wiring board and assembly board> Next, a method for manufacturing a wiring board and an aggregate board in which a plurality of wiring boards are arranged will be described with reference to FIGS. The above-described wiring board 10 and an assembly board in which a plurality of such boards are arranged can be manufactured, for example, by the following method.

[0040] Figures 4, 5, 6(a), 7, 8(a), and 9 are cross-sectional views schematically showing the manufacturing of the wiring substrate shown in Figure 1. Figure 6(b) is a top view of the structure shown in Figure 6(a). Figure 8(b) is a top view of the structure shown in Figure 8(a).

[0041] First, the processing of the core insulating layer 101 will be described with reference to Figures 4 and 5. As shown in Figure 4(a), a composite material including the core insulating layer 101 and conductor layers 105A1 provided on both sides thereof is prepared, and through holes TH1 are formed in this composite material to electrically connect the front and back surfaces of the composite material. Here, as will be described later, an aggregate substrate is first manufactured, and this aggregate substrate is then singulated into multiple wiring substrates 10. Therefore, the dimensions of the composite material prepared here are larger than the dimensions of the assembly formed by arranging multiple wiring substrates 10. The conductor layers 105A1 are, for example, copper foil attached to the core insulating layer 101. The through holes TH1 are formed, for example, using a drill.

[0042] Next, as shown in FIG. 4(b), a conductor layer 105A2 is formed on the sidewall of the through hole TH1 and the surface of the conductor layer 105A1. Here, the conductor layer 105A2 is formed so as not to completely fill the through hole TH1. The conductor layer 105A2 may be formed so as to completely fill the through hole TH1. Note that the portion of the conductor layer 105A2 that covers the sidewall of the through hole TH1 is the conductor layer 102 described above.

[0043] The conductor layer 105A2 is, for example, a laminate of a seed layer and a plating layer provided thereon.

[0044] The seed layer can be formed by, for example, electroless plating. When the seed layer is formed by electroless plating, the material can be, for example, a metal material such as Cu, Pd, Al, Sn, Ni, or Cr.

[0045] The plating layer can be formed, for example, by electroplating using the seed layer as a power supply layer. Materials for the plating layer include, for example, metal materials such as Cu, Cu alloys, Ag, Ag alloys, Sn, Pd, Au, Ni, Cr, Pt, Fe, and combinations of two or more of these.

[0046] Next, as shown in Fig. 4(c), the through hole TH1 is filled with a hole filling resin 103. For example, the through hole TH1 is filled with resin, the resin is cured, and then any unnecessary resin spilling out of the through hole TH1 is removed by buffing or the like. Note that if the through hole TH1 is completely filled with the conductor layer 105A2 as described in Fig. 4(b), the step of Fig. 4(c) is omitted.

[0047] Next, as shown in FIG. 4(d), conductor layers 105A3 are formed on both sides of the composite material obtained as described above. The conductor layer 105A3 is, for example, a laminate of a seed layer and a plating layer provided thereon. The seed layer and plating layer of the conductor layer 105A3 can be formed using, for example, the methods and materials described above for the seed layer and plating layer of the conductor layer 105A2.

[0048] The seed layer of the conductor layer 105A3 can also be formed by sputtering. When forming the seed layer by sputtering, the material can be, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu3N4, a Cu alloy, or a combination of two or more of these.

[0049] 4(b), the step of Fig. 4(d) may be omitted. Also, if it is not necessary to cover the filling resin 103 with a conductor layer, the step of Fig. 4(d) may be omitted.

[0050] Next, a resist resin is applied to both sides of the composite material obtained as described above, or a dry film resist is laminated thereon, and then these resist layers are subjected to pattern exposure and development in sequence to obtain a resist pattern 121 shown in FIG.

[0051] Next, etching is performed using the resist pattern 121 as an etching mask to remove, as shown in Fig. 4(f), portions of the conductor layers 105A1, 105A2, and 105A3 that correspond to the openings in the resist pattern 121. In this way, portions of the laminate consisting of the conductor layers 105A1, 105A2, and 105A3 that are located on the main surface of the core insulating layer 101 are obtained as the above-mentioned conductor layer 105A.

[0052] Next, as shown in FIG. 4(g), the resist pattern 121 is removed from the conductor layer 105A.

[0053] Next, as shown in FIG. 5(h), a first region 201 and a second region 202 are formed in the core insulating layer 101. The second region 202 may be formed so as to surround the first region 201 of the wiring substrate 10, or may be formed only in a portion of the periphery of the first region. The second region 202 is formed using, for example, a router. Laser processing can also be used.

[0054] Next, the first region 201 and the second region 202 in the case of an aggregate substrate in which a plurality of wiring substrates are arranged will be described with reference to Fig. 6. The cross section shown in Fig. 6(a) is a cross section taken along line XX of the structure shown in Fig. 6(b), which is a top view of aggregate substrate 10C. As shown in Fig. 6(a), second region 202 can also be formed together with the second region of an adjacent wiring substrate in aggregate substrate 10C. In FIG. 6(b), the conductor layer 105A is omitted. In FIG. 6(b), the first region 201 is a rectangle with four right-angled corners, but the shape of the first region 201 is not particularly limited and can be any shape. As shown in FIG. 6(b), for example, the second region 202 is preferably provided in a substantially lattice shape corresponding to the dicing lines. In FIG. 6, as described above, the wiring substrate 10 has a square shape when viewed in its thickness direction, and the second region 202 is provided in a substantially square lattice shape as shown in FIG. 6(b). When the wiring substrate 10 has a rectangular shape when viewed in its thickness direction, the second region 202 can be provided in a substantially rectangular lattice shape. 6(c), the third region 204 provided on the outer periphery of the second region 202 is a region that is thicker than the second region 202. The third region 204 is provided to prevent the adhesive layer from flowing out to the outside of the aggregate substrate when the adhesive layer is formed on the second region 202 in a later process.

[0055] Next, the formation of the heat transfer material will be described with reference to FIG. 7. Similar to FIG. 6(a), FIG. 7(a) is a cross section of the structure shown in FIG. 6(b) taken along line XX. FIG. 7(b) is a top view of the assembly substrate 10c. As shown in FIG. 7(a), an adhesive layer 200 is formed in the second region 202 of the core insulating layer 101. The adhesive layer 200 is formed, for example, using a dispenser. In this case, it is preferable to inject the adhesive layer in such a manner that the sum of the volume of the heat transfer material 106 to be placed in the second region and the volume of the adhesive layer 200 after hardening matches the volume of the recess formed by the second region. This setting allows the height of the top surface of the heat transfer material 106 to match the height of the top surface of the first region.

[0056] 7(b), the heat conductive material 106 is placed in the second region 202 and pressed downward. After this, the adhesive layer 200 may be cured by heat or UV. This results in a core substrate on which the heat conductive material 106 is placed. The core substrate may be manufactured by other methods. For example, after forming the heat transfer material 106 and the adhesive layer 200 on the core insulating layer 101, the conductor layer 102, the hole filling resin 103 provided in the through holes of the core insulating layer 101, and the conductor layer 105A may be formed.

[0057] Next, referring to Fig. 8, a case where an aggregate substrate 10C is formed using a heat transfer material 106 having a shape different from that of the heat transfer material 106 described in Fig. 7 will be described. Fig. 8(a) is a cross-sectional view taken along line IX-IX of the structure shown in Fig. 8(b). Fig. 8(b) is a top view of the aggregate substrate 10C. Note that the conductor layer 105A is omitted in Fig. 8(b). 8(a), the heat transfer material 106 is formed independently for each wiring substrate, and the heat transfer material is not placed on the dicing lines that will be used when later separating the aggregate substrate 10C into individual wiring substrates, and the areas that will become the dicing lines are formed with an adhesive layer. By configuring in this way, it is possible to prevent metal powder and the like from being generated from the heat transfer material 106 during the dicing process.

[0058] Next, with reference to FIGS. 9 and 10, a description will be given of a processing step in the region that will become the individual wiring substrates in the aggregate substrate after the heat transfer material 106 has been formed. 9 and 10 are diagrams showing the process of processing the area that will become the wiring substrate. First, as shown in FIG. 9(a), insulating layers 104 having through holes TH2 are formed on both sides of the core substrate at the positions of the pad portions of the conductor layer 105A. The insulating layers 104 are formed using, for example, a thermosetting resin or a photosensitive resin. When using a thermosetting resin, a coating film made of the thermosetting resin is cured, and the cured film is subjected to laser processing such as CO2 laser processing and UV laser processing to obtain the insulating layer 104 having through holes TH2. When using a photosensitive resin, the coating film made of the photosensitive resin is subjected to pattern exposure and development to obtain the insulating layer 104 having through holes TH2.

[0059] 9(b), a seed layer 105B1 is formed to cover the main surface of the insulating layer 104, the sidewall of the through hole TH2, and a region of the surface of the pad portion of the conductor layer 105A that is adjacent to the internal space of the through hole TH2. The seed layer 105B1 can be formed using the method and material described above for the seed layers of the conductor layers 105A2 and 105A3.

[0060] Next, a resist resin is applied to both sides of the composite material obtained as described above, or a dry film resist is laminated thereon, and then these resist layers are subjected to pattern exposure and development in sequence to obtain a resist pattern 122 shown in FIG.

[0061] Next, the plating layer 105B2 shown in Fig. 9(d) is formed by electrolytic plating using the seed layer 105B1 as a power supply layer. The plating layer 105B2 can be made of the metal materials described above for the plating layer of the conductor layer 105A2.

[0062] Next, as shown in FIG. 9(e), the resist pattern 122 is removed. Next, as shown in FIG. 9(f), the portion of the seed layer 105B1 that is not covered with the plating layer 105B2 is removed by etching. This results in the conductor layer 105B, which is composed of the seed layer 105B1 and the plating layer 105B2. Note that the portion of the conductor layer 105B that fills the through hole TH2 is the via portion, and the other portions are the pad portion and the wiring portion.

[0063] Next, the steps described with reference to Figures 9(a) to 9(f) are repeated, thereby obtaining the structure shown in Figure 10(g).

[0064] Next, as shown in FIG. 10(h), insulating layers 107 are formed as continuous films on both sides of the composite material obtained as described above. The insulating layers 107 as continuous films are solder resist layers. The solder resist layer can be formed on the composite material by applying a liquid solder resist or laminating a dry film solder resist. The solder resist is, for example, a photosensitive epoxy resin or a non-photosensitive thermosetting resin. The solder resist may further contain an inorganic filler.

[0065] Next, as shown in FIG. 10(i), through holes TH3 are formed in the insulating layer 107. The through holes TH3 are formed at the positions of the pad portions of the conductor layer 105B covered by the insulating layer 107. When a solder resist containing a photosensitive resin is used, the through holes TH3 can be formed by subjecting the insulating layer 107 in the form of a continuous film to pattern exposure and development. When a solder resist containing a thermosetting resin is used, the through holes TH3 can be formed by subjecting the insulating layer 107 in the form of a continuous film to laser processing such as CO2 laser processing and UV laser processing.

[0066] 10(j), a surface treatment layer 109 is formed on the surface of the pad portion of the conductor layer 105B so as to cover the area adjacent to the internal space of the through hole TH3. The surface treatment layer 109 is provided for the purposes of preventing oxidation of the surface of the conductor layer 105B and improving wettability to solder.

[0067] The surface treatment layer 109 is, for example, an electroless Ni / Pd / Au plating layer. The surface treatment layer 109 may be an OSP (Organic Solderability Preservative) film, i.e., a surface treatment layer made of a water-soluble preflux. Alternatively, the surface treatment layer 109 may be an electroless tin plating or an electroless Ni / Au plating layer.

[0068] Next, as shown in FIG. 10(k), bonding conductors 108 are formed on the surface treatment layer 109. The bonding conductors 108 are, for example, metal bumps such as solder bumps. The bonding conductors 108 can be formed, for example, by printing a metal paste such as solder paste onto the surface treatment layer 109 using a screen printing method. Alternatively, the bonding conductors 108 can be formed by printing flux onto the surface treatment layer 109 using a screen printing method, placing metal balls such as solder balls in the through holes TH3 using a ball throwing method or the like, melting them, and then cooling them. In this manner, the aggregate substrate 10C shown in FIG. 11 is obtained.

[0069] Next, the aggregate substrate 10C is divided into a plurality of wiring substrates 10. Specifically, dicing is performed along dicing lines indicated by dashed lines BL in Fig. 11. In this manner, the wiring substrate 10 shown in Fig. 1 is obtained.

[0070] In the cross-sectional view of aggregate substrate 10C shown in Figure 11, as described above, adhesive layer 200 is provided so as to straddle the boundary regions between adjacent wiring substrate portions. Because these boundary regions correspond to dicing lines, adhesive layer 200 is cut when aggregate substrate 10C is diced. Therefore, in wiring substrate 10 obtained in this manner, the cut surfaces of adhesive layer 200 are exposed at its end surfaces. Therefore, core insulating layer 101, insulating layer 104, insulating layer 107, and adhesive layer 200 are exposed at the end surfaces of wiring substrate 10.

[0071] <Semiconductor package> FIG. 12 is a cross-sectional view schematically showing an example of a semiconductor package including the wiring board shown in FIG.

[0072] The semiconductor package shown in FIG. 12 includes the above-described wiring substrate 10, a semiconductor chip 20, and a sealing resin layer 30.

[0073] The semiconductor chip 20 is, for example, a silicon chip. The semiconductor chip 20 is provided with an integrated circuit. The semiconductor chip 20 is mounted on the wiring substrate 10. Here, the semiconductor chip 20 is flip-chip mounted on the wiring substrate 10. The semiconductor chip 20 is electrically and thermally connected to the conductor layer 105B of the wiring substrate, etc., via a bonding conductor 108 located on the upper surface of the wiring substrate 10.

[0074] The encapsulating resin layer 30 includes a portion interposed between the wiring substrate 10 and the semiconductor chip 20. The encapsulating resin layer 30 is also called an underfill layer. The encapsulating resin layer 30 fixes the semiconductor chip 20 to the wiring substrate 10. The encapsulating resin layer 30 is made of, for example, a thermosetting epoxy resin. The encapsulating resin layer 30 can be formed, for example, by injecting a thermosetting resin between the semiconductor chip 20 and the wiring substrate 10 and heating it.

[0075] This semiconductor package is mounted on a motherboard or the like via a joining conductor 108 located on the underside of the wiring board 10.

[0076] <Semiconductor module> FIG. 13 is a cross-sectional view schematically showing an example of a semiconductor module including the semiconductor package shown in FIG.

[0077] The semiconductor module 1 shown in FIG. 13 includes the above-described semiconductor package and heat sinks 40A and 40B.

[0078] The heat sinks 40A and 40B are, for example, metal parts with an increased surface area provided with a number of fins or pins.

[0079] The heat sink 40A is placed on the semiconductor chip 20. The semiconductor module 1 may use a known heat dissipation plate instead of the heat sink 40A.

[0080] Heat sink 40B is disposed adjacent to wiring board 10 in the xy plane. Heat sink 40B is bonded to adhesive layer 200 of wiring board 10. In the example shown in FIG. 13 , heat sink 40B is in contact with adhesive layer 200 exposed at the end face of wiring board 10 and the cut surface of core insulating layer 101. Heat sink 40B may also be bonded to insulating layer 104 and insulating layer 107 of wiring board 10.

[0081] The heat sink 40B may be bonded to the wiring substrate 10 via an insulating material containing grease. The insulating material containing grease may further contain inorganic particles dispersed in the grease. Such an insulating material has a higher thermal conductivity than an insulating material consisting only of grease.

[0082] The semiconductor module 1 may include only one heat sink 40B. The semiconductor module 1 may include multiple heat sinks 40B. For example, if the semiconductor module 1 includes four heat sinks 40B, the heat sinks 40B may be installed adjacent to the four end faces of the wiring substrate 10, respectively.

[0083] <Effects> By employing the above-described configuration for wiring board 10, it becomes possible to manufacture a semiconductor module with excellent heat dissipation properties, as will be described below.

[0084] Next, a comparative example of the present disclosure will be described with reference to Fig. 14. Fig. 14 is a cross-sectional view that schematically shows a semiconductor module according to the comparative example. The semiconductor module 1X of the comparative example shown in FIG. 14 differs from the embodiment of the present disclosure in that it does not include the heat-conductive material 106, the adhesive layer 200, and the heat sink 40B.

[0085] Fig. 15 is a heat dissipation equivalent circuit diagram of the semiconductor module shown in Fig. 14. Fig. 15 is a heat dissipation equivalent circuit diagram of the semiconductor module shown in Fig. 12.

[0086] 15, the main heat dissipation paths through which heat generated in the semiconductor chip 20 is dissipated to the atmosphere are a first heat dissipation path through which the heat of the semiconductor chip 20 is dissipated to the atmosphere via a heat sink 40A, and a second heat dissipation path through which the heat of the semiconductor chip 20 is dissipated to the atmosphere via the wiring substrate 10X and a motherboard (not shown). The power consumption P of the semiconductor chip 20, the thermal resistance R1 of the first heat dissipation path, the thermal resistance R2 of the second heat dissipation path, the temperature T1 of the semiconductor chip 20, and the temperature T2 of the atmosphere have the relationship shown in the following equation (1), which can be expressed by the heat dissipation equivalent circuit shown in FIG.

[0087]

number

[0088] 13, the main heat dissipation paths through which heat generated in the semiconductor chip 20 is dissipated to the atmosphere are the first and second heat dissipation paths described above, and a third heat dissipation path through which heat from the semiconductor chip 20 is dissipated to the atmosphere via the wiring substrate 10X and the heat sink 40B. The power consumption P of the semiconductor chip 20, the thermal resistance R1 of the first heat dissipation path, the thermal resistance R2 of the second heat dissipation path, the thermal resistance R3 of the third heat dissipation path, the temperature T1 of the semiconductor chip 20, and the temperature T2 of the atmosphere have the relationship shown in the following equation (2), which can be expressed by the heat dissipation equivalent circuit shown in FIG.

[0089]

number

[0090] As is clear from a comparison of equations (1) and (2) and a comparison of Figures 15 and 16, the semiconductor module 1 shown in Figure 13 further includes a third heat dissipation path, and therefore can lower the temperature T1 of the semiconductor chip 20 compared to the semiconductor module 1X shown in Figure 14. To address this issue, a thermal simulation was performed using the structural and heat transfer analysis software ANSYS Mechanical.

[0091] <Comparative Example (Semiconductor Module 1X)> A 35mm square wiring board was set up with two wiring layers on each side of the core insulation layer, and a semiconductor module was installed with a 20mm square semiconductor chip mounted on this board. The temperature of the semiconductor chip was calculated when the power consumption of the semiconductor chip was 50W. As a result, the temperature of the semiconductor chip in the semiconductor module 1X shown in FIG. 14 was 80°C. <Example (Semiconductor Module 1)> A 35mm square wiring board was set up with two wiring layers on each side of the core insulation layer, and a 1500μm thick copper heat transfer material was placed on the core insulation layer of this board.Assuming a semiconductor module equipped with a 20mm square semiconductor chip, the temperature of the semiconductor chip was calculated when the power consumption of the semiconductor chip was 50W. As a result, the temperature of the semiconductor chip in the semiconductor module 1 shown in FIG. 13 reached 62°C.

[0092] [Second embodiment] Next, a second embodiment of the present disclosure will be described with reference to FIG. The second embodiment differs from the first embodiment in that the heat sink 40C has an alignment structure that enables reliable and easy contact with the end face of the wiring board 10, and further has a structure that increases the number of fins that can be arranged by making the area of ​​the top surface on which the fins of the heat sink 40C are arranged larger than the bottom surface, thereby improving heat dissipation. 17 is a cross-sectional view showing the connection between the wiring substrate 10 and the heat sink 40C in the second embodiment. In the following description, the same or equivalent components as those in the first embodiment are denoted by the same reference numerals, and their description will be simplified or omitted. In the second embodiment, as shown in FIG. 17, the heat sink 40C has a notch that aligns with the upper end 170 of the wiring board 10. Therefore, by placing the heat sink 40C on the wiring board 10, the heat sink 40C can be reliably and easily attached to a thin wiring board. Furthermore, in the heat sink 40C, the area of ​​the upper surface on which the fins are formed is set larger than that of the lower surface, and the fins can be arranged up to the vicinity of the heat transfer material 106, thereby improving heat dissipation.

[0093] [Third embodiment] Next, a third embodiment of the present disclosure will be described with reference to FIG. The third embodiment differs from the first embodiment in that the heat sink 40D has an alignment structure that enables reliable and easy contact with the end face of the wiring board 10, and further has a structure that serves as a reference surface for evenly joining the joining conductors 108 of the semiconductor module 1. 18 is a cross-sectional view showing the connection between the adhesive layer and the heat sink in the third embodiment. In the following description, the same or equivalent components as those in the first embodiment are denoted by the same reference numerals, and their description will be simplified or omitted. In the third embodiment, as shown in FIG. 18, the heat sink 40D has a notch that aligns with the lower end 180 of the wiring board 10. Therefore, in a configuration in which the heat sink 40D carries the wiring board 10, the heat sink 40D can be reliably and easily attached to a thin wiring board. Furthermore, the position of the lower surface of heat sink 40D is located 10 to 50 μm above the position of the lower surface of joining conductor 108 of semiconductor module 1. In other words, the height of the lower surface of heat sink 40D is set lower than the lower surface of wiring board 10 by the height of joining conductor 108 of semiconductor module 1 after joining. This ensures that when joining semiconductor module 1 to a printed wiring board or the like, heat sink 40D does not interfere with joining of semiconductor module 1 and the printed wiring board, and also makes it possible to align the height of joining conductor 108 after joining.

[0094] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention. The present disclosure includes the following aspects.

[0095] (Aspect 1) In a wiring board in which a conductor layer and an insulating resin layer are formed on both sides of a core insulating layer, the core insulating layer has a region in the periphery of the wiring board that is thinner than other regions, A wiring board having a heat conductive material disposed above the thin region.

[0096] (Aspect 2) 2. The wiring board according to claim 1, wherein the heat conductive material is bonded to the core insulating layer via an adhesive layer.

[0097] (Aspect 3) 3. The wiring board according to claim 1, wherein the heat-conductive material is not exposed at an end surface of the wiring board, and the core insulating layer, the insulating resin layer, and the adhesive layer are exposed at the end surface of the wiring board.

[0098] (Aspect 4) 4. The wiring board according to any one of aspects 1 to 3, wherein the heat conductive material has a thermal conductivity in the range of 100 to 400 W / m·K.

[0099] (Aspect 5) 5. The wiring board according to any one of aspects 1 to 4, wherein the heat conductive material is a material containing copper.

[0100] (Aspect 6) 5. The wiring board according to any one of aspects 1 to 4, wherein the heat-conductive material is a material containing aluminum.

[0101] (Aspect 7) A semiconductor module including the wiring board according to any one of aspects 1 to 6, a semiconductor element mounted on the wiring board via connection terminals, and a heat sink bonded to an end face of the wiring board.

[0102] (Aspect 8) 8. The semiconductor module according to claim 7, wherein the heat sink is joined to the wiring board via an insulating material containing grease.

[0103] (Aspect 9) 9. The semiconductor module according to embodiment 7 or 8, wherein the heat sink includes an alignment portion for joining to the wiring board.

[0104] (Aspect 10) 10. The semiconductor module according to any one of aspects 7 to 9, wherein the heat sink has an upper surface on which fins or pins are formed that is larger in area than a lower surface.

[0105] (Aspect 11) 10. The semiconductor module according to any one of aspects 7 to 9, wherein the lower surface of the heat sink is positioned 10 to 50 μm above the lower surface of the joining conductor of the semiconductor module.

[0106] (Aspect 12) An aggregate substrate in which a plurality of wiring substrates according to the first or second aspect are arranged.

[0107] (Aspect 13) A method for producing an aggregate substrate according to aspect 12, which relies on aspect 2, comprising: a first step of forming a recess in a core insulating layer base material in a region that will become a peripheral region of the wiring board using a router or laser processing; a second step of injecting adhesive into the recess; a third step of placing the molded heat transfer material in the recessed portion and forcing the heat transfer material into the recessed portion from above, thereby making the height of the core insulation base material other than the recessed portion substantially the same as the height of the molded heat transfer material; A manufacturing method of an aggregate substrate comprising:

[0108] (Aspect 14) A method for manufacturing a wiring board according to aspect 2, comprising: a first step of forming a recess in a core insulating layer base material in a region that will become a peripheral region of the wiring board using a router or laser processing; a second step of injecting adhesive into the recess; a third step of placing the molded heat transfer material in the recessed portion and forcing the heat transfer material into the recessed portion from above, thereby making the height of the core insulation base material other than the recessed portion substantially the same as the height of the molded heat transfer material; A fourth step of dicing the aggregate substrate manufactured by the first step to the third step in an area where the heat transfer material is not placed, thereby dividing the aggregate substrate into individual pieces. A method for manufacturing a wiring board comprising: [Explanation of symbols]

[0109] 1...semiconductor module, 1X...semiconductor module, 1Y...semiconductor module, 10...wiring board, 10C...aggregate board, 10X...wiring board, 10Y...wiring board, 20...semiconductor chip, 30...sealing resin layer, 40A...heat sink, 40B...heat sink, 40C...heat sink, 40D...heat sink, 101...core insulating layer, 102...conductor layer, 103...filling resin, 104...insulating layer, 105A...conductor layer, 105A1...conductor layer, 105A2...conductor layer, 105 A3...conductor layer, 105B...conductor layer, 105B1...seed layer, 105B2...plating layer, 106...heat transfer material, 107...insulating layer, 108...bonding conductor, 109...surface treatment layer, 121...resist pattern, 122...resist pattern, 170...upper end, 180...lower end, 200...adhesive layer, 201...first region, 202...second region, 203...opening, 204...third region, BL...dicing line, TH1...through hole, TH2...through hole, TH3...through hole, h...height.

Claims

1. In a wiring board in which a conductor layer and an insulating resin layer are formed on both sides of a core insulating layer, the core insulating layer has a region in the periphery of the wiring board that is thinner than other regions, A wiring board having a heat conductive material disposed above the thin region.

2. The wiring board according to claim 1 , wherein the heat conductive material is bonded to the core insulating layer via an adhesive layer.

3. The wiring board according to claim 2 , wherein the heat conductive material is not exposed at the end surface of the wiring board, and the core insulating layer, the insulating resin layer, and the adhesive layer are exposed at the end surface of the wiring board.

4. 4. The wiring board according to claim 1, wherein the heat conductive material has a thermal conductivity in the range of 100 to 400 W / m·K.

5. 5. The wiring board according to claim 4, wherein the heat conductive material is a material containing copper.

6. 5. The wiring board according to claim 4, wherein the heat conductive material is a material containing aluminum.

7. 4. A semiconductor module comprising: the wiring board according to claim 1; a semiconductor element mounted on the wiring board via connection terminals; and a heat sink joined to an end face of the wiring board.

8. 8. The semiconductor module according to claim 7, wherein the heat sink is joined to the wiring board via an insulating material containing grease.

9. 8. The semiconductor module according to claim 7, wherein the heat sink has a positioning portion for joining to the wiring board.

10. 10. The semiconductor module according to claim 9, wherein the heat sink has an upper surface on which fins or pins are formed that is larger in area than a lower surface.

11. 10. The semiconductor module according to claim 9, wherein the lower surface of the heat sink is positioned 10 to 50 μm above the lower surface of the joining conductor of the semiconductor module.

12. 3. An aggregate substrate comprising a plurality of wiring substrates according to claim 1 or 2 arranged thereon.

13. The method for manufacturing an aggregate substrate according to claim 12, which relies on claim 2, a first step of forming a recess in a core insulating layer base material in a region that will become a peripheral region of the wiring board using a router or laser processing; a second step of injecting adhesive into the recess; a third step of placing the molded heat transfer material in the recess and forcing the heat transfer material into the recess from above, thereby making the height of the core insulation base material other than the recess substantially the same as the height of the molded heat transfer material; A manufacturing method of an aggregate substrate comprising:

14. 3. The method for manufacturing a wiring board according to claim 2, a first step of forming a recess in a core insulating layer base material in a region that will become a peripheral region of the wiring board using a router or laser processing; a second step of injecting adhesive into the recess; a third step of placing the molded heat transfer material in the recess and forcing the heat transfer material into the recess from above, so that the height of the core insulation base material other than the recess is substantially the same as the height of the molded heat transfer material; A fourth step of dicing the aggregate substrate manufactured by the first step to the third step in an area where the heat transfer material is not placed, thereby dividing the aggregate substrate into individual pieces. A method for manufacturing a wiring board comprising:

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