Semiconductor device and motor device

Abstract

To accurately detect a current flowing through a coil of a motor.SOLUTION: The controller circuit 400 has a test mode in which a time difference between a time (T1) at which the low side switching elements (812, 822, 832) are switched to ON by the control signals (SLu, SLv, SLw) and a time at which the current detection circuit (501, 502, 503) detects the low side current is detected as a delay time (Δ T), and the storage circuit (600) is configured to store information of the delay time (Δ T). The controller circuit (400) is configured to acquire information on the delay time (Δ T) from the storage circuit (600) and generate the detection instruction signal (DCT) at a timing corresponding to the delay time (Δ T).SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a semiconductor device and a motor device using the semiconductor device. [Background technology]

[0002] In motors that do not have a brush-based commutation mechanism, such as permanent magnet synchronous motors, it is necessary to switch the direction of the current supplied to the coils depending on the rotor position. A known method for driving permanent magnet synchronous motors is to use rotor position information obtained from a position sensor such as a Hall sensor (Patent Document 1). For example, when driving a motor using vector control, the current flowing through the motor is detected and various processes are performed based on that current, so it is important to accurately detect the motor current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-58119

[0004] [overview] When driving a motor, particularly when driving the motor by vector control, there is an increasing demand for accurate detection of the current flowing through the coil.

[0005] The semiconductor device disclosed in this specification includes a controller circuit configured to output a control signal to a driver circuit driving a bridge circuit having legs in which high-side and low-side switching elements that switch ON / OFF complementarily are connected in series, the control signal indicating the timing of driving the bridge circuit; a current detection circuit configured to detect a low-side current flowing through the low-side switching element of the leg; and a memory circuit configured to store information. The current detection circuit includes a shunt resistor configured to connect the low-side switching element to a ground terminal and a potential difference detection unit configured to detect a potential difference across the shunt resistor. The controller circuit has a test mode that detects, as a delay time, the time difference between the time when the low-side switching element is switched ON by the control signal and the time when the current detection circuit detects the low-side current. The memory circuit is configured to store information about the delay time. The controller circuit is configured to acquire information about the delay time from the memory circuit, and generate a detection instruction signal that instructs the current detection timing so that the current detection circuit detects the low-side current at a timing delayed by a time corresponding to the delay time from the center time of the period during which the control signal instructs the low-side switching element to be turned ON. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic diagram of a motor device. [Figure 2] FIG. 2 is a diagram showing the configuration of a current detection circuit that detects the low-side current of the U-phase leg and a test circuit. [Figure 3] FIG. 3 is a diagram showing a control signal, a U-phase upper gate signal, a U-phase lower gate signal, an output, a current detection signal, and a tentative detection timing. [Figure 4] FIG. 4 is a diagram showing the control signal, the U-phase upper gate signal, the U-phase lower gate signal, the output, the current detection signal, and the tentative detection timing when a delay occurs. [Figure 5] FIG. 5 is a flowchart showing the operation of calculating the delay time in the test mode. [Figure 6] FIG. 6 is a diagram showing the operation when the actual detection timing is determined. [Figure 7] FIG. 7 is a flowchart showing a procedure for determining the actual detection timing. [Figure 8] FIG. 8 is a diagram showing an example of the state of each signal when the ON period of the control signal is short. [Figure 9] FIG. 9 is a diagram showing the state of each signal when the ON period of the control signal is longer than an appropriate length. [Figure 10] FIG. 10 is a flowchart showing a procedure for determining the minimum value of the length of the ON period of the control signal.

[0007] [Detailed explanation]

[0008] Hereinafter, an embodiment will be described with reference to the drawings. In this specification, "connect" includes "electrically connect."

[0009] <Motor device 100> 1 is a schematic configuration diagram of a motor device 100. The motor device 100 shown in FIG.

[0010] <Motor 200> Motor 200 is a permanent magnet synchronous motor. Motor 200 has a U-phase coil 201, a V-phase coil 202, and a W-phase coil 203. By applying voltages and currents of appropriate magnitude and timing to U-phase coil 201, V-phase coil 202, and W-phase coil 203, motor 200 rotates at a desired rotational speed. Motor 200 is a position sensorless motor that does not have a position sensor such as a Hall sensor that detects the rotational speed and rotational angle of a rotor (not shown). In the case of a position sensorless motor, the motor position may be estimated from the motor current. In this case, high current detection accuracy is required.

[0011] <Bridge circuit 800> The bridge circuit 800 is a circuit that applies a voltage to the U-phase coil 201, the V-phase coil 202, and the W-phase coil 203 of the motor 200. In the motor device 100, the bridge circuit 800 is a three-phase full bridge circuit. 81 , a V-phase leg 82 and a W-phase leg 83 .

[0012] Each phase leg has an upper arm and a lower arm. The upper arm and the lower arm are provided with switching elements 811, 812, 821, 822, 831, and 832. The switching elements 811, 812, 821, 822, 831, and 832 may be metal oxide semiconductor (MOS) field effect transistors. However, the switching elements are not limited to these, and a wide variety of elements that switch on / off based on an input signal, such as bipolar transistors and insulated gate bipolar transistors (IGBTs), may be used.

[0013] As shown in FIG. 1, the upper arm of U-phase leg 81 has a switching element 811, and the lower arm has a switching element 812. In U-phase leg 81, a first end of the upper arm is connected to a power supply terminal and is supplied with a power supply voltage VDD. A second end of the upper arm and a first end of the lower arm are connected in series. A connection point P1u between the second end of the upper arm and the first end of the lower arm is an output terminal. A second end of the lower arm is connected to a ground terminal via a current detection circuit 501.

[0014] U-phase coil 201 is connected to the connection between the upper arm and the lower arm of U-phase leg 81. Current detection circuit 501 detects the current flowing through U-phase coil 201 and supplies current detection signal CSu to controller circuit 400.

[0015] In U-phase leg 81, switching element 811 of the upper arm and switching element 812 of the lower arm are switched on or off in a complementary manner. Here, "complementary" refers to a state in which switching elements 811 and 812 are alternately switched on and off. To explain further, this does not only mean a case in which they are completely switched on and off, but may also include a case in which both switching elements 811 and 812 are OFF, for example. The same applies to V-phase leg 82 and W-phase leg 83.

[0016] The upper arm of the V-phase leg 82 has a switching element 821, and the lower arm has a switching element 822. In the V-phase leg 82, a first end of the upper arm is connected to a power supply terminal and is supplied with a power supply voltage VDD. A second end of the upper arm and a first end of the lower arm are connected in series. A connection point P1v between the second end of the upper arm and the first end of the lower arm is an output terminal. A second end of the lower arm is connected to a ground terminal via a current detection circuit 502.

[0017] A V-phase coil 202 is connected to the connection between the upper arm and lower arm of the V-phase leg 82. A current detection circuit 502 detects the current flowing through the V-phase coil 202 and supplies a current detection signal CSw to the controller circuit 400. In the V-phase leg 82, a switching element 821 of the upper arm and a switching element 822 of the lower arm are switched on or off in a complementary manner.

[0018] The upper arm of the W-phase leg has a switching element 831, and the lower arm has a switching element 832. In the W-phase leg, a first end of the upper arm is connected to a power supply terminal and is supplied with a power supply voltage VDD. A second end of the upper arm and a first end of the lower arm are connected in series. A connection point P1w between the second end of the upper arm and the first end of the lower arm is an output terminal. A second end of the lower arm is connected to a ground terminal via a current detection circuit 503.

[0019] A W-phase coil 203 is connected to a portion where the upper arm and lower arm of the W-phase leg are connected. A current detection circuit 503 detects the current flowing through the W-phase coil 203 and supplies a current detection signal CSw to the controller circuit 400. In the W-phase leg 83, a switching element 821 of the upper arm and a switching element 822 of the lower arm are switched on or off in a complementary manner.

[0020] <Driver circuit 700> The driver circuit 700 includes a U-phase upper gate driver 701 , a V-phase upper gate driver 702 , a W-phase upper gate driver 703 , a U-phase lower gate driver 704 , a V-phase lower gate driver 705 , and a W-phase lower gate driver 706 .

[0021] The U-phase upper gate driver 701, the V-phase upper gate driver 702, and the W-phase upper gate driver 703 may be configured to level-shift supplied signals and supply them to switching elements 811, 821, and 831, for example. Each upper gate driver may be configured to perform processing other than level shifting. Furthermore, the U-phase lower gate driver 704, the V-phase lower gate driver 705, and the W-phase lower gate driver 706 may be configured to level-shift supplied signals and supply them to switching elements 812, 822, and 832, for example. Each lower gate driver may be configured to perform processing other than level shifting.

[0022] The driver circuit 700 receives control signals SHu, SHv, and SHw from the controller circuit 400, which instruct the on / off of the upper arms of the U-phase leg 81, the V-phase leg 82, and the W-phase leg 83. The U-phase upper gate driver 701 level-shifts the control signal SHu to generate a U-phase upper gate signal HU. The U-phase upper gate signal HU is supplied to the gate of the switching element 811 in the U-phase leg 81 to drive the switching element 811.

[0023] Similarly, the V-phase upper gate driver 702 level-shifts the control signal SHv to generate a V-phase upper gate signal HV. The V-phase upper gate signal HV is supplied to the gate of the switching element 821 in the V-phase leg 82 to drive the switching element 821. Furthermore, the W-phase upper gate driver 703 level-shifts the control signal SHw to generate a W-phase upper gate signal HW. The W-phase upper gate signal HW is supplied to the gate of the switching element 831 in the W-phase leg 83 to drive the switching element 831.

[0024] The driver circuit 700 receives control signals SLu, SLv, and SLw from the controller circuit 400, which instruct the on / off of the lower arms of the U-phase leg 81, the V-phase leg 82, and the W-phase leg 83. The U-phase lower gate driver 704 level-shifts the control signal SLu to generate a U-phase lower gate signal LU. The U-phase lower gate signal LU is supplied to the gate of the switching element 812 in the U-phase leg 81 to drive the switching element 812.

[0025] Similarly, the V-phase lower gate driver 705 level-shifts the control signal SLv to generate a V-phase lower gate signal LV. The V-phase lower gate signal LV is supplied to the gate of the switching element 822 in the V-phase leg 82 to drive the switching element 822. Furthermore, the W-phase lower gate driver 706 level-shifts the control signal SLw to generate a W-phase lower gate signal LW. The W-phase lower gate signal LW is supplied to the gate of the switching element 832 in the W-phase leg 83 to drive the switching element 832.

[0026] <Semiconductor device 300> The semiconductor device 300 includes a controller circuit 400, current detection circuits 501, 502, and 503, and a memory circuit 600.

[0027] <Controller circuit 400> The controller circuit 400 is a circuit for controlling the motor 200. The motor 200 is controlled by, for example, vector control by the controller circuit 400. The controller circuit 400 generates control signals SHu, SHv, SHw, SLu, SLv, and SLw that instruct the driver circuit 700 to turn on and off the upper and lower arms of the U-phase leg 81, the V-phase leg 82, and the W-phase leg 83.

[0028] The controller circuit 400 generates control signals SHu, SHv, SHw, SLu, SLv, and SLw based on, for example, a target speed of the motor 200 from an external drive control unit (not shown) and a rotational speed estimated from the currents currently flowing through the U-phase coil 201, V-phase coil 202, and W-phase coil 203 of the motor 200.

[0029] As described above, the switching element 811 of the upper arm and the switching element 812 of the lower arm of the U-phase leg 81 are controlled to be turned on / off in a complementary manner. Therefore, the control signals SHu and SLu that control these switching elements are signals that become high or low in a complementary manner. Similarly, the control signals SHv and SLv are signals that become high or low in a complementary manner, and the control signals SHw and SLw are signals that become high or low in a complementary manner.

[0030] As shown in FIG. 1 , current detection circuits 501, 502, and 503 and a storage circuit 600 are connected to a controller circuit 400. The controller circuit 400 controls the operations of the current detection circuits 501, 502, and 503. The storage circuit 600 has a configuration including a semiconductor storage device such as a ROM (Read Only Memory) and is configured to be able to store various information, programs, and the like. The controller circuit 400 can access the storage circuit 600 and acquire necessary information and programs. Note that the controller circuit 400 may be configured to be able to execute programs, and the controller circuit 400 may read and execute programs stored in the storage circuit 600 to perform control operations.

[0031] <Current detection circuit> The semiconductor device 300 has a current detection circuit 501 that detects the current flowing through the U-phase coil 201, a current detection circuit 502 that detects the current flowing through the V-phase coil 202, and a current detection circuit 503 that detects the current flowing through the W-phase coil 203. The current detection circuits 501, 502, and 503 detect the currents flowing through the U-phase coil 201, V-phase coil 202, and W-phase coil 203, respectively, and supply the results to the controller circuit 400 as current detection signals CSu, CSv, and CSw.

[0032] Details of the current detection circuit will be described with reference to the drawings. Fig. 2 is a circuit diagram showing a current detection circuit 501 and a test circuit. Fig. 2 is a diagram showing the configuration of the current detection circuit 501 that detects the current flowing through the U-phase coil 201 and the test circuit CRst. Note that the current detection circuit 502 (see Fig. 1) that detects the current flowing through the V-phase coil 202 and the current detection circuit 503 (see Fig. 1) that detects the current flowing through the W-phase coil 203 have the same configuration as the current detection circuit 501. Detailed descriptions of the current detection circuits 502 and 503 will be omitted.

[0033] 2, the current detection circuit 501 includes a shunt resistor Rsh and a potential difference detection unit Acs. A first end of the shunt resistor Rsh is connected to a second end of the switching element 812 in the lower arm of the U-phase leg 81, and a second end of the shunt resistor Rsh is connected to the ground terminal. The potential difference detection unit Acs detects the potential difference between the first and second ends of the shunt resistor Rsh and supplies the detected information to the controller circuit 400 as a current detection signal CSu. The current detection signal CSu is determined by the characteristics of the potential difference detection unit Acs.

[0034] When there is no potential difference between the first and second terminals of the shunt resistor Rsh, i.e., when no current flows through the shunt resistor Rsh, the first voltage CSu1 is set. Furthermore, when a potential difference between the first and second terminals of the shunt resistor Rsh is detected, i.e., when a current flows through the shunt resistor Rsh toward the ground terminal, the first voltage CSu1 is set to a voltage greater than the first voltage CSu1. In the example shown in FIG. 3, the current detection signal CSu is set to stabilize at the second voltage CSu2. The controller circuit 400 acquires the potential difference between both ends of the shunt resistor Rsh based on the current detection signal CSu.

[0035] As described above, in the U-phase leg 81, the U-phase coil 201 is connected to the connection point P1u between the high-side switching element 811 and the low-side switching element 821, and when the low-side switching element 821 is in the on state, the current flowing through the U-phase coil 201 flows through the shunt resistor Rsh. Therefore, the controller circuit 400 obtains the current flowing through the U-phase coil 201 from the potential difference between both ends of the shunt resistor Rsh.

[0036] FIG. 3 is a diagram showing control signals SHu, SLu, U-phase upper gate signal HU, U-phase lower gate signal LU, current detection signal CSu, and tentative detection timing DCT_Tmp. For simplicity, the dead time during which the upper gate signal and the lower gate signal are simultaneously turned off is omitted. As will be described later, in the driver circuit 700 and the bridge circuit 800, the output signal is output with a delay relative to the input signal. Therefore, the timing at which the current detection signal CSu is detected without taking the delay into consideration is set as tentative detection timing DCT_Tmp. The tentative detection timing DCT_Tmp is pulse-shaped and indicates that the current detection signal CSu is acquired at the time when it goes high (time T5 in FIG. 3).

[0037] In the motor device 100, the output OUT of the U-phase leg 81 will be described as being either high or low. The diagram in Fig. 3 shows the detection timing of the current detection signal CSu when there is no delay in the operation of the driver circuit 700 and the bridge circuit 800. That is, at time T1 when the control signal SHu switches from high to low and the control signal SLiu switches from low to high, the U-phase upper gate signal HU switches from high to low and the U-phase lower gate signal LU switches from low to high. At the same time, the output OUT switches from high to low.

[0038] At time T4 when the control signal SHu changes from low to high and the control signal SLiu changes from high to low, the U-phase upper gate signal HU changes from low to high and the U-phase lower gate signal LU changes from high to low, and at the same time, the output OUT changes from low to high.

[0039] In the motor device 100, when the output OUT of the U-phase leg 81 switches from high to low, a current flows through the shunt resistor Rsh toward the ground terminal. As shown in FIG. 3, the current detection signal CSu increases over time from time T1, when the output OUT switches from high to low, due to the current flowing through the shunt resistor Rsh. This allows the motor current to be read during the period when the control signal SLiu is high. For example, if the motor current is constant, the signal CSu stabilizes at a constant value. Furthermore, at time T4, when the output OUT switches from low to high, the current detection signal CSu changes from low to high over time (see FIG. 3). In this configuration, the controller circuit 400 determines the tentative detection timing DCT_Tmp to be high, aiming for the center of the period when the output OUT is low, i.e., when the control signal SLiu is high.

[0040] By detecting the current detection signal CSu at time T5, which is the center of the high-level interval (the interval from time T1 to time T4) of the control signal SLiu, a stable current detection signal CSu can be detected. In other words, the controller circuit 400 can detect the current detection signal CSu when it is not in a rising or falling interval. In the motor device 100, the controller circuit 400 can independently determine the duty cycles of the control signals SHu and SLiu. Therefore, it can also determine in advance the time Tm during which the control signal SLiu is at a high level. Therefore, the controller circuit 400 determines the time T5, which is half the time Tm from time T1 when the control signal SLiu switches from a low level to a high level, as the time T5 when the provisional detection timing DCT_Tmp rises to a high level. In other words, the controller circuit 400 can calculate the time T5 by determining the time T1 when the control signal SLi switches from a low level to a high level.

[0041] In the actual driver circuit 700 and bridge circuit 800 of the motor device 100, delays occur due to the configuration of the internal circuits, etc. FIG. 4 is a diagram showing the control signal, U-phase upper gate signal, U-phase lower gate signal, output, current detection signal, and hypothetical detection timing when delays occur. As shown in FIG. 4, time T1 is the time when the control signal SHu switches from high to low and the control signal SLi switches from low to high. In the driver circuit 700, delays occur in operation due to the influence of level shift circuits, etc. Therefore, the time when the U-phase upper gate signal HU switches from high to low and the U-phase lower gate signal LU switches from low to high is time T2, which is delayed from time T1.

[0042] Then, switching element 811 of the upper arm of U-phase leg 81 switches from on to off at time T3, which is delayed from the time when U-phase upper gate signal HU switches. Similarly, switching element 812 of the lower arm of U-phase leg 81 switches from on to off at time T3, which is delayed from the time when U-phase lower gate signal LU switches. Therefore, output OUT changes from high to low at time T3, which is delayed from time T2 when U-phase upper gate signal HU and U-phase lower gate signal LU switch. If the timing of current detection is determined based on time T5, the center of the high-level interval of control signal SLo, when there is a delay in the switching times of each output OUT, the timing of current detection may be shifted, making accurate current detection difficult.

[0043] The delays described above occur due to the circuit configuration, layout, etc., and vary for each motor device 100. In other words, the delay time differs for each motor device 100. For this reason, the semiconductor device 300 of the motor device 100 is provided with a test mode for measuring the delay time.

[0044] An example of a test circuit used in the test mode will be described with reference to the drawings. As shown in Fig. 2, in the motor device 100, a test circuit CRst is connected to a connection point P1u of the U-phase leg 81. The test circuit CRst has a pull-up resistor Rst and a switching element SWst. In the test circuit CRst, a first terminal of the pull-up resistor Rst is connected to a reference voltage terminal, and a second terminal of the pull-up resistor Rst is connected to a first terminal of the switching element SWst. In addition, a second terminal of the switching element SWst is connected to the connection point P1u of the U-phase leg 81.

[0045] Here, the switching element SWst is configured using an NMOS transistor. However, the switching element SWst is not limited to an NMOS transistor. Any element that can switch the connection between the pull-up resistor Rst and the connection point P1u of the U-phase leg 81 between conductive and non-conductive states can be widely used.

[0046] Furthermore, since the voltage supplied from the reference voltage terminal is a voltage used during testing, it may be a voltage generated by a power supply circuit inside the semiconductor device 300, or a voltage supplied from outside the semiconductor device 300.

[0047] A test signal TEST_EN is input to the gate of the switching element SWst. The test signal TEST_EN is a signal supplied from the controller circuit 400, and is a signal that can take on a low level or a high level that has a voltage higher than the low level. The test signal TEST_EN is at a high level when the test mode is executed. When the test signal TEST_EN is at a high level, the switching element SWst is turned on, and when it is at a low level, the switching element SWst is turned off.

[0048] When the switching element SWst is on, a current formed by the reference voltage supplied from the reference voltage terminal and the pull-up resistor Rst flows through the connection between the switching element 811 and the switching element 812 of the U-phase leg 81. The test circuit CRst may be attached to the outside of the motor device 100 or may be provided inside the motor device 100. The test circuit CRst may also be built into the semiconductor device 300.

[0049] Next, the operation in the test mode will be described with reference to the drawings. Fig. 5 is a flowchart showing the operation for calculating the delay time ΔT in the test mode. The test mode will be described with reference to the timing chart in Fig. 4. Note that in the test mode, the current detection signal CSu is continuously input to the controller circuit 400.

[0050] 5, when the controller circuit 400 is instructed to execute the test mode, the controller circuit 400 transitions to the test mode. Upon transitioning to the test mode, the controller circuit 400 outputs a high-level test signal TEST_EN (step S101). This turns on the switching element SWst, and a voltage is applied to the connection point P1u of the U-phase leg 81 by the pull-up resistor Rst connected to the reference voltage terminal.

[0051] 4, at time T1, the controller circuit 400 switches the control signal SHu from high level to low level and switches the control signal SLi from low level to high level (step S102). As described above, in the motor device 100, the time at which the output OUT switches is delayed relative to the time at which the control signals SHu and SLiu switch. At the same time that the output OUT switches from high level to low level, the current detection signal CSu begins to increase from the first voltage CSu1. Therefore, the controller circuit 400 determines whether the current detection signal CSu has increased from the first voltage CSu1 (step S103). The controller circuit 400 repeats step S104 until it determines that the current detection signal CSu has increased from the first voltage CSu1.

[0052] 4, at time T3, the controller circuit 400 recognizes that the current detection signal CSu has increased (Yes in step S103). Then, at time T3, the controller circuit 400 calculates the difference in time between time T1 and time T3 as a delay time ΔT (step S104) and stores the delay time ΔT in the memory circuit 600 (step S105). At time T4, the controller circuit 400 outputs a low-level test signal TEST_EN (step S106) and ends the test mode.

[0053] In the test mode, the controller circuit 400 acquires the delay time by detecting the current flowing through the lower arm switching element 812 of the U-phase leg 81. At this time, the U-phase upper gate signal HU that controls the upper arm switching element 811 is also operated in the same manner as when driving the motor 200.

[0054] Next, a method for determining the detection timing DCT in consideration of delay will be described. Fig. 6 is a diagram showing the operation when the actual detection timing DCT is determined. Fig. 7 is a flowchart showing the procedure for determining the actual detection timing DCT.

[0055] 7, the controller circuit 400 switches the control signal SLi from low level to high level at time T11 (step S201). At this time, the controller circuit 400 determines time T15, at which the tentative detection timing DCT_Tmp is switched to high level, to be the center of an interval during which the control signal SLi is at high level (step S202). Then, the controller circuit 400 accesses the storage circuit 600 and acquires the delay time ΔT (step S203). Then, the controller circuit 400 determines time T16, which is delayed by the delay time ΔT from time T15, at which the tentative detection timing DCT_Tmp is switched to high level, as the time at which the detection timing DCT rises (step S204).

[0056] In addition, in the motor device 100, the delay time is also calculated in test mode for the current detection signal CSv that detects the current flowing in the V-phase leg 82 and the current detection signal CSw that detects the current flowing in the W-phase leg 83, and the detection timing is determined taking the delay time into consideration.

[0057] As described above, the delay of the driver circuit 700 and the bridge circuit 800 varies from circuit to circuit. Therefore, the delay time is actually measured in the test mode in the motor device 100, and the detection timing of the current detection signal is determined taking that delay time into consideration. In this way, even if there are individual differences in the motor device 100, the controller circuit 400 can accurately detect the current flowing through each of the coils 201, 202, and 203 of the motor 200.

[0058] <Modification> In the motor device 100 having the above-described configuration, the case has been described in which the first delay time ΔT1 from the time when the control signal SLiu switches from low level to high level to the time when the U-phase lower gate signal LU switches from low level to high level is the same as the second delay time ΔT2 from the time when the control signal SLiu switches from high level to low level to the time when the U-phase lower gate signal LU switches from high level to low level.

[0059] The first delay time ΔT1 and the second delay time ΔT2 may differ depending on the characteristics of the elements and the circuit. For example, as shown in Figure 8, if the first delay time ΔT1 is longer than the second delay time ΔT2 and the difference between the first delay time ΔT1 and the second delay time ΔT2 is greater than the on-period Tp of the control signal SLiu, the U-phase lower gate signal LU does not switch from low to high. As a result, a low-level output OUT cannot be output (see Figure 8), and current detection by the shunt resistor Rsh is not possible.

[0060] Therefore, the controller circuit 400 may have a function of detecting the minimum value of the on-period Tp of the control signal SLu in test mode and storing the detected on-period Tp as a threshold value. The procedure for detecting the minimum value of the on-period Tp of the control signal SLu by the controller circuit 400 will be described with reference to the drawings. Fig. 9 is a diagram showing the states of each signal when the on-period Tp of the control signal SLu is longer than an appropriate length. Fig. 10 is a flowchart showing the procedure for determining the minimum value of the on-period Tp of the control signal SLu.

[0061] 10, when the controller circuit 400 is instructed to execute the test mode, the controller circuit 400 transitions to the test mode. Upon transitioning to the test mode, the controller circuit 400 outputs a high-level test signal TEST_EN (step S301). This turns on the switching element SWst, and a voltage is applied to the connection point P1u of the U-phase leg 81 by the pull-up resistor Rst connected to the reference voltage terminal.

[0062] The on-period Tp of the control signal SLiu is set to the currently set minimum value Tp_min (step S302). In this state, as shown in Fig. 9, the controller circuit 400 switches the control signal SHu from high level to low level and switches the control signal SLiu from low level to high level. After the on-period Tp has elapsed, the controller circuit 400 switches the control signal SHu from low level to high level and switches the control signal SLiu from high level to low level (step S303).

[0063] Thereafter, the controller circuit 400 checks whether the current detection signal CSu has reached the second voltage CSu2 (step S304). As described above, in the bridge circuit 801, the switching of the switching elements 811 and 812 is delayed relative to the control signals SHu and SLiu. If the current detection signal CSu does not reach the second voltage CSu2 until a predetermined time Tq has elapsed since the control signals SHu and SLiu were switched, it is determined that the period during which the switching element 811 of the U-phase upper arm is at a low level and the switching element 812 of the U-phase lower arm is at a high level is insufficient. In other words, it is considered that the length of the on-period Tp is insufficient.

[0064] That is, if the current detection signal CSu does not reach the second voltage CSu2 (No in step S304), the controller circuit 400 checks whether a predetermined time Tq has elapsed after the process of step S303 (step S305). The time Tq may be a predetermined fixed value, or may be configured to be corrected based on a value obtained when the test mode is executed. Alternatively, the time Tq may be manually changeable by a user or the like.

[0065] If the controller circuit 400 determines that the time Tq has not elapsed (No in step S305), the process returns to step S306. If the controller circuit 400 determines that the time Tq has elapsed (Yes in step S305), the controller circuit 400 determines that the on-period Tp of the current control signal SLiu is not long enough to detect the current, and increases the on-period Tp of the control signal SLiu by an increment ΔTp1 (step S306). Then, the process returns to step S303 and continues. When returning to step S303, the controller circuit 400 performs processing to set the output OUT to a high level, and then transitions to step S303.

[0066] If the current detection signal CSu has reached the second voltage CSu2 (Yes in step S304), the controller circuit 400 sets the on-period Tp of the current control signal SLi to the minimum value Tp_min (step S308).Then, the controller circuit 400 outputs a low-level test signal TEST_EN (step S309) and ends the test mode.

[0067] In this way, the semiconductor device 300 can use the test mode to acquire the minimum value Tp_min of the on-period Tp of the control signal SLu for each motor device 100. The controller circuit 400 can then operate to use the minimum value Tp_min as a threshold for the on-period time, and not output the control signal SLu for an on-period that is equal to or shorter than the threshold. This prevents the motor device 100 from causing the output OUT to go low, and ensures that the current flowing through the U-phase coil 201 of the motor 200 can be detected reliably.

[0068] In addition, the controller circuit 400 can also detect the minimum value of the ON period of the control signals SLv and SLw in a similar manner.

[0069] Although the semiconductor device 300 having the above-described configuration is configured to transmit a control signal to control the bridge circuit 800 having three-phase legs, the configuration is not limited to this. For example, even in a semiconductor device configured to control a bridge circuit having one leg, it is possible to accurately detect the current flowing through the shunt resistor by using a similar configuration.

[0070] The semiconductor device 300 can be widely used as a bridge circuit in which switching elements are connected in series, and a circuit that transmits a control signal to a driver circuit that drives the bridge circuit.

[0071] <Other> The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The various embodiments described so far may be combined as appropriate within a consistent range. The above-described embodiments are merely examples of embodiments of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above embodiments.

[0072] <Additional Notes> The various embodiments described above will be generally described below.

[0073] The semiconductor device (300) described above includes a controller circuit (400) configured to output control signals (SHu, SHv, SHw, SLu, SLv, SLw) instructing the timing of driving the bridge circuit (800) to a driver circuit (700) that drives the bridge circuit (800) having a plurality of legs (81, 82, 83) in which high-side switching elements (811, 821, 831) and low-side switching elements (812, 822, 832) that are switched ON / OFF complementarily; a current sensing circuit (501, 502, 503) configured to sense a low-side current through a low-side switching element (812, 822, 832) of the leg (81, 82, 83); a memory circuit (600) configured to store information; the current detection circuits (501, 502, 503) are configured to include shunt resistors (Rsh) arranged to connect the low-side switching elements (812, 822, 832) to the ground terminals, and potential difference detection units (Acs) configured to detect a potential difference between both ends of the shunt resistors (Rsh); the controller circuit 400 has a test mode for detecting, as a delay time (ΔT), a time difference between a time (T1) at which the low-side switching elements (812, 822, 832) given by the control signals (SLu, SLv, SLw) are switched ON and a time at which the current detection circuits (501, 502, 503) detect the low-side current; The memory circuit (600) is configured to store information about the delay time (ΔT), The controller circuit (400) is configured (first configuration) to acquire information on the delay time (ΔT) from the memory circuit (600) and generate a detection instruction signal (DCT) that instructs the timing of current detection so that the current detection circuit (500) detects the low-side current at timing (T6) delayed by a time corresponding to the delay time (ΔT) from the center time (T5) of the period (Tm) during which the control signals (SLu, SLv, SLw) instruct the low-side switching elements (812, 822, 832) to be turned ON.

[0074] In the semiconductor device (300) of the first configuration, a test circuit (CRst) capable of supplying a predetermined current is connected to the connection points (P1u, P1v, P1w) between the high-side switching elements (811, 821, 831) and the low-side switching elements (812, 822, 832) of the legs (81, 82, 83), and in a test mode, the controller circuit (400) may be configured (second configuration) to connect the test circuit (CRst) to the connection points (P1u, P1v, P1w).

[0075] In the semiconductor device (300) of the second configuration, the test circuit (CRst) has a pull-up resistor (Rst) connected to a power supply terminal and a test switching element (SWst) arranged between the pull-up resistor (Rst) and the connection point, In the test mode, the controller circuit (400) is configured to switch on the test switching element (SWst). 3 The configuration may be as follows:

[0076] Items 1 to 5 above 3 In the semiconductor device (300) having any of the above configurations, in a test mode, the controller circuit (400) determines the minimum value of the on-period of the control signals (SLu, SLv, SLw) based on whether or not a low-side current is detected by the current detection circuits (501, 502, 503) while changing the on-period of the control signals (SLu, SLv, SLw). 4 The configuration may be as follows:

[0077] The motor device (100) described above includes a semiconductor device (300) having any one of the first to fourth configurations described above, a driver circuit (700) connected to the semiconductor device (300); a bridge circuit (800) connected to a driver circuit (700); and a motor (200) driven by a voltage supplied from a bridge circuit (800) (fifth configuration). [Explanation of symbols]

[0078] 100 Motor device 200 motor 201 U-phase coil 202 V-phase coil 203 W-phase coil 300 Semiconductor device 400 Controller Circuit 501, 502, 503 Current detection circuit Rsh Shunt resistance Acs Current Sense Amplifier 600 Memory circuit 700 driver circuit 701 U-phase upper gate driver 702 V-phase upper gate driver 703 W-phase upper gate driver 704 U-phase lower gate driver 705 V-phase lower gate driver 706 W-phase lower gate driver 81 U-phase leg 82 V-phase leg 83 W-phase leg 800 Bridge Circuit 811, 812, 821, 822, 831, 832 Switching elements P1u connection point P1v junction point P1w connection point CRst test circuit Rst pull-up resistor SWst Switching element SHu, SHv, SHw, SLu, SLv, SLw control signals HU U phase upper gate signal HV V-phase upper gate signal HW W phase upper gate signal LU U phase lower gate signal LV V phase lower gate signal LW W phase lower gate signal CSu, CSv, CSw current detection signals CSu1 First voltage CSu2 Second voltage

Claims

1. a controller circuit configured to output a control signal to a driver circuit that drives a bridge circuit having legs in which high-side switching elements and low-side switching elements that are switched ON / OFF complementarily are connected in series, the control signal indicating the timing of driving the bridge circuit; a current sensing circuit configured to sense a low-side current through the low-side switching device of the leg; a memory circuit configured to store information; the current detection circuit is configured to include a shunt resistor configured to connect the low-side switching element and a ground terminal, and a potential difference detection unit configured to detect a potential difference between both ends of the shunt resistor; the controller circuit has a test mode for detecting, as a delay time, a time difference between a time at which the low-side switching element is switched ON by the control signal and a time at which the current detection circuit detects a low-side current; the storage circuit is configured to store information about the delay time; The controller circuit acquires information about the delay time from the memory circuit, and generates a detection instruction signal that instructs the current detection circuit to detect the low-side current at a timing delayed by a time corresponding to the delay time from the center time of the period during which the control signal instructs the low-side switching element to be turned ON.

2. a test circuit capable of supplying a predetermined current is connected to a connection point between the high-side switching element and the low-side switching element of the leg; 2. The semiconductor device according to claim 1, wherein in the test mode, the controller circuit connects the test circuit to the connection point.

3. the test circuit includes a pull-up resistor connected to a power supply terminal, and a test switching element disposed between the pull-up resistor and the connection point; 3. The semiconductor device according to claim 2, wherein in the test mode, the controller circuit is configured to switch on the test switching element.

4. 2. The semiconductor device according to claim 1, wherein, in the test mode, the controller circuit is configured to determine a minimum value of an on-period of the low-side switching element based on whether or not the low-side current is detected by the current detection circuit while changing an on-period of the control signal.

5. A semiconductor device according to any one of claims 1 to 4; the driver circuit connected to the semiconductor device; the bridge circuit connected to the driver circuit; a motor driven by the voltage supplied from the bridge circuit.

Images