Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device and a method of manufacturing the same, capable of suppressing generation of abnormal etch pits, improving mechanical strength after chip assembly, and securing reliability of a product.SOLUTION: The semiconductor device includes a semiconductor substrate 1 of a first conductivity type, an element structure provided on the semiconductor substrate 1, and a main electrode 16 provided on the element structure. The main electrode 16 is an Al alloy film, and an area where the orientation of Al of the Al alloy film is (111) is 99% or more. The average particle diameter of the Al alloy film is 5.5 μm or more and 10 μm or less. The Al alloy film is an Al film, an Al-Si film, or an Al-Si-Cu film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] A technique has been proposed in the past in which an Al film and a Si substrate are sintered at a temperature of, for example, 420°C for 60 minutes to form a uniform (111) surface over the entire surface of the Al film (see, for example, Patent Document 1 below). Another technique has been proposed in which an Al alloy layer and a barrier metal layer are provided on the Al alloy layer, and the Al alloy layer provided on the barrier metal layer is oriented in the (111) plane to form a dense Al alloy layer (see, for example, Patent Document 2 below). Another technique has been proposed in which aluminum is formed as warm aluminum (approximately 350°C to approximately 450°C) by sputtering (see, for example, Patent Document 3 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-77203 [Patent Document 2] Patent Publication No. 2021-77729 [Patent Document 3] Japanese Patent Application Laid-Open No. 2009-21635 Summary of the Invention [Problem to be solved by the invention]

[0004] However, conventional semiconductor devices have a problem in that excessive etch pits are formed on the aluminum (Al) film surface or aluminum-silicon (Al-Si) film surface of the surface electrode, causing the plating film to peel off from the outermost layer of the Al film or Al-Si film.

[0005] The present disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress the generation of abnormal etch pits, improve mechanical strength after chip assembly, and ensure product reliability in order to resolve the problems associated with the conventional technology described above. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object of the present disclosure, the semiconductor device according to the present disclosure has the following features: The semiconductor device includes a semiconductor substrate of a first conductivity type, an element structure provided on the semiconductor substrate, and a main electrode provided on the element structure. The main electrode is an Al alloy film, and the Al orientation of the Al alloy film is (111) in an area of ​​99% or more.

[0007] According to the above disclosure, the area of ​​the Al-Si film (Al alloy film) where the Al orientation is (111) is 99% or more. This suppresses the generation of abnormal etch pits during pre-plating treatment and prevents the etch pits from joining together in the Al-Si film after plating. This improves the mechanical strength after chip assembly and ensures product reliability. [Effects of the Invention]

[0008] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure have the effect of suppressing the generation of abnormal etch pits, improving the mechanical strength after chip assembly, and ensuring the reliability of the product. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an active structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] 1 shows a flowchart of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 3] FIG. 2 is a cross-sectional view showing an Al—Si film sputtering process of the silicon carbide semiconductor device according to the embodiment. [Figure 4]1 is a graph showing the orientation ratios of Al—Si films in a conventional example and an example. [Figure 5] FIG. 1 is a cross-sectional view showing a normal Al—Si film and a plated film of a conventional semiconductor device. [Figure 6] FIG. 1 is a cross-sectional view showing an Al—Si film and a plating film in which many etch pits occur in a conventional semiconductor device. [Figure 7] FIG. 1 is a cross-sectional view showing an Al—Si film and a plating film in which etch pits are connected in a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Summary of Embodiments of the Present Disclosure> In order to solve the above-mentioned problems and achieve the object of the present disclosure, the semiconductor device according to the present disclosure has the following features: The semiconductor device includes a semiconductor substrate of a first conductivity type, an element structure provided on the semiconductor substrate, and a main electrode provided on the element structure. The main electrode is an Al alloy film, and the Al orientation of the Al alloy film is (111) in an area of ​​99% or more.

[0011] According to the above disclosure, the area of ​​the Al-Si film (Al alloy film) where the Al orientation is (111) is 99% or more. This suppresses the generation of abnormal etch pits during pre-plating treatment and prevents the etch pits from joining together in the Al-Si film after plating. This improves the mechanical strength after chip assembly and ensures product reliability.

[0012] Furthermore, in the semiconductor device according to the present disclosure, the average grain size of the Al alloy film is 5.5 μm or more and 10 μm or less.

[0013] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the Al alloy film is an Al film, an Al—Si film, or an Al—Si—Cu film.

[0014] In order to solve the above-mentioned problems and achieve the object of the present disclosure, the method for manufacturing a semiconductor device according to the present disclosure has the following features: First, a first step is performed in which an element structure is formed on a semiconductor substrate of a first conductivity type. Next, a second step is performed in which a main electrode is formed on the element structure. In the second step, the main electrode is formed of an Al alloy film, and the Al alloy film is deposited by a sputtering method, and the wafer temperature during deposition is 350°C or higher and 480°C or lower.

[0015] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure is characterized in that in the second step, the function of the electrostatic chuck is turned off when forming a film by sputtering.

[0016] <Findings underlying this disclosure> First, we will explain the problems with conventional semiconductor devices. In conventional semiconductor devices, an Al-Si film for the surface electrode is formed by sputtering, and electroless Ni plating and Au plating are performed on the Al-Si film, and the surface side of the device is assembled by soldering.

[0017] In this case, during plating, the aluminum oxide film must be removed and the Al-Si film surface must be pretreated in an etching bath or zincate treatment bath in order to allow catalytic zinc (Zn) or iron (Fe) ions to adhere to the Al-Si film surface. During this pretreatment, the Al-Si film is etched and thinned by about 0.2 to 0.5 μm.

[0018] Here, the Al-Si film is polycrystalline, and it is known that the characteristics of the Al orientation vary depending on the sputtering conditions. Figure 5 is a cross-sectional view showing a normal Al-Si film and a plated film in a conventional semiconductor device. When the Al-Si film 116 has a (111) orientation, etch pits 140 caused by the pre-plating process occur sporadically, but do not grow to the point of connecting, and there is no problem with the strength of the plated film 120 on the Al-Si film 116.

[0019] 6 is a cross-sectional view showing an Al-Si film and a plated film in a conventional semiconductor device where many etch pits have occurred. If the orientation of the Al-Si film 116 deviates from (111), etching of aluminum proceeds excessively, resulting in the formation of excessive etch pits 140 due to pre-plating treatment.

[0020] 7 is a cross-sectional view showing an Al-Si film and a plating film in which etch pits are connected in a conventional semiconductor device. If the degree of formation of etch pits 140 worsens, a problem occurs in which adjacent etch pits 140 are connected inside Al-Si film 116. Because cavities are formed between Al-Si film 116 and plating film 120, when such an Al-Si film 116 is plated, the mechanical strength of the surface of Al-Si film 116 cannot be maintained, resulting in a problem in which plating film 120 peels off from the outermost layer of Al-Si film 116 after the assembly process.

[0021] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate a higher or lower impurity concentration than layers or regions without these prefixes, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include variations within 5% in consideration of variations in manufacturing.

[0022] (Embodiment) The semiconductor device according to the present disclosure is configured using a wide bandgap semiconductor. In the embodiments, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example. Figure 1 is a cross-sectional view showing an active structure of the silicon carbide semiconductor device according to the embodiments.

[0023] A silicon carbide semiconductor device 70 according to an embodiment includes an active region 50 and an edge termination region (not shown) surrounding the active region 50 in a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate (semiconductor substrate (semiconductor chip))). The active region 50 is a region through which current flows in the on-state. The edge termination region is a region that relieves the electric field on the front surface side of the substrate in the drift region and maintains a breakdown voltage.

[0024] As shown in FIG. 1, the silicon carbide substrate is a n-type silicon carbide substrate. + Mold support substrate (n + A silicon carbide substrate (first conductivity type semiconductor substrate) 1 is provided on a front surface thereof with an n-type silicon carbide substrate. - type drift region 2 and n - n type drift region 2 + and a p-type base region 5 made of silicon carbide on the surface opposite to the n-type silicon carbide substrate 1 side. + The n-type silicon carbide substrate 1 functions as a drain region. - Type drift region 2 and n + Between the silicon carbide substrate 1 and the n-type silicon carbide substrate 2, for example, + A buffer layer or the like may be provided to reduce the growth of crystal defects from silicon carbide substrate 1.

[0025] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The drift region 2 is an n + The impurity concentration is lower than that of the n-type silicon carbide substrate 1. -The drift region 2 reaches the p-type base region 5 and is connected to the p-type base region 5 and the p-type + The gate insulating film 11 is in contact with the mold portion region 4, and extends in a direction parallel to the front surface of the semiconductor substrate to a trench 25 (described later). - The impurity concentration of the drift region 2 is, for example, 5×10 16 cm -3 Below, the thickness is 5.0 μm or more.

[0026] Also, n - An n-type heavily doped region (not shown) may be provided between the n-type drift region 2 and the p-type base region 5. When an n-type heavily doped region is provided, the n-type heavily doped region is formed between adjacent p-type regions as described later. + The n-type high concentration region is in contact with these regions at the n-type partial region 4, extends in a direction parallel to the front surface of the semiconductor substrate, reaches the trench 25, and is in contact with the gate insulating film 11. The n-type high concentration region is in contact with the p-type base region 5 at its upper surface and - The n-type high concentration region is in contact with the n-type drift region 2. + Lower n than silicon carbide substrate 1 - Higher than type drift region 2.

[0027] n + A drain electrode 17 serving as a back surface electrode is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide base) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the drain electrode 17.

[0028] A trench structure is formed on the first main surface side (p-type base region 5 side) of the silicon carbide substrate. Specifically, the trench 25 is formed between the n-type + The n-type silicon carbide substrate 1 is connected to the surface opposite to the n-type silicon carbide substrate 1 (the first main surface side of the silicon carbide substrate) through the p-type base region 5. - The n-type drift region 2 (or the n-type high concentration region, if provided) is reached.

[0029] A gate insulating film 11 is formed along the inner wall of the trench 25, on the bottom and side walls of the trench 25, and a gate electrode 13 is formed inside the gate insulating film 11 in the trench 25. The gate electrode 13 is formed by the gate insulating film 11. - The gate electrode 13 is insulated from the p-type drift region 2 and the p-type base region 5. A part of the gate electrode 13 may protrude from above the trench 25 (the side where the source electrode pad 16, which will be described later, is provided) toward the source electrode pad 16.

[0030] n - n type drift region 2 + The surface layer on the side opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide substrate) is provided with an upper p + The mold part area 4a is provided. + The mold portion region 4a is provided, for example, between the trenches 25. - In the drift region 2, the upper p + The lower part p that contacts the bottom of the mold part region 4a + The trench 25 has a bottom formed with a p + A mold region 26 is provided. + The mold region 26 is provided at a position facing the bottom of the trench 25 in the depth direction (the direction from the source electrode pad 16 to the back surface electrode). + Mold part region 4a and lower part p + The mold subregion 4b is p + This becomes mold subregion 4.

[0031] p + The width of the mold region 26 is equal to or wider than the width of the trench 25. + The width of the mold part region 4b is the upper p + The width of the trench 25 is equal to or wider than the width of the mold portion region 4a. + The p-type base region 5 and the p-type region 26 may be connected. + n sandwiched between type regions 26 - It may be located within the mold drift region 2.

[0032] Inside the p-type base region 5, an n-type ++ Type source region 7 and p ++ The n-type contact region 6 is selectively provided. ++ Type source region 7 and p ++ The mold contact regions 6 abut each other.

[0033] The interlayer insulating film 14 is provided on the entire first main surface side of the silicon carbide substrate so as to cover the gate electrode 13 embedded in the trench 25. The interlayer insulating film 14 is made of NSG or BPSG. A contact hole is opened in the interlayer insulating film 14, and the bottom of the contact hole has an n ++ Type source region 7 and p ++ A source electrode 18 is provided in contact with the n-type contact region 6. ++ Type source region 7 and p ++ The source electrode 18 is in contact with the gate electrode 13 through the interlayer insulating film 14. A source electrode pad (main electrode) 16 made of an Al-Si film is provided on the source electrode 18. The Al-Si film may be an Al-Si alloy. A barrier metal 15 may be provided between the source electrode 18 and the interlayer insulating film 14 to prevent diffusion of metal atoms from the source electrode 18 toward the gate electrode 13, for example.

[0034] A plating film 20 is selectively provided on the top of the source electrode pad 16, and solder (not shown) is selectively provided on the surface side of the plating film 20. The plating film 20 is, for example, a Ni (nickel) plating film. A pin-shaped electrode (not shown) that serves as a wiring material for extracting the potential of the source electrode 18 to the outside is provided on the solder. The pin-shaped electrode has a needle-like shape and is bonded to the source electrode pad 16 in an upright state. Although FIG. 1 shows only two MOS gate structures (insulated gates made of metal-oxide film-semiconductor) in the active region 50, more MOS gate structures may be arranged in parallel.

[0035] In this embodiment, as will be described later, the Al-Si film 16 is formed while maintaining the wafer temperature at 350°C or higher and 480°C or lower during sputtering. Therefore, the area of ​​the film formation surface where the Al orientation of the Al-Si film 16 is (111) is 99% or higher. The average particle size of the Al-Si particles in the Al-Si film 16 formed in this manner is 5.5 μm or higher and 10 μm or lower, preferably 6 μm or higher and 8 μm or lower.

[0036] In this way, by making the area of ​​the Al-Si film 16 with an Al orientation of (111) greater than or equal to a certain value, the generation of abnormal etch pits during pre-plating treatment can be suppressed and the connection of etch pits within the aluminum sputtered film after plating can be prevented. This improves the mechanical strength of the chip after assembly and ensures product reliability. While the Al-Si film 16 has been used as an example of the main electrode, it may also be an Al film or an Al-Si-Cu film. The Al-Si-Cu film may be an Al-Si-Cu alloy. The Al content of the main electrode may be 90 wt% or more, 95 wt% or more, or 97 wt% or more in at least a portion of the region.

[0037] (Method for manufacturing silicon carbide semiconductor device according to embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Fig. 2 shows a flowchart of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. First, a semiconductor element structure is formed as follows (step S1). + On the front surface of the silicon carbide substrate 1, - The type drift region 2 is epitaxially grown.

[0038] Next, n - A p-type base region 5 is epitaxially grown on the front surface of the n-type drift region 2. The p-type base region 5 may be formed by ion implantation. - Between the n-type drift region 2 and the p-type base region 5, an n-type high concentration region may be formed.

[0039] Next, p-type regions (p + Type subregion 4, p ++ Type contact region 6, p + 26), and then photolithography and ion implantation of n-type impurities are used to form n ++ Next, the n-type source region 7 is formed. - A heat treatment is then performed to activate the impurities ion-implanted into the p-type drift region 2 and the p-type base region 5. This heat treatment for impurity activation may be performed each time an impurity is ion-implanted, or may be performed all at once. Next, trenches 25, gate insulating films 11, and gate electrodes 13 are formed by a general method.

[0040] Next, the p-type base region 5, p ++ type contact region 6 and n ++ An interlayer insulating film 14 is formed on the source region 7, a contact hole is formed in the interlayer insulating film 14, and a source electrode 18 is formed in the contact hole (step S2).

[0041] Next, a Ti film is formed uniformly in the contact hole and on the surface of the interlayer insulating film 14 by sputtering. Next, a TiN film is formed on the surface of the Ti film by sputtering. As a result, barrier metal 15 is stacked on the interlayer insulating film 14 and in the contact hole. Next, the Ti film on the bottom of the contact hole is silicified by heat treatment (annealing).

[0042] Next, an Al-Si film that will become the source electrode pad 16 is formed by, for example, sputtering (step S3). The Al-Si film is, for example, aluminum containing 1% silicon (Al-Si). The source electrode pad 16 may be formed of an Al metal film other than an Al film or an Al-Si film. Next, the Al-Si film is patterned to form the source electrode pad 16.

[0043] FIG. 3 is a cross-sectional view showing an Al-Si film sputtering process for a silicon carbide semiconductor device according to an embodiment. The Al-Si film is formed by a sputtering method. In the sputtering process, a SiC wafer 31 is transported onto a stage 32 by a wafer transport ring 37 in a vacuum chamber (not shown) and secured with a cover ring 36. An inert gas such as argon is introduced into the vacuum chamber, and a high voltage is applied to the inert gas to generate plasma. Argon ions or the like are then collided with a target 34. In reaction to the collision, atoms forming the target 34 are ejected and adhere to the SiC wafer 31, thereby forming an Al-Si film. In the magnetron sputtering process shown in FIG. 3, a source magnet 35 is installed behind the target 34 to generate a magnetic field around the target 34. The magnetic field captures electrons, increasing the electron concentration in the magnetic field and increasing the electron concentration near the target 34, thereby improving sputtering efficiency.

[0044] Here, the results of measuring the orientation ratio of the Al-Si film under different sputtering conditions are shown. FIG. 4 is a graph showing the orientation ratios of the Al-Si films in the conventional example and the example. In FIG. 4, the orientation ratio indicates the degree of orientation deviation from the (111) orientation. In the conventional example, the temperature of the electrostatic chuck 33 was set to 300°C, the electrostatic chuck 33 itself was turned on, and the wafer temperature during film formation was set to less than 350°C. By turning on the electrostatic chuck 33, the function of preventing the temperature of the SiC wafer 31 from rising excessively above a certain level is achieved. In Example 1, the temperature of the electrostatic chuck 33 was set to 160°C, the electrostatic chuck 33 itself was turned off, and the wafer temperature during film formation was set to 350°C or higher. In Example 2, the temperature of the electrostatic chuck 33 was set to 250°C, the electrostatic chuck 33 itself was turned off, and the wafer temperature during film formation was set to 350°C or higher.

[0045] As shown in Figure 4, in the conventional example, the orientation ratio of the Al-Si film in region T in Figure 4 is less than 99% even at the center and periphery, whereas in Examples 1 and 2, the orientation ratio of the Al-Si film is nearly 100% even at the center and periphery, that is, 99% or more. Thus, by turning off the electrostatic chuck 33 and stopping the function of preventing the temperature of the electrostatic chuck 33 from rising too much above a certain level, the wafer temperature during film formation can be set to 350°C or higher, thereby making it possible to make the area of ​​the Al-Si film where the Al orientation is (111) 99% or more. Furthermore, it is preferable that the wafer temperature during film formation be 480°C or lower.

[0046] Furthermore, by increasing the temperature of the stage 32, the wafer temperature during film formation can be kept at 350°C or higher even when the electrostatic chuck 33 is turned on. Even in this case, the area of ​​the Al-Si film where the Al orientation is (111) can be made 99% or higher.

[0047] Furthermore, as a result of analyzing the Al-Si films produced in Examples 1 and 2 by EBSD (Electron Backscatter Diffraction), the average particle diameter of the Al-Si particles in the Al-Si film was found to be 6 μm or more and 8 μm or less. Here, the case where an Al-Si film was used as the source electrode pad 16 was shown, but the same applies to the case where an Al film or other Al alloy film is used.

[0048] Next, the Al-Si film surface is pre-treated for plating in an etching bath or a zincate treatment bath (step S4). Next, a plating film 20 is formed on the Al-Si sputtered film by electroless Ni plating and Au plating (step S5). Thereafter, a gate pad (not shown), a passivation film (not shown), and a drain electrode 17 are formed by a general method. The portion of the source electrode pad 16 exposed in the opening of the passivation film becomes the source pad. Thereafter, the semiconductor wafer is diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 70 of FIG. 1.

[0049] It is also possible to suppress the growth of etch pits by weakening the pretreatment such as zincate treatment, but this is not preferable because it weakens the adhesion between the plating film 20 and the Al-Si film 16. On the other hand, in the embodiment, it is possible to suppress the growth of etch pits without weakening the adhesion.

[0050] As described above, according to the embodiment, the Al-Si film is formed while maintaining the wafer temperature between 350°C and 480°C during the sputtering process, and the area of ​​the Al-Si film on the film formation surface where the Al orientation is (111) is 99% or more. This suppresses the generation of abnormal etch pits during pre-plating treatment and prevents the etch pits from joining together in the Al-Si film after plating. This improves the mechanical strength after chip assembly and ensures product reliability.

[0051] As described above, the present disclosure can be modified in various ways without departing from the spirit of the present disclosure, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, etc. are variously set according to the required specifications, etc. Furthermore, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0052] INDUSTRIAL APPLICABILITY As described above, the semiconductor device and method for manufacturing a silicon carbide semiconductor device according to the present disclosure are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automotive igniters, and the like. [Explanation of symbols]

[0053] 1n + Silicon carbide substrate 2n - Type Drift Region 4 p + type subregion 4a upper p + type subregion 4b lower p + type subregion 5 p-type base region 6 p ++ Mold contact area 7n ++ Type Source Area 11 Gate insulating film 13 Gate electrode 14 Interlayer insulating film 15 Barrier Metal 16 Source electrode pad (Al-Si film) 17 Drain electrode 18 Source electrode 20, 120 plating film 25 Trench 26 pages + type area 31 SiC wafers 32 stages 33 Electrostatic Chuck 34 Target 35 Source Magnet 36 Covering 37 Wafer carrier ring 50 active area 70 Silicon carbide semiconductor device 116 Al-Si film 140 Etchpit

Claims

1. a semiconductor substrate of a first conductivity type; an element structure provided on the semiconductor substrate; a main electrode provided on the element structure; Equipped with the main electrode is an Al alloy film, A semiconductor device characterized in that the area of ​​the Al alloy film where the Al orientation is (111) is 99% or more.

2. 2. The semiconductor device according to claim 1, wherein the average grain size of the Al alloy film is 5.5 [mu]m or more and 10 [mu]m or less.

3. 3. The semiconductor device according to claim 1, wherein the Al alloy film is an Al film, an Al--Si ​​film, or an Al--Si--Cu film.

4. a first step of forming a device structure on a semiconductor substrate of a first conductivity type; a second step of forming a main electrode on the device structure; Including, In the second step, the main electrode is formed of an Al alloy film, the Al alloy film is formed by a sputtering method, and the wafer temperature during film formation is 350°C or higher and 480°C or lower.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the second step, the function of the electrostatic chuck is turned off when the film is formed by sputtering.

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