Method for measuring the internal capacitance of a transistor element

Abstract

A method and an evaluation circuit are disclosed.SOLUTION: The method comprises applying a voltage having a predetermined voltage level between a first load path node (11) and a second load path node (12) of the transistor device (1), measuring a voltage between the control node (13) and the second load path node (12) to obtain a voltage measurement, and determining at least one of a charge stored in the first internal capacitance (21) or a capacitance value (C21) of the internal capacitance (21) effective between the first load path node (11) and the control node (13) based on the first voltage measurement and based on a capacitance value of the second internal capacitance (31) effective between the control node (13) and the second load path node (12).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for measuring the internal capacitance of a transistor element. [Background technology]

[0002] Insulated-gate transistor devices, such as MOSFETs and IGBTs, necessarily have internal capacitance between a load path node and a control node. A first internal capacitance effective between the control node and a first load path node is typically referred to as gate-drain capacitance in MOSFETs and gate-collector capacitance in IGBTs. A second internal capacitance effective between the control node and a second load path node is typically referred to as gate-source capacitance in MOSFETs and gate-emitter capacitance in IGBTs. Insulated-gate transistor devices are typically driven by applying a voltage between the control node and the second load path node.

[0003] Both the first internal capacitance and the second internal capacitance define the switching characteristics of the transistor element. Furthermore, the first internal capacitance and the charge stored on the first internal capacitance when a constant voltage is applied between the first load path node and the second load path node are indicative of the parasitic turn-on tendency of the transistor element and the reliability of the gate dielectric in the off-state of the transistor element.

[0004] Therefore, there is a need to measure the internal capacitance of the transistor element, and in particular, to measure the first internal capacitance or the charge stored in the first internal capacitance when a particular voltage is applied between the first load path node and the second load path node. Summary of the Invention [Means for solving the problem]

[0005] One example relates to a method that includes applying a voltage having a predetermined voltage level between a first load path node and a second load path node of a transistor element, measuring a voltage between a control node of the transistor element and the second load path node to obtain a voltage measurement, and determining at least one of a charge stored on a first internal capacitance or a capacitance value of a first internal capacitance effective between the first load path node and the control node based on the first voltage measurement and based on a capacitance value of a second internal capacitance effective between the control node and the second load path node.

[0006] Another example relates to an evaluation circuit configured to perform the method.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to each other. Features of the various illustrated examples may be combined unless they are mutually exclusive. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 illustrates a transistor element including a first internal capacitance and a second internal capacitance, according to an example. [Figure 2] FIG. 10 illustrates a transistor element including a first internal capacitance and a second internal capacitance according to another example. [Figure 3] FIG. 1 illustrates an example of a method for determining charge stored on a first internal capacitance, the method including applying a voltage between a first load path node and a second load path node, and measuring a voltage between a control node and the second load path node. [Figure 4]FIG. 1 illustrates an example of a method for applying a voltage between a first load path node and a second load path node and measuring a voltage between a control node and the second load path node. [Figure 5] FIG. 10 illustrates an example of a method for determining a second internal capacitance. [Figure 6] 5 shows a variation of the method according to FIG. 4, which includes connecting an internal capacitance between the control node and the second load path node. [Figure 7] 4 shows an example of an evaluation circuit configured to carry out the method according to FIG. 3; [Figure 8] FIG. 2 is a diagram illustrating an example of an evaluation circuit in detail. [Figure 9] FIG. 2 is a diagram illustrating an example of an evaluation circuit including a first parasitic capacitance and a second parasitic capacitance. [Figure 10] 1 shows a schematic diagram of a semiconductor body incorporating a vertical transistor device; [Figure 11] FIG. 1 illustrates a wafer including a plurality of semiconductor bodies and an evaluation circuit coupled to a transistor element integrated in one of the semiconductor bodies for determining a first internal capacitance. [Figure 12] 11 shows a detailed view of one of the semiconductor bodies of the wafer according to FIG. 10. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] The examples described herein provide a method for determining the charge stored in the internal capacitance of a transistor element and / or for determining the capacitance value of the internal capacitance of a transistor element, which can be performed at the wafer level, i.e., measuring the charge stored in the internal capacitance of multiple transistor elements located on the same wafer before the wafer is separated into individual transistor elements.

[0011] While specific examples have been illustrated and described herein, those skilled in the art will recognize that various alternative and / or equivalent implementations can be substituted for the specific examples illustrated and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Accordingly, it is intended that the present invention be limited only by the claims and equivalents thereof.

[0012] It should be noted that the methods and devices, including preferred embodiments thereof, outlined herein may be used alone or in combination with other methods and devices disclosed herein. Furthermore, features outlined in the context of a device are also applicable to the corresponding method, and vice versa. Furthermore, all aspects of the methods and devices outlined herein may be combined in any manner. In particular, the features of the claims may be combined with each other in any manner.

[0013] It should be noted that the description and drawings merely illustrate the principles of the proposed method and system. Those skilled in the art will be able to implement various configurations, not explicitly described or shown herein, which embody the principles of the present invention and fall within its spirit and scope. Moreover, all examples and embodiments outlined herein are expressly intended to be solely for illustrative purposes, primarily to aid the reader in understanding the principles of the proposed method and system. Furthermore, all statements herein providing principles, aspects, and embodiments of the present invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

[0014] Referring to the above, one example disclosed herein relates to a method for determining the charge stored in the internal capacitance of a transistor element. An example of a transistor element including an internal capacitance is shown in Figures 1 and 2.

[0015] 1 and 2, each of the transistor elements includes a first load path node 11, a second load path node 12, a control node 13, a first internal capacitance 21, and a second internal capacitance 31. The first internal capacitance 21 is effective between the first load path node 11 and the control node 13, and the second internal capacitance 31 is effective between the second load path node 12 and the control node 13.

[0016] Each of the transistor elements shown in FIGS. 1 and 2 is a voltage-controlled transistor element that is in an on state or an off state depending on the voltage level of a control voltage (drive voltage) applied between a control node 13 and a second load path node 12. The transistor element is in an on state when the control voltage is higher than the threshold voltage of the transistor element, and is in an off state when the control voltage is lower than the threshold voltage of the transistor element. In the on state, the transistor element is configured to conduct current between the first load path node 11 and the second load path node 12. In the off state, the transistor element is configured to block voltage levels of the load path voltage applied between the first and second load path nodes 11, 12 that are lower than the voltage blocking capability of the transistor element. The voltage blocking capability defines the maximum voltage level of the load path voltage that the transistor element can withstand. The voltage blocking capability depends on the specific implementation of the transistor element and may be in the range of, for example, tens of volts to several kilovolts.

[0017] 1, the transistor element may be implemented as a MOSFET. In a MOSFET, the control node 13 is typically referred to as the gate node, the first load path node 11 is typically referred to as the drain node, and the second load path node is typically referred to as the source node. Thus, the first internal capacitance 21 is typically referred to as the gate-drain capacitance, the second internal capacitance 31 is typically referred to as the gate-source capacitance, and the control voltage is typically referred to as the gate-source voltage.

[0018] The transistor elements in Figure 1 are represented by their circuit symbols. The circuit symbol shown in Figure 1 represents an N-type enhancement MOSFET. However, this is only an example; everything described below applies equally to P-type enhancement MOSFETs.

[0019] 2, the transistor element may be implemented as an IGBT. In an IGBT, the control node 13 is typically referred to as the gate node, the first load path node 11 is typically referred to as the collector node, and the second load path node is typically referred to as the emitter node. Thus, the first internal capacitance 21 is typically referred to as the gate-collector capacitance, the second internal capacitance 31 is typically referred to as the gate-emitter capacitance, and the control voltage is typically referred to as the gate-emitter voltage.

[0020] The first and second internal capacitances 21 and 31 are the internal capacitances of the respective transistor elements. However, for ease of understanding the method described below, in Figures 1 and 2, the first and second internal capacitances 21 and 31 are represented by capacitors shown in addition to the circuit symbols of the respective transistor elements.

[0021] In particular, the first internal capacitance 21 can significantly affect the electrical behavior of a transistor device. Therefore, it is desirable to determine the first internal capacitance and / or the charge stored on the first internal capacitance when a particular load path voltage is applied between the first load path node 11 and the second load path node 12. An example of a method for determining the charge stored on the first internal capacitance when a particular load path voltage is applied between the first load path node 11 and the second load path node 12 is shown in FIG.

[0022] Referring to FIG. 3, the method includes the steps of applying (1001) a load path voltage having a predetermined voltage level between a first load path node 11 and a second load path node 12 of a transistor element 1, measuring (1002) a voltage between a control node 13 and the second load path node 12 to obtain a voltage measurement value, and determining (1003) a charge stored in the first internal capacitance 21 based on the voltage measurement value and based on the capacitance value of the second internal capacitance 31.

[0023] 2 relies on the fact that first internal capacitance 21 and second internal capacitance 31 form a capacitive voltage divider between first load path node 11 and second load path node 12. Thus, when a particular load path voltage is applied between first load path node 11 and second load path node 12, the charge Q21 stored in first internal capacitance 21 is equal to the charge Q31 stored in second internal capacitance 31.

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[0024] Hereinafter, the charge Q21 stored in the first internal capacitance 21 will be referred to as a first charge, and the charge Q31 stored in the second internal capacitance 31 will be referred to as a second charge.

[0025] The second charge 31 is the capacitance value C31 of the second internal capacitance 31 multiplied by the voltage V31 across the second internal capacitor 31.

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[0026] Therefore, by applying a load path voltage between the first load path node 11 and the second load path node 12 so that the first internal capacitance 21 and the second internal capacitance 31 are charged, and measuring the resulting voltage V31 across the second internal capacitance 31, the charge stored in the first internal capacitance 21 can be obtained using equation (2).

[0027] To determine the charge stored in the first internal capacitance using equation (2), it is necessary to know the capacitance value C31 of the second internal capacitance 31. An example of a method for determining the capacitance value C31 of the second internal capacitance 31 will be further described below.

[0028] Figure 4 shows a schematic diagram of one example for carrying out the method according to Figure 3. It should be noted that in Figure 4 and the following figures, only the first and second internal capacitances 21, 31 of the transistor element are shown. The transistor element is according to any of the examples described herein before.

[0029] 4, the method includes applying a load path voltage having a predetermined first voltage level V1 between a first load path node 11 and a second load path node 12, and measuring a voltage level V31 of a voltage across a second internal capacitance 31. Applying the load path voltage may include using a voltage source V41 connected to the load path nodes 11, 12. Measuring the voltage across the second internal capacitance 31 may include using a voltage sensor V42 connected between the control node 13 and the second load path node 12. Because the voltage source V41 is a DC voltage source, the load path voltage applied to the load path of the transistor element is a DC voltage.

[0030] According to one example, based on the determined charge Q21 stored in the first internal capacitance 21, a capacitance value C21 of the first internal capacitance 21 is determined using a difference between the voltage level of the load path voltage V1 and the measured voltage V31 across the second internal capacitance 31 as follows:

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[0031] There may be some time between when a voltage having a first voltage level V1 is applied to the load path and when the first and second internal capacitances 21, 31 are charged to such an extent that the voltages across them settle to their final values, which depends on the voltage (voltage level V1) applied across the load path. This time is due to the unavoidable resistance of the charging path between the voltage source V41 and the capacitance series circuits 21, 31. Essentially, for a given capacitance value of the capacitances 21, 31, the higher the resistance, the longer it takes for the capacitance series circuits 21, 31 to finally charge. This time may range, for example, from a few milliseconds to a few seconds.

[0032] It goes without saying that the voltage across the second internal capacitance 31 is measured when the voltages across the first and second capacitances 21, 31 have settled to their final values. The same applies to the measurement process for applying a voltage to a capacitor or capacitor series circuit, described below. In both cases, the applied voltages are DC voltages, and the measurement of the voltage across the capacitor or capacitor series circuit is performed after the voltage across the capacitor or capacitor series circuit has settled to its final value. In other words, the voltage measurement is performed when the measurement setup and the device under test are in a steady state, i.e., when neither the voltage level V1 nor the voltage across the capacitance is changing. It can also be said that the dV / dt across the capacitance is essentially zero when the measurement is performed. This is in contrast to dynamic measurements, where measurements are performed while the voltage is increasing or decreasing, i.e., measurements where the dV / dt is non-zero.

[0033] The voltage level V1 of the load path voltage applied in the process of determining the charge stored in the first internal capacitance is lower than the breakdown voltage of the transistor element. In one example, the voltage level V1 is selected in the range of 20% to 90%, particularly 50% to 80%, of the breakdown voltage of the transistor element. The voltage blocking capability depends on the specific type of transistor element and can be from a few tens of volts to several kilovolts, for example, 40 V to 10 kV.

[0034] Referring to equation (2), determining the charge Q31 stored in the second internal capacitance 31 includes using a predetermined capacitance value C31 of the second internal capacitance 31. Determining the capacitance value C31 of the second internal capacitance C31 may include charging the second internal capacitance 31 with a predetermined charge ΔQ31 and measuring a voltage difference ΔV31 resulting from charging the second internal capacitance 31 with the predetermined charge ΔQ31. The capacitance value C31 is then given by the quotient of the charge ΔQ31 and the voltage difference ΔV31,

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[0035] If the second internal capacitance 31 is discharged by a certain charge amount ΔQ31, then equation (4) also applies. In this case, the charge stored in the second internal capacitance 31 decreases by a certain amount ΔQ31, and the voltage decreases by ΔV31.

[0036] According to one example, the step of charging the second internal capacitance 31 with a predetermined charge ΔQ31 includes sending a current having a predetermined current level I31 to the second internal capacitance 31 for a predetermined period of time Δt, so that the predetermined charge ΔQ31 is given by the current level I31 multiplied by the time period Δt.

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[0037] 5 schematically illustrates an example of a method for determining the capacitance value C31 of the second internal capacitance 31 according to the aforementioned example. Referring to FIG. 5, a current having a current level I31 for charging the second internal capacitance 31 is provided by a current source 42 connected between the control node 13 and the second load path node 12. A voltage difference ΔV31 resulting from the charging of the second internal capacitance 31 can be measured using the same voltage sensor 42 used to measure the voltage V31 across the second internal capacitance 31 in the method illustrated in FIG. 4.

[0038] Referring to the above, during normal operation, the transistor element may be switched on when a drive voltage (control voltage) greater than the threshold voltage is applied between the control node 13 and the second load path node 12. Furthermore, if it is desired to keep the transistor element in an off state during normal operation, a drive voltage less than the threshold voltage is applied between the control node 13 and the second load path node 12.

[0039] According to one example, in the above-described method for determining the charge Q21 stored on the first internal capacitance 21, the load path voltage V1 applied between the first load path node 11 and the second load path node 12 is selected so that the resulting voltage V31 between the control node 13 and the second load path node 12 is lower than the threshold voltage of the transistor element, preventing the transistor element from switching on. Because the ratio of the capacitance values ​​C21, C31 of the first and second internal capacitances 21, 31 is at least approximately known before the measurement process, the voltage level V1 of the load path voltage applied during the measurement process can be appropriately adapted based on this capacitance value ratio to prevent the voltage level of the control voltage V31 from reaching the threshold voltage.

[0040] Typically, the capacitance value of the second internal capacitance 31 of the transistor element is much larger than the capacitance value of the first internal capacitance 21. Therefore, depending on the capacitance division ratio of the capacitance divider formed by the first and second internal capacitances 21, 31, when the load path voltage V1 is applied between the first and second load path nodes 51, 52, the voltage V31 between the control node 13 and the second load path node 52 is typically much lower than the voltage between the first load path node 51 and the control node 13. According to one example, the transistor element is implemented such that the capacitance value of the first internal capacitance 21 is less than 10%, or even less than 1%, of the capacitance value of the second internal capacitance 31.

[0041] According to an example shown in FIG. 6 , a capacitor 33 is connected in parallel with the second internal capacitance 31 when determining the charge Q21 stored on the first internal capacitance 21. This capacitor 33 is also referred to hereinafter as an additional capacitor or an external capacitor. Connecting the additional capacitor 33 in parallel with the second internal capacitance 31 increases the overall capacitance between the control node 13 and the second load path node 12, thereby reducing the voltage V31 between the control node 13 and the second load path node 12 at a given voltage level V1 of the load path voltage compared to a scenario in which only the second internal capacitance 31 is present between the control node 13 and the second load path node 12. This can help increase the safety margin between the voltage level V31 of the control voltage and the threshold voltage when a particular voltage level V1 of the load path voltage is applied, or can allow for an increase in the voltage level V1 of the load path voltage at a given safety margin.

[0042] According to one example, the further capacitor 33 connected in parallel with the second internal capacitance 31 is selected such that the overall capacitance C3 between the control node 13 and the second load path node 12 is given by the capacitance value of the second internal capacitance 32 plus the capacitance of the further capacitor 33;

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[0043] In the method shown in FIG. 6, the charge stored in the first internal capacitance C21 is given by the charge stored in the parallel circuit including the second internal capacitance 31 and the capacitor 3;

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[0044] According to one example, the method described above is performed by an evaluation circuit (evaluation device) 5 connected to the first and second load path nodes 11 , 12 and the control node 13 .

[0045] 7 shows a schematic block diagram of an evaluation circuit 5 configured to perform the above-described method for determining the charge stored on the first internal capacitance 21. Referring to FIG. 7, the evaluation circuit 5 includes three terminals (also called pins): a first terminal 51 connected to the first load path node 11, a second terminal 52 connected to the second load path node 12, and a third terminal 53 connected to the control node 13. A more detailed example of the evaluation circuit 5 is shown in FIG. 8.

[0046] 8, the evaluation circuit 5 includes a control circuit 8 configured to control the operation of the evaluation circuit 5. In particular, the control circuit 8 is configured to receive measurement signals from a voltage sensor of the evaluation circuit 5 and to control voltage and current sources of the evaluation circuit 5, as will be described in more detail below.

[0047] In the example shown in FIG. 8 , evaluation circuit 5 includes a controllable voltage source 41 connected between first terminal 51 and second terminal 52, and thus between first load path node 11 and second load path node 12 of the transistor element. Voltage source 41 can be activated and deactivated by a control signal S41 received from control circuit 8. When activated, voltage source 41 applies a load path voltage having a predetermined voltage level V1 between first and second terminals 51, 52 and first and second load path nodes 11, 12. When deactivated, voltage source 41 provides a high electrical resistance between first and second terminals 51, 52, so that the presence of voltage source 41 does not affect the charge states of first and second internal capacitances 21, 31.

[0048] 8, evaluation circuit 5 further includes a voltage sensor 71 connected between second terminal 52 and third terminal 53, and thus between control node 13 and second load path node 12. Voltage sensor 71 is configured to sense voltage V31 between control node 13 and second load path node 12 and provide control circuit 8 with a measurement value V31′ representative of the measured voltage V31.

[0049] Optionally, the evaluation circuit 5 further includes a further capacitor 33. The further capacitor 33 is connected between the third terminal 53 and the second terminal 52, and therefore between the control node 13 and the second load path node 12.

[0050] The evaluation circuit 5 may further include a first discharge switch 63 and a second discharge switch 64. The first discharge switch 63 is connected between the first and third terminals 51, 53, and thus between the first load path node 11 and the control node 13. The second discharge switch 64 is connected between the third terminal 53 and the second terminal 52, and thus between the control node 13 and the second load path node 12. The first and second discharge switches 63, 64 each receive a respective control signal S63, S64 from the control circuit 8 and are in an on or off state in response to the respective control signal S63, S64. When the first discharge switch 63 is in an on state, it discharges the first internal capacitance 21. Similarly, when the second discharge switch 64 is in an on state, it discharges the second internal capacitance 31.

[0051] According to one example, the first and second internal capacitances 21, 31 are discharged before the charge stored in the first internal capacitance 21 is determined. To this end, the control circuit 8 may be configured to turn on the first discharge switch 63 and the second discharge switch 64 to discharge the first internal capacitance 21 and the second internal capacitance 31 before the charge stored in the first internal capacitance 21 is determined. Determining the charge stored in the first internal capacitance 21 may include activating the voltage source 41 to apply a load path voltage having a voltage level V1 between the first load path node 11 and the second load path node 12, and measuring a voltage V31 between the control node 13 and the second load path node 12 using the voltage sensor 71. The capacitance value C31 of the second internal capacitance 31 is stored in the control circuit 8, and the control circuit is configured to determine the charge stored in the first internal capacitance 21 according to equation (2) based on the stored capacitance value C31 and the voltage measurement V31′ received from the voltage sensor 71.

[0052] If the evaluation circuit 5 includes a further capacitor 33, in addition to the capacitance value C31 of the first internal capacitance, the capacitance value C33 of the further capacitor 33 is stored in the control circuit 8, or the overall capacitance C3 (=C31+C33) is stored in the control circuit 8. In this example, the control circuit 8 is configured to calculate the charge stored in the first internal capacitor 21 according to equation (7) based on the stored capacitance value C31, C33 or C3 and the voltage measurement value V31′ received from the voltage sensor 71.

[0053] According to one example, the control circuit 8 is configured to display the result of determining the charge Q21 stored on the first internal capacitance 21 on a display element (not shown) or to communicate the result to another entity, such as another controller, via a suitable communication interface (not shown).

[0054] Referring to the above, a capacitance value C21 of the first internal capacitance 21 can be determined based on the determined charge Q21 stored in the first internal capacitance 21. According to one example, the control circuit 8 is configured to determine the capacitance value C21, for example, according to equation (3). In this example, the control circuit 8 is configured to receive, in addition to the measurement V31' representing the voltage V31 between the control node 13 and the second load path node 12, a further voltage measurement V1' representing the voltage level V1 of the load path voltage applied between the first load path node 11 and the second load path node 12, and to calculate the capacitance value C21 based on the determined charge Q21 and the further voltage measurement V1'. This further voltage measurement V1' is provided, for example, by another voltage sensor 72 connected between the first and second load path nodes 11, 12.

[0055] According to one example, the evaluation circuit 5 is further configured to determine a capacitance value C31 of the second internal capacitance 31. To this end, the evaluation circuit 5 includes a controllable current source 42 connected between the third terminal 53 and the second terminal 52 of the evaluation circuit 5, and thus between the control node 13 of the transistor element 1 and the second load path node 12. The current source 42 is configured to receive a control signal S42 from the control circuit 8 and is configured to be activated or deactivated based on the control signal S42. In an activated state, the current source 42 supplies a current having a predetermined current level I31 different from zero. In a deactivated state, the current source 42 does not supply any current (equivalent to supplying a current of current level 0).

[0056] To determine the capacitance value C31 of the second internal capacitance 31, the control circuit 8 is configured to activate the current source 42 for a predetermined period of time Δt so that the second internal capacitance 31 is charged with a predetermined amount of charge ΔQ31. Furthermore, the control circuit 8 is configured to determine a voltage difference ΔV31 in the voltage V31 between the control node 13 and the second load path node 12 before and after charging the second internal capacitance 31 based on the voltage measurement V31' received from the first voltage sensor 71. Furthermore, the control circuit 8 is configured to determine the capacitance value C31 of the second internal capacitance 31 according to equation (4) based on the predetermined amount of charge ΔQ31 and the voltage difference ΔV31.

[0057] 9, the evaluation circuit 5 may include a first parasitic capacitance 22 between the first terminal 51 and the third terminal 53, and a second parasitic capacitance 32 between the third terminal 53 and the second terminal 52. In the example shown in FIG. 9, such parasitic capacitances are shown as capacitors connected between the respective terminals. The remainder of the evaluation circuit is not shown in detail in FIG. 9. The parasitic capacitances 22, 32 of the evaluation circuit 5 may distort the results of determining the charge Q21 stored in the first internal capacitance 21 and may distort the results of determining the capacitance value C31 of the second internal capacitance 31.

[0058] According to one example, before the transistor element is connected to the evaluation circuit 5 and the charge Q21 stored in the first internal capacitance 21 is determined, (a) the charge Q22 stored in the first parasitic capacitance 22 is determined, and (b) in an open-loop process in which the transistor element is not connected to the first, second and third terminals 51, 52, 53 of the evaluation circuit 5, the capacitance value C30 of the capacitance between the third terminal 53 and the second terminal 52 of the evaluation circuit 5 is determined. The capacitance value C30 of the capacitance between the third terminal 53 and the second terminal 52 of the evaluation circuit 5 is given by the capacitance value C32 of the second parasitic capacitance 32 when the evaluation circuit lacks the further capacitance 33,

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[0059] In an open-loop process, the capacitance value C30 of the overall capacitance between the third terminal 53 and the second terminal 52 can be determined in the same manner as described with reference to equations (4) and (5) above, i.e., based on charging / discharging the capacitance between the first terminal 52 and the second terminal 53 with a predetermined charge and measuring the voltage increase / decrease that occurs as a result of the charging process.

[0060] In an open-loop measurement process, a voltage V2 is applied between the first terminal 51 and the second terminal 52 of the evaluation circuit 5 to determine the charge Q22 stored in the first parasitic capacitance 22. According to one example, the voltage level of this voltage V2 is essentially equal to the voltage level of the voltage V1 applied between the first terminal 51 and the second terminal 52 in a transistor measurement process, i.e., when the transistor element is connected to the evaluation circuit 5 and the charge stored in the first internal capacitance 21 of the transistor element is measured. According to one example, "at least approximately equal" includes that the voltage level of the voltage V2 applied in the open-loop measurement process is within a range of 75% to 125% of the voltage level of the voltage V1 applied to the transistor element in the measurement process.

[0061] Determining the charge Q22 stored in the first internal capacitance 22 includes measuring the voltage V32 between the second and third terminals 52, 53 of the evaluation circuit 5. The charge Q22 stored in the first internal capacitance 22 depends on the voltage level of the voltage V32 between the second terminal 52 and the third terminal 53,

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[0062] In the transistor measurement process, i.e., when the transistor element is connected to the evaluation circuit 5, the overall charge Q2 stored by the overall capacitance C2 between the first terminal 51 and the third terminal 53 is determined. This includes the steps of applying a load path voltage V1 between the first terminal 51 and the second terminal 52 of the evaluation circuit 5 (between the first load path node 11 and the second load path node 12 of the transistor element), measuring the voltage V31 between the third terminal 53 and the second terminal 52 (and between the control node 13 and the second load path node 12 of the transistor element), and determining the overall charge Q2 depending on the measured voltage V31 and the capacitance value C3 of the overall capacitance between the third terminal 53 and the second terminal 52.

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[0063] As mentioned above, since the first internal capacitance 21 is usually much lower than the second external capacitance 31, during the transistor measurement process, the voltage V31 between the control node 13 and the second load path node 12 is much lower than the voltage across the first internal capacitance 21 and may be less than 1% of the load path voltage. According to one example, in the evaluation circuit 5 according to FIG. 9 , the capacitance value C22 of the first parasitic capacitance 22 between the first terminal 51 and the third terminal 53 is much lower than the capacitance value C30 of the capacitance between the third terminal 53 and the second terminal 52 of the evaluation circuit 5. As a result, the capacitance division ratio of the capacitance voltage divider including the first internal capacitance 21 and the second internal capacitance 31 in the transistor element is essentially equal to the capacitance division ratio of the capacitance voltage divider including the first parasitic capacitance 22 and the second parasitic capacitance 32 of the evaluation circuit 5 and the optional further capacitor 33. In this case, if the voltage level of the voltage V2 applied between the first terminal 51 and the second terminal 52 in the open-loop process is approximately equal to the voltage level of the voltage V1 applied between the first terminal 51 and the second terminal 52 in the transistor measurement process, the voltages between the first load terminal 51 and the third load terminal 53 in the open-loop process and the transistor measurement process are approximately equal or at least of similar magnitude. In this case, in the transistor measurement process, the charge Q21 stored in the first internal capacitance is approximately given by the following equation:

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[0064] If the voltages between the first terminal 51 and the third terminal 53 in the open-loop process and the transistor measurement process are not approximately equal, the method includes determining the capacitance value C21 of the first internal capacitance 21 based on the capacitance value C22 of the first parasitic capacitance 22 when the transistor element is connected to the evaluation circuit 5 and the capacitance value C2 of the overall capacitance between the third terminal 53 and the second terminal 52.

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[0065] According to an example, a capacitance value C22 of the first parasitic capacitance 22 is determined based on the determined charge Q22 in the open-loop process and the voltage between the first terminal 51 and the third terminal 53 in the open-loop process;

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[0066] According to one example, in the transistor measurement process, the charge Q21 stored in the first internal capacitance 21 is determined based on the determined capacitance C21 and the voltage between the first and third terminals 51, 53.

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[0067] According to an example shown in FIG. 10 , the transistor element is a vertical transistor element. In this case, first and second load path electrodes 91, 92 of transistor element 1 are positioned above opposing surfaces 101, 102 of semiconductor body 100 in which active device regions of transistor element 1 (such as source, body, and drain regions of a MOSFET) are integrated. Transistor element 1 is represented by a circuit symbol in FIG. 10 . For illustrative purposes only, the circuit symbol in FIG. 10 represents a MOSFET. However, this is merely an example. The transistor element may be implemented according to any of the examples described above. The active device regions of transistor element 1 may be integrated into semiconductor body 100 in a conventional manner. Since integrating active device regions of transistor elements into semiconductor bodies is commonly known, no further explanation in this regard is necessary.

[0068] 10, a first load path electrode 91 is formed over a first surface 101 of a semiconductor body 100, and a second load path electrode 92 is formed over a second surface 102 of the semiconductor body 100. The first load path electrode 91 is connected to or forms the first load path node 11 of the transistor element, and the second load path electrode 92 is connected to or forms the second load path node 12 of the transistor element. In a MOSFET, for example, the first load path electrode 91 is the source electrode and the second load path electrode 92 is the drain electrode.

[0069] 10, the transistor element further includes a control electrode 93. The control electrode 93 is connected to or forms the control node 13 of the transistor element. The control electrode 93 is formed over one of the first and second surfaces 101, 102. According to one example shown in FIG. 10, the control electrode 91 is formed on the same surface as the first load path electrode 91, which is the first surface 101 in the example shown in FIG. 10.

[0070] In a transistor device of the type shown in FIG. 10, a load path voltage V1 for determining the charge Q21 stored in the first internal capacitance 21 is applied between first and second load path electrodes 91, 92 formed above opposing first and second surfaces 101, 102.

[0071] It is generally known that multiple transistor elements can be formed based on the same semiconductor wafer that is ultimately divided to form multiple elements. According to one example, the method described herein above for determining the charge Q21 stored in the first internal capacitance 21 of a transistor element is performed at the wafer level. That is, the method is performed while the multiple transistor elements are still part of a common wafer. This is described below with reference to FIGS. 11 and 12.

[0072] 11 schematically illustrates a wafer 200 including a plurality of semiconductor bodies 100, each having an active device region of a vertical transistor device integrated therein. According to one example, each of the semiconductor bodies 100 is formed by a respective portion of a continuous monocrystalline semiconductor layer of the wafer 200. Referring to FIG. 11 , kerf regions 110 are disposed between the semiconductor bodies 100 on the wafer 200. At the end of the manufacturing process, the wafer 200 is separated along the kerf regions 110, which are at least partially removed when the wafer 200 is separated.

[0073] The semiconductor body 100 is shown only schematically in Figure 11. For example, the control and load path electrodes of the transistor elements are not shown. In addition, Figure 11 schematically shows an evaluation circuit (evaluation equipment) 5 configured to determine the charge stored in each of the transistor elements when respective voltages are applied between the first and second load path nodes of the respective transistor elements.

[0074] 12 schematically illustrates a portion of a wafer 200 including a semiconductor body 100 having integrated thereon the active region of a transistor element 1, with a second load path electrode 92 and a control electrode 93 above a first surface 101, and a first load path electrode 91 above a second surface 102 opposite the first surface. According to one example, the first load path electrodes 91 of the transistor elements 1 formed on the same wafer 200 are continuous electrodes that are separated upon separation of the wafer 200 to form the first load path electrodes 91 of the individual transistor elements 1.

[0075] With reference to the above, the evaluation circuit (evaluation device) 5 comprises first, second and third terminals for connection to the first load path electrode 91, the second load path electrode 92 and the control electrode 93. In the example shown in Figures 11 and 12, the first terminal 51 is formed by a conductive carrier on which the wafer 200 is placed such that the first load path electrodes 91 of the individual transistor elements 1 are in contact with the carrier. The conductive carrier forming the first terminal 51 of the evaluation circuit 5 may also be referred to as a chuck.

[0076] The wafer 200 may be held in place on the carrier in a variety of ways. According to one example, the carrier includes through-holes (not shown) and is connected to a vacuum pump (not shown). The vacuum pump is configured to create a vacuum between the wafer 200 and the carrier through the through-holes to hold the wafer 200 in place on the carrier.

[0077] 11 and 12, the second and third terminals 52, 53 are implemented as probes (needles). The needle-like second terminal 52 is configured to make electrical contact with the second load path electrode 92 of the transistor element 1, and the needle-like third terminal 53 is configured to make electrical contact with the control electrode 93 of the respective transistor element 1 to measure the charge stored in the first internal capacitance 21, as described hereinabove.

[0078] According to one example, multiple transistor elements 1 formed on wafer 200 are successively measured, i.e., at each point in time, load path voltage V1 is applied between first and second load path nodes 11, 12 of only one of the transistor elements 1 formed on wafer 200.

[0079] According to one example, the evaluation circuit 5 has a plurality of second terminals 52 and a plurality of third terminals 53. In this example, the control electrodes 93 of a plurality of transistor elements 1 can be simultaneously connected to respective third terminals 53, and the second load path electrodes 91 of a plurality of transistor elements can be simultaneously connected to respective second terminals 52. Nevertheless, individual transistor elements 1 of the plurality of transistor elements having their control electrodes 93 and second load path electrodes 92 simultaneously connected to the third and second terminals 53, 52 of the evaluation circuit 5 are successively measured.

[0080] It should be noted that the present method is not limited to use with vertical transistor elements. The present method may also be used to determine the charge stored on the first internal capacitance in horizontal transistor elements, where the control node and the first and second load path nodes are accessible on the same side of the semiconductor body containing the transistor element. To test a horizontal transistor element, the first terminal may be implemented as a needle instead of a plate.

[0081] Some aspects of the transistor devices and methods described above are briefly summarized below.

[0082] One example relates to a method that includes applying a voltage having a predetermined voltage level between a first load path node and a second load path node of a transistor element; measuring a voltage between a control node and the second load path node to obtain a voltage measurement; and determining at least one of a charge stored on a first internal capacitance or a capacitance value of a first internal capacitance effective between the first load path node and the control node based on the first voltage measurement and based on a capacitance value of a second internal capacitance effective between the control node and the second load path node.

[0083] According to an example, the method further includes determining a capacitance value of a second internal capacitance, which may include charging the second internal capacitance in a charging process, and determining the capacitance value of the second internal capacitance based on the charge provided to the second internal capacitance in the charging process and based on a change in voltage between the control node and the second load path node in the charging process.

[0084] According to one example, the method further includes connecting an external capacitance between the control node and the second load path node when applying a voltage having a predetermined voltage level between the first load path node and the second load path node, and determining a charge stored in the first internal capacitance further based on a capacitance value of the external capacitance.

[0085] According to one example, the transistor device is integrated in a semiconductor body, the semiconductor body being one of a plurality of semiconductor bodies in a wafer.

[0086] The transistor element is an insulated gate transistor element, such as a MOSFET or an IGBT.

[0087] According to one example, applying a voltage having a predetermined voltage level between a first load path node and a second load path node and measuring a voltage between the control node and the second load path node includes using an evaluation circuit. The evaluation circuit can include a first terminal configured to be coupled to the first load path node, a second terminal configured to be coupled to the second load path node, and a third terminal configured to be coupled to the control node. The evaluation circuit can further include a first parasitic capacitance between the first terminal and the third terminal and a second parasitic capacitance between the third terminal and the second terminal, and determining the charge stored on the first internal capacitance can further include determining a capacitance value based on capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance.

[0088] According to one example, the predetermined voltage level of the voltage applied between the first load path node and the second load path node is selected such that the voltage between the control node and the second load path node resulting from the voltage applied between the first load path node and the second load path node is less than the threshold voltage of the transistor element.

[0089] According to one example, the polarity of the voltage applied between the first load path node and the second load path node is such that the internal diode of the transistor element between the first load path node and the second load path node is reverse biased.

[0090] According to one example, the method further includes determining a capacitance value of the first internal capacitance based on the determined charge stored in the first internal capacitance and a difference between a voltage level of the load path voltage and a voltage level of a measured voltage between the control node and the second load path node.

[0091] According to another example, the method described above is used to determine at least one of a charge stored in a first internal capacitance of each of a plurality of transistor elements integrated on a wafer or a capacitance value of the first internal capacitance. According to one example, the method includes continuously determining at least one of a charge stored in the first internal capacitance or a capacitance value of each of the plurality of transistor elements.

[0092] Yet another example relates to an evaluation circuit including a first terminal configured to be coupled to a first load path node of a transistor element, a second terminal configured to be coupled to a second load path node of the transistor element, and a third terminal configured to be coupled to a control node of the transistor element. The evaluation circuit is configured to determine a capacitance value of a first internal capacitance of the transistor element according to the method described above. According to one example, the evaluation circuit further includes an external capacitance between the third terminal and the second terminal. According to one example, each of the first terminal and the third terminal includes a contact needle, and the second terminal includes a contact plate or contact needle.

Claims

1. applying a voltage having a predetermined voltage level between a first load path node (11) and a second load path node (12) of the transistor element (1); measuring a voltage between a control node (13) and the second load path node (12) to obtain a voltage measurement; determining, based on the voltage measurements and based on a capacitance value of a second internal capacitance (31) effective between the control node (13) and the second load path node (12), at least one of a charge stored in a first internal capacitance (21) or a capacitance value (C21) of the first internal capacitance (21) effective between the first load path node (11) and the control node (13); A method comprising:

2. The method further comprises determining the capacitance value of the second internal capacitance (31). The method of claim 1.

3. The step of determining the capacitance value of the second internal capacitance (31) comprises: charging the second internal capacitance (31) in a charging process; determining the capacitance value of the second internal capacitance (31) based on the charge provided to the second internal capacitance (31) during the charging process and based on a change in voltage between the control node (13) and the second load path node (12) during the charging process; Including, The method of claim 2.

4. The method comprises: connecting an external capacitance (33) between the control node (13) and the second load path node (12) when applying the voltage having the predetermined voltage level between the first load path node (11) and the second load path node (12); determining the charge stored on the first internal capacitance (21) further based on a capacitance value of the external capacitance; further comprising:

4. The method according to any one of claims 1 to 3.

5. The transistor element (1) is integrated in a semiconductor body (100), the semiconductor body (100) is one of a plurality of semiconductor bodies of a wafer (200); 5. The method according to any one of claims 1 to 4.

6. The transistor element (1) is an insulated gate transistor element.

6. The method according to any one of claims 1 to 5.

7. The transistor element (1) is a MOSFET or an IGBT. The method of claim 6.

8. applying the voltage having the predetermined voltage level between the first load path node (11) and the second load path node (12) and measuring the voltage between the control node (13) and the second load path node (12) includes using an evaluation circuit (5); The evaluation circuit (5) comprises a first terminal (51) configured to be coupled to the first load path node (11), a second terminal (52) configured to be coupled to the second load path node (12), and a third terminal (53) configured to be coupled to the control node (13).

8. The method according to any one of claims 1 to 7.

9. the evaluation circuit (5) includes a first parasitic capacitance (22) between the first terminal (51) and the third terminal (53), and a second parasitic capacitance (32) between the third terminal (53) and the second terminal (52); The step of determining the charge stored in the first internal capacitance (21) further includes a step of determining the capacitance value based on capacitance values ​​of the first parasitic capacitance (22) and the second parasitic capacitance (32). The method of claim 8.

10. the predetermined voltage level of the voltage applied between the first load path node (11) and the second load path node (12) is selected such that a voltage between the control node (13) and the second load path node (12) resulting from the voltage applied between the first load path node (11) and the second load path node (12) is less than a threshold voltage of the transistor element; 10. The method according to any one of claims 1 to 9.

11. the polarity of the voltage applied between the first load path node (11) and the second load path node (12) is such that an internal diode of the transistor element between the first load path node (11) and the second load path node (12) is reverse biased; 11. The method according to any one of claims 1 to 10.

12. The method comprises: the determined charge (Q21) stored on the first internal capacitance (21); a difference between the voltage level of the load path voltage and the voltage level of the measured voltage between the control node (13) and the second load path node (12); Further comprising determining a capacitance value (C21) of the first internal capacitance (21) based on 12. The method according to any one of claims 1 to 11.

13. 1. A method comprising:

13. The method according to claim 1, further comprising determining at least one of a charge stored in a first internal capacitance (21) of each of a plurality of transistor elements integrated on a wafer (200) or a capacitance value (C21) of the first internal capacitance (21), method.

14. determining at least one of the charge stored in the first internal capacitance (21) or the capacitance value of each of the plurality of transistor elements (1) includes continuously determining at least one of the charge or the capacitance value of the plurality of transistor elements (1); The method of claim 13.

15. a first terminal (51) configured to be coupled to a first load path node (11) of the transistor element (1); a second terminal (52) configured to be coupled to a second load path node (12) of the transistor element (1); a third terminal (53) configured to be coupled to a control node (13) of said transistor element (1); an element configured to determine the capacitance value of a first internal capacitance (21) of the transistor element (1) according to a method according to any one of claims 1 to 12; An evaluation circuit comprising:

16. The evaluation circuit further comprises an external capacitance (33) between the third terminal (53) and the second terminal (52).

16. The evaluation circuit of claim 15.

17. The first terminal (51) and the third terminal (53) each include a contact needle; The second terminal (52) includes a contact plate or a contact needle.

17. An evaluation circuit according to claim 15 or 16.

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