Back contact solar cell, fabrication method and cell assembly

Abstract

To provide a back contact solar cell having a high open circuit voltage and high photoelectric conversion efficiency by reducing interface defects and carrier recombination in a heterojunction region of a backlight surface, and to provide a manufacturing method and a cell assembly.SOLUTION: The backlight side includes first polarity regions A and second polarity regions B that are alternately arranged along a first direction D1, the light-receiving side is a textured side, surfaces of the first polarity regions A and the second polarity regions B are polished sides, and the first polarity structure is disposed in the first polarity region A; The first polarity structure includes a first functional layer 2 and a first electrode structure that are stacked in a direction away from the semiconductor substrate 1, the second polarity structure is arranged in the second polarity region B, and the second polarity structure includes a second functional layer 5 and a second electrode structure that are stacked in the direction away from the semiconductor substrate 1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application is in the field of crystalline silicon solar cells, and in particular relates to back contact solar cells, manufacturing methods and cell assemblies. [Background technology]

[0002] As PERC (Passivated Emitter and Rear Cell) cell technology matures and continues to expand, it is gradually approaching the theoretical limit of its conversion efficiency, and the industry is looking for next-generation technologies. Currently, the mainstream technologies being promoted include TOPCon (Tunnel Oxide Passivated Contact) cells, HJT (Heterojunction) cells, and IBC (Interdigitated back contact, interdigital back contact) batteries. Summary of the Invention [Problem to be solved by the invention]

[0003] Unlike conventional double-sided electrode contact batteries, the biggest feature of back-contact (BC) batteries is that the metal electrode is located on the back surface of the battery, and the metal electrode on the front surface is not shielded, improving light utilization, resulting in higher short-circuit current and conversion efficiency. Among all types of BC technologies, HBC (Hybrid Back Contact) technology has the highest photoelectric conversion efficiency. By adopting hybrid technology, passivation contact technology is applied to the back of the cell to form HBC batteries. Currently, the photoelectric conversion efficiency of HBC batteries still has room for improvement, so how to improve the photoelectric conversion efficiency of HBC batteries is a technical issue that must be resolved as soon as possible. [Means for solving the problem]

[0004] The present application aims to solve at least one of the technical problems existing in the prior art, and therefore proposes a back-contact solar cell, a manufacturing method, and a cell assembly that reduce interface defects and carrier recombination in the heterojunction region of the backlight surface, have high open-circuit voltage and photoelectric conversion efficiency, and have a simplified process suitable for large-scale production.

[0005] According to a first aspect, the present application provides: a semiconductor substrate, a first polarity region, and a second polarity region; the semiconductor substrate has a light-receiving surface and a backlight surface facing each other, the backlight surface including first polarity regions and second polarity regions alternately arranged along a first direction, the light-receiving surface being a textured surface, and the surfaces of the first polarity regions and the second polarity regions being polished surfaces; a first polarity structure is disposed in the first polarity region, the first polarity structure includes a first functional layer and a first electrode structure stacked along a direction away from the semiconductor substrate, the first functional layer includes a first passivation layer and a first impurity semiconductor layer stacked along a direction away from the semiconductor substrate, and one side surface of the first passivation layer facing the semiconductor substrate is a polished surface; a second polarity structure is disposed in the second polarity region, the second polarity structure includes a second functional layer and a second electrode structure stacked along a direction away from the semiconductor substrate, the second functional layer includes a second passivation layer and a second impurity semiconductor layer stacked along a direction away from the semiconductor substrate, and one side surface of the second passivation layer facing the semiconductor substrate is a polished surface; The doping type of the first impurity semiconductor layer is the same as the doping type of the second impurity semiconductor layer. propose the opposite, back-contact solar cells.

[0006] According to the back-contact solar cell of the present application, a passivation contact technology is combined with the back of the semiconductor substrate to form a hybrid back-contact cell, and the backlight surface of the semiconductor substrate is made into a polished surface, thereby reducing interface defects and carrier recombination in the heterojunction region of the backlight surface, and allowing the solar cell to have a high open circuit voltage and photoelectric conversion efficiency.

[0007] According to one embodiment of the present application, the second functional layer extends at least partially to the first polarity region, and a first orthogonal projection of the first functional layer onto the semiconductor substrate at least partially overlaps a second orthogonal projection of the second functional layer onto the semiconductor substrate, There is direct contact between the first functional layer and the second functional layer, or An insulating layer is provided between the first functional layer and the second functional layer, and the material of the insulating layer includes at least one of phosphosilicon glass or borosilicon glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0008] According to one embodiment of the present application, an opening is provided between adjacent first and second electrode structures, and a third orthogonal projection of the opening onto the semiconductor substrate is located within an overlapping region of the first and second orthogonal projections.

[0009] According to one embodiment of the present application, the electrode structure includes a conductive layer located on one side of the impurity semiconductor layer away from the passivation layer, and an electrode located on one side of the conductive layer away from the impurity semiconductor layer; The material of the conductive layer includes at least one of zinc oxide, indium oxide, and tin oxide, and the conductive layer is doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum, and the thickness of the conductive layer is in the range of 10 nm to 150 nm.

[0010] According to one embodiment of the present application, the semiconductor substrate further includes a substrate impurity layer, the substrate impurity layer is located in the first polarity region and is formed on one side adjacent to the first passivation layer, and the doping type of the substrate impurity layer is the same as the doping type of the first impurity semiconductor layer; The thickness range of the substrate impurity layer is 5 nm to 200 nm.

[0011] According to an embodiment of the present application, the distance between the surface of the first polarity region and the light-receiving surface is greater than the distance between the surface of the second polarity region and the light-receiving surface.

[0012] According to one embodiment of the present application, the first passivation layer comprises a tunnel oxide, and the thickness range of the first passivation layer is 0.5 nm to 2.5 nm; the first impurity semiconductor layer comprises doped polycrystalline silicon, and the thickness range of the first impurity semiconductor layer is 10 nm to 250 nm; the second passivation layer comprises intrinsic amorphous silicon, and the thickness range of the second passivation layer is 1 nm to 15 nm; and the second impurity semiconductor layer comprises doped amorphous silicon and / or microcrystalline silicon, and the thickness range of the second impurity semiconductor layer is 1 nm to 60 nm.

[0013] According to one embodiment of the present application, the back contact solar cell further includes a third functional layer and an anti-reflection layer located on the light-receiving surface of the semiconductor substrate and stacked along a direction away from the semiconductor substrate, wherein the third functional layer includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the anti-reflection layer includes at least one of silicon oxide, silicon nitride, and aluminum oxide. , silicon oxynitride, aluminum oxide, and transparent conductive oxide.

[0014] According to a second aspect, the present application provides: providing a semiconductor substrate having opposing light receiving and backlight surfaces, the backlight surface including first polarity regions and second polarity regions arranged alternately along a first direction; treating a surface of the semiconductor substrate to form a textured surface on the light receiving surface and polished surfaces on the surfaces of the first polarity region and the second polarity region; forming polar structures in the first polar region and the second polar region, respectively; The polar structure of the first polarity region includes a first functional layer and a first electrode structure stacked in a direction away from the semiconductor substrate, the first functional layer including a first passivation layer and a first impurity semiconductor layer stacked in a direction away from the semiconductor substrate, one surface of the first passivation layer facing the semiconductor substrate being a polished surface; the polar structure of the second polarity region includes a second functional layer and a second electrode structure stacked in a direction away from the semiconductor substrate, the second functional layer including a second passivation layer and a second impurity semiconductor layer stacked in a direction away from the semiconductor substrate, one surface of the second passivation layer facing the semiconductor substrate being a polished surface; and the doping type of the first impurity semiconductor layer is opposite to the doping type of the second impurity semiconductor layer.

[0015] According to the manufacturing method of the back-contact solar cell proposed in the present application, a passivation contact technology is combined with the back of the semiconductor substrate to form a hybrid back-contact cell, and the backlight surface of the semiconductor substrate is made polished, thereby reducing interface defects and carrier recombination in the heterojunction region of the backlight surface, thereby providing the solar cell with a high open-circuit voltage and photoelectric conversion efficiency. Furthermore, the manufacturing method proposed in the present application has a simpler flow than the conventional process for hybrid back-contact cells, making it advantageous for large-scale production.

[0016] According to one embodiment of the present application, the step of treating the surface of the semiconductor substrate comprises: texturing a light receiving surface and a backlight surface of a semiconductor substrate; forming a mask on a light-receiving surface of a semiconductor substrate; polishing the backlight surface of the semiconductor substrate; and removing the mask.

[0017] According to one embodiment of the present application, the remaining thickness of the mask after the step of polishing the backlight surface of the semiconductor substrate is in the range of 10 nm to 100 nm, and the material of the mask includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0018] According to one embodiment of the present application, before the step of treating the surface of the semiconductor substrate, The method further includes the step of performing a gettering process on the semiconductor substrate.

[0019] According to one embodiment of the present application, the step of performing a gettering process on a semiconductor substrate includes: removing the damaged layer of the semiconductor substrate by wet etching; gettering the semiconductor substrate by high temperature phosphorus diffusion; and removing the gettering layer formed in the gettering process of the semiconductor substrate by wet etching.

[0020] According to one embodiment of the present invention, a polar structure is formed in each of the first polar region and the second polar region. The steps are: forming a first functional layer on a backlight surface of a semiconductor substrate; Etching a first region of the semiconductor substrate corresponding to a second polarity region to remove the first functional layer and a first thickness of the semiconductor substrate in the first region; forming a second functional layer covering the first functional layer on the backlight surface of the semiconductor substrate; Etching a second region in the first polarity region of the semiconductor substrate to remove the second functional layer and the second thickness of the first functional layer in the second region; forming a conductive layer covering the first functional layer and the second functional layer on the backlight surface of the semiconductor substrate; a step of opening each of the overlapping regions of the first functional layer and the second functional layer so as to cut at least the conductive layer and expose at most the first functional layer; forming electrodes in the first region and the second region, each in contact with the conductive layer;

[0021] According to one embodiment of the present application, a wet chemical etching solution is used to remove a first functional layer and a first thickness of a semiconductor substrate in a first region, and the wet chemical etching solution includes an alkaline polishing solution.

[0022] According to one embodiment of the present application, after the step of forming a second functional layer on the backlight surface of the semiconductor substrate, The method further includes sequentially forming a third functional layer and an anti-reflection layer on the light-receiving surface of the semiconductor substrate.

[0023] According to a third aspect, the present application proposes a cell assembly comprising a back contact solar cell as described above or a back contact solar cell manufactured by the manufacturing method as described above.

[0024] The battery assembly of the present application has a high open circuit voltage and a high photoelectric conversion efficiency. Additional aspects and advantages of the present application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present application.

[0025] The above and / or additional aspects and advantages of the present specification will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a schematic diagram showing a cross-sectional structure of a back contact solar cell according to an embodiment of the present application. [Figure 2] 2 is a schematic diagram showing a cross-sectional structure of a back contact solar cell according to an embodiment of the present application. [Figure 3] 1 is a flow chart of a method for manufacturing a back contact solar cell according to an embodiment of the present application. [Figure 4] 1 is a schematic diagram 1 showing a cross-sectional structure at one stage in a manufacturing method according to an embodiment of the present application. [Figure 5] FIG. 2 is a schematic diagram 2 showing a cross-sectional structure at one stage in the manufacturing method according to the embodiment of the present application. [Figure 6] 3 is a schematic diagram 3 showing a cross-sectional structure at one stage in the manufacturing method according to the embodiment of the present application. FIG. [Figure 7] 4 is a schematic diagram 4 showing a cross-sectional structure at one stage in the manufacturing method according to the embodiment of the present application. FIG. [Figure 8] 5 is a schematic diagram 5 showing a cross-sectional structure at one stage in the manufacturing method according to the embodiment of the present application. [Figure 9] 6 is a schematic diagram 6 showing a cross-sectional structure at one stage in the manufacturing method according to the embodiment of the present application. [Figure 10] 7 is a schematic diagram 7 showing a cross-sectional structure at one stage in the manufacturing method according to the embodiment of the present application. [Figure 11] 8 is a schematic diagram showing a cross-sectional structure at one stage in a manufacturing method according to an embodiment of the present application. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions and relative dimensions of layers, regions, and components may be exaggerated for clarity. Herein, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are used only to interpret the present application and should not be understood as limitations of the present application.

[0028] When a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another component or layer, it should be understood that the component or layer may be directly on, adjacent to, connected to, or coupled to the other component or layer, or may be present in an intermediate component or layer. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to," it is not present in an intermediate component or layer. Various components, members, regions, layers, and / or portions may be described using terms such as first, second, third, etc., but these components, members, regions, layers, and / or portions should not be limited by these terms. It should be understood that these terms are used only to distinguish one component, member, region, layer, or portion from another component, member, region, layer, or portion. Accordingly, without departing from the teachings of this disclosure, a first component, member, region, layer, or portion described below may be referred to as a second component, member, region, layer, or portion. On the other hand, when a second component, member, region, layer or section is described, the present disclosure does not necessarily imply that the first component, member, region, layer or section is also present.

[0029] In the description herein, references such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with this embodiment or example are included in at least one embodiment or example of the present application. General references to such terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0030] In related art, HBC battery structures typically have a polished rear TOPCon region and textured rear heterojunction regions and front surfaces, which simplifies the process flow. However, the textured surface has a larger interface area than the polished surface, and the interface defects and carrier recombination on the textured surface are more severe than on the polished surface, resulting in suboptimal passivation of the rear heterojunction region and impacting battery efficiency. Furthermore, the current HBC battery process flow is still relatively complex, making it unsuitable for large-scale production.

[0031] This application proposes a back-contact solar cell, a manufacturing method and a cell assembly, which combines passivation contact technology on the back of a semiconductor substrate to form a hybrid back-contact cell, and fabricates the backlight surface of the semiconductor substrate as a polished surface, thereby reducing interface defects and carrier recombination in the heterojunction region of the backlight surface, and thus the solar cell has a high open circuit voltage and photoelectric conversion efficiency. Compared with the conventional hybrid back-contact battery process, the flow is simplified, making it favorable for large-scale production.

[0032] Please refer to Figure 1, which shows the cross-sectional structure of a back contact solar cell. In one embodiment of the present application, a back contact solar cell is proposed.

[0033] In this embodiment, the back contact solar cell includes a semiconductor substrate 1, a first polarity region, and a second polarity region. The semiconductor substrate 1 has an opposing light receiving surface and a backlight surface. The backlight surface includes first polarity regions A and second polarity regions B alternately arranged along a first direction D1. The light receiving surface is a textured surface, and the surfaces of the first polarity regions A and the second polarity regions B are polished surfaces. A first polarity structure is disposed on the first polarity region A. The first polarity structure includes a first functional layer 2 and a first electrode structure stacked along a direction away from the semiconductor substrate 1. The first functional layer 2 includes a first passivation layer 2-1 stacked along a direction away from the semiconductor substrate 1. and a first impurity semiconductor layer 2-2, one surface of the first passivation layer 2-1 facing the semiconductor substrate 1 is a polished surface, a second polarity structure is disposed in a second polarity region B, the second polarity structure includes a second functional layer 5 and a second electrode structure stacked in a direction away from the semiconductor substrate 1, the second functional layer 5 includes a second passivation layer 5-1 and a second impurity semiconductor layer 5-2 stacked in a direction away from the semiconductor substrate 1, one surface of the second passivation layer 5-1 facing the semiconductor substrate 1 is a polished surface, and the doping type of the first impurity semiconductor layer 2-2 is opposite to the doping type of the second impurity semiconductor layer 5-2.

[0034] In some embodiments, the semiconductor substrate 1 may comprise materials such as monocrystalline silicon, germanium, or gallium arsenide. The doping type of the semiconductor substrate 1 may be N-type doping or P-type doping.

[0035] 1, a first polarity region A and a second polarity region B are disposed adjacent to each other in a first direction D1. A first opening G1 for forming the second polarity region B is formed in the backlight surface of the semiconductor substrate 1. The surface of the first polarity region A is designated as a first surface S1, the surface of the second polarity region B as a second surface S2, and the light-receiving surface of the semiconductor substrate 1 as a third surface S3.

[0036] In some embodiments, the distance between the first surface S1 and the third surface S3 of the first polarity region A is greater than the distance between the second surface S2 and the third surface S3 of the second polarity region B. This ensures that the existing film layer of the first polarity region A is reliably removed when forming the first opening G1.

[0037] The first surface S1 and the second surface S2 have a polished surface structure. For example, the first surface S1 and the second surface S2 may have a polished surface shape that has been polished. Here, the polishing treatment can be performed using a conventional alkaline polishing solution.

[0038] Since the backlight surface of the semiconductor substrate 1 is manufactured as a polished surface, the interface area between the backlight surface of the semiconductor substrate 1 and the polar structure is reduced, thereby reducing interface defects and carrier recombination in the heterojunction region of the backlight surface, and improving the open circuit voltage and photoelectric conversion efficiency of the back contact solar cell.

[0039] The third surface S3 has a textured surface structure, for example, a pyramidal textured surface shape and / or a corrosion pit textured surface shape.

[0040] In some embodiments, the semiconductor substrate 1 further comprises a substrate impurity layer 3. The substrate impurity layer 3 is located in the first polarity region A and is formed on one side adjacent to the first passivation layer 2-1. The doping type of the substrate impurity layer 3 is The doping type is the same as that of the first impurity semiconductor layer 2-2.

[0041] The surface of one side of the substrate impurity layer 3 adjacent to the first passivation layer 2-1 is This is a polished surface. The substrate impurity layer 3 is formed by doping a portion of the semiconductor substrate 1. For example, a P-type substrate impurity layer 3 is formed by doping particles such as boron into the portion of the semiconductor substrate 1 within the first polarity region A, or an N-type substrate impurity layer 3 is formed by doping particles such as arsenic or phosphorus.

[0042] In some embodiments, the thickness range of the substrate impurity layer 3 is 5 nm to 200 nm. For example, the thickness of the substrate impurity layer 3 can be 5 nm, 50 nm, 100 nm, or 200 nm.

[0043] In some embodiments, the material of the first passivation layer 2-1 includes a tunnel oxide. The thickness of the first passivation layer 2-1 is in the range of 0.5 nm to 2.5 nm. For example, the thickness of the first passivation layer 2-1 can be 0.5 nm, 1.5 nm, or 2.5 nm, etc. This provides a good passivation effect for the first surface S1 while ensuring the tunneling effect of majority carriers.

[0044] The surface of one side of the first passivation layer 2-1 adjacent to the semiconductor substrate 1 is also This allows the first passivation layer 2-1 and the semiconductor substrate 1, the interface area between the first passivation layer 2-1 and the semiconductor substrate 1 is reduced. The recombination probability of carriers at the interface with rate 1 is low.

[0045] In some embodiments, the material of the first impurity semiconductor layer 2-2 is doped polycrystalline silicon. The thickness of the first impurity semiconductor layer 2-2 is in the range of 10 nm to 250 nm. For example, the thickness of the first impurity semiconductor layer 2-2 may be 10 nm, 50 nm, 150 nm, or can be 250 nm, etc. This provides better field passivation effect, thinner film thickness, and reduced parasitic absorption.

[0046] The doping type of the first impurity semiconductor layer 2-2 is the same as that of the semiconductor substrate 1. For example, the semiconductor substrate 1 may be of N-type doping type, and the first impurity semiconductor layer 2-2 may be of N-type doping type; It may be P-type doped.

[0047] In some embodiments, the second passivation layer 5-1 comprises intrinsic amorphous silicon; The thickness of the second passivation layer 5-1 is in the range of 1 nm to 15 nm. The thickness of the insulation layer 5-1 can be 1 nm, 10 nm, or 15 nm, etc. This provides a better passivation effect for the second surface S2.

[0048] The surface of one side of the second passivation layer 5-1 adjacent to the semiconductor substrate 1 is also This allows the second passivation layer 5-1 and the semiconductor substrate 1, the interface area between the second passivation layer 5-1 and the semiconductor substrate 1 is reduced. The recombination probability of carriers at the interface with rate 1 is low.

[0049] In some embodiments, the second impurity semiconductor layer 5-2 is doped amorphous silicon and and / or microcrystalline silicon, and the thickness range of the second impurity semiconductor layer 5-2 is 1 nm to 60 nm. For example, the thickness of the second impurity semiconductor layer 5-2 is 1 nm, 30 nm, or 60 nm. m, etc. This provides a better field passivation effect, a thinner film thickness, and reduced parasitic absorption.

[0050] The doping type of the second impurity semiconductor layer 5-2 is opposite to that of the first impurity semiconductor layer 2-2. For example, if the first impurity semiconductor layer 2-2 is N-type doped, The second impurity semiconductor layer 5-2 can be doped with P-type impurity.

[0051] In some embodiments, the second functional layer 5 extends at least partially to the first polar region A, and a first orthogonal projection of the first functional layer 2 onto the semiconductor substrate 1 at least partially overlaps with a second orthogonal projection of the second functional layer 5 onto the semiconductor substrate 1.

[0052] In the first direction D1, the second passivation layer 5-1 and the second impurity semiconductor layer 5-2 both extend to the first polarity regions A on both sides and partially overlap the first passivation layer 2-1 and the first impurity semiconductor layer 2-2 located in the first polarity regions A on both sides, respectively, and the orthogonal projection of this overlapping portion onto the semiconductor substrate 1 is located within the first polarity region A. As a result, there are overlapping portions on both sides of the first polarity region A in the first direction D1.

[0053] As shown in FIG. 1, an insulating layer 4 is provided between the first functional layer 2 and the second functional layer 5. In the overlapping portion between the first functional layer 2 and the second functional layer 5, a second passivation layer 5-1 An insulating layer 4 is provided between the first impurity semiconductor layer 2-2 and the first impurity semiconductor layer 2-3. Here, the material of the insulating layer 4 includes at least one of phosphosilicon glass, borosilicon glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0054] Referring to Figure 2, Figure 2 shows another cross-sectional structure of a back contact solar cell. In some alternative embodiments, there is direct contact between the first functional layer 2 and the second functional layer 5.

[0055] 2, the second passivation layer 5-1 and the first impurity semiconductor layer 2-2 are in direct contact with each other at the overlapping portion between the first functional layer 2 and the second functional layer 5. This improves the passivation quality at the interface between the first polarity region A and the second polarity region B.

[0056] In some embodiments, the electrode structure includes a conductive layer 8 located on one side of the doped semiconductor layer away from the passivation layer, and an electrode located on one side of the conductive layer away from the doped semiconductor layer.

[0057] The first electrode structure can have a P polarity and the second electrode structure can have an N polarity, or the first electrode structure can have an N polarity and the second electrode structure can have a P polarity, depending on the doping type of the functional layer it contacts.

[0058] The first electrode structure includes a first conductive layer 8-1 and a first electrode 9. A second opening G2 is formed on one side of the first impurity semiconductor layer 2-2 away from the first passivation layer 2-1, and the first conductive layer 8-1 covers the second opening G2 and extends toward both sides of the second opening G2 along the first direction D1. The first electrode 9 is located on one side of the first conductive layer 8-1 away from the first impurity semiconductor layer 2-2.

[0059] Between the portion of the first conductive layer 8-1 extending from the second opening G2 and the first functional layer 2, The second functional layer 5 may be interposed. That is, the first conductive layer 8-1 and the first impurity semiconductor layer Between the first and second impurity semiconductor layers 5-1 and 5-2, or between the first and second impurity semiconductor layers 5-1 and 5-2, an insulating layer 4, a second passivation layer 5-1 and a second impurity semiconductor layer 5-2 are interposed. There are.

[0060] The second electrode structure includes a second conductive layer 8-2 and a second electrode 10. The second conductive layer 8-2 is formed on one side of the second impurity semiconductor layer 5-2 away from the second passivation layer 5-1 and covers the second polarity region B. The second electrode 10 is located on one side of the second conductive layer 8-2 away from the second impurity semiconductor layer 5-2.

[0061] In the first direction D1, both sides of the second conductive layer 8-2 are at least The orthogonal projection of the second conductive layer 8-2 onto the semiconductor substrate 1 may extend at least partially. At least partially overlaps the orthogonal projection of the second functional layer 5 onto the semiconductor substrate 1. Between the second conductive layer 8-2 and the first impurity semiconductor layer 2-2, there is an insulating layer 4, a second passivation layer 5-1 and a second impurity semiconductor layer 5-2, or a second passivation layer 5-1 and a second impurity semiconductor layer 5-2 is interposed.

[0062] In some embodiments, the first conductive layer 8-1 and the second conductive layer 8-2 include a transparent conductive oxide. For example, the material of the first conductive layer 8-1 and the second conductive layer 8-2 includes at least one of zinc oxide, indium oxide, and tin oxide. The material of the first electrode 9 and the second electrode 10 can be a metal material such as silver or copper.

[0063] In some embodiments, the first conductive layer 8-1 and the second conductive layer 8-2 may be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum.

[0064] In some embodiments, the first conductive layer 8-1 and the second conductive layer 8-2 have the same thickness, and the thickness ranges from 10 nm to 150 nm. For example, the thickness of the conductive layer 8 can be 10 nm, 50 nm, 150 nm, etc.

[0065] In some embodiments, a third opening G3 is provided between adjacent first and second electrode structures, and a third orthogonal projection of the third opening G3 onto the semiconductor substrate 1 is located within an overlapping region of the first and second orthogonal projections. The first and second electrode structures are separated by the third opening G3 to avoid short circuits.

[0066] The third opening G3 is located between each of the first opening G1 and the second opening G2. The third opening G3 at least separates the first conductive layer 8-1 and the second conductive layer 8-2, exposing at most the first functional layer 2. As shown in FIG. 1 or 2, the third opening G3 separates the first conductive layer 8-1 and the second conductive layer 8-2. The second conductive layer 8-2 is separated from the second passivation layer 5-1 and the second impurity semiconductor layer 5-2, and the second passivation layer 5-1 and the second impurity semiconductor layer 5-2 are cut to expose the insulating layer 4 or the first impurity semiconductor layer 2-2.

[0067] In some embodiments, the back contact solar cell further includes a third functional layer 6 and an anti-reflective layer 7 located on the light-receiving surface of the semiconductor substrate 1. The third functional layer 6 contacts the light-receiving surface of the semiconductor substrate 1, and the anti-reflective layer 7 is located on one side of the third functional layer 6 away from the semiconductor substrate 1 and is in contact with the third functional layer 6. The light-receiving surface of the semiconductor substrate 1 is a textured surface, and the surface of the third functional layer 6 on one side facing the semiconductor substrate 1 is also a textured surface.

[0068] The third functional layer 6 includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The anti-reflection layer 7 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide.

[0069] Referring to Figure 3, Figure 3 shows the manufacturing flow of a back contact solar cell. One embodiment of the present application also proposes a manufacturing method for a back contact solar cell.

[0070] In this embodiment, the method for manufacturing a back contact solar cell includes: Step 10: providing a semiconductor substrate 1 having a light-receiving surface and a backlight surface opposite to each other, the backlight surface including first polarity regions A and second polarity regions B alternately arranged along a first direction; a step 20 of treating the surface of the semiconductor substrate 1 to form a textured surface on the light receiving surface and polished surfaces on the surfaces of the first polarity region A and the second polarity region B; and forming 30 polar structures in the first polar region A and the second polar region B, respectively.

[0071] In this embodiment, the structure of the back contact solar cell manufactured by the manufacturing method can refer to the above examples. The polar structure of the first polarity region A includes a first functional layer 2 and a first electrode structure stacked in a direction away from the semiconductor substrate 1, the first functional layer 2 includes a first passivation layer 2-1 and a first impurity semiconductor layer 2-2 stacked in a direction away from the semiconductor substrate 1, one surface of the first passivation layer 2-1 facing the semiconductor substrate 1 is a polished surface, and a second polarity structure is disposed in the second polarity region B. The polarity structure of the second polarity region B includes a second functional layer 5 and a second electrode structure stacked along a direction away from the semiconductor substrate 1, the second functional layer 5 includes a second passivation layer 5-1 and a second impurity semiconductor layer 5-2 stacked along a direction away from the semiconductor substrate 1, one side surface of the second passivation layer 5-1 facing the semiconductor substrate 1 is a polished surface, and the doping type of the first impurity semiconductor layer 2-2 is opposite to the doping type of the second impurity semiconductor layer 5-2.

[0072] In step 10, the semiconductor substrate 1 can include materials such as single crystal silicon, germanium, or gallium arsenide, etc. The doping type of the semiconductor substrate 1 can be N-type doping or P-type doping.

[0073] In this embodiment, the light-receiving surface and the backlight surface of the semiconductor substrate 1 are first shaped to have a textured surface structure such as a pyramidal texture and / or a corrosion pit texture, and the backlight surface is polished to have a polished light surface, and then each film layer structure is formed on the semiconductor substrate 1 to form a hybrid back-contact solar cell. This simplifies the manufacturing process and is advantageous for large-scale production.

[0074] As an example, in step 20, the specific flow of processing the surface of the semiconductor substrate 1 is to first texturize the light-receiving surface and the backlight surface of the semiconductor substrate 1, then form a mask M1 on the light-receiving surface of the semiconductor substrate 1, then polish the backlight surface of the semiconductor substrate 1, and finally remove the mask M1.

[0075] The semiconductor substrate 1 is immersed in a texture-forming solution to texture both the light-receiving surface and the backlight surface, and then a mask M1 is fabricated on the light-receiving surface to protect the textured surface shape of the light-receiving surface in a subsequent polishing process. The material of the mask M1 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0076] The semiconductor substrate 1 on which the mask M1 has been manufactured is immersed in an alkaline polishing solution, and the backlight surface of the semiconductor substrate 1 is polished to form a polished surface shape on the backlight surface. Among these, the mask M1 ensures that a certain thickness remains after polishing the backlight surface of the semiconductor substrate 1, thereby ensuring the textured surface shape of the light-receiving surface of the semiconductor substrate 1. The remaining thickness can be in the range of 10 nm to 100 nm, for example, 10 nm, 50 nm, or 100 nm.

[0077] In some embodiments, the step of removing the mask M1 may be performed in a subsequent step of fabricating the polar structure, i.e., step 30 may begin after polishing the backlight surface of the semiconductor substrate 1.

[0078] In some embodiments, the method may further include a step of performing a gettering process on the semiconductor substrate 1 before processing the surface of the semiconductor substrate 1. By performing a gettering process on the semiconductor substrate 1, the content of impurity elements in the semiconductor substrate 1 can be reduced, and thus carrier recombination can be reduced.

[0079] For example, the step of performing the gettering treatment on the semiconductor substrate 1 may include the steps of first removing a damaged layer on the semiconductor substrate 1 by wet etching, then performing the gettering treatment on the semiconductor substrate 1 by high-temperature phosphorus diffusion, and again removing the gettering layer formed by the gettering treatment on the semiconductor substrate 1 by wet etching, thereby effectively reducing the content of impurity elements inside the semiconductor substrate 1.

[0080] In some embodiments, the step of forming a polar structure in each of the first polarity region A and the second polarity region B can include the steps of forming a first functional layer 2 on the backlight surface of the semiconductor substrate 1, etching a first region corresponding to the second polarity region B of the semiconductor substrate 1 to remove the first functional layer 2 and the semiconductor substrate 1 of a first thickness in the first region, forming a second functional layer 5 covering the first functional layer 2 on the backlight surface of the semiconductor substrate 1, etching a second region in the first polarity region A of the semiconductor substrate 1 to remove the second functional layer 5 and the first functional layer 2 of a second thickness in the second region, forming a conductive layer 8 covering the first functional layer 2 and the second functional layer 5 on the backlight surface of the semiconductor substrate 1, opening each of the overlapping regions of the first functional layer 2 and the second functional layer 5 by cutting at least the conductive layer 8 and exposing at most the first functional layer 2, and forming electrodes in contact with the conductive layer 8 in the first region and the second region, respectively.

[0081] One embodiment of a method for manufacturing a back contact solar cell according to the present application will now be described in detail with reference to Figures 4-11, which show cross-sectional structures of the cell at each step in the manufacturing flow.

[0082] As shown in Figure 4, Figure 4 shows the structure after surface treatment of the semiconductor substrate 1. In Figure 4, the light-receiving surface (i.e., the third surface S3) of the semiconductor substrate 1 is a textured surface, the backlight surface of the semiconductor substrate 1 is a polished surface, and the mask M1 remains on the light-receiving surface.

[0083] As shown in FIG. 5, a first functional layer 2 is formed on the backlight surface of a semiconductor substrate 1. The first passivation layer 2-1 and the first impurity semiconductor layer 2-2 are manufactured by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). The material of the first passivation layer 2-1 includes tunnel oxide and has a thickness of 0.5 nm to 2.5 nm. For example, the range is 0.5 nm, 1.5 nm, or 2.5 nm. The material of the semiconductor layer 2-2 includes doped polycrystalline silicon, and the thickness is 10 nm to 250 nm. The thickness of the first impurity semiconductor layer 2-2 is in the range of 10 nm, 50 nm, 150 nm, or 250 nm, for example. The method is to manufacture amorphous silicon / polycrystalline silicon and then perform high-temperature annealing to crystallize it, or to manufacture an intrinsic amorphous silicon / polycrystalline silicon layer and then perform high-temperature diffusion to dope and crystallize it.

[0084] In this embodiment, the first functional layer 2 is formed, and at the same time, the impurities in the first impurity semiconductor layer 2-2 are removed. The material element is introduced into the backlight of the semiconductor substrate 1 through the first passivation layer 2-1. The doping type of the substrate impurity layer 3 is the same as that of the first impurity semiconductor layer 2-2. The thickness of the tetra-doped impurity layer 3 ranges from 5 nm to 200 nm, for example, 5 nm, 50 nm, 100 nm, or 200 nm.

[0085] In this embodiment, after forming the first functional layer 2, an insulating layer 4 is fabricated on one side of the first functional layer 2 that faces away from the semiconductor substrate 1. The material of the insulating layer 4 includes at least one of phosphosilicon glass or borosilicon glass, silicon oxide, silicon nitride, and silicon oxynitride. The insulating layer 4 is used to protect the remaining portion of the first functional layer 2 when etching the portion of the first functional layer 2 corresponding to the second polarity region B.

[0086] As shown in Figure 6 or 7, a first region corresponding to the second polarity region B of the semiconductor substrate 1 is etched, and the first functional layer 2 and a first thickness of the semiconductor substrate 1 within the first region are removed. The area of ​​the first region is equal to the area of ​​the second polarity region B. Etching the first region forms a first opening G1, which exposes the second surface S2. The distance between the first surface S1 and the third surface S3 is greater than the distance between the second surface S2 and the third surface S3. Removing a certain thickness of the semiconductor substrate 1 ensures that no substrate impurity layer 3 remains.

[0087] For example, first, a portion of the insulating layer 4 can be removed by laser etching, ink printing, etc., and then, in the area where the insulating layer 4 is not present, the first impurity semiconductor layer 2-2, the first passivation layer 2-1, and the substrate impurity layer 3 can be removed by wet chemical etching. The wet chemical etching further includes synchronously removing the first functional layer 2 and the insulating layer 4, which are deposited on the front surface or wrapped around the front edge with a plating solution, to expose the mask M1, and then removing the mask M1.

[0088] As shown in Figure 6, by leaving the portion of the insulating layer 4 facing the first surface S1, insulation can be formed between the first functional layer 2 and the second functional layer 5 in a subsequent process. Alternatively, as shown in Figure 7, the portion of the insulating layer 4 facing the first surface S1 can be removed to improve passivation at the interface between the first polarity region A and the second polarity region B. The following manufacturing process will be based on the structure shown in Figure 6.

[0089] In some embodiments, the etching solution used in the wet chemical etching may include an alkaline polishing solution, which can remove the substrate impurity layer 3 and polish the second surface S2 to form a polished surface, thereby reducing surface defects.

[0090] As shown in FIG. 8, a second functional layer 5 covering the first functional layer 2 is formed on the backlight surface of the semiconductor substrate 1. A second passivation layer 5-1 and a second impurity semiconductor layer 5-2 are fabricated on the backlight surface of the semiconductor substrate 1 by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). The second passivation layer 5-1 contains intrinsic amorphous silicon and has a thickness ranging from 1 nm to 15 nm. For example, The second impurity semiconductor layer 5-2 is a dopant. The thickness range of the silicon layer is, for example, 1n. The thickness is between 1 nm and 60 nm, such as 10 nm, 30 nm or 60 nm. The doping type of the second impurity semiconductor layer 5-2 is opposite to the doping type of the first impurity semiconductor layer 2-2.

[0091] In some embodiments, after forming the second functional layer 5 on the backlight surface of the semiconductor substrate 1, the method may further include sequentially forming a third functional layer 6 and an anti-reflection layer 7 on the light-receiving surface of the semiconductor substrate 1. The third functional layer 6 and the anti-reflection layer 7 may be formed by LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition). The third functional layer 6 includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The anti-reflection layer 7 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide.

[0092] As shown in FIG. 9, the second region in the first polarity region A of the semiconductor substrate 1 is etched to remove the second functional layer 5 and the first functional layer 2 of the second thickness in the second region.

[0093] In this embodiment, the range of the second region is smaller than the range of the first polarity region A, and at least the second impurity semiconductor layer 5-2, the second passivation layer 5-1, and the second opening G2 of the insulating layer 4 in the second region are removed. The first impurity semiconductor layer 2-2 does not remain in the insulating layer 4 in the second region. In this way, a certain thickness can be removed. The second passivation layer 5-1 is removed by laser etching, and the insulating layer 4 and / or Alternatively, the laser oxide layer can be removed by wet chemical etching.

[0094] As shown in Figure 10, a conductive layer 8 covering the first functional layer 2 and the second functional layer 5 is formed on the backlight surface of the semiconductor substrate 1, and each of the overlapping areas between the first functional layer 2 and the second functional layer 5 is opened so as to cut at least the conductive layer 8 and expose at most the first functional layer 2.

[0095] The conductive layer 8 may be fabricated by physical vapor deposition (PVD) or chemical vapor deposition (CVD), including reactive plasma deposition (RPD), magnetron sputtering, pulsed laser deposition (PLD), vacuum evaporation, and atomic layer deposition (ALD). The conductive layer 8 may be made of at least one of zinc oxide, indium oxide, and tin oxide, which may be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum. The conductive layer 8 may have a thickness ranging from 10 nm to 150 nm, such as 10 nm, 50 nm, or 150 nm.

[0096] Each overlapping region of the first functional layer 2 and the second functional layer 5 is opened by laser etching, ink printing, and / or wet chemical etching to form a third opening G3. The third opening G3 cuts at least the conductive layer 8 and exposes at most the first impurity semiconductor layer 2-2. The conductive layer 8 is divided into a first conductive layer 8-1 and a second conductive layer 8-2 by the third opening G3, and in the first direction D1, the first conductive layer 8-1 is located above the second opening G2 and extends to both sides thereof, The second conductive layer 8-2 is located above the first opening G1 and extends to both sides.

[0097] 11, electrodes are formed in the first and second regions in contact with the conductive layer 8. The first electrode 9 is formed on one side of the conductive layer 8-1 that is away from the semiconductor substrate 1. The second electrode 10 is located on one side of the conductive layer 8-2 that is away from the semiconductor substrate 1. The manufacturing methods of the first electrode 9 and the second electrode 10 include screen printing silver paste, inkjet printing silver paste, electroplating, etc.

[0098] An embodiment of the present application also provides a battery assembly, which includes the back-contact solar cell described above or a back-contact solar cell fabricated according to the fabrication method described above. The specific structure and principle of the back-contact solar cell and the specific steps of the fabrication method can be found in the above-described embodiments, and a description of this embodiment will be omitted here.

[0099] The cell assembly of the present application has low recombination of carriers with interface defects in a back contact solar cell, and has high open circuit voltage and photoelectric conversion efficiency.

[0100] As used herein, the terms "comprise," "comprises," or any other variant thereof are intended to encompass a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements but also other elements not expressly listed or inherent in such process, method, article, or apparatus. Unless further limited, an element defined by the phrase "comprises" does not exclude the element from the process, method, article, or apparatus that includes it, but may also be present in other identical elements. It should also be noted that the scope of the methods and apparatuses of the present application is not limited to performing functions in the order shown or described, but can further include performing functions substantially simultaneously or in reverse order according to related functionality. For example, a described method can be performed in a different order than described, and various steps can be added, omitted, or combined. Furthermore, features described with reference to one example can be combined in other examples.

[0101] Although the embodiments of the present application have been shown and described above, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is limited only by the claims and their equivalents. [Explanation of symbols]

[0102] 1 semiconductor substrate, 2 first functional layer, 2-1 first passivation layer, 2-2 first impurity semiconductor layer, 3 substrate impurity layer, 4 insulating layer, 5 Second functional layer, 5-1 second passivation layer, 5-2 second impurity semiconductor layer, 6 third functional layer, 7 anti-reflection layer, 8 conductive layer, 8-1 first conductive layer, 8-2 second conductive layer, 9 first electrode, 10 second electrode, A first polarity region, B second polarity region, M1 mask, S1 first surface, S2 second surface, S3 third surface, G1 first opening, G2 second opening, G3 third opening.

Claims

1. a semiconductor substrate, a first polarity region, and a second polarity region; the semiconductor substrate has a light-receiving surface and a backlight surface facing each other, the backlight surface including first polarity regions and second polarity regions alternately arranged along a first direction, the light-receiving surface being a textured surface, and the surfaces of the first polarity regions and the second polarity regions being polished surfaces; the first polarity structure is disposed in the first polarity region, the first polarity structure includes a first functional layer and a first electrode structure stacked along a direction away from the semiconductor substrate, the first functional layer includes a first passivation layer and a first impurity semiconductor layer stacked along a direction away from the semiconductor substrate, and one side surface of the first passivation layer facing the semiconductor substrate is a polished surface; the second polarity structure is disposed in the second polarity region, the second polarity structure includes a second functional layer and a second electrode structure stacked along a direction away from the semiconductor substrate, the second functional layer includes a second passivation layer and a second impurity semiconductor layer stacked along a direction away from the semiconductor substrate, and one side surface of the second passivation layer facing the semiconductor substrate is a polished surface; The doping type of the first impurity semiconductor layer is opposite to the doping type of the second impurity semiconductor layer.

1. A back contact solar cell comprising:

2. the second functional layer extends at least partially to the first polar region, and a first orthogonal projection of the first functional layer onto the semiconductor substrate at least partially overlaps a second orthogonal projection of the second functional layer onto the semiconductor substrate; There is direct contact between the first functional layer and the second functional layer, or An insulating layer is provided between the first functional layer and the second functional layer, and the material of the insulating layer includes at least one of phosphorus silicon glass, borosilicon glass, silicon oxide, silicon nitride, and silicon oxynitride.

10. The back contact solar cell of claim 1.

3. An opening is provided between the first electrode structure and the second electrode structure adjacent to each other, and a third orthogonal projection of the opening onto the semiconductor substrate is located within an overlapping region of the first orthogonal projection and the second orthogonal projection.

3. The back contact solar cell of claim 2.

4. the electrode structure includes a conductive layer located on one side of the impurity semiconductor layer away from the passivation layer, and an electrode located on one side of the conductive layer away from the impurity semiconductor layer; The material of the conductive layer includes at least one of zinc oxide, indium oxide, and tin oxide, and the conductive layer is doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum, and the thickness of the conductive layer is in the range of 10 nm to 150 nm. A back contact solar cell according to any one of claims 1 to 3.

5. the semiconductor substrate further includes a substrate impurity layer, the substrate impurity layer being located in the first polarity region and formed on one side adjacent to the first passivation layer, and the doping type of the substrate impurity layer being the same as the doping type of the first impurity semiconductor layer; The thickness of the substrate impurity layer ranges from 5 nm to 200 nm. A back contact solar cell according to any one of claims 1 to 3.

6. The distance between the surface of the first polar region and the light-receiving surface is greater than the distance between the surface of the second polar region and the light-receiving surface.

6. The back contact solar cell of claim 5.

7. the first passivation layer includes a tunnel oxide, and the thickness of the first passivation layer ranges from 0.5 nm to 2.5 nm; the first impurity semiconductor layer includes doped polycrystalline silicon, and the thickness of the first impurity semiconductor layer ranges from 10 nm to 250 nm; the second passivation layer comprises intrinsic amorphous silicon, and the thickness of the second passivation layer ranges from 1 nm to 15 nm; The second impurity semiconductor layer includes doped amorphous silicon and / or microcrystalline silicon, and the thickness of the second impurity semiconductor layer ranges from 1 nm to 60 nm. A back contact solar cell according to any one of claims 1 to 3.

8. The back contact solar cell further includes a third functional layer and an anti-reflection layer located on the light-receiving surface of the semiconductor substrate and stacked along a direction away from the semiconductor substrate, wherein the third functional layer includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the anti-reflection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide. A back contact solar cell according to any one of claims 1 to 3.

9. providing a semiconductor substrate having opposing light-receiving and backlight surfaces, the backlight surface including first and second polarity regions alternately arranged along a first direction; treating a surface of the semiconductor substrate to form a textured surface on the light-receiving surface and polished surfaces on the surfaces of the first polarity region and the second polarity region; forming polar structures in the first polar region and the second polar region, respectively; The polar structure of the first polarity region includes a first functional layer and a first electrode structure stacked in a direction away from the semiconductor substrate, the first functional layer including a first passivation layer and a first impurity semiconductor layer stacked in a direction away from the semiconductor substrate, one side surface of the first passivation layer facing the semiconductor substrate being a polished surface, the polar structure of the second polarity region includes a second functional layer and a second electrode structure stacked in a direction away from the semiconductor substrate, the second functional layer including a second passivation layer and a second impurity semiconductor layer stacked in a direction away from the semiconductor substrate, one side surface of the second passivation layer facing the semiconductor substrate being a polished surface, and the doping type of the first impurity semiconductor layer is opposite to the doping type of the second impurity semiconductor layer.

10. A method for manufacturing a back contact solar cell comprising:

10. The step of treating the surface of the semiconductor substrate comprises: texturing the light receiving surface and the backlight surface of the semiconductor substrate; forming a mask on the light-receiving surface of the semiconductor substrate; polishing the backlight surface of the semiconductor substrate; removing the mask.

10. The method of claim 9, wherein the back contact solar cell is a polycrystalline silicon substrate.

11. The remaining thickness of the mask after polishing the backlight surface of the semiconductor substrate is in the range of 10 nm to 100 nm, and the material of the mask includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

11. The method of claim 10, wherein the back contact solar cell is formed of a silicon dioxide film.

12. before the step of treating the surface of the semiconductor substrate, and further comprising the step of performing a gettering process on the semiconductor substrate. A method for producing a back contact solar cell according to any one of claims 9 to 11.

13. The step of performing a gettering process on the semiconductor substrate includes: removing the damaged layer of the semiconductor substrate by wet etching; gettering the semiconductor substrate by high temperature phosphorus diffusion; and removing the gettering layer formed by the gettering process of the semiconductor substrate by wet etching.

13. The method of claim 12, wherein the back contact solar cell is formed of a silicon dioxide film.

14. The step of forming polar structures in the first polar region and the second polar region, respectively, includes: forming a first functional layer on the backlight surface of the semiconductor substrate; Etching a first region of the semiconductor substrate corresponding to the second polarity region to remove the first functional layer and a first thickness of the semiconductor substrate in the first region; forming a second functional layer covering the first functional layer on the backlight surface of the semiconductor substrate; Etching a second region in the first polarity region of the semiconductor substrate to remove the second functional layer and a second thickness of the first functional layer in the second region; forming a conductive layer covering the first functional layer and the second functional layer on the backlight surface of the semiconductor substrate; a step of opening each of the overlapping regions of the first functional layer and the second functional layer so as to cut at least the conductive layer and expose at most the first functional layer; forming electrodes in contact with the conductive layer in the first region and the second region, respectively. A method for producing a back contact solar cell according to any one of claims 9 to 11.

15. removing the first functional layer and a first thickness of the semiconductor substrate in the first region using a wet chemical etchant, the wet chemical etchant including an alkaline polishing chemistry; 15. The method of claim 14, wherein the back contact solar cell is formed of a silicon dioxide gas.

16. After forming a second functional layer on the backlight surface of the semiconductor substrate, The method further includes sequentially forming a third functional layer and an anti-reflection layer on the light-receiving surface of the semiconductor substrate.

15. The method of claim 14, wherein the back contact solar cell is formed of a silicon dioxide gas.

17. Comprising a back contact solar cell according to any one of claims 1 to 3 or a back contact solar cell produced by the method according to any one of claims 9 to 11. A battery assembly characterized by:

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