Semiconductor device

Abstract

To provide a liquid crystal display device capable of preventing deterioration in image quality, a driving method thereof, a liquid crystal display device capable of recognizing image display in accordance with an environment even in a dim environment or a bright environment, and a liquid crystal display device capable of performing image display in both a reflection mode using external light as an illumination light source and a transmission mode using a light source.SOLUTION: In the liquid crystal display device, the panel includes a pixel portion including a first region and a second region and a plurality of light sources included in a backlight, and the first region and the second region each include a liquid crystal element whose transmittance is controlled in accordance with the voltage of an input image signal and a transistor which controls holding of the voltage. In the case where a full-color image is displayed, the light source sequentially supplies light with different hues to the first region in accordance with a first rotation and also sequentially supplies light with different hues to the second region in accordance with a second rotation different from the first rotation. A monochrome image is displayed by reflecting external light in a reflective region included in a pixel electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an active matrix liquid crystal display device having a transistor in a pixel. [Background technology]

[0002] In the case of a transmissive LCD display, the power consumption of the backlight is proportional to the power consumption of the entire LCD display. Therefore, how to reduce the loss of light inside the panel is crucial to power consumption. The loss of light inside the panel is due to the interlayer insulating film. This is caused by the refraction of light and the absorption of light by color filters. Luta extracts light of a specific wavelength range from white light by utilizing the light absorption by pigments. In principle, the light energy from the backlight is The color filter absorbs more than 70% of the light. This can be said to be one of the factors hindering the reduction of electricity consumption.

[0003] To avoid the problem of light loss due to color filters, field sequential driving is used. FS drive is effective. FS drive sequentially lights up multiple light sources that emit light of different hues. FS drive is a driving method that displays color images by lighting up the color filters. Since there is no need to use a reflective layer, the loss of light inside the panel can be reduced, and the panel This increases the transmittance, thereby increasing the efficiency of light utilization from the backlight. This allows the power consumption of the entire liquid crystal display device to be reduced. Each color can be displayed with one pixel, allowing for high-definition image display. .

[0004] The following Patent Document 1 describes a conventional color image display method using a field sequential method. The present invention discloses a liquid crystal display device that switches to monochrome display when displaying images such as characters. There are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-248463 Summary of the Invention [Problem to be solved by the invention]

[0006] However, FS drive has a problem called color break, where each color image is not synthesized and is viewed individually. This phenomenon is particularly noticeable when displaying moving images. Cheap.

[0007] As described above, when using field sequential driving, the color filter However, the power consumption of the liquid crystal display device can be reduced compared to when the With the spread of electronic devices for personal use, the demand for lower power consumption in LCD devices is becoming increasingly strict. Therefore, there is a demand for further reduction in power consumption.

[0008] In view of the above-mentioned problems, the present invention provides a liquid crystal display device and a driving method thereof that can prevent deterioration of image quality. Alternatively, the present invention aims to reduce power consumption. One of the objectives of the present invention is to propose a liquid crystal display device and a driving method thereof.

[0009] In addition, the LCD display can adjust the image to suit the environment, whether it is in a bright or dimly lit environment. An object of the present invention is to provide a liquid crystal display device in which display can be recognized.

[0010] In addition, both a reflective mode using external light as the illumination light source and a transmissive mode using a backlight are available. An object of the present invention is to provide a liquid crystal display device that can display images at high resolution. [Means for solving the problem]

[0011] A liquid crystal display device according to one aspect of the present invention includes a backlight, a plurality of light sources emitting light of different hues, and a backlight unit. It has a light source and can display full color images or monochrome images. The driving method of the light source is switched depending on whether the light source is in the ON state or the OFF state.

[0012] To display a full-color image, the pixel section is divided into multiple regions, and the above light source is used for each region. The pixel section has a pixel electrode having a transparent area and a reflective area. In one embodiment of the present invention, a pixel portion has at least a first region and a second region, and A plurality of lights having the above structure are sequentially provided to the first region through the transparent region of the pixel electrode in accordance with a first rotation. and a plurality of lights having different hues are also provided in the second region in a different order from the first. They will be supplied in sequence according to the second rotation.

[0013] When a monochrome image is displayed, the supply of light is stopped and the reflective area of ​​the pixel electrode is illuminated by external light. The image is displayed by reflecting the light from the entire pixel area or each area as needed. It is also possible to improve the visibility of the displayed image by supplying a signal.

[0014] Furthermore, in one aspect of the present invention, when the monochrome image is a still image, the monochrome image is The driving frequency is set lower than that for a moving image. In order to lower the frequency, a liquid crystal element and a voltage applied to the liquid crystal element are provided in the pixel portion of the liquid crystal display device. An insulated gate field effect transistor with extremely low off-state current is used to control the retention of the applied voltage. A transistor with extremely low off-state current is provided. By using a transistor, the period during which the voltage applied to the liquid crystal element is maintained can be extended. Therefore, like a still image, the same image is displayed on the pixel area over several consecutive frame periods. When an image signal containing image information is written, even if the driving frequency is lowered, in other words, This means that the image display can be maintained even if the number of times the image signal is written within a certain period is reduced. It is possible.

[0015] In addition, the display is performed by reflecting light (hereinafter also referred to as external light) that is incident on the pixel electrode through the liquid crystal layer. A reflective area is provided for displaying images, and a transmissive area is provided for displaying images by transmitting light from a backlight. The liquid crystal display device can be switched between transmissive and reflective modes. In the reflective mode, the image is displayed using the light from the backlight, and in the backlight mode, the image is displayed using the external light. Displays the image.

[0016] In one embodiment of the present invention, a display device including a plurality of light sources emitting light of different hues and a pixel portion is provided. The element part includes a pixel electrode having a transparent region and a reflective region, and a transistor electrically connected to the pixel electrode. The pixel section is divided into a plurality of regions, and the lighting of the light source is controlled to display the light in the plurality of regions. Each provides light of a different hue, generating image signals for full-color display according to the light of the different hues. The light is then applied to the pixel electrodes via transistors to display full color images. The light is turned off, and the image signal for monochrome display is applied to the pixel electrode via the transistor, and the external light is reflected. A monochrome image is displayed by reflecting the light in the reflective area.

[0017] The above transistors have a wider band gap than silicon semiconductors and a higher intrinsic carrier density. The semiconductor material is characterized by containing a semiconductor material having a lower temperature than silicon semiconductor in the channel forming region. By including a semiconductor material with the above-mentioned properties in the channel formation region, the off-current can be reduced significantly. Such semiconductor materials include, for example, Oxide semiconductors have a band gap about three times larger than that of silicon. The transistor having the above structure is used as a switching element for maintaining a voltage applied to a liquid crystal element. By using it as a semiconductor element, it is possible to Compared to using a transistor with a junction, this can prevent charge leakage from the liquid crystal element. .

[0018] Specifically, a liquid crystal display device according to one aspect of the present invention uses a transparent electrode and a reflective electrode as pixel electrodes. and a panel provided with a driver circuit for controlling input of an image signal to the pixel portion. The pixel section has a plurality of light sources that supply light of different hues to the pixel section. The liquid crystal element controls the transmittance according to the voltage of the image signal, and the transistor controls the voltage retention. The transistor has a channel forming region formed of, for example, an oxide semiconductor. The band gap of semiconductors such as silicon is wider than that of silicon semiconductors, and the intrinsic carrier density is It contains semiconducting materials that are less conductive.

[0019] Specifically, in a method for driving a liquid crystal display device according to one embodiment of the present invention, In the case of displaying, the pixel portion has at least a first region and a second region, and the first region has: A plurality of lights having different hues are sequentially supplied in a first rotation and are directed to a second region. A plurality of lights having different hues are sequentially supplied according to a second rotation different from the first rotation. Each pixel area receives an image signal for full color display according to the hue of the light supplied. When a monochrome image is displayed, the pixel section receives an image for monochrome display. When displaying a monochrome image, the image signal is written within a certain period. The number of writes can be changed.

[0020] After impurities such as water or hydrogen, which act as electron donors, are reduced, oxygen The oxide semiconductor with reduced oxygen vacancies (purified OS) is an i-type (true Therefore, the transistor using the above oxide semiconductor is Specifically, the oxide semiconductor has a characteristic of having a significantly low off-state current. Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration measured by the etry was 5 × 10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 Below, more preferably 1 × 1 0 16 / cm 3 The following is a description of the capacitance of the oxide semiconductor film that can be measured by Hall effect measurement. The carrier density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than, more Preferably 1 x 10 11 / cm 3The band gap of the oxide semiconductor is less than The impurity concentration is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By reducing the concentration and further reducing oxygen vacancies, it is possible to obtain an i-type or substantially i-type oxide semiconductor. By using the organic film, the off-state current of the transistor can be reduced.

[0021] When a color image is displayed using a plurality of light sources having different hues, a monochromatic light source Unlike the case where a color filter is combined with the above multiple light sources, the above multiple light sources are switched sequentially to emit light. The frequency at which the light source is switched is set to a value that is higher than that of a monochromatic light source. For example, if a monochromatic light source is used, the frame frequency must be set to a value higher than the frame frequency when the If the frame frequency is 60Hz, the light sources corresponding to the red, green, and blue colors are used. When FS drive is used, the frequency of switching the light source is approximately three times higher, at 180 Hz. The driving circuit also operates in accordance with the frequency of the light source, so it can operate at a very high frequency. Therefore, the power consumption in the drive circuit is It tends to be more expensive than when combined.

[0022] However, in one embodiment of the present invention, a transistor with extremely low off-state current is used in a pixel portion. This makes it possible to lengthen the period during which the voltage applied to the liquid crystal element is maintained. The drive frequency when displaying still images is lower than the drive frequency when displaying moving images. can be done.

[0023] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The hydrogen concentration in the conductive film was measured using secondary ion mass spectrometry (SIMS). SIMS analysis is performed using ion mass spectrometry (SIMS). It is difficult to obtain accurate data near the sample surface or near the interface between layers of different materials. Therefore, the distribution of hydrogen concentration in the film in the thickness direction was analyzed by SIMS. When analyzing, the values ​​should be almost constant without extreme fluctuations within the range where the target film exists. The average value in the area where the value is obtained is adopted as the hydrogen concentration. When the film thickness is small, the hydrogen concentration in the adjacent film affects the film thickness, and a nearly constant value is obtained. In this case, the hydrogen concentration in the area where the film exists may be The maximum or minimum value of the above is adopted as the hydrogen concentration in the film. In the region, there is no mountain-shaped peak with a maximum value or a valley-shaped peak with a minimum value. If not, the value at the inflection point is used as the hydrogen concentration.

[0024] Specifically, a transistor using an i-type or substantially i-type oxide semiconductor film as an active layer The low off-state current of the transistor can be proven by various experiments. 1×10 6 Even in a device with a channel length of 10 μm, the distance between the source and drain electrodes is When the voltage (drain voltage) is in the range of 1V to 10V, the off-state current (gate electrode and source The drain current when the voltage between the electrodes is set to 0 V or less is measured by the semiconductor parameter analyzer. below the measurement limit, i.e., 1×10 -13 In this case, the characteristic of A or less can be obtained. In this case, the off-current density, which corresponds to the value obtained by dividing the off-current by the channel width of the transistor, is 10 It can be seen that the capacitance is less than 0zA / μm. A circuit is used that controls the charge flowing into or out of the capacitance element using the transistor. In this measurement, the above oxide semiconductor film was used for the transistor. It is used in the channel formation region, and the charge amount per unit time of the capacitance element is used to calculate the capacitance of the transistor. The off-state current density of the transistor was measured. At a voltage of 3 V, even lower off-state current densities of several tens of yA / μm can be obtained. Therefore, in a semiconductor device according to one embodiment of the present invention, The off-state current density of the transistor using the conductive layer was measured as a function of the voltage between the source and drain electrodes. Therefore, it is 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably 1 y Therefore, the oxide semiconductor film can be used as an active layer. The off-state current of a transistor using crystalline silicon is significantly higher than that of a transistor using crystalline silicon. Very low.

[0025] Examples of oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides , In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, I n-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In -Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In- Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, In -Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Z n-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides It is possible.

[0026] For example, an In-Ga-Zn oxide is an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n Materials expressed as (n>0) may also be used. [Effects of the Invention]

[0027] In a liquid crystal display device according to one aspect of the present invention, a pixel portion is divided into a plurality of regions, and each region has a different By sequentially supplying light of different hues, a color image is displayed. By doing so, the hues of the light supplied to adjacent regions can be made different from each other. This prevents each color image from being viewed individually without being combined, making it ideal for video display. This can prevent color breaks, which were prone to occur.

[0028] A liquid crystal display device according to one aspect of the present invention is capable of preventing light from shining in a dimly lit environment even when the surroundings of the liquid crystal display device are bright. In any environment, the display can be switched between a reflective mode using external light as the illumination source and a backlight mode using external light as the illumination source. It is possible to realize a liquid crystal display device that can display images in both a transparent mode and a transparent mode. When displaying moving images, the display should be in transmissive mode, and when displaying still images, the display should be in reflective mode. It can also be done as follows.

[0029] A liquid crystal display device according to one embodiment of the present invention includes a transistor with extremely low off-state current in a pixel portion. By using this, it is possible to lengthen the period during which the voltage applied to the liquid crystal element is maintained. Therefore, the drive frequency when displaying still images is lower than the drive frequency when displaying moving images. Therefore, a liquid crystal display device capable of reducing power consumption can be realized. It is possible. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a block diagram showing a configuration of a liquid crystal display device. [Figure 2] FIG. 2 is a diagram showing the configuration of a panel and pixels. [Figure 3] FIG. 2 is a diagram schematically illustrating the operation of a liquid crystal display device and a backlight. [Figure 4] 10A and 10B are schematic diagrams showing examples of the hues of light supplied to each region. [Figure 5] FIG. 10 is a diagram schematically illustrating an example of turning off the light supplied to each region. [Figure 6] FIG. 2 is a diagram showing the configuration of a scanning line driver circuit. [Figure 7] FIG. 2 is a diagram schematically illustrating an x-th pulse output circuit 20_x. [Figure 8] FIG. 2 is a diagram showing the configuration of a pulse output circuit and its timing chart. [Figure 9] FIG. 2 is a timing chart of a scanning line driver circuit. [Figure 10]FIG. 2 is a timing chart of a scanning line driver circuit. [Figure 11] FIG. 2 is a diagram showing the configuration of a signal line driver circuit. [Figure 12] FIG. 3 is a diagram showing an example of the timing of an image signal (DATA) supplied to a signal line. [Figure 13] FIG. 4 is a diagram showing the timing of scanning a selection signal and the timing of lighting a backlight. [Figure 14] FIG. 4 is a diagram showing the timing of scanning a selection signal and the timing of turning off a backlight. [Figure 15] FIG. 2 is a diagram showing the configuration of a panel and pixels. [Figure 16] FIG. 2 is a diagram showing the configuration of a scanning line driver circuit. [Figure 17] FIG. 2 is a timing chart of a scanning line driver circuit. [Figure 18] FIG. 2 is a diagram showing the configuration of a signal line driver circuit. [Figure 19] FIG. 2 is a diagram showing the configuration of a pulse output circuit. [Figure 20] FIG. 2 is a diagram showing the configuration of a pulse output circuit. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 22] FIG. 1 is a cross-sectional view of a transistor. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device. [Figure 24] FIG. 1 is a top view of a liquid crystal display device. [Figure 25] 1A and 1B are a top view and a cross-sectional view of a liquid crystal display device. [Figure 26] FIG. 1 is a perspective view showing a configuration of a liquid crystal display device. [Figure 27] 1A and 1B are a top view and a cross-sectional view showing the structure of a pixel. [Figure 28] 1A and 1B are a top view and a cross-sectional view showing the structure of a pixel. [Figure 29] FIG. 2 is a cross-sectional view showing the configuration of a pixel. [Figure 30] Diagram illustrating the structure of a transistor [Figure 31] FIG. 1 is a diagram showing the definition of Vth. [Figure 32] FIG. 10 is a graph showing the results of a negative bias light irradiation test. [Figure 33] Electronic equipment illustration. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0032] (Embodiment 1) <Configuration example of liquid crystal display device> The liquid crystal display device 400 shown in FIG. 1 includes a plurality of image memories 401 and an image data selection circuit 40 2, a selector 403, a CPU 404, a controller 405, a panel 406, and The display device includes a backlight 407 and a backlight control circuit 408.

[0033] The plurality of image memories 401 stores a full-color image corresponding to the input image of the liquid crystal display device 400. The image data (full color image data 410) is stored. The image data 410 includes image data corresponding to each of a plurality of hues. The memory 401 stores image data corresponding to each hue.

[0034] The image memory 401 is, for example, a DRAM (Dynamic Random Access Memory). Memory), SRAM (Static Random Access Memory) ) or other memory circuits can be used.

[0035] The image data selection circuit 402 selects an image from a plurality of image memories in accordance with an instruction from the controller 405. The full-color image data corresponding to each hue stored in the selector 401 is read out. Send to 403.

[0036] The liquid crystal display device 400 also stores image data corresponding to a monochrome image (monochrome image data The input monochrome image data 411 is also input to the selector 403. Be encouraged.

[0037] In addition, an image displayed using multiple colors of different hues and gradations of each color is called a full-color image. In addition, an image that uses a single hue and is displayed in gradations of that color is called a monochrome image. Let's say.

[0038] In this embodiment, monochrome image data 411 is directly input to selector 403. However, the present invention is not limited to this configuration. Similarly, monochrome image data 411 is also temporarily stored in image memory 401. In this case, the selector 403 may read out the image data. The configuration is included in the data selection circuit 402.

[0039] The monochrome image data 411 is displayed on the LCD device 400 as full-color image data 410. The compound may be prepared by synthesis in the following manner.

[0040] The CPU 404 can display a full-color image or a monochrome image. Then, the selector 403 and the controller 405 are controlled to switch their operations.

[0041] Specifically, when a full-color image is to be displayed, the selector 403 receives a command from the CPU 404. In accordance with the instruction, the input full-color image data 410 is selected and supplied to the panel 406. In addition, the controller 405 converts full-color image data into A drive signal synchronized with the timer 410 or a power supply voltage used when displaying a full-color image is supplied to the panel 406.

[0042] Alternatively, when a monochrome image is to be displayed, the selector 403 selects Therefore, the input monochrome image data 411 is selected and supplied to the panel 406. In accordance with an instruction from the CPU 404, the controller 405 converts monochrome image data 411 The power supply potential used when displaying a drive signal or monochrome image synchronized with the panel Supply to 406.

[0043] The panel 406 includes a pixel portion 412 having a liquid crystal element in each pixel, a signal line driver circuit 413, a driving circuit 414, and a display panel. The selector 403 selects the full-color image data. The monochrome image data 410 or monochrome image data 411 is supplied to a signal line driving circuit 413. In addition, the drive signal or power supply potential from the controller 405 is supplied to the signal line drive circuit 413 or The signal is supplied to the scanning line driving circuit 414 .

[0044] The drive signal includes a signal line drive circuit start signal for controlling the operation of the signal line drive circuit 413. Pulse signal (SSP), clock signal for signal line driving circuit (SCK), scanning line driving circuit 41 A start pulse signal (GSP) for the scanning line driver circuit that controls the operation of 4, This includes the clock signal (GCK).

[0045] The backlight 407 has a plurality of light sources that emit light of different hues. The roller 405 is connected to the light source of the backlight 407 via the backlight control circuit 408. Control the drive of.

[0046] Note that the display of full color images and monochrome images can be switched manually. In this case, the input device 420 is provided in the liquid crystal display device 400, and the signal from the input device 420 The CPU 404 may control the switching in accordance with the signal.

[0047] The liquid crystal display device 400 exemplified in the embodiment may also include a photometry circuit 421. The photometry circuit 421 measures the brightness of the environment in which the liquid crystal display device 400 is used. Then, according to the brightness detected by the photometry circuit 421, the CPU 404 The display control unit 100 may also control switching between full-color image display and monochrome image display.

[0048] For example, when the liquid crystal display device 400 exemplified in this embodiment is used in a dimly lit environment, According to the signal from the optical circuit 421, the CPU 404 selects the display of a full-color image and adjusts the brightness. When used in a dark environment, the CPU 404 adjusts the monochrome image in accordance with a signal from the photometry circuit 421. It is also possible to select the display of the image. The backlight 407 may be configured to turn on when the ambient brightness falls below a threshold. stomach.

[0049] <Panel configuration example> Next, an example of a specific configuration of a panel of a liquid crystal display device according to one embodiment of the present invention will be described. Let me list and explain.

[0050] FIG. 2(A) is a diagram showing an example of the configuration of a liquid crystal display device. The liquid crystal display device shown in FIG. The liquid crystal display device includes a pixel section 10, a scanning line driving circuit 11, and a signal line driving circuit 12. In this embodiment, the pixel section 10 is divided into a plurality of regions. 10 is divided into three regions (regions 101 to 103). Each region has a plurality of pixels 15 arranged in a matrix.

[0051] The pixel section 10 also includes m scanning lines GL whose potentials are controlled by a scanning line driving circuit 11. and n signal lines SL whose potentials are controlled by a signal line driving circuit 12. The m scanning lines GL are divided into a plurality of groups according to the number of regions of the pixel section 10. For example, in the case of FIG. 2(A), the pixel section 10 is divided into three regions. Therefore, the m scanning lines GL are also divided into three groups. The scanning line GL belonging to the group is connected to a plurality of pixels 15 included in the area corresponding to the group. Specifically, each scanning line GL is connected to a plurality of pixels arranged in a matrix in each region. Of the pixels 15, n pixels 15 arranged in any one row are connected.

[0052] Furthermore, regardless of the region, the signal lines SL are arranged in m rows and n columns in the pixel section 10. Of the plurality of pixels 15, m pixels 15 arranged in any one column are connected.

[0053] In this specification, connection means electrical connection, and the current, voltage, or potential Therefore, the connected state corresponds to the state in which the signal is directly connected. It does not necessarily refer to the state of being connected, but rather to the state in which a current, voltage, or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via a direct connection.

[0054] Even if components that are independent on the circuit diagram are connected, For example, when a part of the wiring also functions as an electrode, one conductive film is connected to a plurality of components. In this specification, the term "connection" refers to such a conductive A membrane that combines the functions of multiple components is also included in this category.

[0055] The source electrode and the drain electrode of the transistor are connected to each other. The name changes depending on the difference in potential applied to the electrodes. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the The electrode that is connected to the drain is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In this specification, either the source electrode or the drain electrode is referred to as a first terminal, and the other is referred to as a second terminal. Assuming two terminals, the connection relationship of the transistor is explained.

[0056] FIG. 2B is a diagram showing an example of a circuit diagram of the pixel 15 included in the liquid crystal display device shown in FIG. 2A. The pixel 15 shown in FIG. 2B includes a transistor 1 that functions as a switching element. 6, and its transmittance is controlled according to the potential of the image signal given through the transistor 16. The liquid crystal element 18 and the capacitance element 17 are connected to each other.

[0057] The liquid crystal element 18 is made up of a pixel electrode, a counter electrode, and a liquid crystal layer to which a voltage is applied between the pixel electrode and the counter electrode. The pixel electrode is an area that reflects light that enters through the liquid crystal layer. The capacitor element 17 has a reflective region and a light-transmitting region. has the function of maintaining the voltage between the pixel electrode and the counter electrode of the liquid crystal element 18.

[0058] Examples of liquid crystal materials used in the liquid crystal layer include nematic liquid crystal, cholesteric liquid crystal, and smectic liquid crystal. mectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low Molecular liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side Examples include chain-type polymer liquid crystals and banana-shaped liquid crystals.

[0059] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is difficult to distinguish it from chiral materials or purple materials. Adding ultraviolet curing resin to improve the temperature range. Contains blue phase liquid crystal and chiral agent. The liquid crystal composition has a short response time of 10 μsec or more and 100 μsec or less, and is optically isotropic. Since it is non-polar, alignment treatment is not required, and it is preferable because it has little viewing angle dependency.

[0060] The liquid crystal driving method is TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, VA (Vertical A) lignment) mode, MVA (Multi-domain Vertical A) lignment) mode, IPS (In-Plane Switching) mode, OCB(Optically Compensated Birefringence) Mode, ECB (Electrically Controlled Birefringence ence) mode, FLC (Ferroelectric Liquid Crystal al) mode, AFLC (AntiFerroelectric Liquid Cry stal) mode, PDLC (Polymer Dispersed Liquid Crystal Crystal mode, PNLC (Polymer Network Liquid Crystal It is possible to apply a guest host mode, a shard mode, etc.

[0061] The pixel 15 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may also include other circuit elements such as a resistor.

[0062] Specifically, in FIG. 2B, the gate electrode of the transistor 16 is connected to the scanning line GL. The transistor 16 has a first terminal connected to the signal line SL and a second terminal connected to the liquid crystal pixel. One electrode of the capacitance element 17 is connected to the pixel electrode of the liquid crystal element 18. The other electrode is connected to a node at a specific potential. A specific potential is also applied to the counter electrode of the liquid crystal element 18. The potential applied to the counter electrode is the same as the potential applied to the other electrode of the capacitor 17. It may be.

[0063] In one embodiment of the present invention, the transistor 16 functioning as a switching element The channel formation region has a wider band gap than silicon semiconductors and an intrinsic carrier density It may also contain semiconductors with lower electrical conductivity than silicon semiconductors. Compound semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and zinc oxide (ZnO) Among these, oxide semiconductors made of metal oxides can be used. It can be produced by sputtering or wet methods (printing, etc.), and is said to be suitable for mass production. In addition, the process temperature for silicon carbide is approximately 1500°C, while that for gallium nitride is approximately 1500°C. The process temperature is about 1100°C, but the oxide semiconductor film formation temperature is 300°C or more, which is higher than the glass transition temperature. The temperature is low, below the transition point, and it is possible to form a film on a glass substrate, which is inexpensive and readily available. Therefore, among the wide-gap semiconductors mentioned above, the oxide semiconductor The advantage of compound semiconductors is that they are easy to mass-produce. Even when trying to obtain a crystalline oxide semiconductor to improve the field-effect mobility, A crystalline oxide semiconductor can be easily obtained by heat treatment at 50 to 800°C.

[0064] In the following description, oxide semiconductors with the above advantages will be used as semiconductors with a large band gap. The case where a compound semiconductor is used is given as an example.

[0065] Unless otherwise specified, the off-state current in this specification refers to the off-state current in an n-channel transistor. In this case, when the drain electrode is at a higher potential than the source and gate electrodes, When the voltage between the gate electrode and the source electrode is less than 0, a current flows between the source electrode and the drain electrode. Alternatively, the off-state current in this specification refers to the current that flows through a p-channel transistor. In the case of a capacitor, when the drain electrode is at a lower potential than the source and gate electrodes, When the voltage between the gate electrode and the source electrode is 0 or more, the source electrode and the drain electrode This refers to the current that flows between

[0066] In FIG. 2B, in the pixel 15, one transistor 16 is used as a switching element. However, the present invention is not limited to this configuration. A plurality of transistors may be used to function as switching elements. When a plurality of transistors function as a single switching element, the plurality of transistors are connected in parallel. They may be connected in series or in a combination of series and parallel. It is okay to use it.

[0067] In this specification, the state in which transistors are connected in series means, for example, Only one of the first and second terminals of the first transistor is connected to the first terminal of the second transistor. This means that the transistor is connected to only one of the second terminals. The state of being connected in a series is when the first terminal of the first transistor is connected to the first terminal of the second transistor. The first terminal of the first transistor is connected to the second terminal of the second transistor. This means that the device is connected.

[0068] By including a semiconductor material having the above-described characteristics in the channel formation region, the off-current can be reduced to an extremely low level. It is possible to realize a transistor 16 that has the lowest temperature and high breakdown voltage. By using the transistor 16 having the above configuration as a switching element, Compared to transistors made of semiconductor materials such as silicon or germanium, This can prevent leakage of the charge accumulated in the crystal element 18.

[0069] By using the transistor 16 with an extremely small off-state current, the voltage applied to the liquid crystal element 18 can be reduced. This allows the pressure to be maintained for a long period of time. Image signals having the same image information are written to the pixel section 10 over several frame periods. In such a case, the driving frequency is lowered, in other words, the driving frequency of the pixel unit 10 within a certain period is Even if the number of times of writing the image signal is reduced, the image display can be maintained. For example, The above-described i-type or substantially i-type oxide semiconductor film is used as an active layer. By using the transistor 16, the interval between writing of the image signal can be set to 10 seconds or more, preferably 3 The time can be set to 0 seconds or more, and more preferably 1 minute or more. The longer the interval between power consumption and power consumption, the more power consumption can be reduced.

[0070] In addition, when viewing an image obtained by writing image signals multiple times, the image is switched multiple times. Therefore, the human eye will perceive the image as fatigue. As described in this embodiment, the number of times of writing image signals is reduced. This also has the effect of reducing eye fatigue.

[0071] Furthermore, since the potential of the image signal can be maintained for a longer period of time, the potential of the image signal can be In order to maintain the image quality, the display image quality is maintained even if the capacitance element 17 is not connected to the liquid crystal element 18. Therefore, by not providing the capacitance element 17, or By reducing the size of the capacitor element 17, the aperture ratio can be increased. This makes it possible to reduce the power consumption of the liquid crystal display device.

[0072] In addition, inversion driving is performed to invert the polarity of the potential of the image signal based on the potential of the counter electrode. This prevents the deterioration of the liquid crystal known as burn-in. When the polarity of the image signal changes, the change in the potential applied to the signal line becomes large, The potential difference between the source electrode and the drain electrode of the transistor 16, which functions as an etching element, is large. As a result, the transistor 16 may experience characteristic degradation such as a shift in threshold voltage. In addition, in order to maintain the voltage held in the liquid crystal element 18, the source electrode and the drain electrode Even if the potential difference between the drain electrodes is large, the off-state current is required to be low. provides transistor 16 with a material having a bandgap larger than that of silicon or germanium, Since a semiconductor such as an oxide semiconductor with a low intrinsic carrier density is used, the transistor 16 Therefore, it is possible to improve the breakdown voltage of the device and significantly reduce the off-state current. Compared to using transistors made of semiconductor materials such as aluminum, This prevents deterioration of the crystal 16 and maintains the voltage held in the liquid crystal element 18.

[0073] <Example of panel and backlight operation> Next, an example of the operation of the panel will be explained together with the operation of the backlight. 3 is a diagram showing the operation of a liquid crystal display device and a backlight. The liquid crystal display device according to the present embodiment operates in a period during which a full-color image is displayed (full-color image display period). A monochrome moving image display period 301) and a monochrome moving image display period 302) 2) and a period in which a monochrome still image is displayed (monochrome still image display period 303). Be separated.

[0074] In the full-color image display period 301, one frame period is composed of a plurality of sub-frame periods. An image signal is written to the pixel section for each sub-frame period. The driving circuits, such as the scanning line driving circuit and the signal line driving circuit, are connected to the Therefore, a full-color image can be displayed. During period 301, the driving circuit is in an operating state. In 01, the hue of the light supplied to the pixel section by the backlight changes every sub-frame period. Then, the image signals corresponding to each hue are written to the pixel section in order, and one frame is An image is formed by writing image signals corresponding to all hues within a single frame period. Therefore, in the full-color image display period 301, the image signal to the pixel unit in one frame period The number of times the image is written is multiple, and the number depends on the number of hues of light provided by the backlight. It is decided.

[0075] During the monochrome moving image display period 302, an image signal is written to the pixel unit for each frame period. The driving circuits, such as the scanning line driving circuit and the signal line driving circuit, are During the display, the drive signal is supplied continuously. During the monochrome moving image display period 302, the drive circuit is in an operating state. In the interval 302, the backlight is turned off and the reflective area of ​​the pixel electrode reflects the external light. To display an image, image signals corresponding to multiple hues are written to the pixel section in sequence. It is not necessary to write an image signal corresponding to one hue to the pixel section within one frame period. Therefore, in the monochrome moving image display period 302, one frame The number of times an image signal is written to the pixel portion during a frame period can be set to one.

[0076] In the monochrome still image display period 303, an image signal is written to the pixel section for each frame period. However, during the full-color image display period 301 and the monochrome video display period 30 Unlike 2, when writing an image signal to the pixel section, a drive signal is supplied to the drive circuit, and the writing After the writing is completed, the supply of the drive signal to the drive circuit is stopped. During the display period 303, the driving circuit is in a non-operating state except when an image signal is written. In the monochrome still image display period 303, the backlight is turned off and the pixel electrodes are exposed to external light. The image is displayed by reflecting the light from the reflective area. It is not necessary to write the image signals corresponding to one hue to the pixel section in order, and the image signals corresponding to one hue are written in one frame period. By writing the above to the pixel area, one image can be formed. In the display period 303, the number of times an image signal is written to the pixel portion in one frame period is set to one. It can be said that:

[0077] During the monochrome moving image display period 302, flickering of the image, such as flicker, is visually recognized. To prevent this, it is recommended to have a period of 60 frames or more per second. In period 303, one frame period can be extremely long, for example, one minute or more. By lengthening the frame period, the period during which the drive circuit is inactive can be lengthened. This reduces the power consumption of the liquid crystal display device. Since there is no need to use a photodiode, the power consumption of the liquid crystal display device can be further reduced.

[0078] Furthermore, the liquid crystal display device according to one embodiment of the present invention does not need to use a color filter. Therefore, power consumption can be reduced compared to a liquid crystal display device using a color filter.

[0079] Note that even during the monochrome moving image display period 302 or monochrome still image display period 303, The backlight can be turned on for the entire pixel area or for each area as needed to improve the visibility of the displayed image. It can also be increased.

[0080] In the full-color image display period 301, in one frame period, A plurality of lights with different hues are sequentially supplied. Figure 4 shows an example of the hues of the light supplied to each region. In addition, in FIG. 4, as shown in FIG. 2(A), the pixel portion is divided into three regions. Furthermore, in FIG. 4, red (R 10 illustrates an example in which blue (B) light, green (G) light, and blue (B) light are supplied.

[0081] First, in FIG. 4A, during the first subframe period, red (R) light is irradiated to the region 101, and red (R) light is irradiated to the region 202. Green (G) light is supplied to area 102, and blue (B) light is supplied to area 103. 4B, in the next subframe period, green (G) is applied to the region 101. blue (B) light is supplied to region 102, and red (R) light is supplied to region 103. 4C shows the state of the area 101 in the next subframe period. Blue (B) light is provided to area 101, red (R) light to area 102, and green (G) light to area 103. This shows how it is being provided.

[0082] When all the sub-frame periods are completed, one frame period is completed. During a frame period, the hue of the light supplied to each area goes through a cycle, producing a full-color image. In addition, when each region is focused on, in the region 101, the light supplied The hue of the area changes in the order of red (R), green (G), and blue (B). The hue of the light supplied changes in the order of green (G), blue (B), and red (R). In 103, the hue of the light supplied changes in the order blue (B), red (R), and green (G). Therefore, in each region, a plurality of lights having different hues are sequentially provided in different rotations. It is known that it is being provided.

[0083] In FIG. 4, only light of one hue is supplied to one region during each subframe period. However, one embodiment of the present invention is not limited to this configuration. Within the area, the hue of the light supplied is switched in order from the part where the writing of the image signal has finished. In this case, the area to which light of each hue is supplied and the pixel portion are divided. This does not necessarily coincide with the area formed by the

[0084] In addition, during the monochrome moving image display period 302 and the monochrome still image display period 303, the supply of light is FIG. 5(A) shows the backlight corresponding to the area 101, the area 102, and the area 103. This shows the light turned off.

[0085] In addition, the backlight can be turned on for the entire pixel area or for each area as needed, The visibility can also be improved. This shows that red (R) light, blue (B) light, and green (G) light are supplied in parallel. By mixing blue (B) light and green (G) light, white (W) light is supplied to area 101. .

[0086] In addition, in FIG. 5(B), a plurality of lights having different hues are mixed to produce a single hue. However, even if light having one hue is supplied to the pixel portion, FIG. 5(C) shows that green (G) light is supplied to the area 101 from the backlight. Shows.

[0087] <Configuration example of scanning line driving circuit 11> 6 is a diagram showing an example of the configuration of the scanning line driving circuit 11 shown in FIG. The line driving circuit 11 includes the first pulse output circuit 20_1 to the m-th pulse output circuit 20_m. The outputs from the first pulse output circuit 20_1 to the m-th pulse output circuit 20_m are The selection signals are respectively supplied to m scanning lines GL (scanning lines GL1 to GLm). will be done.

[0088] The scanning line driving circuit 11 also receives first scanning line driving circuit clock signals (GCK1) to (GCK2). The fourth scanning line driving circuit clock signal (GCK4) and the first pulse width control signal (PWC 1) to 6th pulse width control signals (PWC6) and a start pulse signal for the scanning line driving circuit (GSP) is supplied as a drive signal.

[0089] In FIG. 6, the first pulse output circuit 20_1 to the j-th pulse output circuit 20_j (j is a multiple of 4 less than m / 2) are the scanning lines GL1 to GLj arranged in the area 101. 6 illustrates a case where the j+1th pulse output circuit 20 is connected to the j+1th pulse output circuit 20. The pulse output circuits 20_2j of j+1 to 2j are connected to the scanning lines GL j+1 to GL2j. The j+1th pulse output circuit 20_2j+1 to the mth pulse output circuit 20_m are included in the region 103. 10 illustrates a case where the scanning lines GL2j+1 to GLm are connected to the scanning lines GL2j+1 to GLm. .

[0090] The first pulse output circuit 20_1 to the m-th pulse output circuit 20_m are Operates according to a start pulse signal (GSP) for the scanning line driving circuit input to the circuit 20_1 and outputs a selection signal with pulses shifted sequentially.

[0091] The first pulse output circuit 20_1 to the m-th pulse output circuit 20_m have the same configuration. The first pulse output circuit 20_1 to the m-th pulse output circuit 20_2 can be applied. A specific connection relationship of the circuit 20_m will be described with reference to FIG.

[0092] FIG. 7 is a diagram schematically illustrating an x-th pulse output circuit 20_x (x is a natural number equal to or less than m). Each of the first pulse output circuit 20_1 to the m-th pulse output circuit 20_m is , terminals 21 to 27. Terminals 21 to 24 and terminal 26 are input terminals. and terminals 25 and 27 are output terminals.

[0093] First, the terminal 21 will be described. The terminal 21 of the first pulse output circuit 20_1 is connected to the scanning line driver 20_2. The second pulse output circuit is connected to the wiring that supplies the start pulse signal (GSP) for the drive circuit. The terminals 21 of the circuits 20_2 to 20_m are the terminals of the pulse output circuits in the preceding stages. connected to the child 27.

[0094] Next, the terminal 22 will be described. (a is a natural number equal to or smaller than m / 4) terminal 22 receives a clock signal (G CK1), and the (4a-2) pulse output circuit 20_(4a-2 The terminal 22 of the second scanning line driving circuit is connected to a wiring that supplies a clock signal (GCK2) for the second scanning line driving circuit. The terminal 22 of the pulse output circuit 20_(4a-1) is connected to the third scanning line. It is connected to the wiring that supplies the clock signal (GCK3) for the line driver circuit, and the 4a pulse output The terminal 22 of the circuit 20_4a supplies a clock signal (GCK4) for the fourth scanning line driving circuit. It is connected to the wiring.

[0095] Next, the terminal 23 will be described. The terminal 23 is connected to a wiring that supplies a clock signal (GCK2) for the second scanning line driving circuit. The terminal 23 of the (4a-2) pulse output circuit 20_(4a-2) is connected to the third scanning line It is connected to the wiring that supplies the clock signal (GCK3) for the drive circuit, and the pulse (4a-1) The terminal 23 of the scan output circuit 20_(4a-1) receives the fourth scan line driving circuit clock signal (G CK4), and the terminal 23 of the 4a pulse output circuit 20_4a is It is connected to a wiring that supplies a clock signal (GCK1) for the first scanning line driving circuit.

[0096] Next, the terminal 24 will be described. Terminal 24 (b is a natural number less than or equal to j / 2) provides a first pulse width control signal (PWC1). The terminal 24 of the second pulse output circuit 20_2b is connected to a wiring that supplies a fourth pulse. The pulse width control signal (PWC4) is connected to the wiring for supplying the pulse width control signal (PWC4), and the pulse output circuit 2 The terminal 24 of 0_(2c-1) (c is a natural number between (j / 2+1) and j) is the second power supply. The pulse width control signal (PWC2) is connected to a wiring for supplying the pulse output circuit 20_ The terminal 24 of the second input terminal 2c is connected to a wiring for supplying a fifth pulse width control signal (PWC5). (2d-1) pulse output circuit 20_(2d-1) (d is (j+1) or more and m / 2 or less) A terminal 24 (a natural number) is connected to a wiring that supplies a third pulse width control signal (PWC3). The terminal 24 of the 2d-th pulse output circuit 20_2d receives a sixth pulse width control signal (PWC6 ) is connected to the wiring that supplies

[0097] Next, the terminal 25 will be described. The terminal 25 of the x-th pulse output circuit 20_x is The scanning lines GLx are connected to the scanning lines GLx.

[0098] Next, the terminal 26 will be described. The y-th pulse output circuit 20_y (y is m-1 or less) The terminal 26 of the (y+1)th pulse output circuit 20_(y+1) is connected to the terminal 27 of the (y+1)th pulse output circuit 20_(y+1). The terminal 26 of the m-th pulse output circuit 20_m is connected to the m-th pulse output circuit stop It is connected to the wiring that supplies the stop signal (STP) for the mth pulse output circuit. When the (m+1)th pulse output circuit 20_(m+1) is provided, the signal (STP) is Then, the signal output from the terminal 27 of the (m+1)th pulse output circuit 20_(m+1) Specifically, these signals are actually the (m+1)th pulse as a dummy circuit. By providing an output circuit 20_(m+1), or by directly inputting the signal from the outside, etc. Thus, the m-th pulse can be supplied to the m-th pulse output circuit 20_m.

[0099] The connection relationship of the terminals 27 of each pulse output circuit has already been explained. This will be incorporated herein by reference.

[0100] <Pulse output circuit configuration example 1> Next, FIG. 8A shows one specific configuration of the x-th pulse output circuit 20_x shown in FIG. The pulse output circuit shown in FIG. 8A includes transistors 31 to 39. It has.

[0101] The gate electrode of the transistor 31 is connected to the terminal 21. 31 has its first terminal connected to a node to which a high power supply potential (Vdd) is applied, and The second terminal is connected to the gate electrode of the transistor 33 and the gate electrode of the transistor 38. are.

[0102] The transistor 32 has a gate electrode connected to the gate electrode of the transistor 34 and the transistor 39. The transistor 32 has its first terminal connected to the low power supply potential ( Vss), and its second terminal is connected to the gate of transistor 33. The electrode and the gate electrode of the transistor 38 are connected.

[0103] Transistor 33 has a first terminal connected to terminal 22 and a second terminal connected to terminal 27. It continues.

[0104] The first terminal of the transistor 34 is connected to a node to which a low power supply potential (Vss) is applied. The second terminal of the power supply 10 is connected to the power supply 11 and the second terminal of the power supply 11 is connected to the terminal 27.

[0105] The gate electrode of the transistor 35 is connected to the terminal 21. 35 has a first terminal connected to a node to which a low power supply potential (Vss) is applied, and The second terminal is connected to the gate electrode of transistor 34 and the gate electrode of transistor 39. are.

[0106] The transistor 36 has its gate electrode connected to the terminal 26. 36 has its first terminal connected to a node to which a high power supply potential (Vdd) is applied, and The second terminal is connected to the gate electrode of transistor 34 and the gate electrode of transistor 39. Note that the first terminal of the transistor 36 is at a potential higher than the low power supply potential (Vss). and a node to which a power supply potential (Vcc) that is lower than the high power supply potential (Vdd) is applied. It can also be configured to be connected to a board.

[0107] The gate electrode of the transistor 37 is connected to the terminal 23. 37 has its first terminal connected to a node to which a high power supply potential (Vdd) is applied, and The second terminal is connected to the gate electrode of transistor 34 and the gate electrode of transistor 39. The first terminal of the transistor 37 is connected to a node to which the power supply potential (Vcc) is applied. It can also be configured to be connected to a board.

[0108] Transistor 38 has its first terminal connected to terminal 24 and its second terminal connected to terminal 25. It continues.

[0109] The first terminal of the transistor 39 is connected to a node to which a low power supply potential (Vss) is applied. The second terminal of the power supply 10 is connected to the terminal 25 .

[0110] Next, FIG. 8B shows an example of a timing chart of the pulse output circuit shown in FIG. 8A. It should be noted that the periods t1 to t7 shown in FIG. 8B are of the same length. The periods t1 to t7 are determined by the first scanning line driving circuit clock signal (GCK 1) to 1 / 3 of the pulse width of the fourth scanning line driving circuit clock signal (GCK4), respectively. Correspondingly, the first pulse width control signal (PWC1) to the sixth pulse width control signal (PWC6 ) corresponds to half the pulse width of

[0111] The pulse output circuit shown in FIG. 8A receives an input to the terminal 21 during the period t1 and the period t2. The potential input to the terminals 22, 23, 24 and 26 is at a high level. becomes low level, a low level potential is output from terminal 25 and a low level potential is output from terminal 27. The digits are output.

[0112] Next, during a period t3, the potentials input to the terminals 21 and 24 are at a high level, 22, the potential input to the terminal 23 and the terminal 26 becomes low level, and therefore, the potential input to the terminal 25 becomes high level. A high-level potential is output from terminal 25, and a low-level potential is output from terminal 27.

[0113] Next, during a period t4, the potentials input to the terminals 22 and 24 are at a high level, 21, the potential input to the terminal 23 and the terminal 26 becomes low level, and therefore, A low level potential is output from terminal 27.

[0114] Next, in periods t5 and t6, the potential input to the terminal 22 is at a high level, Since the potentials input to terminals 21, 23, 24, and 26 are at a low level, A low level potential is output from terminal 25, and a high level potential is output from terminal 27.

[0115] Next, during a period t7, the potentials input to the terminals 23 and 26 are at a high level, Since the potential input to terminals 21, 22 and 24 is at a low level, a low voltage is output from terminal 25. A low level potential is output from terminal 27.

[0116] Next, FIG. 8(C) shows another timing chart of the pulse output circuit shown in FIG. 8(A). The periods t1 to t7 shown in FIG. 8C are of the same length. The periods t1 to t7 are determined by the first scanning line driving circuit clock signal ( 1 / 3 of the pulse width of the clock signal (GCK1) to the clock signal (GCK4) for the fourth scanning line driving circuit. The first pulse width control signal (PWC1) to the sixth pulse width control signal (P WC6) respectively.

[0117] The pulse output circuit shown in FIG. 8A receives an input to the terminal 21 during the period t1 to t3. The potential input to the terminals 22, 23, 24 and 26 is at a high level. becomes low level, a low level potential is output from terminal 25 and a low level potential is output from terminal 27. The digits are output.

[0118] Next, during the period t4 to t6, the potentials input to the terminals 22 and 24 are set to high. Since the potentials input to the terminals 21, 23 and 26 are at a low level, A high level potential is output from terminal 25, and a high level potential is output from terminal 27.

[0119] <Example of operation of the scanning line driving circuit during the full-color image display period 301> Next, taking the scanning line driving circuit 11 explained with reference to FIGS. 6, 7 and 8(A) as an example, In the full-color image display period 301 shown in FIG. 3, the operation of the scanning line driving circuit 11 We will explain about this.

[0120] FIG. 9 shows a timing chart of the scanning line driving circuit 11 during the full-color image display period 301. 9 shows an example of a subframe period SF1, a subframe period SF2, and a subframe period SF3. The frame period SF3 is set to one frame period. A timing chart of the sub-frame period SF1 is shown as a representative example in FIG. FIG. 9 illustrates the case where m=3j.

[0121] In FIG. 9, the scanning lines GL1 to GLj are connected to the pixels in the area 101, and the scanning lines GL j+1 to GL2j are connected to the pixels of the region 102, and the scanning lines GL2j+1 to GL2j are connected to the pixels of the region 102. The timing chart shows an example in which the scan line GL3j is connected to the pixels in the area 103. do.

[0122] The first scanning line driving circuit clock signal (GCK1) periodically goes to a high level potential (high voltage A duty cycle that alternates between a low-level potential (Vdd) and a low-level potential (Vss). The second scanning line driving circuit clock signal (GCK2) has a ratio of 1 / 4. is a signal whose phase is delayed by 1 / 4 cycle from the clock signal (GCK1) for the first scanning line driving circuit. The third scanning line driving circuit clock signal (GCK3) is a clock signal for the first scanning line driving circuit. This signal is delayed by 1 / 2 cycle from the clock signal (GCK1) for the fourth scanning line drive. The clock signal for the first scanning line driving circuit (GCK4) is a clock signal for the first scanning line driving circuit (GCK1). It is a signal that is delayed in phase by 3 / 4 period from

[0123] The first pulse width control signal (PWC1) periodically changes to a high level potential (high power supply potential (Vd d)) and low-level potential (low power supply potential (Vss)) are repeated, with a duty ratio of 1 / The second pulse width control signal (PWC2) is a signal of the first pulse width control signal. The third pulse width control signal (PW C3) is a signal whose phase is delayed by 1 / 3 period from the first pulse width control signal (PWC1). The fourth pulse width control signal (PWC4) is a signal obtained by multiplying the first pulse width control signal (PWC1) by 1. The fifth pulse width control signal (PWC5) is a signal delayed by 1 / 2 cycles in phase with the first pulse. The sixth pulse width control signal (PWC1) is delayed by 2 / 3 cycles. The signal (PWC6) is delayed by 5 / 6 cycles in phase from the first pulse width control signal (PWC1). It's a signal.

[0124] In FIG. 9, the first scanning line driving circuit clock signal (GCK1) to the fourth scanning line Pulse width of the drive circuit clock signal (GCK4) and the first pulse width control signal (PWC1) The pulse width ratio of the first to sixth pulse width control signals (PWC6) is 3:2.

[0125] In each sub-frame period SF, the pulse of the start pulse signal (GSP) for the scanning line driving circuit is The start pulse signal for the scanning line driver circuit (GS P) has a pulse width of the clock signal for the first scanning line driving circuit (GCK1) to the clock signal for the fourth scanning line It is about the same as the clock signal for the driving circuit (GCK4). The falling edge of the potential of the pulse of the scan pulse signal (GSP) and the The rising edges of the potentials of the clock signal (GCK1) pulses are synchronized. The falling edge of the potential of the pulse of the start pulse signal (GSP) for the scanning line driving circuit is The first pulse width control signal (PWC1) has a potential that is generated from the rising edge of the first pulse width control signal (PWC1). It appears with a delay of 1 / 6 period of the pulse width control signal (PWC1).

[0126] Then, in response to the above signal, the pulse output circuit shown in FIG. 8(A) outputs the timing chart shown in FIG. 8(B). Therefore, as shown in FIG. 9, Selection signals with pulses sequentially shifted are applied to the scanning lines GL1 to GLj. Moreover, the pulses of the selection signals given to the scanning lines GL1 to GLj have a pulse width of 2. The phase is shifted so as to be delayed for a period equivalent to three-thirds of the scanning line. The pulse width of the selection signal given to the scan line GLj is set to the first pulse width control signal (PWC1). The pulse width is approximately the same as that of the sixth pulse width control signal (PWC6).

[0127] Similarly to the case of the area 101, the scanning lines GLj+1 to G A selection signal with pulses sequentially shifted is given to the scanning line GLj+. The pulse of the selection signal given to the scanning lines GL1 to GL2j corresponds to 2 / 3 of the pulse width. The phase is shifted so as to be delayed during this period. The pulse width of the selection signal given to the first pulse width control signal (PWC1) to the sixth pulse width control signal (PWC2) is It is approximately the same as the pulse width of the pulse width control signal (PWC6).

[0128] Similarly to the case of the area 101, the scanning lines GL2j+1 to GL2j+2 corresponding to the area 103 are A selection signal with pulses sequentially shifted is given to the scanning line GL3j. The pulse of the selection signal given to the j+1 to GL3j scanning lines corresponds to 2 / 3 of the pulse width. The phase is shifted so as to be delayed during the period from the scanning line GL2j+1 to the scanning line G The pulse width of the selection signal given to L3j is determined by the first pulse width control signal (PWC1) to the second pulse width control signal (PWC2). The pulse width is approximately the same as that of the pulse width control signal (PWC6) of 6.

[0129] Then, the selection signals given to the scanning lines GL1, GLj+1, and GL2j+1 are The pulses are sequentially shifted so that the phase is delayed by a period equal to half the pulse width. .

[0130] <Example of operation of the scanning line driving circuit during the monochrome still image display period 303> Next, taking the scanning line driving circuit 11 explained with reference to FIGS. 6, 7 and 8(A) as an example, In the monochrome still image display period 303 shown in FIG. 3, the operation of the scanning line driving circuit 11 We will explain about this.

[0131] FIG. 10 shows the timing chart of the scanning line driving circuit 11 during the monochrome still image display period 303. FIG. 10 shows an example of a graph showing a write period in which an image signal is written to a pixel, and a The holding period for holding the image signal is set to one frame period. are.

[0132] First scanning line driving circuit clock signal (GCK1) to fourth scanning line driving circuit clock signal (GCK2) The signal (GCK4) can be the same as that in FIG.

[0133] The first pulse width control signal (PWC1) and the fourth pulse width control signal (PWC4) are During the first third of the reading period, the high level potential (high power supply potential ( Vdd) and low-level potential (low power supply potential (Vss)) are repeated, and the duty ratio is The signal is a half-power signal, and the other periods have a low-level potential. The fourth pulse width control signal (PWC4) is a signal obtained by dividing the first pulse width control signal (PWC1 ) is a signal with a phase delay of 1 / 2 period.

[0134] The second pulse width control signal (PWC2) and the fifth pulse width control signal (PWC5) are During the middle third of the write period, the high level potential (high voltage) is periodically A duty cycle that alternates between a low-level potential (Vdd) and a low-level potential (Vss). A signal with a ratio of 1 / 2 and a low level potential during other periods. The fifth pulse width control signal (PWC5) is a signal obtained by dividing the second pulse width control signal ( This signal is delayed by 1 / 2 cycle from PWC2.

[0135] The third pulse width control signal (PWC3) and the sixth pulse width control signal (PWC6) are During the last third of the write period, the high-level potential (high power supply The duty cycle repeats between low-level potential (Vdd) and low-level potential (low power supply potential (Vss)). A signal with a 1 / 2 ratio and a low level potential during other periods The sixth pulse width control signal (PWC6) is a signal obtained by dividing the third pulse width control signal (P WC3) is a signal with a phase delay of 1 / 2 period.

[0136] In FIG. 10, the first scanning line driving circuit clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK2) are The pulse width of the clock signal (GCK4) for the line driver circuit and the first pulse width control signal (PWC1 The ratio of the pulse widths of the first to sixth pulse width control signals (PWC6) is 1:1.

[0137] The frame period F is a period during which the voltage of the pulse of the start pulse signal (GSP) for the scanning line driving circuit is The start pulse signal (GSP) for the scanning line driver circuit starts at the falling edge of the The pulse width is set to the first scanning line driving circuit clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK2). The clock signal (GCK4) for the scanning line driver circuit is about the same as the start pulse The falling edge of the potential of the signal (GSP) pulse and the first scanning line driving circuit clock The rising edges of the potentials of the pulses of the signal (GCK1) are synchronized. The falling edge of the potential of the pulse of the start pulse signal (GSP) for the drive circuit and the first pulse The rising edge of the potential of the pulse of the pulse width control signal (PWC1) is synchronized.

[0138] Then, in response to the above signal, the pulse output circuit shown in FIG. 8(A) outputs the timing chart shown in FIG. 8(C). Therefore, as shown in FIG. Selection signals with pulses sequentially shifted are applied to the scanning lines GL1 to GLj. Furthermore, the pulses of the selection signals given to the scanning lines GL1 to GLj have a pulse width of The phase is shifted so as to be delayed for the corresponding period. The pulse width of the selection signal given to j is determined by the first pulse width control signal (PWC1) to the sixth pulse width control signal (PWC2). It is approximately the same as the pulse width of the pulse width control signal (PWC6).

[0139] In addition, pulses are sequentially shifted to all of the scanning lines GL1 to GLj corresponding to the area 101. When the selection signal is given, the scanning lines GLj+1 to GLj+2 corresponding to the area 102 are selected. A selection signal with pulses sequentially shifted is also given to the scanning line GL The pulse of the selection signal given to the j+1 to GL2j scan lines has a period corresponding to the pulse width. The phase is shifted so as to be delayed. The pulse widths of the selection signals to be used are the first pulse width control signal (PWC1) to the sixth pulse width control signal (PWC2). It is approximately the same as the pulse width of the control signal (PWC6).

[0140] Also, pulses are sequentially applied to all of the scanning lines GLj+1 to GL2j corresponding to the region 102. When the shifted selection signal is given, the scan line GL2j+1 corresponding to the region 103 is The scanning lines GL3j to GL3j are also supplied with selection signals whose pulses are sequentially shifted. The pulse of the selection signal given to the scanning lines GL2j+1 to GL3j corresponds to the pulse width The phase is shifted so as to be delayed during the period from the scanning line GL2j+1 to the scanning line G The pulse width of the selection signal given to L3j is determined by the first pulse width control signal (PWC1) to the second pulse width control signal (PWC2). The pulse width is approximately the same as that of the pulse width control signal (PWC6) of 6.

[0141] Next, in the hold period, the supply of the drive signal and the power supply potential to the scanning line drive circuit 11 is stopped. Specifically, first, the supply of the start pulse signal (GSP) for the scanning line driving circuit is stopped. As a result, the output of the selection signal from the pulse output circuit in the scanning line driving circuit 11 is stopped, and all Then, the selection of all the scanning lines by the pulse is completed. The supply of the power supply potential Vdd is stopped. Note that the stop of input or supply means, for example, that the signal or potential The wiring to which the signal or potential has been input is brought into a floating state, or the wiring to which the signal or potential has been input is brought into a floating state. This means that a low level potential is applied to the It is possible to prevent the scanning line driving circuit 11 from malfunctioning. The first scanning line driving circuit clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK2) signal (GCK4), the first pulse width control signal (PWC1) to the sixth pulse width control signal (P The supply of WC6) to the scanning line driving circuit 11 may be stopped.

[0142] By stopping the supply of the drive signal and the power supply potential to the scanning line drive circuit 11, the scanning lines GL1 to Scanning line GLj to scanning line GLj, scanning line GLj+1 to scanning line GL2j, and scanning line GL2j+1 to scanning line GL2j A low level potential is applied to all the scan lines GL3j.

[0143] In addition, in the monochrome moving image display period 302, the scanning line driving circuit 1 The operation of 1 is the same as that of monochrome still image display period 303.

[0144] In one embodiment of the present invention, a transistor with extremely low off-state current is used in a pixel, The period during which the voltage applied to the element is maintained can be extended. This allows a longer hold period to be secured, and the scanning line drive is easier than when the operation shown in Figure 9 is performed. The driving frequency of the circuit 11 can be lowered, and therefore power consumption can be reduced. It is possible to realize a liquid crystal display device that can

[0145] <Configuration Example of Signal Line Driver Circuit 12> FIG. 11 is a diagram showing a configuration example of the signal line driver circuit 12 included in the liquid crystal display device shown in FIG. 2(A). The signal line driver circuit 12 shown in FIG. 11 has first to n-th output terminals. a shift register 120 for transferring image signals (DATA) to signal lines SL1 to SLn; and a switching element group 123 for controlling the supply.

[0146] Specifically, the switching element group 123 includes transistors 121_1 to 121_2. The transistors 121_1 to 121_n are the first The first terminal is connected to the wiring that supplies the image signal (DATA), and the second terminal is connected to the signal line The transistors 121_1 to 121_n are connected to the signal lines SL1 to SLn, respectively. The gate electrodes of the transistors 121_n are connected to the first output terminal to the n-th output terminal, respectively. It has been done.

[0147] The shift register 120 receives a start pulse signal (SSP) for the signal line driver circuit and a signal It operates according to drive signals such as the clock signal (SCK) for the signal line drive circuit, and pulses are sent in order. The next shifted signal is output from the first output terminal to the nth output terminal. When an input is made to the electrode, the transistors 121_1 to 121_n are sequentially It turns on.

[0148] FIG. 12A shows the image signal supplied to the signal line during the full-color image display period 301. 11 is a diagram showing an example of the timing of (DATA). As shown in FIG. 12(A), the pulses of the selection signals input to the two scanning lines overlap. During this period, the image signal (DATA) corresponding to the scanning line on which the pulse first appeared is sampled. Specifically, the selection signal input to the scanning line GL1 is The pulse of the selection signal input to the scanning line GLj+1 is set to 1 / 2 of the pulse width. The scanning lines GL1 and GLj+1 overlap in the corresponding period t4. The first pulse appears on the scanning line GL1. During this period, the image signal (DATA) corresponding to the scanning line GL1 is ta1) is sampled and input to signal lines SL1 to SLn.

[0149] Similarly, during the period t5, the image signal (dataj+1) corresponding to the scanning line GLj+1 is The signals are sampled and input to the signal lines SL1 to SLn. The image signal (data2j+1) corresponding to the scan line GL2j+1 is sampled, and the signal line In the period t7, the image signal corresponding to the scanning line GL2 is input to the signal lines SL1 to SLn. The signal (data2) is sampled and input to the signal lines SL1 to SLn. Then, the same operation is repeated after the period t8, and an image signal is transmitted to the pixel portion. (DATA) is written.

[0150] That is, the image signals are input to the signal lines SL1 to SLn through the scanning lines GLs (s is j), then the pixels connected to the scan line GLj+s, then the pixels connected to the scan line GLj+s, Then, the pixel connected to the scanning line GL2j+s, and then the pixel connected to the scanning line GLs+1 , in that order.

[0151] FIG. 12B shows the monochrome moving image display period 302 and the monochrome still image display period 303. An example of the timing of the image signal (DATA) supplied to the signal line during the writing period. In the signal line driving circuit 12 shown in FIG. 11, as shown in FIG. 12(B), During the period when a pulse of the selection signal input to the scanning line appears, The image signal (DATA) is sampled and input to each signal line. During the period when the pulse of the selection signal input to the scanning line GL1 appears, the image signal (DA TA), the image signal (data1) corresponding to the scanning line GL1 is sampled, and the signal The signals are input to signal lines SL1 to SLn.

[0152] Similarly, the same operation is repeated for all the subsequent scanning lines after the scanning line GL1. As a result, an image signal (DATA) is written to the pixel portion.

[0153] In addition, during the hold period of the monochrome still image display period 303, Supply of start pulse signal (SSP) for signal line driver circuit and signal of image signal (DATA) Specifically, first, the starter pad for the signal line driving circuit 12 is turned off. By stopping the supply of the signal line signal (SSP), the signal line driver circuit 12 After that, the supply of the image signal to the signal line driving circuit 12 and the power supply potential By the above method, when the operation is stopped, the signal line driving circuit 12 is prevented from malfunctioning. In addition to the above configuration, the signal line driving circuit 12 can be prevented from operating. The supply of the clock signal (SCK) for the line driver circuit may be stopped.

[0154] <Example of operation of a liquid crystal display device> FIG. 13 shows the selection of the liquid crystal display device described above during the full-color image display period 301. 1 is a diagram showing the timing of signal scanning and the timing of backlight lighting. In FIG. 13, the vertical axis represents the row in the pixel unit, and the horizontal axis represents time.

[0155] As shown in FIG. 13, in the liquid crystal display device according to the present embodiment, during a full-color image display period In 301, after supplying a selection signal to the scanning line GL1, the scanning line GLj, which is j rows ahead, It is possible to use a driving method that supplies a selection signal to +1. In the same sub-frame period SF, n pixels connected to the scanning line GL1 are n pixels connected to the scanning line GLj are sequentially selected, and n pixels connected to the scanning line GLj+1 are sequentially selected. n pixels connected to the scanning line GL2j are sequentially selected from the pixel of Select n pixels connected to scan line GL3j from n pixels connected to +1 in sequence. This makes it possible to input an image signal to each pixel.

[0156] Specifically, in FIG. 13, in the first sub-frame period SF1, scanning lines GL1 to GL3 are After writing the image signal corresponding to red (R) to the pixel connected to the line GLj, The red (R) light is supplied to the connected pixel. In the region 101 of the pixel portion corresponding to GLj, an image corresponding to red (R) is displayed. can be done.

[0157] In the first sub-frame period SF1, the scanning lines GLj+1 to GL2j are After writing the image signal corresponding to green (G) to the connected pixel, Green (G) light is supplied to the pixel. In the region 102 of the pixel portion corresponding to j, an image corresponding to green (G) can be displayed. Cut.

[0158] In the first sub-frame period SF1, the scanning lines GL2j+1 to GL3j After writing the image signal corresponding to blue (B) to the pixel connected to the scan line, With the above configuration, blue (B) light is supplied to the pixels that have been scanned. In the region 103 of the pixel portion corresponding to L3j, an image corresponding to blue (B) is displayed. can be done.

[0159] Next, in the second sub-frame period SF2 and the third sub-frame period SF3, The same operation as in the first subframe period SF1 is repeated. However, in the second subframe period In the interval SF2, in the region 101 of the pixel portion corresponding to the scanning line GL1 to the scanning line GLj, Displays the image corresponding to blue (B), and the pixels corresponding to the scan line GLj+1 to the scan line GL2j In the area 102 of the image display, an image corresponding to red (R) is displayed, and the image is scanned from the scanning line GL2j+1. In the pixel area 103 corresponding to the scan line GL3j, an image corresponding to green (G) is displayed. In the third sub-frame period SF3, the signals corresponding to the scanning lines GL1 to GLj are In the pixel area 101, an image corresponding to green (G) is displayed, and the scanning lines GLj+1 to GLj+3 are In the pixel area 102 corresponding to the scanning line GL2j, an image corresponding to blue (B) is displayed. In the pixel area 103 corresponding to the scanning lines GL2j+1 to GL3j, Displays the image corresponding to red (R).

[0160] Then, in all the scanning lines GL, the first sub-frame period SF1 to the third sub-frame period SF2 are When the frame period SF3 ends, that is, when one frame period ends, a full-color image is displayed. can be displayed on the pixel portion.

[0161] In one aspect of the present invention, each region is further divided, and an image signal is generated in each divided region. When the writing of the signal is completed, the backlight may be sequentially turned on. For example, in the area 101, scanning lines GL1 to GLh (h is a natural number equal to or less than j / 4) are After writing the image signal corresponding to red (R) to the pixel connected to the scan line GLh+ 1 to GL2h, while writing the image signal corresponding to red (R) to the pixels connected to the scan line GL3h. The red (R) light is supplied to the pixels connected to the scan lines GL1 to GLh. You can do that too.

[0162] FIG. 14 shows the monochrome still image display period 303 in the liquid crystal display device described above. 10 is a diagram showing the timing of scanning the selection signal and the timing of lighting the backlight. FIG. In FIG. 14, the vertical axis represents the row in the pixel unit, and the horizontal axis represents time.

[0163] As shown in FIG. 14, in the liquid crystal display device shown in this embodiment, during a monochrome still image display period In 303, selection signals are sequentially supplied to the scanning lines GL1 to GL3j.

[0164] Specifically, in FIG. 14, for example, in the area 101, the area connected to the scanning line GL1 to the scanning line GLh is After writing the image signal to the connected pixels, the backlight remains off without lighting up. . Then, by performing the same operation on the pixels connected to all subsequent scanning lines, After that, the supply of the driving signal to the driving circuit is stopped. and puts the drive circuit in a non-operating state.

[0165] In the monochrome moving image display period 302, the upper and lower pixels connected to all the scanning lines After the above operation is performed, the drive circuit is not put into a non-operating state and the same operation is repeated again to obtain a monochrome image. All that is required is to display the images continuously on the pixel portion.

[0166] In the liquid crystal display device according to one embodiment of the present invention, red (R) and green (G) light sources are used as the backlight. The liquid crystal display device of the present invention uses a light source corresponding to three colors, i.e., blue (B), green (C), and blue (D). In other words, the liquid crystal display device of the present invention can display any color. It is possible to use a combination of backlights using light sources, for example, red (R), Green (G), Blue (B), White (W) or Red (R), Green (G), Blue (B), Yellow (Y) Use a combination of colors, or three colors: cyan (C), magenta (M), and yellow (Y). It is possible to use a combination of colors.

[0167] In addition, instead of forming white (W) light by mixing colors, a light source that emits white (W) light is used. The light source that emits white (W) light has high luminous efficiency. Therefore, by using this light source to configure a backlight, it is possible to reduce power consumption. In addition, when the backlight has a light source that emits two colors of light that are complementary to each other ( For example, if there are two colors, blue (B) and yellow (Y), the light that exhibits these two colors is mixed. It is also possible to create white (W) light by using a light source. , and blue (B), and a combination of six colors: dark red (R), green (G), and blue (B). Use red (R), green (G), blue (B), cyan (C), magenta (M), yellow It is also possible to use a combination of the six low (Y) colors.

[0168] For example, colors that can be expressed using red (R), green (G), and blue (B) light sources are expressed as chromaticity The colors are limited to those shown inside the triangle formed by the three points on the diagram that correspond to each luminous color. Therefore, by adding a light source whose emission color is outside the triangle on the chromaticity diagram, the liquid crystal This makes it possible to expand the color gamut that can be displayed on a display device and to enrich color reproducibility.

[0169] For example, from the center of the chromaticity diagram, roughly outward toward the point on the chromaticity diagram that corresponds to blue illuminant B. Deep Blue (DB) is represented by a point located at the center of the chromaticity diagram, and red is represented by a point located at the center of the chromaticity diagram. A deeper red, represented by a point located roughly outward toward the point on the chromaticity diagram corresponding to illuminant R. A light source that emits a color (Deep Red: DR) is divided into red (R), green (G), and blue (B) light. It can be used in addition to a backlight with a source.

[0170] As a backlight source, it consumes less power than a cold cathode fluorescent lamp and allows for the intensity of light to be adjusted. It is preferable to use multiple light emitting diodes (LEDs) that can be adjusted. By using D, the intensity of light can be adjusted partially, and the contrast is high and the color visibility is good. It is possible to display high-quality images.

[0171] In addition, before and after the period in which one image is formed in the pixel section, the scanning of the selection signal and the backlight are performed. It is also possible to provide a period during which the light unit is not lit (light-off period). .

[0172] In addition, a plurality of frame periods in which the backlight lights up in different orders may be provided. This can further reduce the occurrence of color breakup.

[0173] <Pulse output circuit configuration example 2> 19(A) shows another example of the configuration of the pulse output circuit. The output circuit has a configuration in which a transistor 50 is added to the pulse output circuit shown in FIG. The transistor 50 has a first terminal connected to a node to which a high power supply potential is applied. and its second terminal is connected to the gate electrode of transistor 32, the gate electrode of transistor 34, and and the gate electrode of transistor 39. Transistor 50 is connected to the gate of The reset electrode is connected to the reset terminal (Reset).

[0174] The reset terminal is connected to the backlight after the hue of the backlight has been switched in the pixel section. In the latter period, a high level potential is input, and in the other periods, a low level potential is input. The transistor 50 is turned on by inputting a high-level potential. This allows the backlight to remain lit for a period after the In this case, the potential of each node can be initialized, making it possible to prevent malfunctions. This becomes:

[0175] When the initialization is performed, the initialization is performed between periods when one image is formed in the pixel section. It is necessary to provide an initialization period. Also, after forming one image on the pixel area, the backlight is turned off. In this case, the initialization can be performed during the period when the light is turned off.

[0176] 19B shows another example of the configuration of the pulse output circuit. The output circuit has a configuration in which a transistor 51 is added to the pulse output circuit shown in FIG. The first terminal of the transistor 51 is connected to the second terminal of the transistor 31 and the The second terminal of the transistor 32 is connected to the gate electrode of the transistor 33 and the second terminal of the transistor 34. The gate electrode of the transistor 51 is connected to the gate electrode of the transistor 38. is connected to a node to which a high power supply potential is applied.

[0177] Note that the transistor 51 is in a state where ... Therefore, by adding the transistor 51, the period t During periods t1 to t6, the gate electrode of the transistor 33 and the gate electrode of the transistor 38 The connection between the electrode and the second terminal of the transistor 31 and the second terminal of the transistor 32 is interrupted. As a result, during the period from period t1 to period t6, It is possible to reduce the load during the bootstrap operation performed in the pulse output circuit.

[0178] 20(A) shows another example of the configuration of the pulse output circuit. The output circuit has a configuration in which a transistor 52 is added to the pulse output circuit shown in FIG. 19(B). The transistor 52 has a first terminal connected to the gate electrode of the transistor 33 and a second terminal connected to the gate electrode of the transistor 33. The second terminal of the resistor 51 is connected to the gate electrode of the transistor 38. The transistor 52 has a gate electrode to which a high power supply potential is applied. connected to the node.

[0179] By providing the transistor 52, the bootstrap performed in the pulse output circuit In particular, the load during pulse output operation can be reduced. The gate electrode of transistor 33 is connected to the source electrode of transistor 33 only by capacitive coupling between the source electrode and the gate electrode of transistor 33. Increasing the potential of the node connected to the load resistor R1 has a significant effect of reducing the load.

[0180] 20(B) shows another example of the configuration of the pulse output circuit. The output circuit is the same as the pulse output circuit shown in FIG. 20(A) except that the transistor 51 is removed. The transistor 53 has a first terminal connected to the transistor The second terminal of the transistor 31, the second terminal of the transistor 32, and the first terminal of the transistor 52 are connected to the The second terminal of the transistor 31 is connected to the gate electrode of the transistor 33. The transistor 53 has its gate electrode connected to a node to which a high power supply potential is applied.

[0181] By providing the transistor 53, the bootstrap performed in the pulse output circuit It is possible to reduce the load during pulse operation. This reduces the effect of the pulse on the switching of transistors 33 and 38. It is possible.

[0182] As described in this embodiment, a liquid crystal display device according to one embodiment of the present invention has a pixel portion divided into a plurality of regions. The color image is displayed by dividing the display into regions and sequentially supplying light of different hues to each region. Therefore, when focusing on a specific time, the hues of the light supplied to adjacent areas can be set to different values. This prevents the images of each color from being viewed individually without being combined. This prevents color breaks that often occur when displaying video. .

[0183] When a color image is displayed using a plurality of light sources having different hues, a monochromatic light source Unlike the case where a color filter is combined with the above multiple light sources, the above multiple light sources are switched sequentially to emit light. The frequency at which the light source is switched is set to a value that is higher than that of a monochromatic light source. For example, if a monochromatic light source is used, the frame frequency must be set to a value higher than the frame frequency when the If the frame frequency is 60Hz, the light sources corresponding to the red, green, and blue colors are used. When FS drive is used, the frequency of switching the light source is approximately three times higher, at 180 Hz. The driving circuit also operates in accordance with the frequency of the light source, so it can operate at a very high frequency. Therefore, the power consumption in the drive circuit is It tends to be more expensive than when combined.

[0184] However, in one embodiment of the present invention, a transistor with extremely low off-state current is used, This allows the period during which the voltage applied to the liquid crystal element is maintained to be longer. The drive frequency when displaying can be lower than the drive frequency when displaying moving images. Therefore, a liquid crystal display device capable of reducing power consumption can be realized.

[0185] (Embodiment 2) In this embodiment, a liquid crystal display according to one aspect of the present invention, which has a panel configuration different from that of the first embodiment, is used. An example of a display device will now be described. <Panel configuration example> A specific configuration of a panel according to one embodiment of the present invention will be described with reference to an example.

[0186] 15(A) is a diagram showing an example of the configuration of a liquid crystal display device. The device has a pixel section 60, a scanning line driving circuit 61, and a signal line driving circuit 62. In one embodiment, the pixel section 60 is divided into a plurality of regions. Specifically, in FIG. 15(A), The pixel section 60 is divided into three regions (regions 601 to 603) as an example. Each region has a plurality of pixels 615 arranged in a matrix.

[0187] The pixel section 60 also includes m scanning lines GL whose potentials are controlled by a scanning line driving circuit 61. and 3×n signal lines SL whose potentials are controlled by a signal line driving circuit 62. The m scanning lines GL are arranged in a plurality of groups in accordance with the number of regions that the pixel section 60 has. For example, in the case of FIG. 15A, the pixel section 60 is divided into three regions. Therefore, the m scanning lines GL are also divided into three groups. The scanning lines GL belonging to the group are assigned to a plurality of pixels 615 in the area corresponding to the group. Specifically, the scanning lines GL are arranged in a matrix in each region. Of the plurality of pixels 615, n pixels 615 arranged in any one row are connected.

[0188] The signal lines SL are also divided into a plurality of groups in accordance with the number of regions that the pixel section 60 has. For example, in the case of FIG. 15(A), the pixel section 60 is divided into three regions. The 3×n signal lines SL are also divided into three groups. The signal line SL is connected to a plurality of pixels 615 in the area corresponding to the group. There are.

[0189] Specifically, in FIG. 15A, 3×n signal lines SL are divided into n signal lines SLa and n signal lines SLa. The example shown is a case where the signal line SLb is composed of n signal lines SLc. In FIG. 15A, n signal lines SLa are arranged in a matrix in an area 601. When the pixel 615 is connected to a pixel 615 arranged in one of the columns of the plurality of pixels 615, In FIG. 15A, n signal lines SLb are arranged in the region 602. Among the plurality of pixels 615 arranged in a matrix, the pixels 61 arranged in any one of the columns 15A, n signal lines SLc However, among the plurality of pixels 615 arranged in a matrix in the region 603, Illustrated is a case where the pixels 615 are connected to a column.

[0190] 15B, 15C, and 15D show pixel 61 in region 601. 5, corresponding to the circuit diagram of pixel 615 in region 602 and pixel 615 in region 603 The pixel 615 has the same configuration in all areas. a transistor 616 that functions as a A liquid crystal element 618 whose transmittance is controlled according to the potential and a pixel included in the liquid crystal element 618 The capacitor 617 holds the voltage between the electrode and the counter electrode.

[0191] However, as shown in FIG. 15B, in the region 601, the signal A signal line SLa, a signal line SLb, and a signal line SLc are provided. In the pixel 615, the gate electrode of the transistor 616 is connected to the scanning line GL. The first terminal of the resistor 616 is connected to the signal line SLa, and the second terminal of the resistor 616 is connected to the liquid crystal element 61. One electrode of the capacitor element 617 is connected to the pixel electrode of the liquid crystal element 618. The other electrode is connected to a node at a specific potential. There are.

[0192] 15C, in the region 602, the signal line 615 is arranged adjacent to the pixel 615. In the region 602, the pixel 615 is provided with a transistor. The gate electrode of the transistor 616 is connected to the scanning line GL. The first terminal is connected to the signal line SLb, and the second terminal is connected to the pixel electrode of the liquid crystal element 618. One electrode of the capacitor element 617 is connected to a pixel electrode of the liquid crystal element 618. The other electrode is connected to a node to which a specific potential is applied.

[0193] 15D, in the region 603, the signal line 615 is adjacent to the pixel 615. SLc is provided. In the region 603, the pixel 615 has a transistor 61 The gate electrode of the transistor 616 is connected to the scanning line GL. The second terminal of the signal line SLc is connected to the pixel electrode of the liquid crystal element 618 . One electrode of the capacitor element 617 is connected to a pixel electrode of the liquid crystal element 618, and the other electrode The poles are connected to nodes at specific potentials.

[0194] In all the pixels 615, a specific potential is also applied to the counter electrode of the liquid crystal element 618. The potential applied to the counter electrode is the other potential of the capacitor 617. It may be common to the potential applied to the electrode.

[0195] The pixel 615 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may further include other circuit elements such as a capacitance.

[0196] In one embodiment of the present invention, the transistor 616 functioning as the switching element The channel formation region of the semiconductor has a wider band gap than silicon semiconductors and an intrinsic carrier density The semiconductor having the above-mentioned properties may include a semiconductor having a lower resistance than a silicon semiconductor. By including a conductive material in the channel formation region, the off-current is extremely low and the breakdown voltage is high. The transistor 616 having the above structure can be realized. By using 616 as a switching element, it is possible to Compared to when a transistor made of a conductive material is used, the amount of charge stored in the liquid crystal element 618 is This can prevent leakage of electric charge.

[0197] By using a transistor 616 with extremely low off-state current, This allows the voltage to be maintained for a long period of time. Image signals having the same image information are written to the pixel section 60 over several frame periods. In this case, the driving frequency is lowered, in other words, the pixel unit 6 within a certain period of time. Even if the number of times the image signal is written to 0 is reduced, the image display can be maintained. For example, the above-mentioned i-type or substantially i-type oxide semiconductor film is used as an active layer. By using the transistor 616, the interval between writing of image signals can be set to 10 seconds or more, which is preferable. The time can be set to 30 seconds or more, and more preferably 1 minute or more. The longer the write interval, the more power consumption can be reduced.

[0198] Furthermore, since the potential of the image signal can be maintained for a longer period of time, the potential of the image signal can be In order to maintain the pixel position, the image displayed can be displayed without connecting the capacitor element 617 to the liquid crystal element 618. Therefore, the capacitor 617 is not required, or the capacitor 618 is required. Even if the size of the element 617 is kept small, the aperture ratio can be increased. This can reduce the power consumption.

[0199] In addition, inversion driving is performed to invert the polarity of the potential of the image signal based on the potential of the counter electrode. This prevents the deterioration of the liquid crystal known as burn-in. When the polarity of the image signal changes, the change in the potential applied to the signal line becomes large, The potential difference between the source electrode and the drain electrode of the transistor 616 functioning as an etching element is Therefore, the transistor 616 may experience characteristic degradation such as a shift in threshold voltage. In addition, in order to maintain the voltage held in the liquid crystal element 618, the source voltage Even if the potential difference between the electrode and the drain electrode is large, the off-state current is required to be low. In an embodiment, transistor 616 is made of a material having a bandgap lower than that of silicon or germanium. Since the transistor uses a semiconductor such as an oxide semiconductor with a large size and low intrinsic carrier density, Therefore, the breakdown voltage of the transistor 616 can be increased and the off-state current can be significantly reduced. Compared to using transistors made of semiconductor materials such as silicon or germanium, This prevents the transistor 616 from deteriorating and maintains the voltage held in the liquid crystal element 618. This can be done.

[0200] 15B to 15D, in the pixel 615, one transistor 616 However, the present invention is not limited to this configuration. It is also possible to use a plurality of transistors that function as a single switching element. When a plurality of transistors function as one switching element, The resistors may be connected in parallel, in series, or in both series and parallel. They may also be combined and connected.

[0201] <Configuration example of scanning line driving circuit 61> FIG. 16 is a diagram showing an example of the configuration of the scanning line driving circuit 61 included in the liquid crystal display device shown in FIG. The scanning line driving circuit 61 shown in FIG. 1 to 613. Each of the output terminals of the shift register 611 has the following areas: The shift register 612 is connected to one of the j scanning lines GL arranged in the area 601. Each of the output terminals is connected to one of the j scanning lines GL arranged in the region 602. The output terminals of the shift register 613 are connected to the j scanning lines GL. That is, the shift register 611 is connected to one of the j scanning lines GL. 01, and the shift register 612 is a shift register that scans the selection signal in the area 602 is a shift register that scans the selection signal, and shift register 613 is a It is a shift register that scans the selection signal in area 603.

[0202] Specifically, the shift register 611 receives a start pulse signal (GSP) for the scanning line driving circuit. When a pulse is input, the scanning lines GL1 to GLj are sequentially pulsed in accordance with the pulse. The shift register 612 supplies a selection signal that shifts every half period. When the start pulse signal (GSP) for the driver circuit is input, the , the selection in which the pulses are shifted every 1 / 2 period from the scanning line GLj+1 to the scanning line GL2j. The shift register 613 supplies a start pulse signal (GS P), the scanning lines GL2j+1 to GL A selection signal is supplied to 3j, in which the pulses are shifted every 1 / 2 period.

[0203] The scanning line driving circuit 61 has a full-color image display period 301 and a monochrome still image display period 302. An example of the operation during the period 303 will be described with reference to FIG.

[0204] In FIG. 17, the clock signal (GCK) for the scanning line driving circuit, the scanning lines GL1 to GL2, Selection signals input to GLj, selection signals input to scanning lines GLj+1 to GL2j The timing chart of the selection signals input to the scanning lines GL2j+1 to GL3j This shows the

[0205] First, the operation of the scanning line driving circuit 61 during the full-color image display period 301 will be described. In the full-color image display period 301, a start pulse signal (GSP The first subframe period SF1 begins according to the pulse of In the interval SF1, the pulses are shifted sequentially from the scanning line GL1 to the scanning line GLj every 1 / 2 period. Also, the scanning lines GLj+1 to GL2j are supplied with a selection signal. A selection signal is supplied that shifts every 1 / 2 period. A selection signal is also supplied to the line GL3j, with the pulses being shifted every 1 / 2 period.

[0206] Then, the pulse of the start pulse signal (GSP) for the scanning line driving circuit is sent to the scanning line driving circuit again. When input to 61, the second sub-frame period SF2 starts in accordance with the pulse. In the second sub-frame period SF2, as in the first sub-frame period SF1, the scanning lines G L1 to scanning line GLj, scanning line GLj+1 to scanning line GL2j, scanning line GL2j+1 to A selection signal with sequentially shifted pulses is input to the scanning line GL3j.

[0207] Then, the pulse of the start pulse signal (GSP) for the scanning line driving circuit is sent to the scanning line driving circuit again. When input to 61, the third sub-frame period SF3 starts in accordance with the pulse. In the third sub-frame period SF3, as in the first sub-frame period SF1, the scanning lines G L1 to scanning line GLj, scanning line GLj+1 to scanning line GL2j, scanning line GL2j+1 to A selection signal with sequentially shifted pulses is input to the scanning line GL3j.

[0208] When the first sub-frame period SF1 to the third sub-frame period SF3 end, one frame is completed. The frame period ends and an image is displayed on the pixel area.

[0209] Next, the operation of the scanning line driving circuit 61 during the monochrome still image display period 303 will be described. In the monochrome still image display period 303, the full color still image is displayed during the image signal writing period. The scanning line driving circuit 61 performs the same operation as that performed in each sub-frame period in the image display period 301. It will be held.

[0210] Next, in the hold period, the supply of the drive signal and the power supply potential to the scanning line drive circuit 61 is stopped. Specifically, first, the supply of the start pulse signal (GSP) for the scanning line driving circuit is stopped. As a result, the output of the selection signal from the scanning line driving circuit 61 is stopped, and the The selection by the pulse is terminated. Then, the supply of the power supply potential to the scanning line driving circuit 61 is stopped. By the above method, when the operation of the scanning line driving circuit 61 is stopped, the scanning line driving circuit 61 In addition to the above configuration, the first scanning line driving circuit The clock signal GCK1 for the fourth scanning line driver circuit to the clock signal GCK4 for the fourth scanning line driver circuit The supply to the drive circuit 61 may be stopped.

[0211] By stopping the supply of the drive signal or power supply potential to the scanning line drive circuit 61, the scanning line GL1 to scanning lines GLj, scanning lines GLj+1 to GL2j, and scanning lines GL2j+1 to GL2j A low level potential is applied to all the scanning lines GL3j.

[0212] In addition, in the monochrome moving image display period 302, the scanning line driving circuit 6 The operation of 1 is the same as that of monochrome still image display period 303.

[0213] In one embodiment of the present invention, a transistor with extremely low off-state current is used in a pixel, The period during which the voltage applied to the element is maintained can be extended. In the still image display period 303, the retention period shown in FIG. 17 can be secured long, and full color The driving frequency of the scanning line driving circuit 61 can be made lower than that in the image display period 301. Therefore, a liquid crystal display device capable of reducing power consumption can be realized.

[0214] <Configuration Example of Signal Line Driving Circuit 62> FIG. 18 is a diagram showing an example of the configuration of the signal line driving circuit 62 shown in FIG. 15(A). The signal line driver circuit 62 includes a shift register 6 having a first output terminal to an n-th output terminal. 20, an image signal (DATA1) input to the area 601, an image signal (DATA2) input to the area 602, signal (DATA2), and the signal line SLa of the image signal (DATA3) input to the area 603 and a switching element group 623 for controlling supply to the signal line SLc.

[0215] Specifically, the switching element group 623 includes transistors 65a1 to 65a n, transistors 65b1 to 65bn, and transistors 65c1 to It has a transistor of 65cm.

[0216] The first terminals of the transistors 65a1 to 65an are connected to the image signal (DAT A1), and the second terminals thereof are connected to the wiring that supplies the signal lines SLa1 to SL The gates of the transistors 65a1 to 65an are connected to the gates of the transistors 65a1 to 65an. The port electrodes are connected to the first output terminal to the n-th output terminal of the shift register 620, respectively. It has been done.

[0217] The first terminals of the transistors 65b1 to 65bn are connected to the image signal (DAT A2), and the second terminals thereof are connected to the wiring that supplies the signal lines SLb1 to SL The gates of the transistors 65b1 to 65bn are connected to the gates of the transistors 65b1 to 65bn. The port electrodes are connected to the first output terminal to the n-th output terminal of the shift register 620, respectively. It has been done.

[0218] The first terminals of the transistors 65c1 to 65cn are connected to the image signal (DAT A3), and the second terminals thereof are connected to the wiring that supplies the signal lines SLc1 to SL The gates of the transistors 65c1 to 65cn are connected to the gates of the transistors 65c1 to 65cn. The port electrodes are connected to the first output terminal to the n-th output terminal of the shift register 620, respectively. It has been done.

[0219] The shift register 620 receives a start pulse signal (SSP) for the signal line driver circuit and a signal It operates according to drive signals such as the clock signal (SCK) for the signal line drive circuit, and pulses are sent in order. The next shifted signal is output from the first output terminal to the nth output terminal. When a signal is input to the electrodes, the transistors 65a1 to 65an and the transistors Transistors 65b1 to 65bn and transistors 65c1 to 65cn Then, the image signal (DATA1) is input to the signal line SLa, An image signal (DATA2) is input to the signal line SLb, and an image signal (DATA 3) is entered and the image is displayed.

[0220] In addition, during the hold period of the monochrome still image display period 303, Supply of a start pulse signal (SSP) for the signal line driver circuit and image signals (DATA1 to The supply of the image signal (DATA3) to the signal line driving circuit 62 is stopped. , by stopping the supply of the start pulse signal (SSP) for the signal line driver circuit, The sampling of the image signal in the circuit 62 is stopped. The supply of the image signal and the supply of the power supply potential are stopped. Furthermore, it is possible to prevent the signal line driving circuit 62 from malfunctioning. , the supply of the signal line driving circuit clock signal (SCK) to the signal line driving circuit 62 is stopped. is also good.

[0221] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0222] (Embodiment 3) In this embodiment, a method for manufacturing a transistor using an oxide semiconductor will be described.

[0223] First, as shown in FIG. 21(A), an insulating film 701 is formed on the insulating surface of a substrate 700. A gate electrode 702 is formed on the insulating film 701 .

[0224] The substrate that can be used as the substrate 700 may be any substrate that is light-transmitting. There are no major limitations on the heat resistance, but the material must at least be heat resistant enough to withstand subsequent heat treatment. For example, the substrate 700 may be made of a material such as a metal or a metal alloy, which is manufactured by a fusion method or a float method. A glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. If the temperature of the subsequent heat treatment is high, it is advisable to use a material with a strain point of 730°C or higher. A substrate made of flexible synthetic resin such as a stick generally has better heat resistance than the above substrates. Although the temperature tends to be low, it can be used if it can withstand the processing temperature in the manufacturing process. It is possible.

[0225] The insulating film 701 is made of a material that can withstand the temperature of a heat treatment in a later manufacturing process. The insulating film 701 is made of silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, or aluminum nitride. It is preferable to use aluminum, aluminum oxide, etc.

[0226] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It means substance.

[0227] The material of the gate electrode 702 is molybdenum, titanium, chromium, tantalum, tungsten, or nickel. Metallic materials such as chromium, scandium, magnesium, etc., and alloys containing these metallic materials as the main components A conductive film using such a material or a nitride of such a metal can be used as a single layer or a laminated layer. In addition, if the metal material can withstand the temperature of the heat treatment to be performed in the subsequent process, Aluminum and copper can also be used as the material. Aluminum and copper are heat-resistant and corrosion-resistant. To avoid corrosion problems, it is recommended to use it in combination with high melting point metal materials. Materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and Indium and the like can be used.

[0228] For example, a gate electrode 702 having a two-layer stack structure may be formed by depositing molybdenum on an aluminum film. Two-layer structure with a molybdenum film laminated on a copper film, two-layer structure with a molybdenum film laminated on a copper film, A two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated, or a titanium nitride film and a molybdenum nitride film are laminated. It is preferable to use a two-layer structure in which a butyl film and a butyl film are laminated. The electrode 702 may be made of an aluminum film, an aluminum-silicon alloy film, or an aluminum and A titanium alloy film or an aluminum and neodymium alloy film is used as an intermediate layer, and a tungsten film, A structure in which a tungsten nitride film, a titanium nitride film, or a titanium film is laminated as an upper and lower layer is used. It is preferable that:

[0229] The gate electrode 702 may be made of indium oxide, an indium oxide tin oxide alloy, or zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or oxide A light-transmitting conductive oxide film such as zinc gallium oxide can also be used.

[0230] The thickness of the gate electrode 702 is 10 nm or more and 400 nm or less, preferably 100 nm or more and 200 nm or less. In this embodiment, a sputtering method using a tungsten target is used. After forming a conductive film for the gate electrode of 150 nm, the conductive film is etched to the desired thickness. The gate electrode 702 is formed by processing (patterning) the gate electrode 702 into the shape shown in FIG. If the end of the gate electrode is tapered, the coverage of the gate insulating film laminated on top of it is improved. The resist mask may be formed by an ink-jet method. When a photomask is formed by the inkjet method, no photomask is used, reducing manufacturing costs. can be reduced.

[0231] Next, as shown in FIG. 21(B), a gate insulating film 703 is formed on the gate electrode 702. Then, an island-shaped oxide semiconductor is formed on the gate insulating film 703 at a position overlapping the gate electrode 702. A conductive film 704 is formed.

[0232] The gate insulating film 703 is a silicon oxide film formed by using a plasma CVD method, a sputtering method, or the like. , silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film aluminum oxide nitride film, aluminum nitride oxide film, hafnium oxide film or oxide The gate insulating film 703 can be formed as a single layer or a stack of tantalum films. It is desirable that the material contains as few impurities as possible, such as hydrogen and oxygen. When forming a silicon nitride film, a silicon target or a quartz target is used as the target. and oxygen or a mixed gas of oxygen and argon is used as the sputtering gas.

[0233] Highly purified oxide semiconductor (highly purified oxide semiconductor) ) is extremely sensitive to interface states and interface charges, so it is difficult to The interface with the gate insulating film 703 is important. The gate insulating film (GI) used in the semiconductor device is required to have high quality.

[0234] For example, high-density plasma CVD using microwaves (frequency 2.45 GHz) produces dense, high-insulation This is preferable because it allows the formation of high-quality insulating films with high pressure. The close contact with the gate insulating film reduces the interface state and improves the interface characteristics. Because it can be done.

[0235] Of course, if a good insulating film can be formed as the gate insulating film 703, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film may be one whose film quality or interface characteristics with the oxide semiconductor are improved by heat treatment. In any case, it goes without saying that the quality of the gate insulating film is good, and Any material that can reduce the interface state density between the film and the oxide semiconductor and form a good interface is acceptable. .

[0236] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 703 having a structure in which an insulating film such as a silicon dioxide film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films are used as insulating films with high barrier properties and oxide semiconductors. As an insulating film with high barrier properties, for example, a silicon nitride film or a silicon nitride oxide film is used. Examples of the film include an aluminum nitride film, an aluminum oxide film, and an aluminum nitride oxide film. By using an insulating film with high barrier properties, impurities in the atmosphere such as moisture and hydrogen can be prevented. Alternatively, impurities such as alkali metals and heavy metals contained in the substrate may be generated in the oxide semiconductor film or the gate electrode. The oxide semiconductor film penetrates into the gate insulating film 703, or into the interface between the oxide semiconductor film and another insulating film and its vicinity. In addition, when an oxide semiconductor film having a low nitrogen content is formed in contact with the oxide semiconductor film, the oxide semiconductor film can be prevented from being broken down. By forming an insulating film such as a silicon film or silicon oxynitride film, the insulating film with high barrier properties can be directly oxidized. This can prevent the metal oxide from coming into contact with the nitride semiconductor film.

[0237] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0)), and a second gate insulating film is formed on the first gate insulating film. As the insulating film, a silicon oxide film (SiO x (x>0) The gate insulating film 703 may be formed by layering the gate insulating film 703 with a thickness of 100 nm. can be set appropriately depending on the characteristics required for the transistor, and is in the range of 350 nm to 400 nm. It can be about m.

[0238] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 70 having a structure in which a silicon oxide film having a thickness of 100 nm formed by Form 3.

[0239] The gate insulating film 703 is in contact with an oxide semiconductor to be formed later. Since the inclusion of hydrogen, hydroxyl groups, and It is desirable that the gate insulating film 703 does not contain hydrogen, hydroxyl groups, and moisture. In order to prevent this from being included, preheating of the sputtering equipment is required as a pretreatment for film formation. The substrate 700 on which the gate electrode 702 is formed is preheated in a chamber, and the moisture adsorbed on the substrate 700 is removed. It is also preferable to desorb and exhaust impurities such as hydrogen. The temperature is 00°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The evacuation means provided in the chamber is preferably a cryopump. Note that this preheating process is omitted. It is also possible.

[0240] The oxide semiconductor film formed over the gate insulating film 703 is processed into a desired shape, and an island-shaped oxide semiconductor film is formed. The thickness of the oxide semiconductor film is preferably 2 nm or more and 200 nm or less. The thickness is 3 nm or more and 50 nm or less, and more preferably 3 nm or more and 20 nm or less. The conductive film is formed by sputtering using an oxide semiconductor as a target. The nitride semiconductor film is grown under a rare gas (e.g., argon) atmosphere, an oxygen atmosphere, or a rare gas (e.g., It can be formed by sputtering in a mixed atmosphere of argon and oxygen.

[0241] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating film 703 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. The treatment may be carried out in an atmosphere containing argon to which chlorine, carbon tetrafluoride, etc. have been added.

[0242] The oxide semiconductor film includes indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, and oxides of ternary metals In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, S n-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In- Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-T b-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er -Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu- Zn-based oxides, quaternary metal oxides such as In-Sn-Ga-Zn-based oxides, and In-Hf -Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide oxides, In-Sn-Hf-Zn oxides, and In-Hf-Al-Zn oxides. can be done.

[0243] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor film i-type (intrinsic), The reduction of oxygen vacancies due to dehydration or dehydrogenation and oxygen supply to the oxide semiconductor film will be described. is valid.

[0244] In this embodiment, the oxide semiconductor film is formed using indium (In), gallium (Ga), and Using a target containing Zn (zinc), a 30 nm thick In-Ga- A Zn-based oxide semiconductor film is formed.

[0245] Examples of targets for forming an oxide semiconductor film by sputtering include those having a composition The ratio of oxide target was In2O3:Ga2O3:ZnO=1:1:1 [molar ratio]. The In-Ga-Zn-O layer is formed using a target. For example, the molar ratio of In2O3:Ga2O3:ZnO=1:1:2 is not limited to the above. An oxide target may also be used.

[0246] When an In-Zn oxide material is used as the oxide semiconductor film, the target to be used is The composition ratio of In:Zn is 50:1 to 1:2 in atomic ratio (In:Zn in mole ratio). 2O3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 ( In terms of molar ratio, In2O3:ZnO=10:1 to 1:2), more preferably I n:Zn=15:1 to 1.5:1 (converted to mole ratio In2O3:ZnO=15: For example, the target used to form an In-Zn-based oxide semiconductor layer is When the atomic ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0247] The relative density of the oxide target is 90% or more and 100% or less, preferably 95% or more and 95% or less. By using a target with a high relative density, the oxide semiconductor film The conductive film can be made dense.

[0248] In this embodiment, the substrate is held in a processing chamber maintained in a reduced pressure state, and the remaining moisture in the processing chamber is removed. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. An oxide semiconductor film is formed over a substrate 700. During the film formation, the substrate temperature is set to 100° C. or higher and 600° C. The temperature may be set to 200° C. or higher and 400° C. or lower. This allows the impurity concentration in the formed oxide semiconductor film to be reduced. In addition, damage caused by sputtering is reduced. To remove residual moisture in the processing chamber, It is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, It is preferable to use a titanium sublimation pump. A cryopump with a cold trap may also be used. When the chamber is evacuated, hydrogen atoms and compounds containing hydrogen atoms, such as water (H2O) (preferably Since the oxide semiconductor film formed in the processing chamber is exhausted, The concentration of impurities contained in the membrane can be reduced.

[0249] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions are suitable for a direct current (DC) power supply of 0.5 kW and an oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced. This is preferable because it also makes the film thickness distribution uniform.

[0250] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pre-treatment for film formation, up to the gate insulating film 703 is formed in the pre-heating chamber of the sputtering device. The substrate 700 is preheated to remove impurities such as moisture or hydrogen adsorbed on the substrate 700. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is preferably 150°C or higher and 300°C or lower. The preheating process can be omitted. The preparatory heating is performed after forming the conductive films 705 and 706 before forming the insulating film 707, which is performed later. The same process may be carried out on the substrate 700.

[0251] Note that the etching for forming the island-shaped oxide semiconductor film 704 is dry etching. Dry etching can be performed by wet etching, or both can be used. The gas may be a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron chloride (B Cl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.) are preferred. fluorine-containing gases (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6 ), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), gases in which rare gases such as helium (He) and argon (Ar) are added to these gases, etc. can be used.

[0252] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0253] ITO-07N (Kanto Chemical Co., Ltd.) was used as the etching solution for wet etching. It's fine.

[0254] A resist mask for forming the island-shaped oxide semiconductor film 704 is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0255] Note that reverse sputtering is performed before forming a conductive film in the next step, and the island-shaped oxide semiconductor film 704 and It is also preferable to remove resist residues adhering to the surface of the gate insulating film 703. .

[0256] Note that the oxide semiconductor film formed by sputtering or the like contains moisture or hydrogen ( The water or hydrogen atoms form donor levels. Therefore, in one embodiment of the present invention, To reduce impurities such as water or hydrogen in semiconductor films (dehydration or dehydrogenation) The island-shaped oxide semiconductor film 704 is heated under reduced pressure with an inert gas such as nitrogen or a rare gas. Atmosphere, oxygen gas atmosphere, or ultra dry air (CRDS (cavity ring down When measured using a dew point meter using the laser spectroscopy method, the moisture content was 20 ppm (- 55°C), preferably 1 ppm or less, preferably 10 ppb or less in air The island-shaped oxide semiconductor film 704 is subjected to heat treatment.

[0257] By performing heat treatment on the island-shaped oxide semiconductor film 704, Specifically, the temperature is 250°C or higher and 750°C or lower, preferably Preferably, the heat treatment is carried out at a temperature of 400° C. or higher and lower than the distortion point of the substrate. If the RTA method is used for the heat treatment, the Since dehydration or dehydrogenation can be performed, processing can be performed at temperatures exceeding the strain point of the glass substrate. can.

[0258] In this embodiment mode, an electric furnace, which is one of the heat treatment devices, is used.

[0259] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0260] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain oxygen or hydrogen. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0261] Through the above steps, the concentration of hydrogen in the island-shaped oxide semiconductor film 704 is reduced and the oxide semiconductor film 704 is highly purified. This makes it possible to stabilize the oxide semiconductor film. Heat treatment below the transition point produces oxides with a wide band gap and few hydrogen-induced carriers. Therefore, it is possible to manufacture a transistor using a large-area substrate. The heat treatment, which can improve mass productivity, can be performed after the formation of the oxide semiconductor film. If so, you can do it anytime.

[0262] When the oxide semiconductor film is heated, the temperature may vary depending on the material of the oxide semiconductor film and heating conditions. Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the single crystal has a c-axis oriented substantially perpendicularly. In the crystal formation region, the ab planes of each crystal coincide, or the a axis or b axis coincides throughout. The oxide semiconductor film is polycrystalline or single crystalline with its c-axis oriented substantially perpendicular to the surface of the oxide semiconductor film. When the surface of the layer on which the oxide semiconductor film is formed is uneven, the plate-like crystal Therefore, the surface of the layer on which the oxide semiconductor film is formed should be as flat as possible. Specifically, the average surface roughness of the surface of the layer on which the oxide semiconductor film is formed is preferably The thickness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. Ra is measured by an atomic force microscope (AFM). It can be evaluated using the following scope.

[0263] Next, as shown in FIG. 21(C), a conductive film 7 which functions as a source electrode and a drain electrode is formed. 05, the conductive film 706, and the conductive film 705, the conductive film 706, and the island-shaped oxide semiconductor film 7 An insulating film 707 is formed on the insulating film 704.

[0264] The conductive films 705 and 706 are formed by a sputtering method so as to cover the island-shaped oxide semiconductor film 704. After forming a conductive film by a vacuum deposition method, the conductive film is patterned by etching or the like. This allows it to be formed.

[0265] The conductive films 705 and 706 are in contact with the island-shaped oxide semiconductor film 704. 05. The conductive film 706 is made of aluminum, chromium, copper, or tantalum. , titanium, molybdenum, tungsten, neodymium, scandium, magnesium, etc. The elements mentioned above, or alloys containing the elements mentioned above, or alloys combining the elements mentioned above In addition, aluminum or copper is used to avoid problems of heat resistance and corrosion. Therefore, it is recommended to use it in combination with a high melting point metal material. Ni, titanium, chromium, tantalum, tungsten, neodymium, scandium, yttrium etc. can be used.

[0266] The conductive film may have a single layer structure or a stacked structure of two or more layers. a single layer structure of aluminum film containing titanium; a two-layer structure of titanium film laminated on aluminum film; A titanium film is then formed on top of the titanium film, and an aluminum film is then laminated on top of that. Examples include a three-layer structure with a membrane.

[0267] The conductive films 705 and 706 are formed using a conductive metal oxide. The conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium oxide. Indium tin oxide alloy, indium oxide zinc oxide alloy or metal oxide material with silicon or Alternatively, a material containing silicon oxide can be used.

[0268] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that

[0269] Note that it is preferable that the island-shaped oxide semiconductor film 704 is not removed as much as possible when the conductive film is etched. The materials and etching conditions are adjusted accordingly. The exposed portion of the island-shaped oxide semiconductor film 704 is partially etched, whereby a groove (a recess ) may also be formed.

[0270] In this embodiment mode, a titanium film is used as the conductive film. Conductive films can be selectively wet-etched using a solution containing ammonium peroxide. Specifically, the solution containing ammonia hydrogen peroxide is a mixture of 31% by weight of hydrogen peroxide and 28% by weight of hydrogen peroxide. % ammonia water and water in a volume ratio of 2:1:1. The conductive film is dry-etched using gases containing fluorine (Cl2), boron chloride (BCl3), etc. That's fine.

[0271] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives the applied light multiple levels of intensity is used. The resist mask formed using the multi-tone mask may be formed by etching a plurality of resist masks. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A single multi-tone mask can be used to create a register that corresponds to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, which simplifies the process.

[0272] Before forming the insulating film 707, a plasma treatment using a gas such as N2O, N2, or Ar is performed. The island-shaped oxide semiconductor film 704 is subjected to plasma treatment. Water adsorbed on the surface of the island-shaped oxide semiconductor film 704 is removed. Alternatively, the plasma treatment may be performed using a mixed gas of argon and fluorine.

[0273] The insulating film 707 preferably contains as little impurities as possible, such as moisture and hydrogen, and is a single-layer insulating film. The insulating film 707 may be a single film, or may be made up of a plurality of laminated insulating films. When hydrogen is contained in the oxide semiconductor film, the hydrogen penetrates into the oxide semiconductor film or is absorbed in the oxide semiconductor film. Oxygen is extracted, and the resistance of the back channel portion of the island-shaped oxide semiconductor film 704 is reduced (to n-type). Therefore, the insulating film 707 should be as thin as possible. It is important that the deposition method does not use hydrogen, so that the resulting film is hydrogen-free. It is desirable to use a material with high barrier properties for the insulating film 707. For example, Examples of the insulating film include silicon nitride film, silicon nitride oxide film, aluminum nitride film, aluminum oxide film, Alternatively, an aluminum nitride oxide film or the like can be used. In this case, insulating films such as silicon oxide films and silicon oxynitride films with low nitrogen content are used as the barrier. The insulating film having a high viscosity is formed closer to the island-shaped oxide semiconductor film 704 than the insulating film having a high viscosity. The conductive film 705, the conductive film 706, and the island-shaped oxide film are formed by sandwiching an insulating film having a low content of silicon between them. An insulating film with high barrier properties is formed so as to overlap with the semiconductor film 704. By using the film, the island-shaped oxide semiconductor film 704, the gate insulating film 703, or the island-shaped oxide semiconductor film 704 can be formed. Impurities such as moisture or hydrogen exist at the interface between the oxide semiconductor film 704 and the other insulating film and in the vicinity thereof. In addition, the insulating film 704 is formed in such a manner that it is in contact with the island-shaped oxide semiconductor film 704. By forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio, Therefore, the insulating film using a material having high thermal conductivity can be prevented from being in direct contact with the island-shaped oxide semiconductor film 704. Cut.

[0274] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 707 has a structure in which a silicon nitride film having a film thickness of 100 nm formed by the method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. Set the temperature to 100°C.

[0275] Note that heat treatment may be performed after the insulating film 707 is formed. In an atmosphere of dry air or a rare gas (argon, helium, etc.), preferably 20 The temperature is between 0°C and 400°C, for example between 250°C and 350°C. The content is 20 ppm or less, preferably 1 ppm or less, and preferably 10 ppb or less. In this embodiment, for example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. Alternatively, before forming the conductive films 705 and 706, moisture or hydrogen may be reduced. Similar to the heat treatment performed on the oxide semiconductor film for the purpose of After the insulating film 707 containing oxygen is provided, heat treatment is performed. Therefore, it is assumed that oxygen vacancies are generated in the island-shaped oxide semiconductor film 704 by the previous heat treatment. Even if the insulating film 707 is not formed, oxygen is supplied to the island-shaped oxide semiconductor film 704. By supplying oxygen to the oxide semiconductor film 704, the island-shaped oxide semiconductor film 704 This reduces the oxygen vacancies that act as donors, making it possible to satisfy the stoichiometric ratio. It is preferable that the compound semiconductor film 704 contains oxygen in an amount exceeding the stoichiometric ratio. As a result, the island-shaped oxide semiconductor film 704 can be made closer to an i-type oxide film, and a transistor due to oxygen vacancy can be prevented. This reduces the variation in the electrical characteristics of the transistor, thereby improving the electrical characteristics. The timing of the heat treatment is not particularly limited as long as it is after the insulating film 707 is formed. For example, a heat treatment for forming a resin film or a heat treatment for reducing the resistance of a transparent conductive film By combining the oxide semiconductor film 704 with the silicon dioxide film 706, the island-shaped oxide semiconductor film 704 can be made nearly i-type without increasing the number of steps. It can be attached.

[0276] Further, by performing heat treatment on the island-shaped oxide semiconductor film 704 in an oxygen atmosphere, the oxide semiconductor Oxygen is added to the oxide semiconductor film 704 to reduce oxygen vacancies that serve as donors. The temperature of the heat treatment may be, for example, 100° C. or higher and lower than 350° C., preferably 150° C. The heat treatment is carried out at a temperature of 250°C or higher. It is preferable that the oxygen gas introduced into the heat treatment device does not contain hydrogen. The degree is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, ( That is, it is preferable to keep the impurity concentration in oxygen to 1 ppm or less, preferably 0.1 ppm or less. Desirable.

[0277] Alternatively, the island-shaped oxide semiconductor film 7 may be formed by using an ion implantation method or an ion doping method. By adding oxygen to 04, the oxygen vacancies that act as donors can be reduced. For example, 2. When oxygen plasma generated by a microwave of 45 GHz is added to the island-shaped oxide semiconductor film 704, That's good.

[0278] Note that after a conductive film is formed over the insulating film 707, the conductive film is patterned to form an island-like A back gate electrode may be formed so as to overlap with the oxide semiconductor film 704. When a back gate electrode is formed, it is desirable to form an insulating film so as to cover the back gate electrode. The back gate electrode is formed of the same material as the gate electrode 702, the conductive film 705, or the conductive film 706. It is possible to form it using the material and structure.

[0279] The thickness of the back gate electrode is 10 nm to 400 nm, preferably 100 nm to 200 nm. For example, a structure in which a titanium film, an aluminum film, and a titanium film are stacked is After forming the conductive film, a resist mask is formed by photolithography or the like. Unnecessary parts are removed by etching, and the conductive film is processed into the desired shape (patterning). By doing so, a back gate electrode can be formed.

[0280] Through the above steps, the transistor 708 is formed.

[0281] The transistor 708 includes a gate electrode 702 and a gate insulating film 703 on the gate electrode 702. and an island-shaped oxide semiconductor layer overlapping the gate electrode 702 on the gate insulating film 703. a pair of conductive films 705 or a pair of conductive films 706 formed over the island-shaped oxide semiconductor film 704; Further, the transistor 708 has an insulating film 707 as a component thereof. The transistor 708 shown in FIG. 21C includes a conductive film 705 and a conductive film 706. A channel etch structure in which part of the island-shaped oxide semiconductor film 704 is etched is formed between the oxide semiconductor film 704 and the island-shaped oxide semiconductor film 704. It is made of

[0282] Note that although the transistor 708 has been described as a single-gate transistor, Optionally, a plurality of electrically connected gate electrodes 702 may be provided to facilitate channel formation. A transistor having a multi-gate structure having multiple regions can also be formed.

[0283] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0284] (Fourth embodiment) In this embodiment, a structural example of a transistor will be described. A part or a part having the same function and a step can be performed in the same manner as in the above embodiment. Therefore, the repeated explanation in this embodiment will be omitted. do.

[0285] A transistor 2450 shown in FIG. 22A has a gate electrode 2401 formed on a substrate 2400. A gate insulating film 2402 is formed on the gate electrode 2401, and the gate insulating film 240 2, an oxide semiconductor film 2403 is formed on the source electrode 2 The oxide semiconductor film 240 is formed on the gate electrode 405a and the drain electrode 2405b. 3. An insulating film 2407 is formed on the source electrode 2405a and the drain electrode 2405b. A protective insulating film 2409 may be formed over the insulating film 2407. 2450 is one of the bottom gate structure transistors, and is an inverted staggered transistor. At least one.

[0286] A transistor 2460 shown in FIG. 22B has a gate electrode 2401 formed on a substrate 2400. A gate insulating film 2402 is formed on the gate electrode 2401, and the gate insulating film 240 2, an oxide semiconductor film 2403 is formed on the oxide semiconductor film 2403, and a channel protective layer 2406 is formed on the channel protective layer 2406 and the oxide semiconductor film 2403. A source electrode 2405a and a drain electrode 2405b are formed on the gate electrode 2405. A protective insulating film 2409 may be formed over the gate electrode 2405a and the drain electrode 2405b. The 2460 is a bottom gate diode known as a channel protection type (also known as a channel stop type). It is one of the gate structure transistors and also one of the inverted staggered transistors. The protective layer 2406 can be formed using the same materials and methods as those for other insulating films.

[0287] A transistor 2470 shown in FIG. 22C is a transistor in which a base film 2436 is formed over a substrate 2400. The oxide semiconductor film 2403 is formed over the base film 2436. A source electrode 2405a and a drain electrode 2405b are formed on the base film 2436. The oxide semiconductor film 2403, the source electrode 2405a, and the drain electrode 2405b are A gate insulating film 2402 is formed, and a gate electrode 2401 is formed on the gate insulating film 2402. A protective insulating film 2409 may be formed on the gate electrode 2401. Transistor 2470 is one of the top-gate structure transistors.

[0288] The transistor 2480 shown in FIG. 22D has a first gate electrode 24 11 is formed, and a first gate insulating film 2413 is formed on the first gate electrode 2411. The oxide semiconductor film 2403 is formed over the first gate insulating film 2413. 2403 and the first gate insulating film 2413, a source electrode 2405a and a drain electrode 2406a are formed on the first gate insulating film 2403 and the first gate insulating film 2413. The oxide semiconductor film 2403 and the source electrode 2405 are formed on the oxide semiconductor film 2403. A second gate insulating film 2414 is formed on the gate electrode 2405a and the drain electrode 2405b. A second gate electrode 2412 is formed on the gate insulating film 2414. A protective insulating film 2409 may be formed on the protective electrode 2412 .

[0289] The transistor 2480 is a combination of the transistors 2450 and 2470. The first gate electrode 2411 and the second gate electrode 2412 are electrically connected to each other. The first gate electrode 2411 and the second gate electrode 2412 can function as one gate electrode. One of the two gate electrodes 2412 is simply called the gate electrode, and the other is called the back gate. It is sometimes called a port electrode.

[0290] The threshold voltage of the transistor is changed by changing the potential of the back gate electrode. The back gate electrode overlaps with a channel formation region of the oxide semiconductor film 2403. The back gate electrode is formed in a floating state where it is electrically insulated. In the latter case, the back gate electrode may be in a state where a potential is applied. The potential may be the same as that of the gate electrode, or may be a fixed potential such as ground. By controlling the level of the potential applied to the back gate electrode, The threshold voltage of the transistor 2480 can be controlled.

[0291] In addition, by covering the oxide semiconductor film 2403 with the back gate electrode, Therefore, light can be prevented from entering the oxide semiconductor film 2403 from the side. It prevents the light degradation of the conductive film 2403 and reduces the characteristics such as the shift of the threshold voltage of the transistor. This can prevent deterioration from occurring.

[0292] The insulating film in contact with the oxide semiconductor film 2403 (in this embodiment, the gate insulating film 240 2, insulating film 2407, channel protection layer 2406, base film 2436, first gate insulating film 2 413, and the second gate insulating film 2414 correspond to the first gate insulating film 2413.) contains a group 13 element and oxygen. It is preferable to use an insulating material. Many oxide semiconductor materials contain elements of Group 13. Insulating materials containing Group 13 elements are compatible with oxide semiconductors, and they can be used to form oxide semiconductor films. By using it as an insulating film in contact with the oxide semiconductor film, the state of the interface with the oxide semiconductor film can be kept good. .

[0293] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Aluminum gallium is a material that has a higher aluminum content (atomic %) than the gallium content (atomic %). Gallium aluminum oxide refers to the gallium content (atomic %) of indicates an aluminum content (atomic %) of 100 or more.

[0294] For example, when an insulating film is formed in contact with an oxide semiconductor film containing gallium, By using a material containing gallium oxide, the interface characteristics between the oxide semiconductor film and the insulating film can be maintained good. For example, an oxide semiconductor film and an insulating film containing gallium oxide can be provided in contact with each other. This can reduce the pileup of hydrogen at the interface between the oxide semiconductor film and the insulating film. When an element of the same group as the component element of the oxide semiconductor film is used for the insulating film, For example, it is possible to obtain the same effect by using a material containing aluminum oxide. It is also effective to form a film of aluminum oxide, which has the characteristic of being difficult for water to pass through. Therefore, the use of this material is effective in preventing water from entering the oxide semiconductor film. This is also preferable in this respect.

[0295] The insulating film in contact with the oxide semiconductor film 2403 is subjected to heat treatment in an oxygen atmosphere or oxygen deposition. It is preferable to make the insulating material have more oxygen than the stoichiometric composition ratio by using a groove or the like. Oxygen doping refers to adding oxygen to the bulk. The term is used to clarify that the element is added not only to the surface of the thin film but also to the inside of the thin film. Oxygen doping includes oxygen plasma doping, in which oxygen plasma is added to the bulk. The oxygen doping may be performed by ion implantation or ion doping.

[0296] For example, when gallium oxide is used as an insulating film in contact with the oxide semiconductor film 2403, oxygen By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to GaO X (X=3+α, 0<α<1).

[0297] When aluminum oxide is used as the insulating film in contact with the oxide semiconductor film 2403, By heat treatment in a nitrogen atmosphere or oxygen doping, the composition of aluminum oxide is changed to A l2O X (X=3+α, 0<α<1).

[0298] In addition, an insulating film in contact with the oxide semiconductor film 2403 is formed of gallium aluminum oxide (aluminum oxide). When using aluminum gallium, heat treatment in an oxygen atmosphere or oxygen doping can be performed. By this, the composition of gallium aluminum oxide (aluminum gallium oxide) is Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0299] By performing oxygen doping treatment, an insulating film having a region in which oxygen is present in a larger amount than the stoichiometric composition ratio is formed. When the insulating film having such a region is in contact with the oxide semiconductor film, As a result, excess oxygen in the insulating film is supplied to the oxide semiconductor film, and the oxide semiconductor film The oxygen vacancies at the interface between the oxide semiconductor film and the insulating film are reduced, and the oxide semiconductor film is made into an i-type or An oxide semiconductor that is as close to i-type as possible can be obtained.

[0300] Note that the insulating film having a region with more oxygen than the stoichiometric composition is the oxide semiconductor film 2403 Among the insulating films in contact with the It may be used in only one of the insulating films, but it is preferable to use it in both insulating films. The insulating film having a region with a larger amount of oxygen is formed on the upper layer of the insulating film in contact with the oxide semiconductor film 2403. The oxide semiconductor film 2403 is sandwiched between the insulating film 2402 and the insulating film 2403. This can further enhance the above effects.

[0301] The insulating films used as the upper and lower layers of the oxide semiconductor film 2403 have the same structure. The insulating film may have a constituent element, or may have a different constituent element. For example, both the upper and lower layers have a composition of GaO X (X=3+α, 0<α<1) gallium oxide and Alternatively, one of the upper and lower layers may have a composition of GaO. X Oxidation of (X=3+α, 0<α<1) The other is gallium, and the other is AlO X Aluminum oxide (X=3+α, 0<α<1) It is also possible to do so.

[0302] In addition, the insulating film in contact with the oxide semiconductor film 2403 has a region containing more oxygen than the stoichiometric composition. For example, an insulating film having a composition of G may be stacked on an upper layer of the oxide semiconductor film 2403. a2O X (X=3+α, 0<α<1) gallium oxide is formed on it, and the composition is Ga X A l 2-X O 3+αGallium aluminum oxide (aluminum gallium oxide) where (0 < X < 2, 0 < α < 1) may be formed. Note that the lower layer of the oxide semiconductor film 2403 may be a stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio, or both the upper and lower layers of the oxide semiconductor film 2403 may be a stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio. It is also possible to form an insulating film having a region where oxygen is more than the stoichiometric composition ratio. The lower layer of the oxide semiconductor film 2403 may be a stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio, or both the upper and lower layers of the oxide semiconductor film 2403 may be a stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio. It is also possible to form an insulating film having a region where oxygen is more than the stoichiometric composition ratio. A stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio may be used.

[0303] This embodiment can be implemented in appropriate combination with other embodiments.

[0304] (Embodiment 5) In this embodiment, one form of a substrate used in a liquid crystal display device according to an aspect of the present invention will be described using FIGS. 23 and 24. First, a peeling layer 6201 is formed on a substrate 6200 through a peeling layer 6201 (see FIG. 23(A)).

[0305] As the substrate 6200, a quartz substrate, a sapphire substrate, a ceramic substrate, a glass substrate, a metal substrate, or the like can be used. These substrates can be used to accurately form elements such as transistors by using those having a thickness that does not clearly exhibit flexibility. The degree that does not clearly exhibit flexibility means the elastic modulus of a glass substrate usually used when manufacturing a liquid crystal display, or a larger elastic modulus. See FIG. 23(A).

[0306] As the substrate 6200, a quartz substrate, a sapphire substrate, a ceramic substrate, a glass substrate, a metal substrate, or the like can be used. These substrates can be used to accurately form elements such as transistors by using those having a thickness that does not clearly exhibit flexibility. The degree that does not clearly exhibit flexibility means the elastic modulus of a glass substrate usually used when manufacturing a liquid crystal display, or a larger elastic modulus. These substrates can be used to accurately form elements such as transistors by using those having a thickness that does not clearly exhibit flexibility. The degree that does not clearly exhibit flexibility means the elastic modulus of a glass substrate usually used when manufacturing a liquid crystal display, or a larger elastic modulus. By using those having a thickness that does not clearly exhibit flexibility, elements such as transistors can be accurately formed. The degree that does not clearly exhibit flexibility means the elastic modulus of a glass substrate usually used when manufacturing a liquid crystal display, or a larger elastic modulus. The degree that does not clearly exhibit flexibility means the elastic modulus of a glass substrate usually used when manufacturing a liquid crystal display, or a larger elastic modulus.

[0307] The peeling layer 6201 can be formed by sputtering, plasma CVD, coating, printing, or the like, using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), Ruthenium (Ru), Rhodium (Rh), Palladium (Pd), Osmium (Os), An element selected from iridium (Ir) and silicon (Si), or an alloy material whose main component is an element Alternatively, a layer made of a compound material containing the element as a main component is formed as a single layer or a stacked layer.

[0308] When the peeling layer 6201 has a single layer structure, it is preferably a tungsten layer, a molybdenum layer, or a titanium layer. A layer containing a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing tungsten oxide or molybdenum is formed. a layer containing an oxide or oxynitride of molybdenum, a layer containing an oxide or oxynitride of molybdenum, or a layer containing tungsten A layer containing an oxide or oxynitride of a mixture of stainless steel and molybdenum is formed. The mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. do.

[0309] When the peeling layer 6201 has a laminated structure, it is preferable to form a metal layer as the first layer and a metal layer as the second layer. The metal oxide layer is formed by the addition of tungsten or molybdenum as the first layer. Alternatively, a layer containing a mixture of tungsten and molybdenum is formed, and a second layer containing tungsten is formed. , oxides, nitrides, oxynitrides or mixtures of molybdenum and tungsten The second metal oxide layer is formed by depositing an oxide layer on the first metal layer. By forming an oxide layer (such as silicon oxide, which can be used as an insulating layer), It may also be possible to apply the formation of an oxide of the metal on the surface of the layer.

[0310] The peeled layer 6116 may include a transistor, an interlayer insulating film, a wiring, a pixel electrode, and, if necessary, The substrate includes elements necessary for the device, such as a counter electrode, a shielding film, and an alignment film. These materials, manufacturing methods, and structures can be fabricated as usual on the separation layer 6201. As these are the same as those described in the above embodiment, the explanation will be omitted. As such, transistors and electrodes can be fabricated with high precision using known materials and methods. do.

[0311] Next, the peeled layer 6116 is adhered to a temporary support substrate 6202 using a peeling adhesive 6203. After that, the layer to be peeled 6116 is peeled off from the peeling layer 6201 of the substrate 6200 and transposed (see FIG. 23). (See (B)). As a result, the peeled layer 6116 is provided on the temporary support substrate side. In the specification, the step of transferring the release layer from the fabrication substrate to the temporary support substrate is referred to as a transfer step.

[0312] The temporary support substrate 6202 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like. In addition, a heat-resistant substrate that can withstand the subsequent processing temperatures can be used. A tungsten substrate may also be used.

[0313] The peeling adhesive 6203 used here is soluble in water or solvents, or irradiated with ultraviolet light or other light. The temporary support substrate 6202 and the layer to be peeled off can be plasticized by irradiation when necessary. Use an adhesive that can be separated from 6116.

[0314] The transfer step onto the temporary support substrate 6202 can be carried out by various methods. For example, a film containing a metal oxide film is formed on the side in contact with the layer to be peeled 6116 as the peeling layer 6201. In this case, the metal oxide film is crystallized and weakened, and the peeled layer 6116 is separated from the base. The substrate 6200 can be peeled off from the plate 6200. When an amorphous silicon film containing hydrogen is formed as the peeling layer 6201, laser light irradiation or The amorphous silicon film containing hydrogen is removed by etching, and the peeled layer 6116 is attached to the substrate 62. 00. The peeling layer 6201 can be peeled off from the substrate containing nitrogen, oxygen, hydrogen, or the like. films (e.g., amorphous silicon films containing hydrogen, hydrogen-containing alloy films, oxygen-containing alloy films, etc.) In this case, the peeling layer 6201 is irradiated with laser light to remove nitrogen and oxygen contained in the peeling layer 6201. and hydrogen are released as gas to promote separation of the layer to be peeled 6116 and the substrate 6200. As another method, a liquid may be permeated into the interface between the peeling layer 6201 and the layer to be peeled 6116. The layer to be peeled 6116 may be peeled from the substrate 6200 by using a tungsten The peeling layer 6201 is formed by etching with ammonia hydrogen peroxide. There are also.

[0315] Furthermore, by combining a plurality of the above-mentioned peeling methods, the transposition step can be carried out more easily. Laser irradiation, etching of the peeling layer with gas or solution, sharp knives or scalpels The peeling layer and the layer to be peeled are partially mechanically removed by a method to make the peeling layer and the layer to be peeled easier to peel from each other. This includes a process of peeling using physical force (using a machine, etc.). When the layer 1 is formed by laminating a metal and a metal oxide, the layer 1 is formed by irradiating a laser beam. The material is physically pulled out from the peeling layer due to grooves in the peeling layer or scratches caused by a sharp knife or scalpel. It also becomes easy to peel off.

[0316] Furthermore, the peeling may be carried out while pouring a liquid such as water.

[0317] Another method for separating the layer to be peeled 6116 from the substrate 6200 is to The formed substrate 6200 can be removed by mechanical polishing or by using a solution, NF3, Etching with halogen fluoride gases such as BrF3 and ClF3 can also be used. In this case, the peeling layer 6201 does not need to be provided.

[0318] Subsequently, the peeling layer 6201 or the layer to be peeled 611 is peeled from the substrate 6200 and exposed. 6. A first adhesive layer 6111 made of an adhesive different from the peeling adhesive 6203 is used on the surface. A transfer substrate 6110 is attached (see FIG. 23(C)).

[0319] The material of the first adhesive layer 6111 may be a light-curing adhesive such as an ultraviolet-curing adhesive, a reflective adhesive, or the like. Various curing adhesives such as reactive curing adhesives, thermosetting adhesives, and anaerobic adhesives can be used. This can be done.

[0320] As the transfer substrate 6110, various substrates with high toughness are used, for example, organic resin filters. A substrate with high toughness is excellent in impact resistance. The organic resin film is lightweight, and the metal substrate is also thin. Since it is lightweight, it is possible to significantly reduce the weight compared to using a normal glass substrate. By using such a substrate, it is possible to manufacture a liquid crystal display device that is light and resistant to breakage. It will be possible to manufacture

[0321] In the case of a transmissive or semi-transmissive liquid crystal display device, the transfer substrate 6110 is made of a tough It is sufficient to use a substrate that has a large surface area and is transparent to visible light. Examples of the material include polyethylene terephthalate (PET) and polyethylene naphtha. Polyester resins such as phthalate (PEN), acrylic resins, polyacrylonitrile resins , polyimide resin, polymethyl methacrylate resin, polycarbonate resin (PC), Polyethersulfone resin (PES), polyamide resin, cycloolefin resin, poly Examples of such resins include polyethylene resin, polyamide-imide resin, and polyvinyl chloride resin. The substrate made of resin has high toughness, making it highly impact resistant and difficult to break. In addition, these organic resin films are lightweight, so they are easier to install than ordinary glass substrates. In comparison, it is possible to manufacture a liquid crystal display device that is extremely lightweight. The transfer substrate 6110 has openings at least in the areas overlapping with the light transmitting areas of the pixels. It is preferable that the metal plate 6206 is further provided. Therefore, the transfer substrate has high toughness while suppressing dimensional changes, and is highly resistant to impact and breakage. Furthermore, by reducing the thickness of the metal plate 6206, it is possible to construct a conventional glass A transfer substrate 6110 that is lighter than the substrate can be constructed. By using such a substrate, It becomes possible to manufacture a liquid crystal display device that is light and not easily damaged (see FIG. 23(D)). (see).

[0322] FIG. 24(A) is an example of a top view of a liquid crystal display device. As shown in FIG. 24(A), The first wiring layer 6210 and the second wiring layer 6211 intersect with each other, and the first wiring layer 6210 and the second wiring layer 6211 intersect with each other. In the case of a liquid crystal display device in which the area surrounded by the line layer 6211 is a light transmitting area 6212, as shown in FIG. As shown in 24(B), the portions overlapping the first wiring layer 6210 and the second wiring layer 6211 remain. Therefore, a metal plate 6206 with openings in a grid pattern can be used. By using such a metal plate 6206, the organic resin This can prevent deterioration of alignment accuracy due to the use of a substrate and dimensional changes due to the expansion of the substrate. If a polarizing plate (not shown) is required, the transfer substrate 6110 and the metal plate 620 6, or may be provided outside the metal plate 6206. It may be attached to the metal plate 6206. From the viewpoint of weight reduction, It is preferable to use a thin substrate within a range that can achieve the above-mentioned dimensional stabilization effect. .

[0323] Thereafter, the temporary support substrate 6202 is separated from the layer to be peeled 6116. The peeling adhesive 6203 The temporary support substrate 6202 and the peeled layer 6116 are formed of a material that allows them to be separated when necessary. Therefore, the temporary support substrate 6202 can be separated by a method suitable for the material. The backlight is illuminated as shown by the arrow in the drawing (see FIG. 23(E)).

[0324] As a result of the above, the layer to be peeled 6116 (if necessary) in which the transistor to the pixel electrode is formed is A counter electrode, a shielding film, an alignment film, etc. may be provided on the transfer substrate 6110. This makes it possible to manufacture a lightweight and highly impact-resistant element substrate.

[0325] <Modification> The liquid crystal display device having the above-described configuration is one embodiment of the present invention, and The present invention also includes the following liquid crystal display device having the above-mentioned transposition process (FIG. 23(B) After the above, before attaching the transfer substrate 6110, the exposed peeling layer 6201 or the peeled layer A metal plate 6206 may be attached to the surface of the layer 6116 (see FIG. 23(C')). In this case, contaminants from the metal plate 6206 may affect the characteristics of the transistor in the peeled layer 6116. To prevent adverse effects, it is advisable to provide a barrier layer 6207 between them. When the barrier layer 7 is provided, the barrier layer 7 is formed on the surface of the exposed peeling layer 6201 or the peeled layer 6116. After providing the barrier layer 6207, the metal plate 6206 is attached. The insulating layer may be formed from a metal or organic material, typically silicon nitride. The barrier layer is not limited to these as long as it can prevent contamination of the transistor. The light-transmitting layer is formed of a light-transmitting material or a thin film having light-transmitting properties. The metal plate 6206 is fabricated to have transparency to at least visible light. A second adhesive layer (not shown) is formed using an adhesive different from the release adhesive 6203, and the adhesive Just wear it.

[0326] After that, a first adhesive layer 6111 is formed on the surface of the metal plate 6206, and a transfer substrate 6110 is attached. 23(D')), and the temporary support substrate 6202 is separated from the peeled layer 6116 (FIG. 23(D')). 3(E')), a lightweight and highly impact-resistant element substrate can be produced. Light is emitted from the backlight as shown by the arrow in the drawing.

[0327] The lightweight and highly impact-resistant element substrate thus fabricated is sandwiched between the opposing substrate and a liquid crystal layer. By bonding the two together and fixing them with a sealing material, a lightweight and highly impact-resistant liquid crystal display device can be manufactured. The opposing substrate is preferably a substrate that has high toughness and is transparent to visible light. A substrate (similar to a plastic substrate that can be used for the transfer substrate 6110) can be used. If necessary, a polarizing plate, a shielding film, a counter electrode and an alignment film may be provided. The liquid crystal layer can be formed by the conventional dispenser method or injection method. It is possible.

[0328] The lightweight and highly shock-resistant liquid crystal display device manufactured as described above can be used without using minute devices such as transistors. Thin elements can be fabricated on glass substrates, which have relatively good dimensional stability. Since conventional manufacturing methods can be applied, even minute elements can be shaped with high precision. This allows for impact resistance while still providing high-definition, high-quality images. It is therefore possible to provide a lightweight liquid crystal display device.

[0329] Furthermore, the liquid crystal display device fabricated as described above can be made flexible.

[0330] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0331] (Embodiment 6) Next, a panel of a liquid crystal display device according to one embodiment of the present invention will be described with reference to FIG. FIG. 25(A) shows a substrate 4001 and an opposing substrate 4006 bonded together with a sealing material 4005. 25(B) is a cross-sectional view taken along the dashed line A-A' in FIG. 25(A). Corresponding to the figure.

[0332] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a substrate 4001. A sealing material 4005 is provided. An opposing substrate 4006 is provided on the pixel portion 4002. 004 is a liquid crystal display panel 400 formed by a substrate 4001, a sealing material 4005, and an opposing substrate 4006. It is sealed together with 7.

[0333] In addition, in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, A substrate 4021 on which a signal line driver circuit 4003 is formed is mounted. A transistor 4009 included in the line driver circuit 4003 is illustrated.

[0334] The pixel portion 4002 and the scanning line driver circuit 4004 provided on the substrate 4001 are In FIG. 25B, the pixel portion 4002 includes a plurality of transistors. 4010 and transistor 4022 are illustrated. The counter substrate 4006 includes an oxide semiconductor in a channel formation region. The formed shielding film 4040 overlaps the transistor 4010 and the transistor 4022. By shielding the transistor 4010 and the transistor 4022 from light, the oxide semiconductor The threshold voltage of the transistor 4010 and the transistor 4022 is This can prevent deterioration of characteristics such as shifting of the signal.

[0335] The pixel electrode 4030 of the liquid crystal element 4011 is made up of a reflective electrode 4032 and a transparent electrode 4033. 033 and electrically connected to the transistor 4010. The counter electrode 4031 is formed on the counter substrate 4006. The portion where the counter electrode 4031 and the liquid crystal 4007 overlap corresponds to the liquid crystal element 4011 .

[0336] In addition, the spacer 4035 is a spacer for reducing the distance between the pixel electrode 4030 and the counter electrode 4031 (cell size). In FIG. 25(B), the spacer 4035 However, the case where the insulating film is patterned is shown as an example, but the spherical spacer is It is also possible to use "sa".

[0337] Also, a signal line driver circuit 4003, a scanning line driver circuit 4004, and a pixel portion 4002 are provided with Various signals and potentials are supplied from a connection terminal 4016 via a wiring 4014 and a wiring 4015. The connection terminal 4016 is connected to a terminal of the FPC 4018 and the anisotropic conductive film 40 19.

[0338] The substrate 4001, the counter substrate 4006, and the substrate 4021 may be made of glass, ceramics, or plastic. Plastics can be used. FRP (Fiberglass- Reinforced Plastics (PVF) plate, PVF (Polyvinyl Fluoride) film Film, polyester film, acrylic resin film, etc. A sheet with a structure in which aluminum foil is sandwiched between PVF films can also be used.

[0339] However, the substrate positioned in the direction of light extraction from the liquid crystal element 4011 is made of glass plate, plus A transparent material such as plastic, polyester film, or acrylic film is used. There are.

[0340] 26 is an example of a perspective view showing the structure of a liquid crystal display device according to one embodiment of the present invention. The liquid crystal display device shown in FIG. 6 includes a panel 1601 having a pixel portion, a first diffusion plate 1602, A prism sheet 1603, a second diffusion plate 1604, a light guide plate 1605, and a backlight A panel 1607, a circuit board 1608, and a substrate 1611 on which a signal line driver circuit is formed are It has.

[0341] A panel 1601, a first diffusion plate 1602, a prism sheet 1603, and a second diffusion plate 1604, a light guide plate 1605, and a backlight panel 1607 are laminated in this order. The backlight panel 1607 has a backlight 1612 made up of multiple light sources. The light from the backlight 1612 diffused inside the light guide plate 1605 is diffused through the first diffusion layer. The panel 160 is formed by the plate 1602, the prism sheet 1603 and the second diffusion plate 1604. It is irradiated to 1.

[0342] In this embodiment, a first diffusion plate 1602 and a second diffusion plate 1604 are used. However, the number of the diffusion plates is not limited to this, and may be one or three or more. The scattering plate may be provided between the light guide plate 1605 and the panel 1601. The diffusion plate may be provided only on the side closer to the panel 1601 than the sheet 1603. Even if the diffusion plate is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603, good.

[0343] The cross section of the prism sheet 1603 is not limited to the sawtooth shape shown in FIG. It is sufficient that the shape can condense the light from the plate 1605 onto the panel 1601 side.

[0344] The circuit board 1608 includes a circuit for generating various signals to be input to the panel 1601, or In FIG. 26, a circuit board 160 is provided. 8 and the panel 1601 are connected via a COF tape 1609. The substrate 1611 on which the driving circuit is formed is formed by using the COF (Chip on Film) method. It is connected to COF tape 1609.

[0345] In FIG. 26, a control circuit for controlling the driving of a backlight 1612 is mounted on a circuit board 1608. The control circuit and the backlight panel 1607 are connected via an FPC 1610. However, the control circuit is formed on the panel 1601. In this case, the panel 1601 and the backlight panel 1607 are connected by an FPC. etc. to be connected.

[0346] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0347] (Embodiment 7) In this embodiment, an example of a pixel configuration of a liquid crystal display device according to one embodiment of the present invention will be described with reference to FIG. 27(A) is a plan view of a pixel portion used in a liquid crystal display device. 27(B) shows the line Y1-Y2 in FIG. 27(A), and a cross-sectional view taken along line Z1-Z2.

[0348] In FIG. 27A, a plurality of source wirings (including a source electrode or a drain electrode 505a) ) are arranged parallel to each other (extending in the vertical direction in the drawing) and spaced apart from each other. The gate wiring (including the gate electrode 501) extends in a direction substantially perpendicular to the source wiring (left and right in the drawing). The capacitance wiring 508 extends in the direction perpendicular to the gate electrode 501 and is spaced apart from each other. The gate lines are arranged adjacent to each other and are oriented in a direction roughly parallel to the gate lines. The wiring extends in a direction (horizontal direction in the drawing) that is substantially perpendicular to the source wiring.

[0349] The liquid crystal display device of FIGS. 27(A) and 27(B) is a semi-transmissive liquid crystal display device, and the pixel region is a reflective region. The reflective area 598 is made up of a transparent electrode 546 and a transparent area 599. A reflective electrode 547 is laminated as a pixel electrode, and a transparent electrode 599 is laminated as a pixel electrode. 27(A)(B), only a transparent film 546 is formed on the interlayer film 513. Although an example in which the electrode 546 and the reflective electrode 547 are laminated in this order has been shown, it is also possible to laminate the reflective electrode 547 on the interlayer film 513. The transistor 550 may have a structure in which the transparent electrode 547 and the transparent electrode 546 are stacked in this order. Insulating films 507 and 509 and an interlayer film 513 are provided. In the opening (contact hole) formed in the film 513, the transparent electrode 546 and the reflective electrode 547 is electrically connected to transistor 550 .

[0350] As shown in FIG. 27(B), the second substrate 542 is provided with a common electrode (also called a counter electrode) 548. The transparent electrode 546 and the reflective electrode 547 on the first substrate 541 and the liquid crystal layer 544 are formed. 27(A)(B), the liquid crystal display device has a transparent electrode 546 An alignment film 560a is provided between the reflective electrode 547 and the liquid crystal layer 544, and a common electrode 548 An alignment film 560b is provided between the alignment film 560a and the liquid crystal layer 544. is an insulating layer that has the function of controlling the alignment of liquid crystals, and may not be provided depending on the liquid crystal material. good.

[0351] The transistor 550 is an example of a bottom-gate inverted staggered transistor. An electrode 501, a gate insulating film 502, an oxide semiconductor film 503, a source electrode or a drain electrode 505a, and a source or drain electrode 505b. The capacitor wiring 508, the gate insulating film 502, and the source electrode or the drain electrode are formed in the same process. A conductive layer 549 formed in the same process as the electrodes 505a and 505b is laminated to form a capacitor. The capacitor wiring 508 is covered with a reflective film such as aluminum (Al) or silver (Ag). It is preferable to form a reflective electrode 547 made of a conductive film.

[0352] In addition, the reflective electrode 547 is formed to cover the transistor 550, so that the second substrate 5 The light incident from the side 42 is prevented from reaching the oxide semiconductor film 503. This prevents deterioration of the characteristics of the transistor 550, such as a shift in the threshold voltage. The transistor 550 is a bottom-gate transistor. Therefore, by using a light-shielding conductive material for the gate electrode 501, light entering from the first substrate 541 side can be prevented. It can block the light that is irradiated.

[0353] The semi-transmissive liquid crystal display device of this embodiment controls the on / off of the transistor 550. The color display of the moving image in the transparent area 599 and the still image in the reflective area 598 are shown. It is possible to display in black and white.

[0354] In the transmission region 599, incident light from a backlight provided on the first substrate 541 side On the other hand, in the reflective area 598, the second substrate 542 External light incident from the side is reflected by the reflective electrode 547, thereby enabling display.

[0355] 28 is different from FIG. 27 in that the transistor 550 is not covered with the reflective electrode 547. 28 shows an example of a liquid crystal display device. In addition, in the liquid crystal display device shown in FIG. A shielding film 555 is formed to cover the oxide semiconductor film 503. By providing the reflective electrode 547, when the reflective electrode 547 does not cover the transistor 550, In this case, deterioration of the oxide semiconductor due to light incident from the second substrate 542 side can be prevented.

[0356] The shielding film 555 may be made of a material having a light-shielding property. The shielding film 555 can be formed using the same material and method as the back electrode, the reflective electrode, etc. It may be formed using a material having light-shielding and conductive properties and function as a back gate electrode. stomach.

[0357] Next, an example of forming unevenness on the reflective electrode 547 in a liquid crystal display device is shown in FIG. 9, in the reflective region 598, the surface of the interlayer film 513 is made uneven, so that the reflective electrode 54 7. The unevenness on the surface of the interlayer film 513 is formed by selective etching. For example, a photosensitive organic resin can be processed by a photolithography process. By performing this process, an interlayer film 513 having a concave-convex shape can be formed.

[0358] As shown in FIG. 29, when the surface of the reflective electrode 547 is uneven, incident external light is diffused. Therefore, better display can be achieved, and visibility of the display is improved.

[0359] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0360] (Embodiment 8) In this embodiment, the transistor 951 and Two types of transistors were fabricated: a transistor 952 with a back gate electrode and a negative bias voltage. The results of evaluating the amount of change in threshold voltage (Vth) before and after the bias test are shown.

[0361] First, the stacked structure and manufacturing method of the transistor 951 will be described with reference to FIG. On the substrate 900, a silicon nitride film (thickness: 200 mm) is formed as an underlayer film 936 by a CVD method. A laminated film of a silicon oxynitride film (thickness 400 nm) and a base film 93 was formed. On the substrate 6, a tantalum nitride film (thickness 30 nm) and a tungsten film (thickness 1 A stacked film having a thickness of 00 nm was formed and selectively etched to form a gate electrode 901.

[0362] Next, a gate insulating film 902 is formed on the gate electrode 901 by a high density plasma CVD method. A silicon oxynitride film (thickness: 30 nm) was formed.

[0363] Next, an In-Ga-Zn oxide semiconductor target is formed on the gate insulating film 902 by sputtering. An oxide semiconductor film (thickness: 30 nm) was formed using the target. The oxide semiconductor film 903 was formed in an island shape by selectively etching the oxide semiconductor film 903 .

[0364] Next, a first heat treatment was carried out in a nitrogen atmosphere at 450° C. for 60 minutes.

[0365] Next, a titanium film (thickness: 100 nm) and an aluminum film (thickness: 2 A laminated film of a titanium film (100 nm thick) and a titanium film (100 nm thick) was formed by sputtering. The source electrode 905a and the drain electrode 905b were formed by selective etching.

[0366] Next, a second heat treatment was carried out in a nitrogen atmosphere at 300° C. for 60 minutes.

[0367] Next, a source electrode 905a and a drain electrode 905b are formed in contact with a part of the oxide semiconductor film 903. On b, a silicon oxide film is formed as an insulating film 907 by a sputtering method. Then, a polyimide resin layer (thickness: 1.5 μm) was formed as an insulating film 908 .

[0368] Next, a third heat treatment was carried out in a nitrogen atmosphere at 250° C. for 60 minutes.

[0369] Next, a polyimide resin layer (thickness 2.0 μm) is formed on the insulating film 908 as an insulating film 909. Successful.

[0370] Next, a fourth heat treatment was carried out in a nitrogen atmosphere at 250° C. for 60 minutes.

[0371] The transistor 952 shown in FIG. 30B can be manufactured in a manner similar to that of the transistor 951. Note that the transistor 951 has a back gate between the insulating film 908 and the insulating film 909. The back gate electrode 912 is formed on the insulating film 908. Titanium film (thickness 100 nm), aluminum film (thickness 200 nm), and titanium film ( A laminated film (100 nm thick) is formed by sputtering and selectively etched. The back gate electrode 912 was electrically connected to the source electrode 905a.

[0372] In addition, both the transistor 951 and the transistor 952 have a channel length of 3 μm. The width was set to 20 μm.

[0373] Next, the transistors 951 and 952 manufactured in this embodiment are subjected to The negative bias light irradiation test will now be described.

[0374] The negative bias light test is a type of accelerated test in which transistors are exposed to light. This allows for the evaluation of changes in transistor characteristics in a short time. The amount of change in Vth of the transistor is an important index for examining reliability. In the test, the smaller the change in Vth, the more reliable the transistor. The change in Vth before and after the negative bias light stress test is preferably 1 V or less, and more preferably 0.5 V or less. The bottom is even better.

[0375] Specifically, the negative bias light irradiation test is carried out by changing the temperature of the substrate on which the transistor is formed (substrate temperature ) is kept constant, the source electrode and the drain electrode of the transistor are set to the same potential, and light is irradiated. While applying the voltage to the gate electrode, a potential lower than that of the source electrode and the drain electrode is applied to the gate electrode for a certain period of time. This is done by:

[0376] The stress intensity of the negative bias light test depends on the light irradiation conditions, substrate temperature, and the stress applied to the gate insulating film. It can be determined by the electric field strength and the electric field application time. The potential is determined by setting the source electrode and the drain electrode at the same potential, and It is determined by dividing the potential difference between the gate electrode and the gate insulating film by the thickness of the gate insulating film. If you want to apply a 2MV / cm electric field to the gate insulating film, the potential difference should be 20V. That's fine.

[0377] In addition, under an environment where light is irradiated, the potential of the source electrode and the drain electrode is higher than that of the A test in which a low potential is applied to the gate electrode is called a positive bias light test. The negative bias light irradiation test is more likely to cause fluctuations in transistor characteristics than the negative bias light irradiation test. The shape is evaluated by a negative bias light test.

[0378] In the negative bias temperature stress test in this embodiment, the substrate temperature was set to room temperature (25° C.), and the gate insulating film The electric field strength applied to the film 902 was set to 2 MV / cm, and the light irradiation and electric field application time was set to 1 hour. The light irradiation conditions were as follows: Asahi Spectroscopy's xenon light source "MAX-302" was used. , peak wavelength 400nm (half width 10nm), irradiance 326μW / cm 2 It was decided.

[0379] Prior to the negative bias temperature stress test, the initial characteristics of the transistor to be tested were measured. In this embodiment, the substrate temperature is set to room temperature (25° C.), and the voltage between the source electrode and the drain electrode is (hereinafter referred to as drain voltage or Vd) is set to 3V, and the voltage between the source electrode and the gate electrode (hereafter referred to as gate voltage or Vg) is changed from -5V to +5V. The change characteristics of the current flowing between the electrode and the drain electrode (hereinafter referred to as drain current or Id) , that is, the Vg-Id characteristics were measured.

[0380] Next, light irradiation is started from the insulating film 909 side, and the source and drain electrodes of the transistor are The electric potential of the gate insulating film 902 of the transistor is set to 0V, and the electric field strength applied to the gate insulating film 902 of the transistor is set to 2MV / A negative voltage was applied to the gate electrode 901 so that the gate Since the thickness of the gate insulating film 902 is 30 nm, a voltage of −6 V is applied to the gate electrode 901. The voltage was applied for one hour, but the time can be adjusted depending on the purpose. You may change it.

[0381] Next, the voltage application was stopped, and the Vg-Id was measured under the same conditions as in the measurement of the initial characteristics while the light was still irradiated. The characteristics were measured to obtain the Vg-Id characteristics after a negative bias light exposure test.

[0382] Here, the definition of Vth in this embodiment will be explained with reference to FIG. The horizontal axis of 31 shows the gate voltage on a linear scale, and the vertical axis shows the square root of the drain current ( The curve 921 shows the Vg-Id characteristic. This is a curve that expresses the value of Id in terms of the square root (hereinafter also referred to as the √Id curve).

[0383] First, the √Id curve (curve 921) is obtained from the measured Vg-Id curve. Find the tangent 924 on the line at the point where the differential value of the √Id curve is maximum. Next, find the tangent 924 Vg when Id becomes 0 A on the tangent line 924, that is, the gate voltage axis of the tangent line 924 The value of the intercept 925 is defined as Vth.

[0384] FIG. 32 shows the characteristics of the transistors 951 and 952 before and after the negative bias temperature stress test. 32(A) and 32(B), the horizontal axis represents the gate voltage (Vg). The vertical axis shows the drain current (Id) versus gate voltage on a logarithmic scale.

[0385] FIG. 32A shows the Vg-Id characteristics of the transistor 951 before and after the negative bias temperature stress test. The initial characteristic 931 shows the Vg-Id of the transistor 951 before the negative bias light irradiation test. The post-test characteristic 932 is the Vg-I of the transistor 951 after the negative bias light irradiation test. The Vth of the initial characteristic 931 is 1.01 V, and the Vt of the post-test characteristic 932 is h was 0.44V.

[0386] FIG. 32B shows the Vg-Id characteristics of the transistor 952 before and after the negative bias temperature stress test. Also, Fig. 32(C) is an enlarged view of a portion 945 in Fig. 32(B). An initial characteristic 941 is a Vg-Id characteristic of the transistor 952 before the negative bias temperature stress test. A post-test characteristic 942 is a Vg-Id characteristic of the transistor 952 after the negative bias light irradiation test. The Vth of the initial characteristic 941 is 1.16 V, and the Vth of the post-test characteristic 942 is 1.1 The back gate electrode 912 of the transistor 952 was connected to the source electrode 905. a, the potential of the back gate electrode 912 and the source electrode 905a are at the same potential.

[0387] In FIG. 32(A), the post-test characteristic 932 has a negative Vth compared to the initial characteristic 931. In FIG. 32(B), the post-test characteristic 942 is different from the initial characteristic Compared to 941, Vth has changed by 0.06 V in the negative direction. The amount of change in Vth of both transistor 951 and transistor 952 is 1 V or less, and they are highly reliable transistors. It can be seen that the transistor 952 is provided with a back gate electrode 912. The change in Vth is less than 0.1V, which is more reliable than the transistor 951. It can be confirmed that this is a high-performance transistor. [Example]

[0388] By using a liquid crystal display device according to one embodiment of the present invention, a high-quality image can be displayed. Alternatively, it is possible to provide an electronic device capable of displaying a liquid crystal display according to one embodiment of the present invention. By using the device, it is possible to provide electronic equipment with low power consumption. In the case of a portable electronic device that is difficult to constantly receive power, the liquid crystal display device according to one embodiment of the present invention Adding additional components to the system also provides the benefit of longer continuous use. can be done.

[0389] The liquid crystal display device according to one aspect of the present invention is applicable to a display device, a notebook personal computer, a recording medium, and the like. Image playback devices equipped with recording media (typically DVD: Digital Versatile A device that plays back recording media such as discs and has a display that can display the images In addition, the liquid crystal display device according to one embodiment of the present invention can be used. Examples of electronic devices that can be used include mobile phones, portable game consoles, personal digital assistants, e-books, and video cameras. , digital still camera, goggle-type display (head-mounted display), Navigation systems, audio playback devices (car audio, digital audio players) etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs, vending machines, etc. Specific examples of these electronic devices are shown in Figure 33.

[0390] FIG. 33A shows an electronic book having a housing 7001, a display portion 7002, and the like. The liquid crystal display device according to this embodiment can be used in the display portion 7002. By using a liquid crystal display device according to one embodiment of the present invention, an electronic device capable of displaying high-quality images can be realized. It is possible to provide a book or an electronic book with low power consumption. By creating a panel using a plate and making the touch panel flexible, This allows for flexibility, making it a flexible, lightweight and user-friendly e-book reader. can be provided.

[0391] FIG. 33B shows a display device, which includes a housing 7011, a display portion 7012, a support base 7013, and the like. The liquid crystal display device according to one embodiment of the present invention can be used in the display portion 7012. By using the liquid crystal display device according to one embodiment of the present invention for the display portion 7012, it is possible to obtain a high-quality image. It is possible to provide a display device capable of displaying or a display device with low power consumption. Display devices include all information displays for personal computers, TV broadcast reception, advertising displays, etc. A display device for displaying information is included.

[0392] FIG. 33C shows an automated teller machine, which includes a housing 7021, a display unit 7022, a coin slot, and a There is an entrance 7023, a bill slot 7024, a card slot 7025, a bankbook slot 7026, etc. The liquid crystal display device according to one embodiment of the present invention can be used in the display portion 7022. By using the liquid crystal display device according to one embodiment of the present invention for the display portion 7022, it is possible to obtain a high-quality image. Displayable automated teller machines or low-power automated teller machines can be provided.

[0393] FIG. 33D shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The liquid crystal display device according to one embodiment of the present invention includes a display portion 7033, a display The display portion 7033 and the display portion 7034 can be used as an embodiment of the present invention. A portable game machine capable of displaying high-quality images by using the liquid crystal display device according to the present invention. Alternatively, a portable game machine with low power consumption can be provided. The portable game machine has two display units 7033 and 7034. The number of display units that the game machine has is not limited to this.

[0394] FIG. 33E shows a mobile phone, which includes a housing 7041, a display unit 7042, an audio input unit 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The liquid crystal display device according to one embodiment of the present invention can be used for the display portion 7042. By using a liquid crystal display device according to one embodiment of the present invention in the display device 42, high-quality images can be displayed. It is possible to provide a mobile phone that is capable of receiving data or consumes low power.

[0395] FIG. 33(F) shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 33(F) has a modem built in a housing 7051. The liquid crystal display device according to one embodiment of the present invention can be used for the display portion 7052. By using the liquid crystal display device according to one embodiment of the present invention for the display portion 7052, a high-quality image can be obtained. It is possible to provide a portable information terminal capable of displaying images or a portable information terminal with low power consumption. Cut.

[0396] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0397] 10 Pixel section 11 Scanning line driving circuit 12 Signal line driver circuit 15 pixels 16 transistors 17 Capacitor element 18 Liquid crystal element 20 Pulse output circuit 21 terminals 22 terminals 23 terminals 24 terminals 25 terminals 26 terminals 27 terminals 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 50 transistors 51 Transistor 52 transistors 53 Transistor 60 pixel section 61 Scanning line driving circuit 62 Signal line driver circuit 101 areas 102 areas 103 areas 120 Shift Register 121 Transistor 123 Switching elements 301 Full color image display period 302 Monochrome video display period 303 Monochrome still image display period 326 Irradiance 400 LCD display device 401 Image Memory 402 Image data selection circuit 403 Selector 404 CPU 405 Controller 406 Panel 407 Backlight 408 Backlight control circuit 410 full color image data 411 Monochrome image data 412 pixel section 413 Signal line driver circuit 414 Scanning line driving circuit 420 Input Device 421 Photometric circuit 501 gate electrode 502 Gate insulating film 503 Oxide semiconductor film 507 Insulating film 508 Capacitance wiring 513 Interlayer Film 541 Circuit Board 542 PCB 544 Liquid Crystal Layer 546 Transparent electrode 547 Reflecting electrode 548 Common electrode 549 Conductive Layer 550 transistors 555 Shielding membrane 598 Reflection area 599 Transparent area 601 area 602 areas 603 area 611 Shift Register 612 Shift Register 613 Shift Register 615 pixels 616 Transistor 617 Capacitor element 618 Liquid crystal element 620 Shift Register 623 Switching elements 700 boards 701 Insulating film 702 gate electrode 703 Gate insulating film 704 Oxide semiconductor film 705 Conductive film 706 Conductive film 707 Insulating Film 708 Transistor 900 boards 901 Gate electrode 902 Gate insulating film 903 Oxide semiconductor film 907 Insulating film 908 Insulating film 909 Insulating film 912 Back gate electrode 921 curve 924 Tangent line 925 Gate voltage axis intercept 931 Initial Characteristics 932 Post-test characteristics 936 Base film 941 Initial Characteristics 942 Post-test characteristics 945 parts 951 Transistor 952 transistors 1601 Panel 1602 Diffuser 1603 Prism Sheet 1604 Diffuser 1605 Light guide plate 1607 Backlight Panel 1608 Circuit Board 1609 COF tape 1610 FPC 1611 PCB 1612 backlight 2400 board 2401 Gate electrode 2402 Gate insulating film 2403 Oxide semiconductor film 2406 Channel Protection Layer 2407 Insulating film 2409 Protective insulating film 2411 Gate electrode 2412 Gate electrode 2413 Gate insulating film 2414 Gate insulating film 2436 Base film 2450 transistor 2460 transistor 2470 transistor 2480 transistor 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Opposing substrate 4007 LCD 4009 Transistor 4010 transistor 4011 Liquid crystal element 4014 Wiring 4015 Wiring 4016 Connection terminal 4018 FPC 4019 Anisotropic conductive film 4021 board 4022 transistor 4030 pixel electrode 4031 Counter electrode 4032 Reflective electrode 4033 Transparent electrode 4035 Spacer 4040 Shielding membrane 6110 Transposition Board 6111 Adhesive layer 6116 Peeling layer 6200 board 6201 Peeling layer 6202 Temporary support substrate 6203 Peeling adhesive 6206 Metal plate 6207 Barrier layer 6210 Wiring layer 6211 Wiring layer 6212 area 7001 Case 7002 Display section 7011 Case 7012 Display section 7013 Support stand 7021 Housing 7022 Display section 7023 Coin slot 7024 Bill slot 7025 Card slot 7026 Passbook slot 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section 7051 Housing 7052 Display section 7053 Operation Key 2405a Source electrode 2405b Drain electrode 505a Drain electrode 505b Drain electrode 560a Alignment film 560b alignment film 65a1 transistor 65an transistor 65b1 transistor 65bn transistor 65c1 transistor 65cm transistor 905a Source electrode 905b Drain electrode

Claims

1. a transistor and an insulating film, the insulating film is located above a channel formation region of the transistor, a channel formation region of the transistor includes an oxide semiconductor film, the oxide semiconductor film contains indium, In a negative bias light test, The temperature of the substrate on which the transistor is formed is set to 25°C, Irradiating the insulating film with light from above with a peak wavelength of 400 nm (half width 10 nm) and an irradiance of 326 μW / cm Applying an electric field strength of 2 MV / cm to the gate insulating film of the transistor and applying 0 V to the source electrode and the drain electrode of the transistor; The light irradiation and electric field application time was set to 1 hour. a threshold voltage calculated from the Vg-Id characteristics when the drain voltage of the transistor was set to 3 V before the negative bias temperature stress test; and After the negative bias light irradiation test, the difference between the threshold voltage calculated from the Vg-Id characteristics when the drain voltage of the transistor is set to 3 V while the light is still irradiated and the threshold voltage is 1 V or less.

2. In claim 1, The insulating film is a resin layer.

3. In claim 1 or claim 2, a gate insulating film of the transistor located below a channel forming region of the transistor; The semiconductor device comprises a gate insulating film of the transistor containing nitrogen and silicon.

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