Wiring board and method of manufacturing the same

Abstract

The present application discloses a technique capable of improving the quality of the shape of a plurality of solder bumps.SOLUTION: A method of manufacturing a wiring substrate of the present embodiment includes preparing a wiring substrate having a plurality of solder bumps in each of a plurality of electronic component mounting portions, a first flattening step of flattening upper surfaces of the plurality of solder bumps included in one electronic component mounting portion of the plurality of electronic component mounting portions, and a second flattening step of flattening upper surfaces of the plurality of solder bumps included in another electronic component mounting portion of the plurality of electronic component mounting portions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board having an electronic component mounting portion on which a plurality of solder bumps are arranged in a grid pattern, and a method for manufacturing the same. [Background technology]

[0002] Conventionally, as this type of wiring board, there is known one in which a plurality of solder bumps on an electronic component mounting portion are pressed by a pressure plate to flatten the tops of the plurality of solder bumps (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-140110 A (Fig. 3) Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional wiring boards described above, those having multiple electronic component mounting areas have a problem in that some solder bumps are not sufficiently crushed or flattened due to warping or partial unevenness on the top surface of the wiring board. Therefore, this application discloses a technology that can improve the quality of the shape of multiple solder bumps. [Means for solving the problem]

[0005] A first aspect of the presently disclosed invention is a method for manufacturing a wiring board, the method including: preparing a wiring board having a plurality of solder bumps on each of a plurality of electronic component mounting portions; a first planarization process for planarizing the top surfaces of the plurality of solder bumps included in one of the plurality of electronic component mounting portions; and a second planarization process for planarizing the top surfaces of the plurality of solder bumps included in another of the plurality of electronic component mounting portions.

[0006] A second aspect of the presently disclosed invention is a wiring board having a plurality of solder bumps on each of a plurality of electronic component mounting portions, wherein a plurality of first upper flat surfaces included in a common imaginary first press surface are formed on the plurality of solder bumps included in one of the plurality of electronic component mounting portions, and a plurality of second upper flat surfaces included in a common imaginary second press surface are formed on the plurality of solder bumps included in another of the plurality of electronic component mounting portions. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a side cross-sectional view of a wiring board according to this embodiment. [Figure 2] 2A and 2B are enlarged cross-sectional side views of an electronic component mounting portion. [Figure 3] Figure 3 shows a top view of the wiring board. [Figure 4] 4A to 4C are side cross-sectional views showing a method for manufacturing a wiring board. [Figure 5] 5A and 5B are side cross-sectional views showing a manufacturing method of a wiring board. [Figure 6] 6A and 6B are side cross-sectional views showing a manufacturing method of a wiring board. [Figure 7] FIG. 7 is a side cross-sectional view of a wiring board according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] The wiring board 10 of this embodiment will be described with reference to Figures 1 to 6. As shown in Figure 1, the wiring board 10 of this embodiment has a structure in which a plurality of conductive layers 12 and a plurality of insulating layers 13 are alternately laminated on the front and back of a core substrate 11, and a solder resist layer 20, which is an insulating layer, is laminated on the outermost layer.

[0009] The core substrate 11 is provided with a plurality of through-hole conductors 14 that penetrate the core substrate 11 in the thickness direction, and the plurality of insulating layers 13 are provided with a plurality of via conductors 15 that penetrate the insulating layers 13 in the thickness direction. The conductive layers 12 on the front and back of the core substrate 11 are connected to each other by the plurality of through-hole conductors 14, and adjacent conductive layers 12 sandwiching the insulating layer 13 are connected to each other by the plurality of via conductors 15.

[0010] The solder resist layer 20 has a plurality of openings 21 formed therein to expose a plurality of pads 12A included in the underlying conductive layer 12. In addition, solder balls are fixed to some or all of the plurality of openings 21 to form a plurality of solder bumps 30.

[0011] Although the plurality of through-hole conductors 14 in this embodiment are cylindrical and cover the inner surfaces of the plurality of through-holes 14H penetrating the core substrate 11, and are filled with resin 14J inside, the plurality of through-hole conductors 14 may also be solid columns that fill the entire inside of the through-holes 14H. Furthermore, although the wiring board 10 in this embodiment includes the core substrate 11, it may also have a structure in which a plurality of conductive layers 12 and a plurality of insulating layers 13 are stacked without including the core substrate 11.

[0012] Hereinafter, the upper surface of wiring board 10 in FIG. 1 will be simply referred to as "upper surface of wiring board 10," and the lower surface of wiring board 10 in FIG. 1 will be simply referred to as "lower surface of wiring board 10," and the detailed structure of wiring board 10 will be described.

[0013] As shown in FIGS. 1 and 3 , the top surface of the wiring substrate 10 is provided with a plurality of electronic component mounting sections 31 and 32 on which a plurality of electronic components 91 and 92 are mounted, and the plurality of solder bumps 30 described above are arranged in a grid pattern on each of the electronic component mounting sections 31 and 32. Specifically, the wiring substrate 10 is an interposer on which a plurality of chiplets are mounted as a plurality of electronic components, and is provided with a plurality of electronic component mounting sections corresponding to the plurality of chiplets. The plurality of electronic component mounting sections on the top surface of the wiring substrate 10 may also include electronic component mounting sections on which electronic components other than chiplets are mounted as necessary. FIGS. 1 and 3 show only the electronic components 91 and 92, which are some of the plurality of chiplets, and only the electronic component mounting sections 31 and 32, on which the electronic components 91 and 92 are mounted, among the plurality of electronic component mounting sections. Below, the electronic components 91 and 92, which are some of the plurality of chiplets, and the electronic component mounting sections 31 and 32, which are some of the plurality of chiplets, are described as examples.

[0014] In the multiple electronic component mounting areas 31, 32 on the upper surface of the wiring board 10, the electronic components 91, 92 are arranged, for example, two-dimensionally and grouped together, and are arranged inward from the outer edge of the upper surface of the wiring board 10. Furthermore, the multiple pads 12A connected to the multiple power lines of the electronic components 91, 92 are arranged densely inward from the outer edge of the lower surface of the wiring board 10, while the multiple pads 12A connected to the multiple signal lines of the electronic components 91, 92 are arranged sparsely along the outer edge of the lower surface of the wiring board 10. Correspondingly, the multiple through-hole conductors 14 of the core substrate 11 are arranged densely inward from the outer edge of the core substrate 11, specifically, directly below the multiple electronic component mounting areas 31, 32, but are arranged sparsely along the outer edge of the core substrate 11. Accordingly, the multiple via conductors 15 included in the insulating layer 13 and the circuits included in the conductive layer 12 are also arranged densely inward from the outer edge of the wiring board 10. Therefore, the conductive layer 12 formed by the plating film is thinner on the inside than on the outer edge of the wiring board 10, and the upper and lower surfaces of the wiring board 10 have a curved shape such that the inside is lower than the outer edge.

[0015] A flat upper surface 30J is formed on the top of the multiple solder bumps 30. In this embodiment, for example, the inclination of the upper surface 30J of the multiple solder bumps 30 differs for each of the electronic component mounting portions 31, 32. Specifically, as shown in FIGS. 1, 2A, and 2B, the electronic component mounting portion 31 is inclined upward to the left, for example, due to the warping of the upper surface of the wiring substrate 10 described above, and the upper surface 30J of the multiple solder bumps 30 of the electronic component mounting portion 31 is formed so as to be included in an imaginary first pressed surface 31P that is inclined upward to the left in accordance with the inclination. Furthermore, the electronic component mounting portion 32 is inclined upward to the right, for example, and as shown in FIG. 2B, the upper surface 30J of the multiple solder bumps 30 of the electronic component mounting portion 32 is formed so as to be included in an imaginary second pressed surface 32P that is inclined upward to the right.

[0016] 1, 2A, and 2B, the top surface of wiring board 10 including electronic component mounting portions 31 and 32 is inclined two-dimensionally, but it may also be inclined in the depth direction of the page, i.e., it may be inclined three-dimensionally. In accordance with this inclination, imaginary first pressed surface 31P and second pressed surface 32P may also be inclined three-dimensionally.

[0017] The method for manufacturing the wiring board 10 of this embodiment is, for example, as follows. (1) A copper-clad laminate 11D is prepared in which copper foil (not shown) is laminated on both the front and back surfaces of a core substrate 11, and a plurality of through holes 14H are formed by, for example, drilling (see FIG. 4A).

[0018] (2) Electroless plating and electrolytic plating are performed to form first plating films 16A on both sides of the copper-clad laminate 11D, and cylindrical through-hole conductors 14 are formed on the inner surfaces of the through-holes 14H.

[0019] As described above, the through-hole conductors 14 are densely packed inside the outer edge of the core substrate 11 (directly below the electronic component mounting portions 31, 32), but are sparsely distributed around the outer edge of the core substrate 11. Therefore, the area covered by the first plating film 16A is larger on the inside of the core substrate 11 than on the outer edge. Therefore, in this process, the thickness of the first plating film 16A (more specifically, the thickness of the first plating film 16A laminated on the inner surface of the through hole 14H and the thickness of the first plating film 16A laminated on the upper surface of the copper foil) is made thinner on the inside of the core substrate 11 than on the outer edge.

[0020] (3) Next, after resin 14J is filled into the multiple through-hole conductors 14, the portion of resin 14J that protrudes above the surface of first plating film 16A is polished so that the end face of resin 14J and the surface of first plating film 16A are approximately flush with each other, as shown in Figure 4B.

[0021] (4) Further, electroless plating and electrolytic plating are performed to form a second plating film 16B on the first plating film 16A and the resin 14J. Then, an etching resist (not shown) is formed on the second plating film 16B, and then the copper foil, the first plating film 16A, and the second plating film 16B exposed by the etching resist are removed, and then the etching resist is removed. This results in a conductive layer 12 consisting of the first plating film 16A and the second plating film 16B on the core substrate 11 (see FIG. 4C ). Note that in this process of forming the second plating film 16B, the difference in the area covered by the second plating film 16B between the inside and outer edge of the core substrate 11 is small because no through-hole conductors are formed. Therefore, it is considered that the difference in thickness of the second plating film 16B between the inside and outer edge of the core substrate 11 is small or nonexistent.

[0022] 5A, a plurality of insulating layers 13 and a plurality of conductive layers 12 are alternately stacked by the SAP method. At this time, the plurality of via conductors 15 included in insulating layer 13 and the circuits included in conductive layer 12 are densely packed inward due to the outer edge of wiring board 10, so that conductive layer 12 formed by plating is thinner on the inside than on the outer edge of wiring board 10, and the top and bottom surfaces of wiring board 10 have a warped shape in which the inside is lower than the outer edge.

[0023] (6) As shown in Fig. 5B, a solder resist layer 20 having a plurality of openings 20H is laminated. This forms a plurality of pads 12A exposed from the plurality of openings 20H of the solder resist layer 20. Note that Fig. 5B and Fig. 6 only show the upper surface side of the wiring board 10 above the core substrate 11.

[0024] (7) As shown in FIG. 6A, for example, solder balls are fixed to some or all of the pads 12A to form a plurality of solder bumps 30.

[0025] (8) Next, in order to flatten the tops of the plurality of solder bumps 30, as shown in FIG. 6B , the pressure plate P is pressed against each of the electronic component mounting portions 31 and 32 separately. Specifically, for example, the pressure plate P is pressed against the electronic component mounting portion 31 and then the electronic component mounting portion 32 in that order. At this time, the press surface P1 of the pressure plate P pressing against the plurality of solder bumps 30 on the electronic component mounting portion 31 is inclined upward to the left in FIG. 6B to match the inclination of the upper surface of the wiring board 10 on which the electronic component mounting portion 31 is disposed, whereas the press surface P1 of the pressure plate P pressing against the plurality of solder bumps 30 on the electronic component mounting portion 32 is inclined upward to the right in FIG. 6B to match the inclination of the upper surface of the wiring board 10 on which the electronic component mounting portion 32 is disposed. Thus, the inclination of the pressure plate P differs between the electronic component mounting portions 31 and 32. Furthermore, in addition to the inclination of the press surface P1 of the pressure plate P, the amount of vertical movement of the pressure plate P from its standby position is also adjusted as necessary for each of the electronic component mounting portions 31, 32. As a result, as shown in Fig. 1, an upper flat surface 30J included in the imaginary first press surface 31P is formed above the plurality of solder bumps 30 of the electronic component mounting portion 31, and an upper flat surface 30J included in the imaginary second press surface 32P is formed above the plurality of solder bumps 30 of the electronic component mounting portion 32. In this way, the wiring substrate 10 is completed.

[0026] In addition, the configuration is not limited to the above-described configuration in which the pressure plate P is pressed against each of the electronic component mounting portions 31, 32 in sequence, but may also be a configuration in which multiple pressure plates P corresponding to multiple electronic component mounting portions 31, 32 are provided and multiple pressure plates P are pressed against each other simultaneously.

[0027] In this process, the inclination of the pressure plate P or the vertical position of the pressure plate P is determined for each electronic component mounting portion 31, 32 in accordance with the warping of the upper surface of the wiring board 10, thereby reducing the variation in the amount of crushing of the multiple solder bumps 30 in each electronic component mounting portion 31, 32, and making the area of ​​the upper flat surface 30J of the multiple solder bumps 30 approximately uniform.

[0028] This completes the description of the structure of the wiring board 10 and its manufacturing method according to this embodiment. Next, the effects of the wiring board 10 will be described. As described above, in the wiring board 10 according to this embodiment, the pressure plate P is pressed against the plurality of solder bumps 30 separately for each of the electronic component mounting portions 31, 32, so that it is possible to accommodate warping of the upper surface of the wiring board 10. This allows the plurality of solder bumps 30 to be sufficiently crushed, improving the quality of the shape of the solder bumps 30. Furthermore, in this embodiment, the pressure plate P is pressed against each of the electronic component mounting portions 31, 32, so the precision of the flatness of the upper flat surface 30J of the plurality of solder bumps 30 on each of the electronic component mounting portions 31, 32 is improved, improving the reliability of the connection with the plurality of electronic components 91, 92.

[0029] Furthermore, in this embodiment, the inclination of the pressure plate P can be changed for each electronic component mounting portion 31, 32, and the inclination of the pressure plate P is adjusted to match the inclination caused by warping on the upper surface of the wiring board 10, thereby further improving the flatness accuracy of the upper surface 30J of the multiple solder bumps 30 on each electronic component mounting portion 31, 32.

[0030] [Other embodiments] In the above embodiment, the inclinations of the imaginary planes 31P, 32P including the upper planes 30J of the plurality of solder bumps 30 of the electronic component mounting portions 31, 32 are different, but for example, the inclinations of the imaginary planes 31P, 32P may be the same but the positions in the vertical direction may be different. Also, in the above embodiment, the imaginary planes 31P, 32P are inclined in accordance with the inclination due to the warping of the upper surface of the wiring substrate 10, but for example, as shown in Fig. 7, the imaginary planes 31P, 32P may be horizontal and the positions in the vertical direction of the imaginary planes 31P, 32P may be different.

[0031] In the above embodiment, the upper surface of wiring substrate 10 is warped so that it becomes lower as it approaches the center, but for example, the upper surface of wiring substrate 10 may be warped so that it becomes higher as it approaches the center. In addition, the lowest or highest position on the upper surface of wiring substrate 10 is not limited to the center of wiring substrate 10 in a plan view, and may be any position. Furthermore, in the above embodiment, an example has been described in which the entire upper surface of wiring substrate 10 is warped, but the upper surface of wiring substrate 10 may be configured to be partially raised.

[0032] In the above embodiment, an example is shown in which the top surface of wiring board 10 is warped or partially undulating due to the arrangement density of multiple through-hole conductors 14 in core substrate 11 or the arrangement of circuits in multiple conductive layers 12, but the causes of the top surface of wiring board 10 being warped or partially bulging are not limited to this. For example, the top surface of wiring board 10 may be warped or partially bulged due to electronic components being embedded in core substrate 11 or in a layer outer than core substrate 11.

[0033] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, and also includes parts of the specific examples taken out alone. [Explanation of symbols]

[0034] 10. Wiring board 11 Core substrate 14 through-hole conductor 15 Via conductor 30 Solder bumps 30J Upper plane (1st upper plane, 2nd upper plane) 31, 32 Electronic component mounting section 31P 1st press page 32P 2nd press page 91,92 Electronic Components P pressure plate P1 Press surface

Claims

1. A wiring board having a plurality of solder bumps on each of a plurality of electronic component mounting portions is prepared; a first planarization step of planarizing upper surfaces of the plurality of solder bumps included in one of the plurality of electronic component mounting portions; a second planarization step of planarizing upper surfaces of the plurality of solder bumps included in other electronic component mounting portions of the plurality of electronic component mounting portions.

2. 2. The method for manufacturing a wiring board according to claim 1, The first planarizing step and the second planarizing step are performed using separate pressure plates.

3. 2. The method for manufacturing a wiring board according to claim 1, The first planarizing step and the second planarizing step are performed using the same pressure plate.

4. 2. The method for manufacturing a wiring board according to claim 1, The inclination of the pressure plate is changed between the first planarizing step and the second planarizing step.

5. 2. The method for manufacturing a wiring board according to claim 1, The wiring board has a warp on the upper surface, The inclination of the pressure plate in each of the first planarization step and the second planarization step is determined in accordance with the inclination due to the warp of the upper surface of the wiring substrate.

6. A wiring board having a plurality of solder bumps on each of a plurality of electronic component mounting portions, a plurality of first upper flat surfaces included in a common imaginary first press surface are formed on the plurality of solder bumps included in one of the plurality of electronic component mounting portions; A wiring board in which a plurality of second upper flat surfaces included in a common imaginary second press surface are formed on the plurality of solder bumps included in other electronic component mounting portions among the plurality of electronic component mounting portions.

7. 7. The wiring board according to claim 6, The first press surface and the second press surface have different inclinations.

8. 7. The wiring board according to claim 6, The wiring board has a warp on the upper surface, The first press surface and the second press surface are each inclined to match the inclination caused by the warp of the upper surface of the wiring substrate.

9. 9. The wiring board according to claim 6, The plurality of solder bumps included in the one electronic component mounting portion and the plurality of solder bumps included in the other electronic component mounting portion are connected by wiring inside the wiring board.

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