Memory system and method

Abstract

To provide a memory system and method capable of suitably correcting a value of a read level.SOLUTION: The memory system includes a memory controller and a NAND flash memory (NAND memory). The memory controller reads data from the first page of each of the N memory cell groups by using a value of a first read level obtained by changing a set value of the first read level in a change pattern defined by each different row of the first planning matrix, the plurality of first coefficients of the first model formula are calculated based on the number of error bits included in the data read from the first page of each of the N memory cell groups and the first pseudo inverse matrix, the correction amount of the set value of the first read level is calculated based on the calculated values of the plurality of first coefficients and the first model formula, and the set value of the first read level is updated based on the correction amount.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiments relate to a memory system and method. [Background technology]

[0002] Conventionally, memory systems having memory cell transistors are widely known, and in such memory systems, during a read operation, data held in the memory cell transistors is determined based on a comparison between the threshold voltage of the memory cell transistor and a read level.

[0003] The threshold voltage of a memory cell transistor can change due to various factors, so the memory system is configured to be able to correct the value of the read level. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2020-47318 [Patent Document 2] U.S. Patent No. 9,922,707 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a memory system and method capable of appropriately correcting the value of the read level. [Means for solving the problem]

[0006] According to one embodiment, a memory system includes a nonvolatile first memory, a second memory, and a memory controller. The first memory includes a plurality of word lines and a plurality of memory cell groups, each connected to one of the plurality of word lines. Each of the plurality of memory cell groups includes a first page, which is a storage area from which data is read using a first read level, and a second page, which is a storage area from which data is read using a second read level. The second memory stores first information, second information, and third information. The first information is information in which a setting value of the first read level is recorded. The second information is second information in which a first design matrix having N rows (N is an integer equal to or greater than 2) that defines a change pattern of the first read level is recorded. The third information is information in which a first pseudo-inverse matrix that is a pseudo-inverse matrix of the first model matrix is ​​recorded. The first model matrix has N rows and is a model matrix corresponding to the first design matrix and the first model formula. The first model formula has the first read level as an explanatory variable, the number of error bits as a response variable, a position-dependent term that is a term that depends on the position in N memory cell groups among the plurality of memory cell groups, and a plurality of first coefficients. The memory controller reads data from the first page of each of the N memory cell groups using a first read level value obtained by changing the setting value of the first read level according to a change pattern defined by each different row of the first design matrix. The memory controller calculates a plurality of first coefficients based on the number of error bits included in the data read from the first page of each of the N memory cell groups and a first pseudoinverse matrix. The memory controller calculates a correction amount for the setting value of the first read level to reduce the number of error bits generated during a read operation for the first page of the N memory cell groups based on the calculated values ​​of the plurality of first coefficients and the first model formula. The memory controller updates the setting value of the first read level recorded in the first information based on the correction amount. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a memory system according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a memory chip CP according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing the circuit configuration of a block BLK according to the first embodiment. [Figure 4] FIG. 2 is a diagram for explaining an example of data coding according to the first embodiment. [Figure 5] FIG. 10 is a diagram showing another example of threshold voltages that the memory cell of the first embodiment can take. [Figure 6] FIG. 2 is a diagram for explaining an example of a sequential read method according to the first embodiment. [Figure 7] FIG. 10 is a diagram showing an example of the relationship between the FBC resulting from one read level and the value of the read level according to the first embodiment. [Figure 8] FIG. 10 is a diagram showing a model formula according to the first embodiment that represents FBC that occurs in a read operation on a lower page. [Figure 9] FIG. 10 is a diagram showing an example of the configuration of a correction unit for a read level correction operation for a lower page according to the first embodiment. [Figure 10] 10A and 10B are diagrams showing examples of a design matrix Dl and a model matrix Xl related to a read level correction operation for a lower page according to the first embodiment. [Figure 11] FIG. 10 is a diagram showing an example of the configuration of a correction unit for a read level correction operation for a middle page according to the first embodiment. [Figure 12] FIG. 10 is a diagram showing a model formula according to the first embodiment that represents an FBC that occurs in a read operation on a middle page. [Figure 13] 10A and 10B are diagrams showing examples of a design matrix Dm and a model matrix Xm related to a read level correction operation for a middle page according to the second embodiment. [Figure 14] FIG. 10 is a diagram showing an example of the configuration of a correction unit for a read level correction operation for an upper page according to the first embodiment. [Figure 15] FIG. 2 is a diagram showing an example of data stored in a RAM included in the memory system of the first embodiment. [Figure 16] FIG. 4 is a schematic diagram for explaining a data flow in a read level correction operation according to the first embodiment. [Figure 17] 4 is a flowchart showing an example of the operation of the memory system according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, a memory system and a method according to embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0009] (First embodiment) Fig. 1 is a diagram showing an example of the configuration of a memory system according to the first embodiment. As shown in Fig. 1, the memory system 1 can be connected to a host 2. The host 2 is, for example, a server, a personal computer, or a mobile information processing device. The memory system 1 functions as an external storage device for the host 2. The host 2 can issue commands to the memory system 1. The commands to the memory system 1 include read commands and write commands.

[0010] The memory system 1 includes a memory controller 10, a NAND flash memory (NAND memory) 20, and a RAM (Random Access Memory) 30. The NAND memory 20 includes one or more memory chips CP.

[0011] Each memory chip CP includes a plurality of memory cell transistors and is capable of storing data in a nonvolatile manner. Each memory chip CP is connected to the memory controller 10 via a channel CH.

[0012] As an example, the NAND memory 20 includes four memory chips CP0-0, CP0-1, CP1-0, and CP1-1. The memory system 1 includes two channels CH0 and CH1. The memory chips CP0-0 and CP0-1 are connected to the memory controller 10 via the channel CH0. The memory chips CP1-0 and CP1-1 are connected to the memory controller 10 via the channel CH1.

[0013] The RAM 30 may be configured with a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination thereof. The functions of the RAM 30 may be realized by any other type of memory that can operate faster than the NAND memory 20. The functions of the RAM 30 may be realized by two or more types of memory.

[0014] The memory controller 10 includes a CPU (Central Processing Unit) 11, a host interface (host I / F) 12, a RAMC (Random Access Memory Controller) 13, a NANDC (NAND memory controller) 14, and an ECC circuit (Error Correction Code circuit) 15.

[0015] The memory controller 10 may be configured as, for example, a System-On-a-Chip (SoC). The memory controller 10 may be configured with multiple chips. The memory controller 10 may include an FPGA (field-programmable gate array) or an ASIC (application specific integrated circuit) instead of or in addition to the CPU 11. That is, the memory controller 10 may be configured with software, hardware, or a combination thereof. The RAM 30 may be disposed within the memory controller 10.

[0016] The host interface 12 is connected to the host 2 via a bus conforming to the SATA (Serial Advanced Technology Attachment) standard, the SAS (Serial Attached SCSI) standard, or the PCI (Peripheral Components Interconnect) Express™ standard, for example. The host interface 12 is a circuit that controls communication between the memory controller 10 and the host 2.

[0017] The NANDC 14 is a circuit that is connected to each memory chip CP via one of the channels CH and controls communication between the memory controller 10 and each memory chip CP.

[0018] The CPU 11 controls the operation of the memory controller 10 .

[0019] The RAMC 13 is connected to the RAM 30. The RAMC 13 is a circuit that controls communication between the memory controller 10 and the RAM 30.

[0020] The ECC circuit 15 uses an error correction code to detect error bits and correct the detected error bits. The detection of error bits and the correction of the detected error bits are simply referred to as error correction.

[0021] Furthermore, when error bits are detected, the ECC circuit 15 can output the number of detected error bits. The number of detected error bits is referred to as FBC (Fail Bit Count). The ECC circuit 15 calculates the FBC based on a comparison between the data before and after error correction, and outputs the calculated FBC.

[0022] The calculation of the FBC may be performed by another circuit (for example, the CPU 11). The location where the ECC circuit 15 is provided is not limited to outside the NANDC 14. The ECC circuit 15 may be provided inside the NANDC 14.

[0023] 2 is a diagram showing an example of the configuration of the memory chip CP according to the first embodiment. As shown in the figure, the memory chip CP includes a processing circuit 210 and a memory cell array 211.

[0024] The memory cell array 211 is divided into multiple subarrays, each belonging to a different plane P. Here, the memory cell array 211 is divided into a subarray belonging to plane P0 and a subarray belonging to plane P1. Each subarray includes multiple blocks BLK (BLK0, BLK1, ...), each of which is a collection of multiple nonvolatile memory cell transistors. Each block BLK includes multiple string units SU (SU0, SU1, ...), each of which is a collection of memory cell transistors associated with a word line and a bit line. Each string unit SU includes multiple NAND strings 214, each of which is formed by serially connecting memory cell transistors. The number of NAND strings 214 in a string unit SU is arbitrary. The number of divisions of the memory cell array 211 is not limited to two. The memory cell array 211 does not necessarily have to be divided into multiple subarrays.

[0025] The processing circuit 210 includes, for example, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generation circuit. The processing circuit 210 performs a program operation, a sense operation, and an erase operation on the sub-arrays of each plane P in response to an instruction from the memory controller 10.

[0026] The program operation is an operation for writing data to the memory cell array 211. The sense operation is an operation for reading data from the memory cell array 211.

[0027] A series of operations in which the memory controller 10 writes data to the memory chip CP is referred to as a write operation. The write operation is composed of a data-in operation in which the memory controller 10 transfers data to the memory chip CP, and a program operation in which the processing circuit 210 writes the data received by the data-in operation to the memory cell array 211.

[0028] A series of operations in which the memory controller 10 reads data from the memory chip CP is referred to as a read operation. The read operation is composed of a sense operation in which the processing circuit 210 reads data from the memory cell array 211, and a data-out operation in which the memory controller 10 acquires the data read by the sense operation from the memory chip CP.

[0029] 3 is a diagram showing the circuit configuration of a block BLK according to the first embodiment. Each block BLK has the same configuration. The block BLK has, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings 214.

[0030] Each of the NAND strings 214 includes, for example, 64 memory cell transistors MT (MT0 to MT63) and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer and store data in a non-volatile manner. The 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The memory cell transistors MT may be of the MONOS type, which uses an insulating film for the charge storage layer, or of the FG type, which uses a conductive film for the charge storage layer. Furthermore, the number of memory cell transistors MT in the NAND string 214 is not limited to 64.

[0031] The gates of the select transistors ST1 in each of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In contrast, the gates of the select transistors ST2 in each of the string units SU0 to SU3 are commonly connected to, for example, a select gate line SGS. The gates of the select transistors ST2 in each of the string units SU0 to SU3 may be connected to select gate lines SGS0 to SGS4 that differ for each string unit SU. The control gates of the memory cell transistors MT0 to MT63 in the same block BLK are commonly connected to word lines WL0 to WL63, respectively.

[0032] The drains of the select transistors ST1 of the NAND strings 214 in the string units SU are connected to different bit lines BL (BL0 to BL(L-1), where L is a natural number equal to or greater than 2). The bit lines BL commonly connect one NAND string 214 in each string unit SU across multiple blocks BLK. The sources of the select transistors ST2 are commonly connected to a source line SL.

[0033] That is, a string unit SU is a collection of NAND strings 214 connected to different bit lines BL and the same select gate line SGD. A block BLK is a collection of multiple string units SU that share a word line WL. The memory cell array 211 is a collection of multiple blocks BLK that share a bit line BL.

[0034] The program operation and sense operation for one plane P by the processing circuit 210 are performed collectively on the memory cell transistors MT connected to one word line WL in one string unit SU. Hereinafter, a group of memory cell transistors MT selected collectively during the program operation and sense operation for one plane P will be referred to as a memory cell group WLSC. A storage area for a collection of 1-bit data written to or read from one memory cell group WLSC will be referred to as a "page."

[0035] Hereinafter, the memory cell transistor MT will be simply referred to as a memory cell.

[0036] Each memory cell can be written with n (n≧1) bits of data. When n bits of data are written to each memory cell, the storage capacity per memory cell group WLSC is equal to the size of n pages. A mode where n is 1 is called SLC (Single Level Cell) mode. A mode where n is 2 is called MLC (Multi Level Cell) mode. A mode where n is 3 is called TLC (Triple Level Cell) mode. A mode where n is 4 is called QLC (Quad Level Cell) mode.

[0037] The threshold voltage of each memory cell is controlled within a certain range by the processing circuit 210. The controllable range of the threshold voltage is divided into a number of divisions equal to the nth power of 2, and a different value is assigned to each division.

[0038] Hereinafter, an example in which memory cells are used in TLC mode will be described. That is, each memory cell group WLSC is assumed to constitute three pages. Note that the embodiment is not limited to a system in which memory cells are used in TLC mode, but can be applied to a system in which memory cells are used in any mode.

[0039] FIG. 4 is a diagram for explaining an example of data coding according to the first embodiment.

[0040] As mentioned above, in the TLC mode, three bits of data are stored per memory cell. The bits constituting the three bits of data stored in the memory cell are referred to as the upper bit, the middle bit, and the lower bit according to their order. Of the three pages included in the memory cell group MSG, the page in which the group of upper bits is stored is referred to as the upper page, the page in which the group of middle bits is stored is referred to as the middle page, and the page in which the group of lower bits is stored is referred to as the lower page.

[0041] In the TLC mode, the range of possible threshold voltages is divided into eight ranges. These eight ranges are referred to as the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G” state, in ascending order of threshold voltage. The threshold voltage of each memory cell is controlled by the processing circuit 210 so that it belongs to one of the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G” state. As a result, when the number of memory cells is plotted against the threshold voltage, the memory cells ideally form a distribution of eight non-overlapping lobes, each belonging to a different state, as shown in the middle of Figure 4. Hereinafter, the distribution of each state may be simply referred to as a lobe.

[0042] The eight states correspond to three bits of data. The upper table in Figure 4 shows an example of the correspondence between states and three bits of data, i.e., data coding. In this example, the "Er" state corresponds to "111," the "A" state corresponds to "110," the "B" state corresponds to "100," the "C" state corresponds to "000," the "D" state corresponds to "010," the "E" state corresponds to "011," the "F" state corresponds to "001," and the "G" state corresponds to "101." When three bits of data are written as "abc," "a" is the upper bit, "b" is the middle bit, and "c" is the lower bit. In this way, each memory cell can store data corresponding to the state to which its threshold voltage belongs. The correspondence between states and data shown in Figure 4 is an example of data coding. Data coding is not limited to the example shown in this figure.

[0043] The threshold voltage is lowered to the "Er" state by an erase operation, and the threshold voltage is either maintained in the "Er" state or raised to any of the "A", "B", "C", "D", "E", "F", and "G" states by a program operation.

[0044] Specifically, in a program operation, the processing circuit 210 selects a bit line BL corresponding to a column address. The processing circuit 210 sets the potential of the selected bit line BL to zero. The processing circuit 210 selects a word line WL corresponding to a row address and applies a programming pulse to the selected word line WL. This injects electrons into the charge storage layer of the memory cell located at the intersection of the selected bit line BL and the selected word line WL, resulting in an increase in the threshold voltage of the memory cell. The processing circuit 210 reads data at a predetermined timing to verify whether the threshold voltage of the memory cell has reached a target state corresponding to the write data (verify read). The processing circuit 210 continues applying the program pulse until the threshold voltage of the memory cell reaches the target state.

[0045] Hereinafter, a memory cell whose threshold voltage has been set to a certain state by a program operation may be referred to as a memory cell belonging to that state.

[0046] A read level, which is a potential for determining data, is set between two adjacent states. For example, as illustrated in Figure 4, a read level VA is set between the "Er" state and the "A" state, a read level VB is set between the "A" state and the "B" state, a read level VC is set between the "B" state and the "C" state, a read level VC is set between the "C" state and the "D" state, a read level VE is set between the "D" state and the "E" state, a read level VF is set between the "E" state and the "F" state, and a read level VG is set between the "F" state and the "G" state.

[0047] In the sense operation, the processing circuit 210 sequentially applies a plurality of read levels to the selected word line WL, and determines for each memory cell whether the memory cell is in a conductive state (i.e., an on state) or a non-conductive state (i.e., an off state) when each read level is applied. Then, the processing circuit 210 determines the data associated with the state to which the memory cell belongs by performing a logical operation using the determination results obtained for each applied read level.

[0048] Hereinafter, the operation of applying a single type of read level VX (X is any one of A to G) to a selected word line WL and determining for each memory cell whether the memory cell is in an on state or an off state will be referred to as X read, or in some figures, abbreviated as XR. Also, the determination result by X read will be referred to as determination result XR.

[0049] When the data coding shown in FIG. 4 is adopted, if a memory cell belongs to any of the “Er” state, “E” state, “F” state, and “G” state, the lower bit of the data held by that memory cell is “1.” If a memory cell belongs to any of the “A” state, “B” state, “C” state, and “D” state, the lower bit of the data held by that memory cell is “0.” Therefore, the processing circuit 210 determines the data of the upper page by using two read levels, VA and VE. Specifically, the processing circuit 210 performs an A read and an E read, and acquires the data of the lower page by a logical operation using the determination result AR obtained by the A read and the determination result ER obtained by the E read. In other words, the lower page is a storage area from which data is read using the read levels VA and VE.

[0050] When a memory cell belongs to any of the “Er” state, “A” state, “D” state, and “E” state, the middle bit of the data held by the memory cell is “1.” When a memory cell belongs to any of the “B” state, “C” state, “F” state, and “G” state, the middle bit of the data held by the memory cell is “0.” Therefore, the processing circuit 210 determines the data of the middle page by using three read levels: VB, VD, and VF. Specifically, the processing circuit 210 performs a B read, a D read, and an F read. Then, the processing circuit 210 obtains the data of the middle page by performing a logical operation using the determination result BR obtained by the B read, the determination result DR obtained by the D read, and the determination result DF obtained by the F read. In other words, the middle page is a storage area from which data is read using the read levels VB, VD, and VF.

[0051] When a memory cell belongs to any of the "Er" state, "A" state, "B" state, and "G" state, the upper bit of the data held by that memory cell is "1." When a memory cell belongs to any of the "C" state, "D" state, "E" state, and "F" state, the upper bit of the data held by that memory cell is "0." Therefore, the processing circuit 210 determines the data of the upper page by using two read levels, VC and VG. Specifically, the processing circuit 210 performs a C read and a G read, and acquires the data of the upper page by a logical operation using the determination result CR obtained by the C read and the determination result GR obtained by the G read. In other words, the upper page is a storage area from which data is read using the read levels VC and VG.

[0052] In this way, the type of read level used to determine the data differs depending on the type of page to be read. The processing circuit 210 acquires data of the page to be read by combining the results of determining whether the threshold voltage of the memory cell is higher or lower than the read level, using each of multiple read levels corresponding to the type of page to be sensed individually.

[0053] Hereinafter, the lower page, middle page, and upper page will be referred to as page types.

[0054] FIG. 4 illustrates a memory cell with eight non-overlapping lobes. However, the threshold voltage of a memory cell can change due to various factors. For example, the threshold voltage of a memory cell tends to change depending on the time elapsed since the completion of a program operation. The rate of change in the threshold voltage of a memory cell is fastest immediately after the completion of a program operation and slows down as time passes. The more times a memory cell undergoes erase and program cycles, the more likely it is that its threshold voltage will change. Furthermore, the change in the threshold voltage of a memory cell can be affected not only by the time elapsed since the completion of a program operation, but also by the sensing operation of the memory cell, the sensing operation of adjacent memory cells, the temperature during access, and so on. Because the threshold voltage of a memory cell can change, in reality, two adjacent lobes may overlap each other during a sensing operation.

[0055] FIG. 5 is a diagram showing another example of threshold voltages that memory cells according to the first embodiment can take. For ease of explanation, the diagram illustrates the distribution of memory cells belonging to either the "A" state or the "B" state. The solid line indicates the distribution of memory cells belonging to either the "A" state or the "B" state. The dashed line indicates the lobe of the "A" state, and the dashed line indicates the lobe of the "B" state. In this example, a portion of the high-voltage side of the lobe of the "A" state overlaps a portion of the low-voltage side of the lobe of the "B" state. In other words, the maximum value of the threshold voltage of memory cells belonging to the "A" state exceeds the read level VB, and the minimum value of the threshold voltage of memory cells belonging to the "B" state is below the read level VB. When a memory cell belonging to the "A" state and whose threshold voltage is greater than the read level VB is read, the memory cell is recognized as belonging to the "B" state. That is, data programmed as "110" is read as "100." When a memory cell in the "B" state whose threshold voltage is lower than the read level VB is read, the memory cell is recognized as belonging to the "A" state. That is, data programmed as "100" is read as "110."

[0056] In this way, the data read by the sense operation may change from the value at the time of the program operation due to a change in the threshold voltage. The memory controller 10 responds to changes in the data and threshold voltage by performing error correction or the like. Specifically, the memory controller 10 performs error correction on the read data using the ECC circuit 15. The memory controller 10 may be provided with an error correction function that is more powerful than that of the ECC circuit 15 in case the error correction by the ECC circuit 15 fails.

[0057] Note that a failed error correction means that the data before the change cannot be restored from the data after the change. Specifically, a failed error correction means that an error bit contained in the read data cannot be corrected. A successful error correction means that all error bits contained in the read data have been corrected.

[0058] There is an upper limit to the error correction capability of the memory controller 10. The memory controller 10 is configured to be able to change the value of the read level to perform a read operation so that errors in the read data can be corrected using the error correction capability of the memory controller 10. A read operation performed by changing the value of the read level is referred to as a shift read.

[0059] The read level can be expressed by various amounts. In one example, a fixed value is set in advance for each type of read level (VA to VG), and the read level is expressed by a shift amount (i.e., a difference) from the fixed value. Also, a fixed value is recorded for each type of read level in a predetermined location in the memory chip CP. In shift read, the memory controller 10 instructs the memory chip CP on the shift amount from the fixed value for each type of read level.

[0060] The method of expressing and indicating the read level is not limited to this. For example, the value of the read level may be expressed as a net voltage value rather than a difference, and the read level may be indicated to the memory chip CP as a net voltage value.

[0061] The memory controller 10 adjusts the read level setting at a predetermined timing to minimize the number of error bits generated during a read operation. The read level value that minimizes the number of error bits generated during a read operation is referred to as the optimal read level for convenience. For example, when the threshold voltages are distributed as shown in the graph of FIG. 5, the voltage value VB' at which the distribution of memory cells belonging to either the "A" state or the "B" state reaches a minimum is considered to be the optimal read level VB_opt for the read level VB.

[0062] The memory controller 10 corrects the set value of the read level using a predetermined condition as a trigger, thereby preventing the number of error bits from exceeding the upper limit determined by the error correction capability of the memory controller 10. Hereinafter, the operation of correcting the set value of the read level will be simply referred to as the read level correction operation.

[0063] One of the read methods for efficiently acquiring data requested by the host 2 from the NAND memory 20 is the sequential read method.

[0064] 6 is a diagram for explaining an example of the sequential read method of the first embodiment. In the example shown in this diagram, the memory chip CP includes four planes P (i.e., planes P0 to P3).

[0065] The memory controller 10 executes successive read operations on the memory chips CP0-0 and CP0-1 commonly connected to the channel CH0 in the order shown by the dotted lines in Figure 6. A logical block is formed by the blocks BLKa of plane P0, BLKb of plane P1, BLKc of plane P2, and BLKd of plane P3 collected from the memory chip CP0-0, and the blocks BLKe of plane P0, BLKf of plane P1, BLKg of plane P2, and BLKh of plane P3 collected from the memory chip CP0-1. The memory controller 10 then executes a read operation of the lower page of all blocks BLK, a read operation of the middle page of all blocks BLK, and a read operation of the upper page of all blocks BLK for that logical block, in that order. When the memory controller 10 completes a read operation of the lower pages of all blocks BLK, a read operation of the middle pages of all blocks BLK, and a read operation of the upper pages of all blocks BLK for one memory cell group WLSC, it executes a read operation of the lower pages of all blocks BLK, a read operation of the middle pages of all blocks BLK, and a read operation of the upper pages of all blocks BLK for another memory cell group WLSC.

[0066] All planes P included in CP0-0 and all planes P included in CP0-1 can operate independently of each other. However, CP0-0 and CP0-1 are commonly connected to channel CH0. Therefore, while a data-out operation is being performed on one plane P, it is not possible to perform a data-out operation on data obtained from another page or to transfer a command via channel CH0.

[0067] In the sequential read method, the memory controller 10 performs a sense operation on another plane P while the channel CH0 is occupied by a data-out operation on a certain plane P. For example, while the memory controller 10 is causing the memory chip CP0-0 to sequentially perform a data-out operation to output data of the lower pages of the memory cell group WLSC0 for four planes P, the memory controller 10 causes the memory chip CP0-1 to perform a sense operation to acquire data of the lower pages of the memory cell group WLSC0 for four planes P. Then, while the memory controller 10 is causing the memory chip CP0-1 to sequentially perform a data-out operation to output data of the lower pages of the memory cell group WLSC0 for four planes P, the memory controller 10 causes the memory chip CP0-0 to perform a sense operation to acquire data of the middle pages of the memory cell group WLSC0 for four planes P.

[0068] In this way, the sequential read method effectively utilizes the period during which the channel CH is occupied by the data-out operation, thereby reducing the total time required to read data from all blocks BLK included in a logical block. By using this method, the memory controller 10 can efficiently read data requested by the host 2 from the NAND memory 20.

[0069] The read level correction operation requires a read operation (more accurately, a shift read) for the NAND memory 20. Therefore, if the sequential read method can be used in the read level correction operation as well, the efficiency of the read level correction operation will be improved.

[0070] Two technologies to be compared with the embodiment will be described. These two technologies to be compared with the embodiment will be referred to as a first comparative example and a second comparative example. According to the first comparative example and the second comparative example, a read level correction operation different from the read level correction operation of the embodiment will be performed. The read level correction operation performed in the first comparative example and the second comparative example will be referred to as a read level correction operation according to the comparative example.

[0071] According to the read level correction operation of the comparative example, the memory controller reads data from all page types of pages (e.g., lower page, middle page, and upper page) of one memory cell group WLSC. Then, the memory controller compares the data before error correction with the data after error correction for the data read from each page type of page, thereby obtaining the number of bits in which data corresponding to the “Si” state was erroneously read as data corresponding to the “Si+1” state adjacent to the “Si” state, and the number of bits in which data corresponding to the “Si+1” state was erroneously read as data corresponding to the “Si” state. The “Si” state is the “Er” state, the “A” state, the “B” state, the “C” state, the “D” state, the “E” state, or the “F” state. The “Si+1” state is the state adjacent to the “Si” state on the high-voltage side among the “A” state, the “B” state, the “C” state, the “D” state, the “E” state, the “F” state, and the “G” state. The memory controller estimates an optimum read level corresponding to the boundary between the "Si" state and the "Si+1" state based on the ratio between the number of bits in which data corresponding to the "Si" state is erroneously read as data corresponding to the "Si+1" state adjacent to the "Si" state and the number of bits in which data corresponding to the "Si+1" state is erroneously read as data corresponding to the "Si" state. The memory controller acquires the number of bits in which data corresponding to the "Si" state is erroneously read as data corresponding to the "Si+1" state adjacent to the "Si" state and the number of bits in which data corresponding to the "Si+1" state is erroneously read as data corresponding to the "Si" state, and estimates the optimum read level based on the ratio between the acquired numbers for each read level.

[0072] In the first comparative example, the memory controller uses a sequential read method in the read level correction operation according to the comparative example. According to the example of the sequential read method shown in Figure 6, it is necessary to hold in a buffer (e.g., RAM) the data before and after error correction read from the pages of two page types (i.e., the lower page and the middle page) for each of the other seven memory cell groups WLSC that are different in plane P or memory chip CP until reading for all page types of pages in one memory cell group WLSC is completed. Therefore, in the first comparative example, a large-capacity buffer is required, which is disadvantageous in terms of cost.

[0073] In the second comparative example, the memory controller executes a read operation using a dedicated method different from the sequential read method. To acquire data from pages of all page types in one memory cell group WLSC, the memory controller executes sequential reads on the same memory cell group WLSC. For example, the memory controller executes reads on pages of all page types in the memory cell group WLSC0 of block BLKa belonging to plane P0 of memory chip CP0-0. Then, the memory controller executes reads on pages of all page types in the memory cell group WLSC0 of block BLKb belonging to plane P1 of memory chip CP0-0. In this way, the memory controller sequentially switches the read unit targeted for the read level correction operation, with the read of pages of all page types in one memory cell group WLSC of one block BLK belonging to one plane P of one memory chip CP being considered as one read unit.

[0074] However, in the second comparative example, the efficiency of retrieving data from the NAND memory is lower than when a read operation is performed using the sequential read method. Also, it becomes necessary to switch the read method between reading data requested by the host and the read level correction operation according to the comparative example, which complicates control in the memory controller.

[0075] In contrast, in the embodiment, the memory controller 10 can perform a read level correction operation that can be performed using a sequential read method without requiring a large-capacity buffer. Next, the read level correction operation according to the embodiment will be described.

[0076] In an embodiment, the memory controller 10 performs a read level correction operation using D-optimal design and response surface methodology, both of which are part of experimental design. According to these techniques, a model matrix corresponding to a model formula and a design matrix are prepared in advance. The design matrix is ​​a matrix obtained by vertically arranging multiple vectors, each of which is formed by arranging specific values ​​for linear terms of explanatory variables included in the model formula in the horizontal direction. The model matrix is ​​a matrix obtained by vertically arranging multiple vectors, each of which is formed by arranging specific values ​​for all explanatory variables included in the model formula in the horizontal direction. Therefore, the design matrix is ​​also a submatrix of the model matrix. A vector of specific values ​​of the objective variable can be expressed as the product of the model matrix and a coefficient vector that collects coefficients of the model formula. In an embodiment, a design matrix is ​​set in advance, in which specific values ​​for the read level value (or the amount of change in the read level value) are arranged, based on a model formula that uses at least the read level value (or the amount of change in the read level value) as an explanatory variable.

[0077] Specifically, in the read level correction operation, the memory controller 10 changes the value of the read level according to a preset design matrix (matrix D described below) and executes a shift read for pages of the same page type in a plurality of different memory cell groups WLSC. The memory controller 10 acquires an FBC for each of a plurality of data read from pages of the same page type in a plurality of different memory cell groups WLSC. Based on the acquired group of FBCs and a pseudo-inverse matrix of the model matrix, the memory controller 10 calculates a correction amount for bringing the read level closer to the optimal read level, in other words, a correction amount for reducing the number of error bits generated during reading.

[0078] The memory controller 10 executes a read level correction operation for each page type. That is, the read level correction operation includes an operation of correcting the read level required for a read operation of a lower page (i.e., read levels VA and VE), an operation of correcting the read level required for a read operation of a middle page (i.e., read levels VB, VD, and VF), and an operation of correcting the read level required for a read operation of an upper page (i.e., read levels VC and VG). The operation of correcting the read level required for a read operation of a lower page is referred to as a read level correction operation for a lower page. The operation of correcting the read level required for a read operation of a middle page is referred to as a read level correction operation for a middle page. The operation of correcting the read level required for a read operation of an upper page is referred to as a read level correction operation for an upper page.

[0079] First, the read level correction operation for the lower page will be described.

[0080] The model matrix is ​​generated based on a model formula that uses FBC as the response variable and lead level as the explanatory variable.

[0081] For example, as shown in Figure 7, in the vicinity of the optimal read level for a single read level, the FBC due to that single read level can be approximated by a polynomial of the value of that single read level, which is quadratic or higher. In Figure 7, x indicates the value of the read level, and the vertical axis indicates the FBC. x opt indicates the optimum read level. The optimum read level is considered to depend on the offset from the beginning of a word line group within a certain range in one block BLK. Therefore, the FBC caused by one read level can be expressed by the following equation (1), for example.

number

[0082] In equation (1), w is the offset from the beginning of a word line group within a certain range. Hereinafter, w will be referred to as the word line offset. A more detailed explanation of the word line offset will be given later. a and b are constants.

[0083] The FBC of data obtained by a read operation on one page is considered to be equal to the sum of the FBC determined by a read using one read level for the multiple read levels required for the read operation on that page.The FBC generated by a read operation is also considered to depend on the word line offset.

[0084] Therefore, it can be assumed that the FBC that occurs during a read operation on the lower page can be expressed by the model formula described below.

[0085] 8 is a diagram showing a model formula of the first embodiment that represents the FBC that occurs in a read operation for the lower page. In formula (2) shown in this figure, x1 represents the value of the read level VA, and x2 represents the value of the read level VE. w is the word line offset. β0 to β 12 is the coefficient. y is the FBC. e is the error.

[0086] According to the model equation shown in equation (2), the FBC, y, is expressed as the sum of a constant term, a read level dependent term, an interaction term between the read level and the word line offset, a word line offset dependent term, and an error. The read level dependent term includes a linear term of x1, a linear term of x2, a quadratic term of x1, and a quadratic term of x2. The word line offset dependent term includes a linear term, a quadratic term, a cubic term, and a quartic term of the word line offset. The interaction terms include a term obtained by multiplying x1 by w, a term obtained by multiplying x2 by w, a term obtained by multiplying x1 by the square of w, and a term obtained by multiplying x2 by the square of w.

[0087] The word line offset dependent term is a fourth-order polynomial, but the order of the word line offset dependent term is not limited to 4. Also, the order of w in the interaction term is 2, but the order of w in the interaction term is not limited to 2. A designer can observe an actual phenomenon and create a model formula of a polynomial that includes at least the read level and the word line offset.

[0088] The memory controller 10 changes one or both of the read level VA and the read level VE to perform a read operation on the lower page of each different memory cell group WLSC. Then, the memory controller 10 performs a regression analysis using the formula (2) as a model formula based on the results (FBC) of the read operation on the lower page of each different memory cell group WLSC, and thereby calculates the coefficients β0 to β 12 Estimate.

[0089] A set of memory areas (here, lower pages) to be acquired by FBC is selected from different memory cell groups WLSC. In this specification, this set of memory areas to be acquired by FBC is referred to as a correction unit.

[0090] FIG. 9 is a diagram illustrating an example of the configuration of a correction unit for the read level correction operation for the lower page according to the first embodiment.

[0091] For example, one correction unit Ul1 is configured by the lower page of the memory cell group WLSC0, the lower page of the memory cell group WLSC1, and the lower page of the memory cell group WLSC2 in the block BLKa included in the page P0 of the memory chip CP0-0.

[0092] Furthermore, of the block BLKb included in page P1 of the memory chip CP0-0, the lower page of the memory cell group WLSC0, the lower page of the memory cell group WLSC1, and the lower page of the memory cell group WLSC2 configure another correction unit Ul2.

[0093] Furthermore, of the block BLKc included in page P2 of the memory chip CP0-0, the lower page of the memory cell group WLSC0, the lower page of the memory cell group WLSC1, and the lower page of the memory cell group WLSC2 configure another correction unit Ul3.

[0094] In a similar manner, correction units Ul4 to Cl8 are formed.

[0095] In this way, the lower pages of a predetermined number (represented as N) of memory cell groups WLSC constitute a correction unit U. N is an integer equal to or greater than 2. However, N is a function of the coefficients β0 to β 12 9, the number of storage areas constituting each correction unit U is set to three in order to prevent the diagram from becoming too complicated.

[0096] The pattern of change of the read level (i.e., one or both of the read level VA and the read level VE) used in the read operation of the lower page is determined based on experimental design. A design matrix indicating the read level change pattern and a model matrix including the design matrix as a part thereof are set in advance based on experimental design. The memory controller 10 changes the read level for each storage area included in one correction unit U according to the design matrix, and performs a shift read for each storage area. The memory controller 10 calculates coefficients β0 to β 12 Calculate.

[0097] Hereinafter, the design matrix will be referred to as design matrix D. The model matrix will be referred to as model matrix X. Note that the design matrix D and model matrix X (and the pseudo-inverse matrix A described later) are defined for each type of page. Each matrix for a lower page is given the subscript l. Each matrix for a middle page is given the subscript m. Each matrix for an upper page is given the subscript u.

[0098] FIG. 10 shows the plan matrix D regarding the read level correction operation for the lower page of the first embodiment. l and the model matrix X l FIG.

[0099] Design matrix D l and the model matrix X l has N rows, which is the same as the number of storage areas that make up one correction unit U. Then, the design matrix D l and the model matrix X l The arrangement of N rows corresponds to the arrangement of N storage areas that make up the correction unit U.

[0100] 10, one block BLK has five string units SU. Then, a memory cell group WLSC is selected for each string unit SU from nine word lines with consecutive word line numbers, and one correction unit U is configured by the lower pages of the selected 45 memory cell groups WLSC (=9 word lines×5 string units). Therefore, the design matrix D l and the model matrix X l has 45 rows, which is the same number as the number of storage areas that make up one correction unit U.

[0101] As an example, the arrangement of the memory areas constituting the correction unit U is set to be the same as the execution order of the read operation by the sequential read method for the 45 memory areas constituting the correction unit U. Here, the lower pages of five memory cell groups WLSC included in the same word line and belonging to different string units SU are treated as one set, and the read operation is executed in the order of the word line numbers. Therefore, the design matrix D l and the model matrix X l This arrangement corresponds to the arrangement of storage areas arranged in the order of word line numbers in units of lower pages for five memory cell groups WLSC included in the same word line and belonging to different string units SU.

[0102] The word line offset of each word line included in a range of nine word lines with consecutive word line numbers is set as a relative value with the median of the word line numbers of the nine word lines as the reference (i.e., 0). For example, the word line offsets (i.e., the value of w) of nine word lines with word line numbers ranging from i to i+8 are set as follows: That is, the word line offset of the word line with word line number i is set to "-4", the word line offset of the word line with word line number i+1 is set to "-3", the word line offset of the word line with word line number i+2 is set to "-2", the word line offset of the word line with word line number i+3 is set to "-1", the word line offset of the word line with word line number i+4 is set to "0", the word line offset of the word line with word line number i+5 is set to "1", the word line offset of the word line with word line number i+6 is set to "2", the word line offset of the word line with word line number i+7 is set to "3", and the word line offset of the word line with word line number i+8 is set to "4".

[0103] The word line offset set in this manner is considered to indicate the position of each word line in the memory cell group WLSC. Note that the method for setting the word line offset is not limited to the above example, as long as it indicates the position of each word line in the memory cell group WLSC.

[0104] Design matrix D l Each row of the design matrix D is a vector having the amount of change in x1 (i.e., lead level VA) and the amount of change in x2 (i.e., lead level VE) as elements. l Each row specifies a read level change pattern. The unit of each change amount is the minimum read level change amount generated by the digital-to-analog converter included in the processing circuit 210. This minimum change amount may be referred to as DAC.

[0105] Each row of the model matrix X is a l The coefficients β0 to β when the change amount of x1 and the change amount of x2 defined by are substituted into x1 and x2 in equation (2) 12 It is a vector that lists the values ​​to be multiplied by each of the above.

[0106] For example, the design matrix D l The first line of the formula specifies a change pattern in which x1 is changed by "+1" and x2 is not changed. The corresponding model matrix X l In the first line, "1" is set in the position corresponding to the constant term, "1" (the same as the change amount of x1) and "0" (the same as the change amount of x2) are set in the position corresponding to the linear term of the read level dependent term, and "1" (the value obtained by squaring 1) and "0" (the value obtained by squaring 0) are set in the position corresponding to the quadratic term of the read level dependent term. For the word line offset dependent term, -4 is set as w, and "-4", "16" (the value obtained by squaring -4), "-64" (the value obtained by cubing -4), and "256" (the value obtained by quarticing -4) are set in the position corresponding to the word line offset dependent term. For the linear term of the interaction term, "-4" (the value obtained by multiplying w (i.e., -4) by the change amount of x1 (i.e., 1)) and "-0" (the value obtained by multiplying w (i.e., -4) by the change amount of x2 (i.e., 0)) are set in the position corresponding to the linear term of the interaction term. The position corresponding to the quadratic term of the interaction term is set to "16", which is obtained by multiplying the square of w (i.e., -4) by the change in x1 (i.e., 1), and "0", which is obtained by multiplying the square of w (i.e., -4) by the change in x2 (i.e., 0).

[0107] Thus, the model matrix X l is the design matrix D l and the model formula (2).

[0108] Note that the model matrix X l The two columns corresponding to the first-order terms of the lead-level dependent terms in l That is, the design matrix D l is the model matrix X l It is also part of.

[0109] Design matrix D l and the model matrix X l is determined by the designer. The design matrix D l Once this is determined, the design matrix D land the model matrix X based on the model formula (i.e., formula (2)). l is determined. The coefficients β0 to β 12 To be able to estimate the design matrix D, the designer must determine the optimality of the design matrix D based on the D-optimality criterion. l The design matrix D l The method for determining is not limited to the method based on the D-optimality criterion.

[0110] Coefficient β0~β 12 A vector having as its elements is denoted as a coefficient vector β. A vector having as its elements the FBC obtained by a read operation on each storage area constituting one correction unit U is denoted as an FBC vector Y. Note that the coefficient vector β and the FBC vector Y are also given a subscript l, a subscript m, or a subscript u depending on the page type of the page to be read.

[0111] Coefficient vector β l , FBC vector Y l , and the model matrix X l There is a relationship between them as shown in the following equation (3).

number

[0112] Therefore, the coefficient vector β l can be estimated by the following equation (4):

number

[0113] The memory controller 10 calculates the coefficient vector β l In order to estimate the matrix X l Pseudo inverse matrix A of l is given in advance by the designer.

number

[0114] The memory controller 10 calculates the FBC vector Y l , the FBC vector Y l and the pseudoinverse matrix A l By calculating the following equation (6) using l Get.

number

[0115] The memory controller 10 calculates the coefficient vector β l Once we obtain the coefficient vector β l Coefficients β0 to β 12 The coefficients β1 to β4 included in the read level dependent term are used to obtain the correction amount for bringing the read level value closer to the optimum value. Hereinafter, the correction amount for bringing the read level value closer to the optimum value will be simply referred to as the correction amount.

[0116] For example, FBC for lead level VA VA is expressed as the following equation (7) using the coefficients β1 and β3 included in the lead level dependent term. VA is a constant.

number

[0117] As explained using Figures 7 and 8, Equation (7) is expected to be a downward convex quadratic function. In other words, the sign of coefficient β3 should be positive. Therefore, y in Equation (7) VA The value of x1 at which x1 takes the minimum value (or the smallest value) is set as the correction amount ΔVA, which is the correction amount for the read level VA.

[0118] FBC for lead level VE VE is also expressed as the following equation (8) using the coefficients β2 and β4 included in the lead level dependent term. VE is a constant.

number

[0119] Equation (8) is also expected to be a downward convex quadratic function, just like equation (7). In other words, the sign of coefficient β4 should be positive. Therefore, y in equation (8) VE The value of x2 at which the value of x2 is the minimum value (or the smallest value) is set as the correction amount ΔVE, which is the correction amount for the read level VE.

[0120] As described above, the read level is changed in units of DAC. Therefore, the correction amounts ΔVA and ΔVE are integer values. That is, the memory controller 10 calculates y VA The memory controller 10 obtains the integer value closest to the value of x1 at which y in equation (8) is the minimum value. VE The integer value closest to the value of x2 at which the value of x2 is the minimum is obtained as the correction amount ΔVE.

[0121] The memory controller 10 obtains the correction amounts ΔVA and ΔVE based on equations (7) and (8), and corrects the read levels VA and VE using the obtained correction amounts ΔVA and ΔVE, thereby making it possible to bring the read levels VA and VE closer to the optimum read levels.

[0122] The read level correction operation for the middle page is performed in the same manner as the read level correction operation for the lower page.

[0123] A correction unit U is also formed in the read level correction operation for the middle page.

[0124] 11 is a diagram showing an example of the configuration of correction units for the read level correction operation for the middle page of Embodiment 1. A plurality of correction units U are set, such as correction units Um1 to Um8 shown in this diagram.

[0125] 12 is a diagram showing a model formula of the first embodiment that represents the FBC that occurs in a read operation on the middle page. In formula (9), which is a model formula that represents the FBC that occurs in a read operation on the middle page, x1 represents the value of the read level VB, x2 represents the value of the read level VD, and x3 represents the value of the read level VF. w is the word line offset. β0 to β 16 is the coefficient. y is the FBC. e is the error.

[0126] The number of read levels required for a read operation on the lower page is one more than the number of read levels required for a read operation on the lower page. Therefore, according to equation (9), the read level dependency term and the interaction term each have two more terms than equation (2). Therefore, the number of coefficients β included in equation (9) is four more than the number of coefficients β included in equation (2).

[0127] FIG. 13 shows the plan matrix D regarding the read level correction operation for the middle page of the second embodiment. m and the model matrix X m FIG.

[0128] Design matrix D l and the model matrix X l Similarly, the design matrix D m and the model matrix X m The row arrangement corresponds to the arrangement of 45 storage areas that make up one correction unit U.

[0129] Design matrix D m Each row of is a vector whose elements are the amount of change in x1 (i.e., read level VB), the amount of change in x2 (i.e., read level VD), and the amount of change in x3 (i.e., read level VF).

[0130] Model matrix X m Each row of the design matrix D m The coefficients β0 to β 16It is a vector that lists the values ​​to be multiplied by each of the above.

[0131] Regarding the lead level correction operation for the middle page, the model matrix X m is the design matrix D m and the model equation (9). m The three columns corresponding to the first-order terms of the lead-level dependent terms of m matches.

[0132] Design matrix D m and the model matrix X m is determined by the designer. The design matrix D m Once this is determined, the design matrix D m and the model matrix X m The designer determines the design matrix D based on the D-optimality criterion. m The design matrix D m The method for determining is not limited to the method based on the D-optimality criterion.

[0133] The memory controller 10 also has a model matrix X m Pseudo inverse matrix A of m is given in advance by the designer. The memory controller 10 then calculates the FBC vector Y m and the pseudoinverse matrix A m The coefficient vector β calculated using m and the obtained coefficient vector β m and obtaining correction amounts for each of the read levels VB, VD, and VF using the coefficients β1 to β6, which are coefficients included in the read level dependent terms.

[0134] A correction unit U is also formed in the read level correction operation for the upper page.

[0135] 14 is a diagram showing an example of the configuration of correction units for the read level correction operation for the upper page of the first embodiment. As shown in this diagram, multiple correction units U are set so that the upper page of each memory cell group WLSC is included in one of the correction units, as in the correction units Uu1 to Uu8.

[0136] The read operation for the upper page uses two read levels (i.e., read levels VC and VG), which is the same as the number of read levels required for the read operation for the lower page. Therefore, the design matrix D l The design matrix D has the same structure as u and the model matrix X l The model matrix X with the same structure as u Pseudo inverse matrix A of u and are used. Note that the design matrix D u The value of each element of the design matrix D l It may be the same as or different from the pseudo-inverse matrix A. u The value of each element of the pseudo-inverse matrix A l The read level correction operation for the upper page is performed in a similar manner to the read level correction operation for the lower page, and therefore further detailed description will be omitted.

[0137] FIG. 15 is a diagram showing an example of data stored in the RAM 30 of the memory system 1 of the first embodiment.

[0138] The RAM 30 stores read level information 301, design matrix information 302, pseudo matrix information 303, and FBC information 304.

[0139] The design matrix information 302 is the design matrix D l , design matrix D m , and the design matrix D u is the recorded information.

[0140] The pseudo-matrix information 303 is the pseudo-inverse matrix A l , pseudo-inverse matrix A m , and the pseudoinverse matrix Au is the recorded information.

[0141] The design matrix information 302 and the pseudo matrix information 303 are provided as setting information. For example, a designer generates the design matrix information 302 and the pseudo matrix information 303 by calculation. The generated design matrix information 302 and the pseudo matrix information 303 are stored in a nonvolatile memory (e.g., the NAND memory 20) in the memory system 1 during manufacturing of the memory system 1. When the memory system 1 is in operation, the design matrix information 302 and the pseudo matrix information 303 are loaded from the nonvolatile memory to the RAM 30, and the memory controller 10 performs a read level correction operation using the design matrix information 302 and the pseudo matrix information 303 loaded to the RAM 30.

[0142] The read level information 301 is information in which the current setting values ​​of the read levels VA to VG of each memory cell group WLSC are recorded. In a read operation to read data requested by the host 2, the memory controller 10 performs a shift read using the setting values ​​recorded in the read level information 301.

[0143] In the first embodiment, the set value of the read level is corrected for each correction unit U. Therefore, the set value of the read level is recorded for each correction unit U in the read level information 301.

[0144] The FBC information 304 is information in which a group of FBCs obtained in the read level correction operation is recorded. The memory controller 10 records the FBCs obtained by shift reading for each storage area in the read level correction operation in the FBC information 304.

[0145] 16 is a schematic diagram for explaining the flow of data in the read level correction operation according to the first embodiment. For ease of understanding, the read level correction operation for the lower page of a certain correction unit U (referred to as the target correction unit U in the explanation of FIG. 16) will be explained here.

[0146] The CPU 11 acquires the set values ​​of the read levels AR and ER used in the read operation for the storage area that constitutes the target correction unit U from the read level information 301. The CPU 11 also acquires the set values ​​of the read levels AR and ER used in the read operation for the storage area that constitutes the target correction unit U from the plan matrix information 302. l The CPU 11 obtains the design matrix D l The values ​​of the read levels AR and ER used in the shift read are generated by adding the amounts of change in the read levels AR and ER defined by (S101). The value of the read level AR used in the shift read is denoted as read level AR', and the value of the read level ER used in the shift read is denoted as read level ER'.

[0147] In addition, the design matrix D l According to the above, the change amounts of the read levels AR and ER are individually defined for each storage area constituting one correction unit U. In S101, the CPU 11 generates the read levels AR' and ER' for each storage area. That is, the values ​​of the read levels AR and ER are calculated by the planning matrix D l The data is modified for each storage area in a modification pattern defined by different rows of the table.

[0148] The CPU 11 controls the memory controller 10 to perform a shift read using the read levels AR' and ER' and error correction on the data obtained by the shift read for each memory area (here, the lower page of each memory cell group WLSC) that constitutes the target correction unit U (S102).

[0149] The CPU 11 acquires the FBC for each storage area that constitutes the target correction unit U in S102, and records the acquired FBC in the FBC information 304.

[0150] After FBCs are acquired for all storage areas that make up the target correction unit U, the CPU 11 calculates the correction amounts ΔAR and ΔER (S103).The CPU 11 then corrects the set values ​​of the read levels AR and ER by adding the correction amounts ΔAR and ΔER to the set values ​​of the read levels AR and ER.The CPU 11 then updates the set values ​​of the read levels AR and ER recorded in the read level information 301 with the corrected set values.

[0151] 16, according to the first embodiment, information indicating the FBC for all storage areas constituting each correction unit U is temporarily stored in a buffer (here, RAM 30). Therefore, compared to Comparative Example 1 and Comparative Example 2 in which the read level correction operation according to the comparative example requiring a pair of data before error correction and data after error correction is executed, the capacity required for the buffer can be significantly reduced. In other words, according to the first embodiment, it is possible to preferably correct the read level value.

[0152] Furthermore, since the buffer capacity required per correction unit U is significantly smaller than that of the read level correction operation according to the comparative example, it is possible to execute the shift read included in the read level correction operation in the order of the sequential read method while suppressing the required buffer capacity compared to comparative example 1. The read level correction operation can be executed in a short time, so the read level value can be suitably corrected.

[0153] 17 is a flowchart showing an example of the operation of the memory system 1 of the first embodiment. Here, a read level correction operation for one correction unit U (referred to as a target correction unit U in the explanation of FIG. 17) will be described.

[0154] First, the CPU 11 acquires the set value of the read level for the target correction unit U from the read level information 301 (S201).

[0155] Next, CPU 11 initializes i, which is an index for the loop processing of S203 to S210, to 1 (S202). Note that the loop processing of S203 to S210 is executed for each storage area included in the target correction unit U. In other words, if the number of storage areas included in the target correction unit U is N, the loop processing of S203 to S210 is executed N times.

[0156] The CPU 11 acquires the amount of change in the read level from the i-th row of the plan matrix D corresponding to the page type of the target correction unit (S203), and then adds the amount of change to the set value of the read level (S204).

[0157] The CPU 11 controls the memory controller 10 to execute a shift read for the i-th storage area of ​​the target correction unit U using a read level whose value is obtained by adding the change amount to the set value (S205).

[0158] The ECC circuit 15 performs error correction on the data read from the i-th storage area of ​​the correction unit U by the shift read in S205 (S206).

[0159] If the error correction has failed (S207: No), the read level correction operation ends for the target correction unit U. Note that the process when the error correction has failed is not limited to this.

[0160] If the error correction is successful (S207: Yes), the CPU 11 acquires the FBC from the ECC circuit 15 and records the acquired FBC in the FBC information 304 (S208).

[0161] Next, the CPU 11 determines whether the value of the loop index i is equal to N (S209). If the value of the loop index i is not equal to N (S209: No), the CPU 11 increments the value of the loop index i by 1 (S210), and the control transitions to S203.

[0162] If the value of the loop index i is equal to N (S209: Yes), that is, if the processes of S203 to S208 have been executed for all storage areas included in the target correction unit U, an FBC vector Y for the target correction unit U is completed in the FBC information 304. The CPU 11 multiplies the FBC vector Y by a pseudo inverse matrix A corresponding to the page type of the target correction unit (S211). In S211, the CPU 11 acquires a coefficient vector β.

[0163] The CPU 11 calculates the correction amount Δ of the read level using the coefficients included in the read level dependent term of the coefficient vector β (S212). Note that the minimum unit of change in the read level is DAC. Therefore, in S212, the CPU 11 calculates the correction amount Δ discretized in DAC units.

[0164] Using the correction amount Δ obtained by calculation, the CPU 11 updates the read level setting value for the target correction unit U recorded in the read level information 301 (S213). That is, the CPU 11 calculates a new read level setting value by adding the correction amount Δ to the read level setting value, and records the new read level setting value obtained by the addition in an overwrite format in the read level information 301. This completes the read level correction operation for the target correction unit U.

[0165] It should be noted that the shift read in S206 of the series of operations shown in Fig. 17 can be executed by the sequential read method. For example, when correction units Ul1 to Ul8 (see Fig. 9), correction units Um1 to Um8 (see Fig. 11), and correction units Uu1 to Uu8 (see Fig. 14) are configured and the series of operations shown in Fig. 17 are executed for each of the correction units Ul1 to Ul8, Um1 to Um8, and Uu1 to Uu8, the memory controller 10 can execute the shift read in S206 for each storage area in the order shown in Fig. 6. This makes it possible to read data from all correction units U in a short time, and to complete the read level correction operations for all of the correction units Ul1 to Ul8, Um1 to Um8, and Uu1 to Uu8 in a short time.

[0166] The trigger for the series of operations shown in FIG. 17 is not limited to a specific trigger. In one example, when the address range requested to be read by a read command received from the host 2 includes the target correction unit, the memory controller 10 can execute a read level correction operation using the sequential read method in parallel with the execution of the read requested by the host 2. The read command includes a logical address range indicating the location of the data to be read. The memory controller 10, for example, in the CPU 11 (or hardware supporting the processing), converts each location within the logical address range into a physical address including the chip number of the memory chip CP, block number, WL number, SU number, and page type, thereby identifying the physical address range to be read. The determination of whether the target correction unit is included in the physical address range to be read can be executed, for example, by the CPU 11 (or hardware supporting the processing).

[0167] In another example, the memory controller 10 may execute the series of operations shown in Fig. 17 during a period when the memory controller 10 is not executing a process in response to a command from the host 2, as background processing independent of the process in response to a command from the host 2. In addition, in the background processing, the memory controller 10 may execute the series of operations shown in Fig. 17 using a sequential read method.

[0168] In yet another example, when performing a sequential read in response to a read command received from the host 2, the memory controller 10 may execute the series of operations shown in FIG. 17 when performing a sequential read in response to the read command. Specifically, the memory controller 10 determines whether or not a sequential read is possible based on the physical address range of the read target identified in response to the read command. If it is determined that a sequential read is possible, the memory controller 10 executes the series of operations shown in FIG. 17 when reading data requested to be read by the host 2 in the sequential read mode.

[0169] In the above description, the NAND memory 20 is an example of a non-volatile first memory. One of the lower page, middle page, and upper page is an example of a first page. One of the lower page, middle page, and upper page that is different from the first page is an example of a second page. The read level used to determine the data of the first page is an example of a first read level. The read level used to determine the data of the second page is an example of a second read level.

[0170] For example, if the first page is the lower page, the read level VA and the read level VE correspond to the first read level, and if the second page is the middle page, the read level VB, the read level VD, and the read level VF correspond to the second read level.

[0171] The read level information 301 is an example of first information. The design matrix information 302 is an example of second information. The pseudo-inverse matrix information 303 is an example of third information. The RAM 30 is an example of a second memory configured to store the first information, the second information, and the third information. The second memory may be configured by a plurality of memory devices, and the first information, the second information, and the third information may be stored in a distributed manner across the plurality of memory devices.

[0172] In equation (2) or equation (9), the interaction term and the word line offset dependent term are examples of position dependent terms.

[0173] According to the first embodiment, the memory controller 10 reads data from each storage area constituting the target correction unit U by using first read level values ​​obtained by changing a setting value of a first read level corresponding to a first page, which is a certain page type of the target correction unit U, in accordance with change patterns defined by different rows of a design matrix D (an example of a first design matrix) corresponding to the first page (see, for example, S203 to S205 in the loop processing of S203 to S210 in FIG. 17 ). The memory controller 10 calculates a coefficient vector β based on the FBC of the data read from each storage area constituting the target correction unit U and a pseudo inverse matrix A (an example of a first pseudo inverse matrix) corresponding to the first page (see, for example, S211 in FIG. 17 ). The memory controller 10 calculates a correction amount of the first read level to reduce the number of error bits generated during a read operation for the target correction unit U based on the calculated value of the coefficient vector β and the model formula (see, for example, S212 in FIG. 17 ). The memory controller 10 updates the setting value of the first read level based on the correction amount (see, for example, S213 in FIG. 17).

[0174] Therefore, the required capacity of the buffer for the read level correction operation can be significantly reduced compared to Comparative Example 1 and Comparative Example 2. In other words, it is possible to preferably correct the read level value.

[0175] Furthermore, since the buffer capacity required per correction unit U is significantly smaller than that of the read level correction operation according to the comparative example, it is possible to use the sequential read method while suppressing the required buffer capacity compared to comparative example 1. When the sequential read method is used, it is possible to complete the read level correction operation for a large number of correction units U in a short time. In other words, the read level value can be suitably corrected because the read level correction operation can be completed in a short time.

[0176] According to the first embodiment, the read level correction operation is performed for each page type. The memory controller 10 reads data from each storage area constituting the target correction unit U using the second read level values ​​obtained by changing the setting value of the second read level corresponding to the second page, which is a page type different from the first page of the target correction unit U, using change patterns defined by different rows of the design matrix D (an example of a second design matrix) corresponding to the second page (see, for example, S203 to S205 in the loop processing of S203 to S210 in FIG. 17). The memory controller 10 calculates a coefficient vector β based on the FBC of the data read from each storage area constituting the target correction unit U and the pseudo inverse matrix A (an example of a second pseudo inverse matrix) corresponding to the second page (see, for example, S211 in FIG. 17). The memory controller 10 calculates a correction amount of the second read level to reduce the number of error bits generated during a read operation for the target correction unit U based on the calculated value of the coefficient vector β and the model formula (see, for example, S212 in FIG. 17). The memory controller 10 updates the setting value of the second read level based on the correction amount (see, for example, S213 in FIG. 17).

[0177] Furthermore, according to the first embodiment, the memory controller 10 calculates the correction amount using a coefficient included in the read level dependent term of the coefficient vector β obtained by calculation. This calculation method is equivalent to calculating the correction amount by substituting 0 as the word line offset into the model formula. That is, in the first embodiment, the memory controller 10 uses the correction amount obtained by substituting the value of one word line offset of the storage areas constituting the correction unit U into the model formula to correct the read level for the correction unit U.

[0178] In this way, if the read levels for the correction unit U are corrected collectively using the correction amount obtained by substituting the value of the word line offset of one of the storage areas that make up the correction unit U into the model formula, it is only necessary to manage the read level setting value for each correction unit U, and the size of the read level information 301 can be reduced.

[0179] (Second embodiment) 17, an upper limit may be set on the positive side of the correction amount and a lower limit may be set on the negative side of the correction amount. Specifically, for example, the CPU 11 may limit the correction amount to a range from -1DAC to +1DAC. By limiting the correction amount to a predetermined range in this way, it is possible to prevent the read level from being changed significantly by a single operation.

[0180] Furthermore, there may be cases where the sign of the coefficient β applied to the quadratic term of the lead level dependent term becomes negative for some reason. If the sign of the coefficient β applied to the quadratic term of the lead level dependent term becomes negative, the lead level dependent term does not have a minimum point, and the lead level value at which the lead level dependent term takes its minimum value cannot be determined. By setting upper and lower limits on the correction amount, it is possible to conveniently determine the lead level value at which the lead level dependent term takes its minimum value, even if the sign of the coefficient β applied to the quadratic term of the lead level dependent term is negative.

[0181] Note that correction is performed in DAC units. When the correction amount is limited to the range from -1DAC to +1DAC, the correction amount candidates are limited to three: -1DAC, 0, and +1DAC. Therefore, the CPU 11 may simply substitute -1, 0, and +1 into x in equations (7), (8), etc., in order, and determine the value of x that minimizes the value of y as the correction amount.

[0182] (Third embodiment) According to the first embodiment, one pair of a design matrix D and a pseudo inverse matrix A is prepared for one page type. A plurality of pairs of a design matrix D and a pseudo inverse matrix A may be prepared for one page type.

[0183] For example, for a certain page type, multiple pairs of a planning matrix D and a pseudo inverse matrix A are prepared. More specifically, the planning matrix information 302 records a first planning matrix D and a third planning matrix D for the same page type. Like the first planning matrix D, the third planning matrix D is a matrix that defines a change pattern of the first read level, and has the same number of rows as the number of storage areas that make up the correction unit U. The pseudo inverse matrix information 303 records a first pseudo inverse matrix A and a third pseudo inverse matrix A. The third pseudo inverse matrix A is a pseudo inverse matrix of a third model matrix X. The third model matrix X is a matrix that has the same number of rows as the number of storage areas that make up the correction unit U, and is a model matrix that corresponds to the third planning matrix D and the same model formula as the first planning matrix D. After performing a read level correction operation using a first planning matrix D and a first pseudo inverse matrix A on a certain correction unit U, the memory controller 10 uses a third planning matrix D and a third pseudo inverse matrix A when performing a read level correction operation on the correction unit U again.

[0184] In this way, when performing multiple read level correction operations on one correction unit U, the memory controller 10 switches between the pair of design matrix D and pseudo inverse matrix A to use them.

[0185] For example, during operation of the memory system 1, the memory system 1 may encounter a situation in which the design matrix D and the pseudo inverse matrix A are not suitable for correction to bring the set value of the read level closer to the optimal read level. In such a case, the memory controller 10 can enable correction to bring the set value of the read level closer to the optimal read level by switching the design matrix D and the pseudo inverse matrix A used in the read level correction operation.

[0186] In addition, when multiple pairs of a design matrix D and a pseudo-inverse matrix A are prepared for the same page type, one of the two design matrices D for the same page type may be equivalent to a matrix obtained by changing the row order of the other of the two design matrices.

[0187] (Fourth embodiment) In the first embodiment, the memory controller 10 calculates the read level correction amount using the coefficients included in the read level dependent term of the estimated coefficient vector β. The method for calculating the read level correction amount is not limited to this. The memory controller 10 may also perform read level correction on a storage area basis.

[0188] For example, the memory controller 10 calculates the correction amount for each storage area constituting the correction unit U based on a model formula in which the position-dependent term is substituted with the value of the word line offset of each storage area constituting the correction unit U. Then, the memory controller 10 corrects the setting value of the read level for each storage area constituting the correction unit U based on the correction amount calculated for each storage area constituting the correction unit U.

[0189] Therefore, it is possible to bring the read level of each storage area constituting the correction unit U close to the optimum read level with high accuracy.

[0190] In addition, the memory controller 10 may calculate the correction amount for each memory area that constitutes the correction unit U based on a model formula in which the value of the word line offset of each memory area that constitutes the correction unit U is substituted into the position-dependent term, and then calculate the average value of the correction amounts calculated for all memory areas that constitute the correction unit U, and use this average value to correct the setting value of the read level for the correction unit U.

[0191] Therefore, similarly to the first embodiment, it is sufficient to manage the set value of the read level for each correction unit U, and the size of the read level information 301 can be reduced.

[0192] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0193] 1 Memory system, 2 Host, 10 Memory controller, 20 NAND flash memory (NAND memory), 11 CPU, 12 Host interface, 13 RAMC, 14 NANDC, 15 ECC circuit, 20 NAND memory, 210 Processing circuit, 211 Memory cell array, 214 NAND string, 301 Read level information, 302 Design matrix information, 303 Pseudo matrix information, 304 FBC information.

Claims

1. a non-volatile first memory including a plurality of word lines and a plurality of memory cell groups each connected to one of the plurality of word lines, each of the plurality of memory cell groups constituting a first page which is a storage area from which data is read using a first read level and a second page which is a storage area from which data is read using a second read level; a second memory configured to store first information in which a setting value of the first read level is recorded, second information in which a first design matrix having N (where N is an integer of 2 or more) rows defining a change pattern of the first read level is recorded, and third information in which a first pseudo-inverse matrix that is a pseudo-inverse matrix of a first model matrix is ​​recorded; the first model matrix has N rows and is a model matrix corresponding to the first design matrix and a first model formula, and the first model formula is a formula having the first read level as an explanatory variable, having the number of error bits as a response variable, having a position-dependent term that is a term that depends on positions in N memory cell groups out of the plurality of memory cell groups, and having a plurality of first coefficients; reading data from the first page of each of the N memory cell groups using the first read level value obtained by changing the setting value of the first read level in a change pattern defined by each different row of the first design matrix; calculating the plurality of first coefficients based on the number of error bits included in the data read from the first page of each of the N memory cell groups and the first pseudo inverse matrix; calculating a correction amount for the setting value of the first read level for reducing the number of error bits generated during a read operation for the first page of the N memory cell group based on the calculated values ​​of the plurality of first coefficients and the first model equation; updating the set value of the first read level recorded in the first information based on the correction amount; a memory controller configured to: A memory system comprising:

2. The first information records a set value of the second read level, The second information records a second design matrix having N rows that defines a change pattern of the second read level, The third information records a second pseudo-inverse matrix that is a pseudo-inverse matrix of the second model matrix, the second model matrix has N rows and corresponds to the second design matrix and a second model equation; the second model formula is an equation having the second read level as an explanatory variable, the number of error bits as a response variable, the position-dependent term, and a plurality of second coefficients; The memory controller reading data from the second page of each of the N memory cell groups using the second read level values ​​obtained by changing the setting values ​​of the second read level in a change pattern defined by different rows of the second design matrix; calculating the plurality of second coefficients based on the number of error bits included in the data read from the second page of each of the N memory cell groups and the second pseudo inverse matrix; calculating a correction amount for the setting value of the second read level for reducing the number of error bits generated when reading the second page of the N memory cell group based on the calculated values ​​of the plurality of second coefficients and the second model formula; updating the set value of the second read level recorded in the first information based on the correction amount of the set value of the second read level; Further configured as follows:

10. The memory system of claim 1.

3. The second information records a third design matrix different from the first design matrix having N rows that defines a change pattern of the first read level, The third information records a third pseudo-inverse matrix that is a pseudo-inverse matrix of the third model matrix, the third model matrix has N rows and corresponds to the third design matrix and the first model equation; The memory controller updating the set value of the first read level using the first design matrix and the first pseudo inverse matrix, and then updating the set value of the first read level using the third design matrix and the third pseudo inverse matrix; Further configured as follows:

10. The memory system of claim 1.

4. The third design matrix is ​​equivalent to a matrix obtained by changing the row order of the first design matrix.

4. The memory system of claim 3.

5. The memory controller is further configured to calculate a correction amount for the setting value of the first read level based on the first model formula in which a value representing a position of one of the N memory cell groups is substituted into the position-dependent term.

5. The memory system according to claim 1.

6. The memory controller is further configured to calculate a correction amount of the setting value of the first read level for each of the N memory cell groups based on the first model formula in which a value representing each position of the N memory cell groups is substituted for the position-dependent term.

5. The memory system according to claim 1.

7. The memory controller calculating an average value of the correction amounts of the set values ​​of the first read levels calculated for each of the N memory cell groups; updating the set value of the first read level using the average value; Further configured as follows:

7. The memory system of claim 6.

8. A method for controlling a nonvolatile memory comprising a plurality of word lines and a plurality of memory cell groups each connected to one of the plurality of word lines, each of the plurality of memory cell groups constituting a first page which is a storage area from which data is read using a first read level and a second page which is a storage area from which data is read using a second read level, reading data from the first page of each of N memory cell groups among the plurality of memory cell groups using values ​​of the first read level obtained by changing the set value of the first read level in a change pattern defined by different rows of a first design matrix having N rows (N is an integer of 2 or more) defining a change pattern of the first read level; calculating a plurality of first coefficients based on the number of error bits included in the data read from the first page of each of the N memory cell groups and a first pseudo-inverse matrix that is a pseudo-inverse matrix of a first model matrix, the first model matrix having N rows and corresponding to the first design matrix and a first model formula, the first model formula having the first read level as an explanatory variable, the number of error bits as a response variable, a position-dependent term that is a term that depends on a position in the N memory cell groups among the plurality of memory cell groups, and the plurality of first coefficients; calculating a correction amount for a setting value of the first read level based on the calculated values ​​of the plurality of first coefficients and the first model equation, to reduce the number of error bits generated during a read operation for the first page of the N memory cell group; updating a set value of the first read level based on the correction amount; A method comprising:

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