Method of manufacturing semiconductor device and semiconductor device

Abstract

To efficiently manufacture a semiconductor device of high breakdown voltage.SOLUTION: A method for manufacturing a semiconductor device according to one aspect includes a step of preparing a semiconductor substrate of a first conductivity type, a step of doping the semiconductor substrate with impurities of a second conductivity type to form a plurality of impurity regions that are two-dimensionally distributed in a plane perpendicular to a thickness direction of the semiconductor substrate in the semiconductor substrate, and a step of thermally diffusing impurities in the plurality of impurity regions to form a buried layer of the second conductivity type in the semiconductor substrate.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Patent Document 1 describes a semiconductor device including a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, and a buried layer formed between the semiconductor substrate and the epitaxial layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-43285

[0004] [overview] An object of the present disclosure is to efficiently manufacture a high-voltage semiconductor device.

[0005] The present disclosure provides a method for manufacturing a semiconductor device, including the steps of preparing a semiconductor substrate of a first conductivity type, doping the semiconductor substrate with impurities of a second conductivity type to form a plurality of impurity regions in the semiconductor substrate that are distributed two-dimensionally in a plane perpendicular to the thickness direction of the semiconductor substrate, and thermally diffusing the impurities in the plurality of impurity regions to form a buried layer of the second conductivity type in the semiconductor substrate. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of an exemplary device. [Figure 3] FIG. 3 is a diagram showing the distribution of impurity concentration in the buried layer. [Figure 4] FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5]FIG. 5 is a cross-sectional view showing one step of the method for manufacturing a semiconductor device. [Figure 6] 6(a) to 6(c) are plan views showing exemplary mask layers. [Figure 7] FIG. 7 is a plan view illustrating an exemplary mask layer opening. [Figure 8] FIG. 8 is a cross-sectional view showing a step subsequent to FIG. [Figure 9] FIG. 9 is a plan view schematically showing a semiconductor substrate in which a plurality of impurity regions are formed. [Figure 10] FIG. 10 is a cross-sectional view showing a step subsequent to FIG. [Figure 11] FIG. 11 is a diagram schematically illustrating the process of thermal diffusion of impurities. [Figure 12] FIG. 12 is a cross-sectional view showing a step subsequent to FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a step subsequent to FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a step subsequent to FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a step subsequent to FIG. [Figure 16] FIG. 16 is a cross-sectional view showing a step subsequent to FIG. [Figure 17] FIG. 17 is a perspective view of an exemplary mask layer.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicate explanations will be omitted. The drawings may be partially simplified or exaggerated to facilitate understanding, and the dimensional ratios and the like are not limited to those shown in the drawings.

[0008] FIG. 1 is a plan view of a semiconductor device 100. As shown in FIG.

[0009] The semiconductor device 100 has a rectangular parallelepiped shape. The semiconductor device 100 has a first side 103. A back surface is located on the opposite side of the first main surface 103. The semiconductor device 100 has a first side 5A, a second side 5B, a third side 5C, and a fourth side 5D that connect the first main surface 103 and the back surface. In FIG. 1, the thickness direction of the semiconductor device 100 is the Z-axis direction, the direction perpendicular to the Z-axis is the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is the Y-axis direction.

[0010] The first main surface 103 and the back surface are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 103 when viewed from the normal direction (Z axis direction) of the first main surface 103 is rectangular (quadrilateral). The back surface of the semiconductor substrate has a rectangular (quadrilateral) shape in plan view. The first side surface 5A and the second side surface 5B, which constitute two opposing sides of the rectangle in plan view, each extend along the X axis direction. The third side surface 5C and the fourth side surface 5D, which constitute the other two opposing sides of the rectangle in plan view, each extend along the Y axis direction. These adjacent side surfaces are orthogonal in plan view, but may also intersect at an angle other than orthogonal.

[0011] The semiconductor device 100 includes a plurality of device regions 10 provided on a first main surface 103. There is a gap between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the semiconductor device 100. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0012] Various devices are formed in each device region 10. At least one device region 10 includes a device 50.

[0013] The devices 50 formed in each device region 10 are field-effect transistors. Field-effect transistors include MISFETs (Metal Insulator Semiconductor Field Effect Transistors: insulated gate field-effect transistors). MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) can be used as MISFETs. Power MOSFETs can include DMOSs (Double-diffused MOSFETs), and lateral LDMOSs can also be used. Known drain-source voltages for MISFETs include high voltage (HV: e.g., 100 V to 1000 V), medium voltage (MV: e.g., 30 V to 100 V), and low voltage (LV: e.g., 1 V to 30 V).

[0014] The semiconductor material constituting the semiconductor device 100 in this example is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor device 100. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Si-containing semiconductors such as SiC and SiGe can be used as IV-IV compound semiconductors.

[0015] In this example, each semiconductor region constituting the device region 10 of the semiconductor device has a first conductivity type of N-type and a second conductivity type of P-type, but these conductivity types are interchangeable. An exemplary P-type impurity (trivalent element) is boron (B). An exemplary N-type impurity (pentavalent element) is phosphorus (P) or arsenic (As).

[0016] FIG. 2 is a schematic cross-sectional view of an exemplary device 50. The device 50 shown in FIG. 2 is a DMOS-FET. As shown in FIG. 2, the device 50 includes a semiconductor substrate 1, an epitaxial layer 2, and a buried layer 3. The semiconductor substrate 1 is made of silicon (Si) and has a P-type conductivity. As mentioned above, the semiconductor substrate 1 may be made of a material other than silicon.

[0017] The epitaxial layer 2 has a P-type conductivity and is formed on the semiconductor substrate 1. The epitaxial layer 2 is a semiconductor layer made of, for example, silicon (Si). The epitaxial layer 2 may be made of a material other than silicon, such as silicon carbide (SiC). A well region 11 is formed in the epitaxial layer 2. The well region 11 is a semiconductor layer having an N-type conductivity. The well region 11 is formed on the buried layer 3 and is in contact with the upper surface of the buried layer 3.

[0018] The buried layer 3 is disposed between the semiconductor substrate 1 and the well region 11, and its lower and upper surfaces are in contact with the semiconductor substrate 1 and the well region 11, respectively. The buried layer 3 has an N-type conductivity. The buried layer 3 has an impurity concentration higher than the impurity concentration of the well region 11.

[0019] The buried layer 3 has an impurity concentration that changes periodically in an in-plane direction perpendicular to the stacking direction of the semiconductor substrate 1, the buried layer 3, and the well region 11 (thickness direction of the semiconductor substrate 1). FIG. 3 shows the distribution of the impurity concentration in the buried layer. Darker shaded areas in FIG. 3 indicate higher impurity concentrations. As shown in FIG. 3, the buried layer 3 is formed with a plurality of high-concentration regions R1 arranged two-dimensionally in the in-plane direction and a plurality of low-concentration regions R2 arranged between the plurality of high-concentration regions R1. The high-concentration regions R1 have a relatively high impurity concentration. The low-concentration regions R2 have an impurity concentration lower than the impurity concentration of the high-concentration regions R1. Therefore, the average impurity concentration of the buried layer 3 is lower than the impurity concentration of the high-concentration regions R1.

[0020] In one embodiment, the center-to-center spacing d of the multiple high concentration regions R1 in the in-plane direction of the buried layer 3 may be 10 μm or less, 5 μm or less, or 3 μm or less. The center-to-center spacing d indicates the distance between the centers of adjacent high concentration regions R1 among the multiple high concentration regions R1.

[0021] 2 and 3, the film thickness of the buried layer 3 varies periodically in the in-plane direction of the buried layer 3. In one embodiment, the boundary surface between the semiconductor substrate 1 and the buried layer 3 and the boundary surface between the buried layer 3 and the well region 11 are formed in a wavy shape. Specifically, the film thickness of the buried layer 3 is large at positions where multiple high-concentration regions R1 are formed in the in-plane direction of the buried layer 3, and the film thickness of the buried layer 3 is small at positions where multiple low-concentration regions R2 are formed.

[0022] As shown in FIG. 2, a drift region 12 is formed on the surface of the well region 11. The drift region 12 is a semiconductor layer having P-type conductivity. A drain region 13 having P-type conductivity is formed within the drift region 12. The impurity concentration of the drain region 13 is higher than the impurity concentration of the drift region 12. The drain region 13 has a substantially rectangular planar shape, and a portion of its surface is exposed from the drift region 12.

[0023] Furthermore, a body region 15 having N-type conductivity is formed on the surface of the well region 11. The impurity concentration of the body region 15 is higher than the impurity concentration of the well region 11. In the embodiment shown in FIG. 2, the device 50 includes two body regions 15 arranged with the well region 11 between them. The body region 15 is arranged to be spaced apart from the drift region 12 via a part of the well region 11.

[0024] A source region 16 and a body contact region 17 are formed in the body region 15. The source region 16 has a P-type conductivity, and a portion of its surface is exposed from the body region 15. The impurity concentration of the source region 16 is higher than the impurity concentration of the drift region 12. The body contact region 17 has an N-type conductivity, and a portion of its surface is exposed from the body region 15. The impurity concentration of the body contact region 17 is higher than the impurity concentration of the body region 15. The source region 16 is located closer to the drain region 13 than the body contact region 17.

[0025] A first insulating layer 21 is formed in the drift region 12. The first insulating layer 21 is disposed between the drain region 13 and the source region 16, and covers at least a portion of the surface of the drift region 12. The first insulating layer 21 is, for example, a local oxidation of silicon (LOCOS) oxide film formed by selectively oxidizing the surface of the drift region 12. The first insulating layer 21 may be STI (Shallow Trench Isolation).

[0026] A second insulating layer 22 is formed in the body region 15. The second insulating layer 22 is disposed between the source region 16 and the body contact region 17, and covers at least a portion of the surface of the body region 15. The second insulating layer 22 is, for example, a local oxidation of silicon (LOCOS) oxide film formed by selectively oxidizing the surface of the body region 15. The second insulating layer 22 may be an STI (Shallow Trench Isolation) film.

[0027] A third insulating layer 23 is formed on the surface of the epitaxial layer 2. The third insulating layer 23 is provided outside the body contact region 17 in the in-plane direction of the epitaxial layer 2. The third insulating layer 23 is a local oxidation of silicon (LOCOS) oxide film formed by selectively oxidizing the surfaces of the epitaxial layer 2, the well region 11, and the body region 15. The third insulating layer 23 may be STI (Shallow Trench Isolation).

[0028] A gate electrode 24 is formed on the epitaxial layer 2. The gate electrode 24 is made of, for example, conductive polysilicon. The gate electrode 24 is disposed so as to straddle the drift region 12 and the body region 15.

[0029] A channel region 20 is formed in the well region 11 at a position between the drift region 12 and the body region 15. The channel region 20 is provided so as to face at least a part of the gate electrode 24. In one embodiment, an insulating film is formed between the channel region 20 and the gate electrode 24.

[0030] In one embodiment, device 50 further comprises a drain contact electrode 31, a source contact electrode 32, a body contact electrode 33, and a gate contact electrode .

[0031] The drain contact electrode 31 is electrically connected to the drain region 13. The drain contact electrode 31 supplies a drain voltage to the drain region 13. The source contact electrode 32 is electrically connected to the source region 16. The source contact electrode 32 supplies a source voltage to the source region 16.

[0032] The body contact electrode 33 is electrically connected to the body contact region 17. The body contact electrode 33 supplies a source voltage to the body contact region 17. The gate contact electrode 34 is electrically connected to the gate electrode 24. The gate contact electrode 34 supplies a gate voltage to the gate electrode 24.

[0033] In device 50, when a gate voltage is applied to gate electrode 24, device 50 is turned on, a channel is formed between drain region 13 and source region 16, and a current flows according to the source and drain voltages. That is, in device 50, the flow of current is controlled according to the gate voltage.

[0034] Next, a method for manufacturing the semiconductor device 100 including the above-described device 50 will be described. Figure 4 is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment.

[0035] In the manufacturing method shown in Fig. 4, first, a semiconductor substrate 1 is prepared (step ST1). Next, a mask layer 40 for forming the buried layer 3 is formed (step ST2). When forming the mask layer 40, a resist is applied to the surface of the semiconductor substrate 1, and then an uncured region is set in a plan view, exposure is performed, and the resist is developed. As a result, the resist in the uncured region is removed, and as shown in Fig. 5, a mask layer 40 having a plurality of openings 44 patterned therein is formed.

[0036] 6(a) to 6(c) are plan views of an exemplary mask layer 40. As shown in FIG. 5(a) to 6(c), the mask layer 40 has a plurality of openings 44 penetrating the mask layer 40 in the thickness direction. The plurality of openings 44 are arranged spaced apart from one another and are distributed two-dimensionally within the plane of the mask layer 40. The openings 44 may have any planar shape, such as a polygonal shape, a circular shape, an elliptical shape, or a slit shape. Typically, the planar shape of the openings 44 is a regular polygonal shape or a circular shape.

[0037] The opening width of the openings 44 may be 5 μm or less. The opening width of the openings 44 refers to the width of the openings formed in the mask layer 40 by the openings 44. For example, if the openings 44 have a circular planar shape, the diameter of the circular opening is defined as the opening width of each opening 44. If the openings 44 have a regular polygonal planar shape, the diameter of a circle inscribed in the regular polygonal opening 44 is defined as the opening width of each opening 44. The mask layer 40 shown in FIGS. 6(a) to 6(c) has a plurality of openings 44, each of which has a substantially square planar shape.

[0038] 6(a), the plurality of openings 44 are perpendicular to the thickness direction of the mask layer 40 and are arranged in a grid pattern along a first direction D1 and a second direction D2 that are perpendicular to each other. The plurality of openings 44 are formed spaced apart from each other. Typically, the plurality of openings 44 are arranged at substantially equal intervals in the first direction D1 and the second direction D2.

[0039] In another embodiment, as shown in Fig. 6(b), the plurality of openings 44 may be arranged along the first direction D1 and may not be aligned in the second direction D2. In yet another embodiment, as shown in Fig. 6(c), the plurality of openings 44 may be arranged at intervals along concentric circular loci. In any of the embodiments shown in Figs. 5(a) to 5(c), the plurality of openings 44 in the mask layer 40 are regularly arranged two-dimensionally.

[0040] 7, the opening 44 may extend in the first direction D1 or the second direction D2. In the embodiment shown in FIG. 7, the opening 44 has an opening width L in the first direction D1 and an opening width W in the second direction D2 that is larger than the opening width L. That is, the opening 44 extends in the second direction D2. In this case, the ratio (W / L) of the opening width W of the opening 44 in the second direction D2 to the opening width L of the opening 44 in the first direction D1 may be 10 or less.

[0041] 8, portions of the semiconductor substrate 1 exposed from the plurality of openings 44 are doped with N-type impurities via the mask layer 40 to form a plurality of impurity regions 42 on the surface of the semiconductor substrate 1 (step ST3). The doping of the N-type impurities is performed by ion implantation or the like. As described above, the plurality of openings 44 are formed two-dimensionally, and therefore, as shown in FIG. 9, the plurality of impurity regions 42 are formed two-dimensionally in an in-plane direction perpendicular to the thickness direction of the semiconductor substrate 1. Typically, as shown in FIG. 9, the plurality of impurity regions 42 are formed two-dimensionally at equal intervals on the surface of the semiconductor substrate 1.

[0042] Next, the mask layer 40 is removed from the semiconductor substrate 1, and an epitaxial layer 2 is formed on the semiconductor substrate 1 (step ST4). The epitaxial layer 2 is a P-type semiconductor layer. Many methods for epitaxially growing silicon are known. For example, when using chemical vapor deposition (CVD), a source gas containing Si is introduced into a chamber together with a carrier gas, and the semiconductor substrate 1 is heated to a high temperature (1000°C or higher) to grow an epitaxial layer 2 made of silicon on the semiconductor substrate 1. The source gas used during growth can contain P-type impurities.

[0043] When the epitaxial layer 2 is formed, the semiconductor substrate 1 is heated, and the N-type impurities in the plurality of impurity regions 42 are thermally diffused within the semiconductor substrate 1 and the epitaxial layer 2. As a result, a buried layer 3 is formed between the semiconductor substrate 1 and the epitaxial layer 2, as shown in FIG.

[0044] At this time, as shown in Fig. 11, the impurities in the impurity region 42 are diffused in all directions from the impurity region 42 by thermal diffusion. The dashed lines in Fig. 11 indicate the range into which the impurities in the impurity region 42 are diffused by heating the semiconductor substrate 1. Therefore, a difference in impurity concentration occurs between the center of the impurity region 42 and positions away from the center after the semiconductor substrate 1 is heated. Therefore, as shown in Fig. 2, a distribution of impurity concentration occurs in the buried layer 3 such that the distribution changes periodically in the in-plane direction of the buried layer 3.

[0045] The center-to-center distance d (see FIG. 3) between adjacent high-concentration regions R1 in the in-plane direction of the buried layer 3 depends on the center-to-center distance between adjacent impurity regions 42. That is, by setting the center-to-center distance between adjacent impurity regions 42 to 10 μm or less, the center-to-center distance d between adjacent high-concentration regions R1 can be set to 10 μm or less.

[0046] As described above, the buried layer 3 can be formed with a thickness that varies periodically in the in-plane direction by thermally diffusing the impurities in the plurality of impurity regions 42. As shown in Fig. 10, the buried layer 3 has portions with a relatively large thickness and portions with a relatively small thickness that alternate in the in-plane direction of the buried layer 3.

[0047] In the manufacturing method shown in FIG. 4, the impurities in the plurality of impurity regions 42 are diffused by the heat generated when forming the epitaxial layer 2. However, in one embodiment, the semiconductor substrate 1 may be heated using a heating furnace to diffuse the impurities in the plurality of impurity regions 42 and form the buried layer 3.

[0048] Next, a first insulating layer 21, a second insulating layer 22, and a third insulating layer 23 are formed on the epitaxial layer 2 (step ST5). For example, the first insulating layer 21, the second insulating layer 22, and the third insulating layer 23 are formed by oxidizing exposed portions of the epitaxial layer 2 through a mask having a pattern corresponding to the shapes of these insulating films. Figure 12 shows a device 50 in the middle of fabrication in which the first insulating layer 21, the second insulating layer 22, and the third insulating layer 23 have been formed.

[0049] Next, a well region 11 is formed in the epitaxial layer 2 (step ST6). The well region 11 is formed by doping the epitaxial layer 2 with an N-type impurity through a mask having a pattern corresponding to the shape of the well region 11. The doping of the N-type impurity is performed by ion implantation or the like. FIG. 13 shows a device 50 in the middle of fabrication in which the well region 11 has been formed.

[0050] Next, the drift region 12 and the body region 15 are formed in the well region 11 (step ST7). The drift region 12 is formed by doping the well region 11 with P-type impurities through a mask having a pattern corresponding to the shape of the drift region 12. The body region 15 is formed by doping the well region 11 with N-type impurities through a mask having a pattern corresponding to the shape of the body region 15. The doping of the P-type and N-type impurities is performed by ion implantation or the like. FIG. 14 shows a device 50 in the middle of fabrication in which the drift region 12 and the body region 15 have been formed.

[0051] Next, a gate electrode 24 is formed on the epitaxial layer 2 (step ST8). The gate electrode 24 is formed by depositing polysilicon on the surface of the epitaxial layer 2 by a chemical vapor deposition (CVD) method or the like. Figure 15 shows a device 50 in the process of being manufactured in which the gate electrode 24 has been formed.

[0052] Next, a drain region 13 and a source region 16 are formed in the drift region 12 and the body region 15, respectively (step ST9). The drain region 13 and the source region 16 are formed by doping the drift region 12 and the body region 15 with P-type impurities using a mask having a pattern corresponding to the shapes of the drain region 13 and the source region 16. A body contact region 17 is also formed in the body region 15. The body contact region 17 is formed by doping the body region 15 with N-type impurities using a mask having a pattern corresponding to the shape of the body contact region 17. FIG. 16 shows a device 50 in the middle of fabrication in which the drain region 13, the source region 16, and the body contact region 17 have been formed.

[0053] Next, drain contact electrode 31, source contact electrode 32, body contact electrode 33, and gate contact electrode 34 are formed on drain region 13, source region 16, body contact region 17, and gate electrode 24, respectively (step ST10), resulting in device 50 shown in FIG.

[0054] As described above, the device 50 includes the buried layer 3 disposed between the semiconductor substrate 1 and the well region 11. The buried layer 3 contributes to the passivation of parasitic elements within the device 50. A parasitic element is an electronic element unintentionally formed in the device 50, typically a parasitic transistor. The passivation effect of the parasitic element depends on the N-type impurity concentration of the buried layer 3; the higher the impurity concentration of the buried layer 3, the greater the passivation effect of the parasitic element. On the other hand, as the impurity concentration of the buried layer 3 increases, the breakdown voltage between the semiconductor substrate 1 and the buried layer 3 decreases.

[0055] In order to increase the breakdown voltage between the semiconductor substrate 1 and the buried layer 3, it is conceivable to reduce the impurity concentration of the buried layer 3. However, when manufacturing multiple types of semiconductor devices with different breakdown voltages, it is necessary to change the manufacturing process depending on the impurity concentration to be doped into the semiconductor substrate 1, and therefore it is not easy to change the impurity concentration of the buried layer 3. Furthermore, when manufacturing multiple types of semiconductor devices with different breakdown voltages, doping is performed using a dedicated mask for each type of semiconductor device, which increases the manufacturing cost of the semiconductor devices.

[0056] In contrast, in the method for manufacturing a semiconductor device according to the above embodiment, a plurality of impurity regions 42 arranged two-dimensionally are formed, and then the impurities in these impurity regions 42 are thermally diffused to form the buried layer 3. As a result, the average impurity concentration of the buried layer 3 is lower than the impurity concentration of the impurity regions 42. That is, it is possible to reduce the impurity concentration of the buried layer 3 without changing the impurity concentration doped into the semiconductor substrate 1. Therefore, it is possible to reduce the impurity concentration of the buried layer 3 while maintaining the conventional doping conditions. As a result, it is possible to manufacture a semiconductor device 100 with a high breakdown voltage at low cost.

[0057] 17 , in one embodiment, the mask layer 40 may have openings 46 for doping a predetermined region with an impurity at a uniform impurity concentration and openings 44 for forming a plurality of two-dimensionally arranged impurity regions 42. With this mask layer 40, a semiconductor device having a buried layer with a uniform and relatively high impurity concentration can be manufactured by doping the semiconductor substrate 1 with an N-type impurity through the openings 46. Furthermore, a semiconductor device having a buried layer 3 with a relatively low impurity concentration can be manufactured by doping the semiconductor substrate 1 with an N-type impurity through the openings 44. In other words, semiconductor devices with different breakdown voltages can be manufactured using the same mask, thereby reducing the manufacturing cost of the semiconductor device.

[0058] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

[0059] In the above embodiment, the first conductivity type is P type and the second conductivity type is N type, but as mentioned above, these conductivity types can be interchanged.

[0060] The present disclosure includes the following contents.

[0061] [A1] preparing a semiconductor substrate of a first conductivity type; doping the semiconductor substrate with impurities of a second conductivity type to form a plurality of impurity regions in the semiconductor substrate, the impurity regions being distributed two-dimensionally in a plane perpendicular to a thickness direction of the semiconductor substrate; forming a buried layer of the second conductivity type in the semiconductor substrate by thermally diffusing the impurities in the plurality of impurity regions; A method for manufacturing a semiconductor device, comprising:

[0062] [A2] further forming a semiconductor layer on the plurality of impurity regions; The method for manufacturing a semiconductor device according to [A1], wherein the impurities in the plurality of impurity regions are thermally diffused by heat generated during the step of further forming the semiconductor layer.

[0063] [A3] The method for manufacturing a semiconductor device according to [A1] or [A2], wherein the plurality of impurity regions are formed so as to be arranged along an in-plane direction perpendicular to the thickness direction.

[0064] [A4] The method for manufacturing a semiconductor device according to any one of [A1] to [A3], wherein the plurality of impurity regions are arranged at substantially equal intervals in the in-plane direction.

[0065] [A5] The method for manufacturing a semiconductor device according to [A3], wherein the center-to-center spacing of the plurality of impurity regions in the in-plane direction is 10 μm or less.

[0066] [A6] The method for manufacturing a semiconductor device according to any one of [A1] to [A5], wherein the plurality of impurity regions are formed by doping the impurities through a mask layer having a plurality of openings arranged two-dimensionally.

[0067] [A7] The method for manufacturing a semiconductor device according to [A6], wherein the ratio of the opening width of each opening of the mask layer in a first direction to the opening width of each opening of the mask layer in a second direction perpendicular to the first direction is 10 or less.

[0068] [A8] The method for manufacturing a semiconductor device according to [A6] or [A7], wherein each opening in the mask layer has a regular polygonal or circular planar shape.

[0069] [A9] The method for manufacturing a semiconductor device according to [A8], wherein the opening width of each opening in the mask layer is 5 μm or less.

[0070] [A10] A semiconductor substrate of a first conductivity type; a semiconductor layer provided on the semiconductor substrate; a buried layer of a second conductivity type disposed between the semiconductor substrate and the semiconductor layer; Equipped with The semiconductor device, wherein the buried layer has an impurity concentration that changes periodically in an in-plane direction perpendicular to a stacking direction of the semiconductor substrate, the buried layer, and the semiconductor layer.

[0071] [A11] The buried layer includes a plurality of high-concentration regions two-dimensionally arranged in a plane perpendicular to the stacking direction, and a plurality of low-concentration regions arranged between the plurality of high-concentration regions, The semiconductor device according to [A10], wherein the plurality of high concentration regions have an impurity concentration higher than the impurity concentration of the plurality of low concentration regions.

[0072] [A12] The method for manufacturing a semiconductor device according to [A11], wherein the center-to-center spacing of the plurality of high concentration regions in the in-plane direction is 10 μm or less.

[0073] [A13] The semiconductor device according to any one of [A10] to [A12], wherein the film thickness of the buried layer varies in the in-plane direction. [Explanation of symbols]

[0074] 1...semiconductor substrate, 2...epitaxial layer, 3...buried layer, 11...well region, 12...drift region, 13...drain region, 15...body region, 16...source region, 17...body contact region, 20...channel region, 21...first insulating layer, 22...second insulating layer, 23...third insulating layer, 24...gate electrode, 31...drain contact electrode, 32...source contact electrode, 33...body contact electrode, 34...gate contact electrode, 40...mask layer, 42...multiple impurity regions, 44...opening, 50...device, 100...semiconductor device, D1...first direction, D2...second direction.

Claims

1. providing a semiconductor substrate of a first conductivity type; doping the semiconductor substrate with impurities of a second conductivity type to form a plurality of impurity regions in the semiconductor substrate, the impurity regions being distributed two-dimensionally in a plane perpendicular to a thickness direction of the semiconductor substrate; forming a buried layer of the second conductivity type in the semiconductor substrate by thermally diffusing the impurities in the plurality of impurity regions; A method for manufacturing a semiconductor device, comprising:

2. further forming a semiconductor layer on the plurality of impurity regions; 2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurities in said plurality of impurity regions are thermally diffused by heat generated during the step of further forming said semiconductor layer.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said plurality of impurity regions are formed so as to be arranged along an in-plane direction perpendicular to said thickness direction.

4. 4. The method for manufacturing a semiconductor device according to claim 3, wherein said plurality of impurity regions are arranged at substantially equal intervals in said in-plane direction.

5. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the center-to-center spacing of the plurality of impurity regions in the in-plane direction is 10 [mu]m or less.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said plurality of impurity regions are formed by doping said impurities through a mask layer having a plurality of openings arranged two-dimensionally.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein a ratio of an opening width of each opening of the mask layer in a second direction perpendicular to the first direction to an opening width of each opening of the mask layer in the first direction is 10 or less.

8. 7. The method for manufacturing a semiconductor device according to claim 6, wherein each opening in the mask layer has a regular polygonal or circular planar shape.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein each opening in the mask layer has a width of 5 [mu]m or less.

10. a semiconductor substrate of a first conductivity type; a semiconductor layer provided on the semiconductor substrate; a buried layer of a second conductivity type disposed between the semiconductor substrate and the semiconductor layer; Equipped with The semiconductor device, wherein the buried layer has an impurity concentration that changes periodically in an in-plane direction perpendicular to a stacking direction of the semiconductor substrate, the buried layer, and the semiconductor layer.

11. the buried layer includes a plurality of high-concentration regions two-dimensionally arranged in a plane perpendicular to the stacking direction, and a plurality of low-concentration regions arranged between the plurality of high-concentration regions, 11. The semiconductor device according to claim 10, wherein said plurality of high concentration regions have impurity concentrations higher than impurity concentrations of said plurality of low concentration regions.

12. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the center-to-center spacing of the plurality of high concentration regions in the in-plane direction is 10 [mu]m or less.

13. 11. The semiconductor device according to claim 10, wherein the film thickness of said buried layer varies in said in-plane direction.

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