Epitaxial wafer

Abstract

To provide an epitaxial wafer having a function as a stop layer in an etching / polishing process when thinning the wafer after bonding, particularly in a silicon device manufacturing process.SOLUTION: An epitaxial wafer having a single crystal Si epitaxial layer (Si epilayer) on a single crystal Si substrate, wherein the Si epilayer has a lattice spacing of single crystal Si of 5.408 Å or less, and a dopant in the single crystal Si substrate is diffused while decreasing from the single crystal Si substrate into the Si epilayer, the epitaxial wafer has a concentration profile in which segregation is locally higher on the Si epitaxial layer side than on the single crystal Si substrate side at an interface between the single crystal Si substrate and the Si epitaxial layer, the epitaxial wafer is a wafer for bonding, and the Si epitaxial layer has a function as an etching stop layer or a polishing stop layer in thinning after bonding.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an epitaxial wafer, and more particularly to an epitaxial wafer for fabricating a device having a junction structure. [Background technology]

[0002] In addition to miniaturization and structural changes (from planar to fin structure), in recent years, wafer bonding has come to be used to improve device performance. As an example, in the case of a solid-state imaging device, a wafer on which a photodiode is fabricated and a wafer on which a peripheral circuit is fabricated are separately prepared and then bonded together (Non-Patent Document 1). Furthermore, in recent years, a structure has been proposed and considered in which the power supply wiring, which was previously formed on the device surface via an insulating layer, is wired to a separate wafer and then bonded (Non-Patent Document 2).

[0003] In bonding devices where wafers are bonded in this way, it is necessary to thin the wafers. To achieve this thinning with precision and without thickness variations, it is possible to provide an etching stop layer or to use SOI and use a BOX film (oxide film) as the stop layer.

[0004] Of these, the use of SOI substrates has the advantage of good thickness uniformity and the presence of a BOX film, which acts as an effective stop layer. However, current 300mm diameter SOI substrates are made using a bonding method, which requires the use of two substrates. Therefore, using SOI substrates requires the use of three or more wafers.

[0005] On the other hand, if a material or structure with a different etching rate is available, this layer can be used as an etching stop layer. Also, when thinning a film by chemical mechanical polishing (CMP), the different etching rates make it effective as a polishing stop layer.

[0006] Based on this idea, it is possible to have layers of materials with different physical properties in the substrate (SOI with an oxide film is an example of this) or to grow layers with different resistances. However, simply growing layers with different resistances sequentially by epitaxial growth often results in a dull resistance profile, causing sagging and preventing the device from fulfilling its intended function.

[0007] To address this issue, several techniques have been disclosed. For example, Patent Document 1 describes a method for forming a gettering layer between a silicon wafer and an epitaxial film by adding carbon at a rate of 1E18 to 1E20 atoms / cm 3 A method for producing wafers and epitaxial wafers doped at a concentration of 1000 .mu.m is disclosed. Furthermore, Patent Document 2 describes that although the carbon atoms are the same, impurities segregate in and around carbon aggregates in a modified layer in which carbon is solid-dissolved and formed by implantation directly below the epitaxial layer. In another example (Patent Document 3), a multilayer composite structure is proposed in which a silicon dioxide layer, a carbon-doped amorphous silicon layer in contact with the silicon dioxide layer, a dielectric layer in contact with the amorphous silicon layer, and a semiconductor element layer in contact with the dielectric layer are formed on the surface of a semiconductor substrate having an area resistivity of approximately 500 Ω·cm. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-051348 [Patent Document 2] Japanese Patent Application Publication No. 2018-142689 [Patent Document 3] Special Publication No. 2017-526190 [Non-patent literature]

[0009] [Non-Patent Document 1] W. Hafez et. al., “Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing”, Abst. of VLSI Symposium 2023, T6-1 [Non-patent document 2] Y. Kikuchi et. al., “Noise Performance Improvements of 2-Layer Transistor PixelStacked CMOS Image Sensor with Non-doped Pixel-FinFETs”, Abst. of VLSI Symposium 2023, T7-4 Summary of the Invention [Problem to be solved by the invention]

[0010] However, the techniques described in the above documents are insufficient in terms of the function as an etching stop layer and in terms of device fabrication.

[0011] The present invention has been made to solve the above problems, and its object is to provide an epitaxial wafer that functions as a stop layer in the etching and polishing steps that are performed to thin the wafer after bonding in the silicon device manufacturing process. [Means for solving the problem]

[0012] In order to achieve the above object, the present invention provides an epitaxial wafer having a single crystal silicon epitaxial layer on a single crystal silicon substrate, comprising: the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less; The dopant in the single crystal silicon substrate is are diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer in a decreasing manner; the single crystal silicon epitaxial layer has a concentration profile at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer that is locally higher on the single crystal silicon epitaxial layer side than on the single crystal silicon substrate side, The epitaxial wafer is a wafer for bonding, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding.

[0013] Since the lattice spacing of the single crystal silicon in the single crystal silicon epitaxial layer is within the above-mentioned range, segregation can be generated in the diffusion concentration profile of the dopant at the interface between the single crystal silicon epitaxial layer and the single crystal silicon substrate. Furthermore, the presence of such segregation can result in a sharp change in dopant concentration at the interface. Therefore, the single crystal silicon epitaxial layer side and the single crystal silicon substrate side can have clearly different resistivities at the interface, making the single crystal silicon epitaxial layer an excellent stop layer for thinning. Furthermore, since the layer functioning as the etching stop layer or the like is a single-crystal silicon epitaxial layer, this is particularly effective when a single-crystal epitaxial layer for device fabrication is formed thereon. For example, in a layer formed by implanting carbon ions rather than a single-crystal silicon epitaxial layer as in the present invention, the ion implantation causes damage to the crystal lattice and the generation of defects, which may adversely affect the device formation layer or the like formed thereon. However, the present invention can eliminate such concerns. This makes it an epitaxial wafer suitable for producing devices with junction structures, which are intended to be bonded together to form thin films. Moreover, the number of substrates used can be reduced compared to when the BOX layer of the SOI substrate is used as the etching stop layer, and the device can be manufactured at a relatively low cost.

[0014] In this case, the single crystal silicon epitaxial layer has a carbon concentration of 6×10 20 atoms / cm 3 That's it, 4 x 10 21 atoms / cm 3 It can be the following:

[0015] In this case, it is possible to more reliably increase the lattice strain while maintaining the single crystal structure, and to have the above-mentioned dopant segregation.

[0016] The dopant in the single crystal silicon substrate may be boron.

[0017] Boron is a common dopant and is therefore convenient. + It may have a / p interface. [Effects of the Invention]

[0018] The epitaxial wafer of the present invention has an excellent function as an etching stop layer or a polishing stop layer, and can be used as an inexpensive and excellent bonding wafer that is also effective for device fabrication, and is therefore suitable for fabricating devices having a bonded structure. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a schematic diagram showing an example of an epitaxial wafer of the present invention. [Figure 2]1 is a graph showing an example of the relationship between the carbon concentration in single crystal silicon and the evaluation results of the lattice spacing by X-ray diffraction (XRD) and Vegard's law. [Figure 3] 10 is a graph showing an example of a diffusion concentration profile of boron when the carbon concentration is 1E20 atoms / cm 3 . [Figure 4] 10 is a graph showing an example of a diffusion concentration profile of boron when the carbon concentration is 3E20 atoms / cm 3 . [Figure 5] 10 is a graph showing an example of a diffusion concentration profile of boron when the carbon concentration is 6E20 atoms / cm 3 . [Figure 6] 10 is a graph showing an example of a diffusion concentration profile of boron when the carbon concentration is 8E20 atoms / cm 3 . DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention will be described in detail below as an example of an embodiment with reference to the drawings, but the present invention is not limited to this. As described above, there has been a demand for a bonding wafer having a layer that functions as an etching stop layer or the like and that can be used for thinning, particularly for fabricating devices having a bonded structure. Therefore, the present inventors have conducted extensive research into such a bonding wafer.

[0021] For example, in Patent Document 1, sequential growth is performed using epitaxial technology, with a carbon-doped layer formed on a silicon substrate and an epitaxial layer formed on top of that. Patent Document 1 is also originally a gettering technology that primarily targets metals using carbon, but dopants such as boron are naturally also affected by this gettering layer, so for example, boron can be segregated to form a layer with a different resistivity and used as an etching stop layer. In this case, the carbon concentration in the carbon-doped layer is 1E18 to 1E20 atoms / cm 3However, as will be described later, in reality, the lattice constant of silicon hardly changes within this range, and the effect as an etching stop layer is insufficient.

[0022] Patent Document 2 describes a method for forming a gettering layer by injecting carbon through ion implantation. While metals are important targets for gettering, dopants such as boron are also affected by this gettering layer. Therefore, for example, boron can be segregated to form a layer with a different resistivity, which can be used as an etching stop layer. However, because this method is based on ion implantation technology, there are concerns about lattice damage and defect generation, even if the implanted species is carefully selected. Therefore, these factors can have a negative impact on device fabrication.

[0023] In addition, in Patent Document 3, the layer is doped with carbon to form an amorphous layer. In this case, when sequential epitaxial growth is considered on a silicon substrate, for example, the presence of the amorphous layer poses a problem (issue) in that the layer grown on top of this will not become single crystal.

[0024] The present inventors have identified these problems and conducted research to find a solution to the problem. As a result, they have conceived of an epitaxial wafer (having a silicon epitaxial layer on a single crystal silicon substrate) characterized in that (1) the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less, (2) dopants in the single crystal silicon substrate are diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer while decreasing, and have a concentration profile in which the dopant is locally higher on the single crystal silicon epitaxial layer side at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer than on the single crystal silicon substrate side, and (3) the epitaxial wafer is a wafer for bonding, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding. The inventors have found that such a wafer can be an inexpensive and excellent wafer for bonding that has a good etching stop layer (or polishing stop layer) and minimizes adverse effects on device fabrication, and have completed the present invention.

[0025] That is, the present invention provides an epitaxial wafer having a single crystal silicon epitaxial layer on a single crystal silicon substrate, wherein the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less, and wherein a dopant in the single crystal silicon substrate is diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer while decreasing, and has a concentration profile in which the dopant is locally higher on the single crystal silicon epitaxial layer side at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer than on the single crystal silicon substrate side, the epitaxial wafer is a wafer to be bonded, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding.

[0026] An example of an epitaxial wafer of the present invention is shown in Figure 1. As shown in Figure 1, the epitaxial wafer 1 of the present invention is a wafer for bonding used in the manufacture of devices having a bonded structure, and is designed to be thinned (by etching or polishing) after bonding. It is composed of a substrate 2, a first epitaxial layer (also referred to as a first EP layer) 3 on the substrate 2, and a second epitaxial layer (also referred to as a second EP layer) 4 on the first epitaxial layer 3.

[0027] Here, the substrate 2 is a single crystal silicon substrate. The substrate 2 is doped with a dopant. Here, an example is given in which the substrate 2 is doped with boron as the dopant (p-type), but this is not limiting. For example, the substrate 2 may be doped with Ga.

[0028] The first EP layer 3 is a single crystal silicon epitaxial layer. The lattice spacing (lattice constant) of the single crystal silicon in this first EP layer 3 is 5.408 Å or less. Compared to the lattice spacing of a typical single crystal silicon substrate, which is 5.43 Å, this is approximately 0.41% narrower (lattice distortion).

[0029] This lattice spacing can be evaluated by, for example, X-ray diffraction (XRD). An example of an apparatus that can be used for evaluation is the Smart Lab manufactured by Rigaku Corporation. Using this apparatus, the substrate was placed in an out-of-plane configuration, and the lattice spacing (inter-lattice distance) was determined.

[0030] In order to generate the lattice distortion in the first EP layer 3, for example, a dopant (for lattice distortion) may be doped. Here, carbon is used as an example, but the present invention is not limited to this. Instead of carbon, another atom (e.g., Ge) may be doped as the dopant (for lattice distortion).

[0031] Here, the relationship between the concentration of carbon as a dopant (for lattice distortion) and the lattice spacing of single crystal silicon doped with that concentration of carbon is shown in Figure 2. More specifically, the lattice spacing at each carbon concentration in single crystal silicon doped with carbon at various concentrations was evaluated using X-ray diffraction (XRD) and Vegard's law. The plots in Figure 2 are the results of evaluation using XRD, and the dashed line graph is the results of evaluation using Vegard's law. Figure 2 also illustrates a range of lattice spacings that is wider than the range of lattice spacings in the present invention. Vegard's law is an empirical rule that states that there is an approximate proportional relationship between the lattice constant of an alloy and the concentration of its constituent elements.

[0032] From these results, it can be seen that the evaluation results of XRD and those of Vegard's law show good agreement, and the carbon concentration is 1E20 atoms / cm 3 It can be seen that the lattice spacing is affected only when the lattice spacing becomes larger than about 5.425 to 5.428 Å (the lattice spacing is about 5.425 to 5.428 Å). However, in the first EP layer 3 of the epitaxial wafer 1 of the present invention, about 5.425 to 5.428 Å is not narrow enough, and as mentioned above, the lattice spacing needs to be 5.408 Å or less. In the case of carbon doping, it is 6E20 atoms / cm 3 By using the above doping concentration, such a narrow lattice spacing can be achieved more reliably. Furthermore, as the carbon concentration increases, the lattice spacing narrows. However, in order to effectively prevent the carbon concentration from becoming too high and changing from single crystal to amorphous, in the present invention, the carbon concentration is set to 4E21 atoms / cm 3 The carbon concentration is preferably in the following range (lattice spacing is about 5.385 Å):

[0033] The agreement between the XRD evaluation results and those of Vegard's law suggests that carbon exists at substitutional sites in the single crystal silicon. This has been confirmed separately by infrared absorption spectroscopy.

[0034] FIG. 3-6 shows the results of checking the actual boron concentration profile (diffusion from the substrate) of the epitaxial wafer while changing the carbon concentration in the first EP layer 3. Here, a carbon-containing single-crystal silicon epitaxial layer B was grown to a thickness of approximately 1 μm on a single-crystal silicon substrate A, and then epitaxial growth was carried out for another hour at 1050°C (single-crystal silicon epitaxial layer C).The boron concentration of the epitaxial wafer from which epitaxial layer C was removed was evaluated using secondary ion mass spectrometry (SIMS). The reason for removing the single crystal silicon epitaxial layer C before evaluation as described above is to shorten the evaluation time using SIMS (and also because the information we particularly wanted to know was near the interface between the single crystal silicon substrate A and the single crystal silicon epitaxial layer B).

[0035] The details of the single crystal silicon substrate A and the single crystal silicon epitaxial layers B and C are as follows: [Single crystal silicon substrate A] Boron-doped substrate: boron concentration is 7E14 atoms / cm 3 It is carbon-undoped and the carbon concentration is 7E15 atoms / cm 3 [Single crystal silicon epitaxial layer B] Carbon doped layer: carbon concentration is 4 patterns (1E20 atoms / cm 3 , 3E20atoms / cm 3 , 6E20atoms / cm 3 , 8E20atoms / cm 3 ) [Single crystal silicon epitaxial layer C] Non-doped carbon layer

[0036] The equipment used for the SIMS evaluation was a 7f manufactured by CAMECA Co., Ltd. Using this equipment, the concentration profile of each element was measured from the surface of the sample to 2 μm.

[0037] In these Figures 3-6, the carbon-doped region (single-crystal silicon epitaxial layer B) extends from the surface to the dotted line (the interface between single-crystal silicon epitaxial layer B and single-crystal silicon substrate A) in the depth direction on the horizontal axis. The boron diffusion profile when no carbon is doped is also shown.

[0038] First, Figure 3 shows the carbon concentration of 1E20 atoms / cm 3 In the case of (Fig. 2, the lattice spacing is about 5.425 to 5.428 Å), Fig. 4 shows the carbon concentration of 3E20 atoms / cm 3 This is an example of the case where the lattice spacing is approximately 5.418 to 5.42 Å. Overall, it can be seen that boron is diffusing from the single-crystal silicon substrate A into the single-crystal silicon epitaxial layer B (carbon-doped layer) while decreasing, but there is no sign of boron segregation anywhere. All that can be seen is that boron is diffusing less when carbon is doped than when carbon is not doped. Even near the interface, no significant (sudden) change in the concentration profile is observed, and the concentration only decreases gradually toward the surface. Therefore, even if an etching process is performed from the single-crystal silicon substrate A side toward the single-crystal silicon epitaxial layer B side, it is difficult to see any significant change in the etching rate at the interface, and the layer cannot fully function as an etching stop layer (or polishing stop layer).

[0039] Also, Figure 5 shows the carbon concentration of 6E20 atoms / cm 3 In the case of (lattice spacing is 5.408Å), the carbon concentration is 8E20 atoms / cm 3 (the lattice spacing is 5.402 Å). These are examples of the epitaxial wafer 1 of the present invention, in which the single crystal silicon substrate A corresponds to the substrate 2, and the single crystal silicon epitaxial layer B corresponds to the first EP layer 3 (and the single crystal silicon epitaxial layer C corresponds to the second EP layer 4). In the case of these carbon concentrations, it can be seen that, overall, boron is being diffused from the single crystal silicon substrate A into the single crystal silicon epitaxial layer B (carbon-doped layer) while decreasing in amount. However, in the vicinity of the dotted line shown as the interface, the boron concentration on the carbon-doped layer side is locally higher than on the single crystal silicon substrate A side, and segregation is observed (the area indicated by the arrow in the graph).

[0040] Specifically, the boron concentration combination at the interface between the single crystal silicon epitaxial layer B (corresponding to the first EP layer 3) and the single crystal silicon substrate A (corresponding to the substrate 2) is 6.3E14 atoms / cm in FIG. 3 / 1.9E14atoms / cm 3 and +4.4Eatoms / cm across the interface. 3 The concentration difference is about 3.3 times higher. In Figure 6, 6.4E14 atoms / cm 3 / 1.4E14atoms / cm 3 and +5.0E14 atoms / cm 3 The concentration difference is about 4.6 times higher.

[0041] In this way, by making the lattice spacing of the single crystal silicon in the first EP layer 3 5.408 Å or less (in the case of carbon doping, 6E20 atoms / cm 3 At a concentration of 0.1 to 100 carbon atoms (carbon concentration), the above-described boron segregation can occur at the interface between the substrate 2 and the first EP layer 3. The presence of such segregation results in a sharp and clear change in resistivity across the interface. Therefore, the first EP layer 3 can fully fulfill its role (function) as an etching stop layer (or polishing stop layer) when the epitaxial wafer 1 is bonded to another substrate or the like and a thinning process (etching or polishing) is performed from the substrate 2 side.

[0042] Another advantage of the epitaxial wafer of the present invention is that it is inexpensive because fewer substrates are used than when the BOX layer of an SOI substrate is used as an etching stop layer.

[0043] In this case, the concentration is 6E20 atoms / cm 3 to 8E20 atoms / cm 3 However, similar functionality can be expected when the carbon concentration is higher than 1E21 atoms / cm. 3 The carbon concentration can be even higher, that is, 4×100 atoms / cm or more (lattice spacing is 5.393 to 5.402 Å or less), and in that case, the function as an etching stop layer can be similarly effective. However, as mentioned above, the carbon concentration is 4×100 atoms / cm 3 It is more preferable that the lattice spacing is about 5.385 Å or more.

[0044] The epitaxial wafer 1 of the present invention needs to have at least the substrate 2 and first EP layer 3 as described above, but as shown in FIG. 1, the second EP layer 4 may also be formed. This second EP layer 4 can be, for example, a single-crystal silicon epitaxial layer, and can be a layer on which a device is formed. Because the first EP layer 3 is a single-crystal silicon epitaxial layer, it is easy to form a good single-crystal epitaxial layer (second EP layer 4) of silicon or the like on it, and therefore this second EP layer 4 can be a layer suitable for device formation. In other words, the first EP layer 3 in the present invention has no (or extremely suppressed) damage or defects to the crystal lattice compared to carbon-implanted layers (modified layers) in the substrate formed by ion implantation as in the prior art (e.g., Patent Document 2), making it possible to prevent adverse effects on device fabrication.

[0045] Furthermore, when formed by ion implantation, the film thickness is characterized by being very thin (for this reason, the modified layer in Patent Document 2 is evaluated using a 3D atom probe). On the other hand, the first EP layer 3 of the present invention can be easily adjusted to an appropriate thickness as an etching stop layer (or polishing stop layer) by adjusting the epitaxial growth time, etc. Therefore, the present invention is advantageous in this respect as well.

[0046] The epitaxial wafer 1 of the present invention and a device having a junction structure using the same can be manufactured, for example, as follows. First, prepare the substrate 2. For example, the substrate 2 can be prepared by slicing a single crystal silicon ingot produced by the CZ method or FZ method while doping it with boron using a wire saw, and then performing grinding, lapping, etching, polishing, etc.

[0047] Then, a carbon-doped single-crystal silicon layer (first EP layer 3) is epitaxially grown under reduced pressure in a low-pressure CVD apparatus using trimethylsilane, monomethylsilane, monosilane gas, or the like. The temperature is not particularly limited, but deposition at a temperature in the range of 700°C to 900°C, preferably 730°C to 750°C, can result in an epitaxial layer with fewer defects. The carbon concentration is not particularly limited, but as mentioned above, it is controlled to an appropriate doping concentration so that the lattice spacing of the single-crystal silicon in the first EP layer 3 is 5.408 Å or less. In particular, 6E20 atoms / cm 3 Above, 4E21atoms / cm 3 At this time, a boron diffusion concentration profile such as that shown in Figure 5-6 is obtained. That is, at the interface between the substrate 2 and the first EP layer 3, a high segregation of boron is obtained on the first EP layer 3 side, and the resistivity changes sharply across the interface.

[0048] Then, single crystal silicon not containing carbon is epitaxially grown on this (second EP layer 4), thereby completing the epitaxial wafer 1 of the present invention as shown in FIG.

[0049] Next, after forming desired devices on the second EP layer 4 of the epitaxial wafer 1 of the present invention, the epitaxial wafer 1 is bonded to another wafer on which devices and the like are formed to produce a bonded wafer. At this time, the side of the second EP layer 4 on which the devices are formed serves as the bonding surface.

[0050] Then, etching (or polishing) is performed on the bonded wafer from the substrate 2 (single crystal silicon substrate) side of the epitaxial wafer 1 portion to thin the surface. At this time, the etching (polishing) is performed while measuring the etching rate (polishing rate). The following describes thinning by etching as an example. Etching can be performed by, for example, wet etching, and as an etching solution for the substrate 2 (single crystal silicon substrate), a mixed solution of hydrofluoric acid and nitric acid, or an aqueous solution of sodium hydroxide or potassium hydroxide can be used.

[0051] At this time, as shown in the boron diffusion concentration profile in Figure 5-6, the boron concentration in the substrate 2 near the interface with the first EP layer 3 gradually decreases toward the interface, and therefore the etching rate in that region also gradually decreases toward the interface. When the etching reaches the interface, the resistivity changes sharply as described above, and the etching rate also increases sharply. This change in the etching rate indicates that the etching has reached the interface, and the etching process is terminated at this point. In this way, the thinning process is completed, and a device having a junction structure can be fabricated. [Example]

[0052] EXAMPLES The present invention will be explained in more detail below by showing examples of the present invention, but the present invention is not limited to these examples. Example 1 Diameter 300 mm, (110) surface, boron doped (boron concentration: 7E14 atoms / cm 3 , Carbon concentration: 7E15atoms / cm 3 ), a single crystal silicon substrate (substrate 2) with a resistivity of 10 Ω·cm was prepared. In a low-pressure CVD apparatus, monosilane gas (SiH4) and trimethylsilane gas (SiH(CH3)3) were used as source gases, and carbon was deposited on the single-crystal silicon substrate at a temperature of 700°C and a pressure of 10 Torr (1333 Pa) at a rate of 6E20 atoms / cm. 3 Then, a single crystal silicon epitaxial layer doped with SiO 2 at a concentration of 1 μm was grown (first EP layer 3). Subsequently, silicon epitaxial growth was carried out using dichlorosilane gas (SiH2Cl2) as a source material at a temperature of 1050°C for a growth time of 60 minutes (second EP layer 4). In this manner, the epitaxial wafer of the present invention was manufactured.

[0053] Thereafter, the lattice spacing in the first EP layer 3 was evaluated by XRD, and the boron concentration was evaluated by SIMS. Since the purpose of this evaluation was to evaluate the substrate 2 and the first EP layer 3, the second EP layer 4 was removed by polishing before the evaluation in order to shorten the evaluation time. These evaluations were carried out using the above-mentioned device.

[0054] Evaluation revealed that the lattice spacing was 5.408 Å. Furthermore, a boron concentration profile similar to that in FIG. 5 was obtained, and segregation of boron on the first EP layer 3 side at the interface between the substrate 2 and the first EP layer 3 was confirmed.

[0055] Example 2 The flow rate of trimethylsilane gas was changed to 8E20 atoms / cm 3 of carbon to be doped in the first EP layer 3. 3 The epitaxial wafer was produced and evaluated in the same manner as in Example 1, except that the above-mentioned conditions were met. Evaluation revealed that the lattice spacing was 5.402 Å. Moreover, a boron concentration profile similar to that in FIG. 6 was obtained, and boron segregation was confirmed on the first EP layer 3 side at the interface.

[0056] Example 3 The flow rate of trimethylsilane gas was changed to increase the carbon doping concentration in the first EP layer 3 to 4E21 atoms / cm 3 The epitaxial wafer was produced and evaluated in the same manner as in Example 1, except that the above-mentioned conditions were met. Evaluation revealed that the lattice spacing was 5.385 Å. Furthermore, a boron concentration profile similar to that in FIG. 5-6 was obtained, and boron segregation was confirmed on the first EP layer 3 side at the interface.

[0057] (Comparative Example 1) A single crystal silicon substrate (boron concentration: 7E14 atoms / cm) similar to that of Example 1 was used. 3 , Carbon concentration: 7E15atoms / cm 3 ) was prepared, and a single crystal silicon epitaxial layer was grown to a thickness of 1 μm at a temperature of 700° C. and a pressure of 10 Torr (1333 Pa) in a low pressure CVD apparatus using monosilane as a source gas. Next, in the same manner as in Example 1, silicon epitaxial growth was carried out using dichlorosilane gas as a raw material at a temperature of 1050° C. for a growth time of 60 minutes. An epitaxial wafer was manufactured in this manner, and then evaluated in the same manner as in Example 1. Evaluation revealed that the lattice spacing was 5.43 Å. Furthermore, a boron concentration profile similar to that in Figure 3 was obtained, and no boron segregation was observed near the interface. The carbon concentration in the single crystal silicon epitaxial layer directly on the single crystal silicon substrate was 7E15 atoms / cm, the same as that of the single crystal silicon substrate. 3 It was.

[0058] (Comparative Example 2) By changing the flow rate of trimethylsilane gas, the carbon doping in the single crystal silicon epitaxial layer directly above the single crystal silicon substrate was increased to 3E20 atoms / cm 3 The epitaxial wafer was produced and evaluated in the same manner as in Example 1, except that the above-mentioned conditions were met. Evaluation revealed that the lattice spacing was 5.42 Å. Furthermore, a boron concentration profile similar to that in Figure 4 was obtained, and no boron segregation was observed near the interface.

[0059] Furthermore, the epitaxial wafers (single crystal silicon substrate + single crystal silicon epitaxial layer + single crystal silicon epitaxial layer) produced in Examples 1 to 3 and Comparative Examples 1 and 2 were bonded to another wafer to produce a bonded wafer, and then an etching process was performed to thin the wafer. In the case of the epitaxial wafer of Example 1-3, the etching rate gradually decreased as the etching process progressed, but then there was a point where it suddenly increased. Therefore, the etching process was terminated at that point, assuming that the etching process had reached the interface. This enabled the production of a bonded wafer that had been thinned using the carbon-doped layer as an etching stop layer. On the other hand, in the cases where the epitaxial wafers of Comparative Examples 1 and 2 were used, the etching rate continued to decrease gradually, and the interface could not be found, so the etching process was terminated midway.

[0060] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and that provides similar effects is included within the technical scope of the present invention. [Explanation of symbols]

[0061] 1... epitaxial wafer of the present invention, 2... substrate, 3...first epitaxial layer, 4...second epitaxial layer.

Claims

1. An epitaxial wafer having a single crystal silicon epitaxial layer on a single crystal silicon substrate, the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less; The dopant in the single crystal silicon substrate is are diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer in a decreasing manner; the single crystal silicon epitaxial layer has a concentration profile at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer that is locally higher on the single crystal silicon epitaxial layer side than on the single crystal silicon substrate side, The epitaxial wafer is a wafer for bonding, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding.

2. The single crystal silicon epitaxial layer has a carbon concentration of 6×10 ２０ atoms / cm ３ That's it, 4 x 10 ２１ atoms / cm ３ 2. The epitaxial wafer according to claim 1, wherein:

3. 3. The epitaxial wafer according to claim 1, wherein the dopant in the single crystal silicon substrate is boron.

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