Semiconductor device and method of manufacturing the same

Abstract

To improve the performance of a semiconductor device.SOLUTION: The semiconductor package includes a printed circuit board 2t having an upper surface SUB1, a semiconductor package SUB1 mounted on the printed circuit board CHP1, and a stiffening ring 4 fixed to the printed circuit board SUB1 via a plurality of adhesive layers BND. The upper surface 2t is a quadrangle, and a center line 2CL1, a center line 2CL2, a diagonal 2d1, and a diagonal 2d2 can be drawn. The stiffener ring 4 has four extending portions and four corner portions. The plurality of bonding layers BND include four bonding layers BND1, BND2, BND3, and BND4 which overlap the four extending portions, respectively, and are disposed at positions overlapping the center line 2CL1 or the center line 2CL2. In addition, the plurality of bonding layers BND include other four bonding layers 2d1, BND6, BND7, and BND8 which overlap with the four corner portions and are disposed at positions overlapping with the diagonal line 2d2 or the diagonal line. BND5.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a semiconductor device in which a semiconductor chip is mounted on a wiring substrate, there is a technique for mounting a plate (stiffener) on the wiring substrate to reinforce the wiring substrate (see, for example, Patent Document 1 (JP 2003-51568 A) and Patent Document 2 (JP 2014-130961 A)). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-51568 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-130961 Summary of the Invention [Problem to be solved by the invention]

[0004] A stiffener ring mounted on a wiring board is required to have the function of suppressing warpage of the wiring board. The stiffener ring is fixed to the wiring board via an adhesive layer. One possible method for ensuring the adhesive strength required to suppress warpage of the wiring board is to have an adhesive layer continuously disposed around the entire periphery of the stiffener ring.

[0005] On the other hand, from the viewpoint of reducing the amount of material used for the adhesive layer, for example, it is preferable that there are regions where the adhesive layer is interposed between the stiffener ring and the wiring substrate and regions where the adhesive layer is not interposed.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a wiring substrate having a top surface, a semiconductor chip mounted on the top surface of the wiring substrate, and a stiffener ring fixed to the top surface of the wiring substrate via a plurality of spaced-apart adhesive layers. The top surface is rectangular, and a first centerline, a second centerline, a first diagonal, and a second diagonal can be drawn. The stiffener ring has four extending portions and four corners. The plurality of adhesive layers includes four adhesive layers that overlap the four extending portions and are positioned to overlap the first centerline or the second centerline. The plurality of adhesive layers also includes four other adhesive layers that overlap the four corners and are positioned to overlap the first diagonal or the second diagonal.

[0008] A method for manufacturing a semiconductor device according to another embodiment includes the steps of (a) mounting a semiconductor chip on an upper surface of a wiring substrate and (b) mounting a stiffener ring in a first region of the upper surface of the wiring substrate. The step (b) includes the steps of (b1) applying an adhesive to multiple locations in the first region, (b2) placing the stiffener ring on the first region and adhering the stiffener ring via the adhesive, and (b3) curing the adhesive to form multiple adhesive layers spaced apart from one another, thereby fixing the stiffener ring to the wiring substrate. The upper surface is rectangular, and a first center line, a second center line, a first diagonal line, and a second diagonal line can be drawn. The first region has four extensions and four corners. In the step (b1), the plurality of adhesives applied to be spaced apart from one another include four adhesives that overlap the four extension portions, respectively, and are applied at positions that overlap the first center line or the second center line, and the plurality of adhesives also include four other adhesives that overlap the four corner portions, respectively, and are applied at positions that overlap the first diagonal line or the second diagonal line. [Effects of the Invention]

[0009] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a bottom view of the semiconductor device shown in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 4] 2 is a transparent plan view showing an adhesive layer between the stiffener ring and the wiring substrate through the stiffener ring shown in FIG. 1. FIG. [Figure 5] 10A and 10B are explanatory diagrams schematically illustrating the relationship between the direction in which the wiring board deforms and the stiffener ring mounted on the wiring board. [Figure 6] 2 is a plan view showing a state in which the stiffener ring and adhesive layer shown in FIG. 1 have been removed. [Figure 7] FIG. 5 is a plan view showing a modification of FIG. 4. [Figure 8] FIG. 2 is a plan view showing a semiconductor device which is a modified example of the semiconductor device shown in FIG. [Figure 9] FIG. 9 is an explanatory diagram of the semiconductor device shown in FIG. [Figure 10] 9 is a transparent plan view showing an adhesive layer between the stiffener ring and the wiring substrate through the stiffener ring shown in FIG. 8. FIG. [Figure 11] FIG. 11 is a transparent plan view showing a modification of FIG. [Figure 12] FIG. 2 is a plan view showing another modified example of FIG. [Figure 13] FIG. 1 is an explanatory diagram showing an example of a flow of an assembly process of a semiconductor device according to an embodiment; [Figure 14] 14 is a plan view showing a modified example of the wiring board prepared in the wiring board preparing step shown in FIG. 13. FIG. [Figure 15] 14 is a plan view showing a state in which an adhesive has been applied onto the wiring board in the adhesive application step shown in FIG. 13. FIG. [Figure 16] FIG. 16 is a plan view showing a modification of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Explanation of the description format, basic terms and usage in this application) In this application, the description of the embodiments will be divided into multiple sections, etc., for convenience, as necessary. However, unless otherwise expressly stated, these are not mutually independent and separate, and regardless of the order of description, they are each part of a single example, one being a partial detail of the other, or a partial or complete modification, etc. Furthermore, as a general rule, repeated explanations of similar parts will be omitted. Furthermore, each component in the embodiments is not essential unless otherwise expressly stated, there is a theoretical limit to the number, or it is clearly not essential from the context.

[0012] Similarly, in the description of embodiments, when a material, composition, etc. is described as "X consisting of A," this does not exclude elements other than A, unless otherwise expressly stated or clearly indicated by the context. For example, when referring to a component, it means "X containing A as its primary component." For example, a "silicon component" does not necessarily refer to pure silicon, but also includes SiGe (silicon-germanium) alloys and other multi-component alloys containing silicon as the primary component, as well as components containing other additives. Furthermore, unless otherwise expressly stated, gold plating, Cu layer, nickel plating, etc., include not only pure components but also components containing gold, Cu, nickel, etc. as their primary components.

[0013] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, unless it is theoretically limited to that number, or unless it is clearly not the case from the context, the number may be greater than that specific number or less than that specific number.

[0014] Furthermore, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated in principle.

[0015] In the accompanying drawings, hatching may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the description, etc. Furthermore, hatching or dot patterns may be added even in cases where the drawing is not a cross section to clearly indicate that the hole is not a void or to clearly indicate the boundary of the area.

[0016] <Semiconductor device> Fig. 1 is a top view of a semiconductor device according to one embodiment. Fig. 2 is a bottom view of the semiconductor device shown in Fig. 1. Fig. 3 is a cross-sectional view taken along line AA in Fig. 1. In Fig. 1, the outline of a semiconductor chip CHP1 covered with a stiffener ring 4 is shown by a dotted line.

[0017] In Figures 1 to 3, any of the X direction (see Figures 1 to 3), the Y direction (see Figures 1 and 2), and the Z direction (see Figure 3) is depicted. The Y direction is the side that intersects with the X direction, and in the following description, the X direction and the Y direction are perpendicular to each other. The Z direction is a direction perpendicular to both the X direction and the Y direction. In other words, the Z direction is the normal direction to the XY plane that includes the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Furthermore, in the following description, "planar view" generally means a planar view looking at the XY plane.

[0018] The semiconductor device PKG1 of this embodiment includes a wiring substrate SUB1 and a semiconductor chip CHP1 (see FIG. 3) mounted on the wiring substrate SUB1. The semiconductor device PKG1 also includes a stiffener ring 4 disposed so as to continuously surround the periphery of the semiconductor chip CHP1 in a plan view.

[0019] In recent years, as semiconductor devices have become more sophisticated, the planar size of the wiring board SUB1 has tended to increase. As the planar size of the wiring board SUB1 increases, the possibility of warping deformation of the wiring board SUB1 increases. This is because, for example, stress applied to the wiring board SUB1 due to temperature cycle load increases in proportion to the length of the diagonal of the wiring board SUB1.

[0020] In the present embodiment, a stiffener ring 4 is mounted on the wiring board SUB1 as a member for suppressing warpage deformation of the wiring board SUB1.

[0021] The details of the semiconductor device PKG1 will be explained below in order.

[0022] 3, the wiring board SUB1 of the semiconductor device PKG1 has an upper surface 2t which is a chip mounting surface and a lower surface 2b opposite to the upper surface 2t. The lower surface 2b functions as a mounting surface for the semiconductor device PKG1.

[0023] The wiring board SUB1 of the semiconductor device PKG1 has internal interface terminals (pads 2PD) exposed from the insulating film SR1 on the upper surface 2t, and external interface terminals (lands 2LD) exposed from the insulating film SR2 on the lower surface 2b, which is the mounting surface.

[0024] The wiring board SUB1 also has multiple wiring layers that electrically connect the internal interface terminals and the external interface terminals. In the example shown in Fig. 3, the wiring board SUB1 is an eight-layer wiring board including wiring layer WL1, wiring layer WL2, wiring layer WL3, wiring layer WL4, wiring layer WL5, wiring layer WL6, wiring layer WL7, and wiring layer WL8. However, the number of wiring layers of the wiring board SUB1 is not limited to eight, and may be seven or less, or nine or more.

[0025] Each wiring layer is located between the upper surface 2t and the lower surface 2b. Each wiring layer has a conductor pattern such as wiring that is a path for supplying electrical signals and power. The wiring layers are electrically connected to each other via via wiring 2v, which is an interlayer conductive path that penetrates the insulating layer 2e, or through-hole wiring 2THW. An insulating layer 2e is arranged between each wiring layer. The multiple insulating layers 2e arranged between each wiring layer include a core insulating layer (insulating layer, core material, core insulating layer) 2CR arranged between the upper surface 2t and the lower surface 2b. The core insulating layer 2CR is a core member that ensures the rigidity of the wiring board SUB1 and is made of, for example, prepreg made of glass fiber impregnated with resin.

[0026] Among the multiple wiring layers, the wiring layer WL1 arranged closest to the top surface 2t is covered with an insulating film SR1. Openings are provided in the insulating film SR1, and each of the multiple pads 2PD provided on the wiring layer WL1 is exposed from the insulating film SR1 through the openings.

[0027] Of the multiple wiring layers, the wiring layer WL8, which is located closest to the lower surface 2b of the wiring board SUB1, is provided with multiple lands 2LD. The wiring layer WL8 is covered with an insulating film SR2. Each of the insulating films SR1 and SR2 is a solder resist film made of an organic material that can suppress the spread of solder. The multiple pads 2PD provided on the wiring layer WL1 and the multiple lands 2LD provided on the wiring layer WL8 are electrically connected to each other via conductor patterns (wires 2d and large-area conductor patterns 2CP), via wiring 2v, and through-hole wiring 2THW formed on each wiring layer of the wiring board SUB1.

[0028] The wiring 2d, pad 2PD, via wiring 2v, via land (not shown), through-hole land (not shown), through-hole wiring 2THW, land 2LD, and conductive pattern 2CP are each made of, for example, copper or a metal material containing copper as a main component.

[0029] The wiring board SUB1 is formed, for example, by stacking a plurality of wiring layers on each of the upper surface 2Ct and the lower surface 2Cb of a core insulating layer (insulating layer, core material, core insulating layer) 2CR by a build-up method. The wiring layer WL4 on the upper surface 2Ct side of the core insulating layer 2CR and the wiring layer WL5 on the lower surface 2Cb side are electrically connected via a plurality of through-hole wirings 2THW embedded in a plurality of through holes (through holes) provided so as to penetrate from one side of the upper surface 2Ct to the other side of the lower surface 2Cb.

[0030] 3, a plurality of solder balls (solder material, external terminals, electrodes, external electrodes) SB are formed on the lower surface 2b of the wiring board SUB1. More specifically, a solder ball SB is connected to each of a plurality of lands 2LD of the wiring board SUB1. The solder balls SB are conductive members that electrically connect a plurality of terminals (not shown) on a motherboard (not shown) to a plurality of lands 2LD when the semiconductor device PKG1 is mounted on the motherboard. The solder balls SB are, for example, a solder material made of an Sn-Pb solder material containing lead (Pb), or a so-called lead-free solder that does not substantially contain Pb. Examples of lead-free solder include tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. Here, lead-free solder means solder containing 0.1 wt% or less lead (Pb), and this content is set as a standard by the RoHS (Restriction of Hazardous Substances) Directive.

[0031] As shown in FIG. 2, the solder balls SB are arranged in a matrix (array or matrix). Although not shown in FIG. 2, the lands 2LD (see FIG. 3) to which the solder balls SB are bonded are also arranged in a matrix. A semiconductor device in which the external terminals (solder balls SB, lands 2LD) are arranged in a matrix on the mounting surface of the wiring board SUB1 is called an area array type semiconductor device. Area array type semiconductor devices are advantageous in that they can effectively utilize the mounting surface (lower surface 2b) of the wiring board SUB1 as a space for arranging the external terminals, thereby preventing an increase in the mounting area of ​​the semiconductor device even if the number of external terminals increases. In other words, semiconductor devices with an increasing number of external terminals as the functionality and integration become more sophisticated can be mounted in a space-saving manner.

[0032] The semiconductor device PKG1 has a semiconductor chip CHP1 mounted on a wiring substrate SUB1. As shown in Fig. 3, each of the semiconductor chips CHP1 has a front surface (main surface, upper surface) 3t on which a plurality of protruding electrodes 3BP are arranged, and a back surface (main surface, lower surface) 3b opposite to the front surface 3t.

[0033] The semiconductor chip CHP1 has a rectangular outer shape with a smaller plane area than the wiring board SUB1 in a plan view, as shown in Fig. 1. In the example shown in Fig. 1, the semiconductor chip CHP1 is mounted in the center of the upper surface 2t of the wiring board SUB1. Furthermore, each of the four sides of the semiconductor chip CHP1 extends along each of the four sides (side 2s1, side 2s2, side 2s3, and side 2s4) of the upper surface 2t of the wiring board SUB1.

[0034] As shown in Figure 3, a plurality of electrodes (pads, electrode pads, bonding pads) 3PD are formed on the surface 3t side of the semiconductor chip CHP1. The surface 3t is the outermost surface of the semiconductor chip CHP1. The surface 3t includes the upper surface of a passivation film (not shown) and the upper surfaces of the electrodes 3PD exposed from the passivation film. Since the plurality of protruding electrodes 3BP are formed on the electrodes 3PD, it can be said that the plurality of protruding electrodes 3BP are formed on the surface 3t.

[0035] 3, the semiconductor chip CHP1 is mounted on the wiring board SUB1 with its surface 3t facing the upper surface 2t of the wiring board SUB1. This mounting method is called a face-down mounting method or a flip-chip connection method.

[0036] Although not shown in the drawings, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CHP1 (more specifically, a semiconductor element formation region provided on the element formation surface of a semiconductor substrate that is the base material of the semiconductor chip CHP1). The plurality of electrodes 3PD are electrically connected to the plurality of semiconductor elements, respectively, via wiring (not shown) formed in a wiring layer arranged inside the semiconductor chip CHP1 (more specifically, between the surface 3t and the semiconductor element formation region, not shown).

[0037] The semiconductor chip CHP1 (more specifically, the semiconductor substrate of the semiconductor chip CHP1) is made of, for example, silicon (Si). An insulating film (a passivation film, not shown) covering the semiconductor substrate and wiring of the semiconductor chip CHP1 is formed on the surface 3t, and a portion of each of the multiple electrodes 3PD is exposed from the passivation film at an opening formed in the passivation film. Each of the multiple electrodes 3PD is made of metal, and in this embodiment, is made of, for example, aluminum (Al).

[0038] 3, protruding electrodes 3BP are connected to the electrodes 3PD, respectively, and the electrodes 3PD of the semiconductor chip CHP1 and the pads 2PD of the wiring substrate SUB1 are electrically connected to each other via the protruding electrodes 3BP. The protruding electrodes (bump electrodes) 3BP are metal members (conductive members) formed so as to protrude from the surface 3t of the semiconductor chip CHP1. In this embodiment, the protruding electrodes 3BP have a structure in which a columnar electrode (so-called copper pillar electrode) made of, for example, copper is formed on the electrodes 3PD, and a solder material is laminated on the tip of the columnar electrode. As with the solder balls SB described above, the solder material laminated on the tip of the columnar electrode can be a lead-containing solder material or a lead-free solder.

[0039] When mounting the semiconductor chip CHP1 on the wiring board SUB1, a bonding material (e.g., a base metal film or solder paste) with good bonding properties with solder is formed in advance on the multiple pads 2PD. By carrying out a heat treatment (reflow treatment) while the solder material at the tip of the columnar electrode and the bonding material on the pad 2PD are in contact with each other, the solder is integrated to form the protruding electrode 3BP. As a variation of this embodiment, a columnar electrode made of nickel (Ni) or a so-called solder bump formed by forming a micro solder ball on the electrode 3PD via a base metal film may be used as the protruding electrode 3BP.

[0040] As shown in FIG. 3, an underfill resin (insulating resin) UF is disposed between the semiconductor chip CHP1 and the wiring board SUB1. The underfill resin UF is disposed so as to fill the space between the surface 3t of the semiconductor chip CHP1 and the upper surface 2t of the wiring board SUB1. Each of the plurality of protruding electrodes 3BP is sealed with the underfill resin UF. The underfill resin UF is made of an insulating (non-conductive) material (e.g., a resin material) and is disposed so as to seal the electrical connection portions (joints of the plurality of protruding electrodes 3BP) between the semiconductor chip CHP1 and the wiring board SUB1. Covering the joints between the plurality of protruding electrodes 3BP and the plurality of pads 2PD with the underfill resin UF in this manner can reduce stress occurring in the electrical connection portions between the semiconductor chip CHP1 and the wiring board SUB1. Furthermore, stress occurring in the joints between the plurality of electrodes 3PD of the semiconductor chip CHP1 and the plurality of protruding electrodes 3BP can also be reduced. Furthermore, the main surface of the semiconductor chip CHP1 on which the semiconductor elements (circuit elements) are formed can also be protected.

[0041] As shown in FIG. 3, the stiffener ring 4 is adhesively fixed onto the wiring substrate SUB1 via multiple adhesive layers, including adhesive layers BND3 and BND4. As shown in FIG. 1, the stiffener ring 4 is an annular member arranged so as to continuously surround the periphery of the semiconductor chip CHP1 in a plan view. The stiffener ring 4 is made of a metal such as copper (Cu). When a copper stiffener ring 4 is used, a metal film such as nickel may be formed on the surface (e.g., the upper, lower, and inner surfaces) of the stiffener ring 4 to prevent oxidation of the surface.

[0042] One of the purposes of mounting the stiffener ring 4 on the wiring board SUB1 is to suppress warpage of the wiring board SUB1. Warpage of the wiring board SUB1 occurs due to stress that occurs when a temperature change occurs in the wiring board SUB1. In a plan view, the greatest stress is applied to the peripheral portion of the top surface 2t of the wiring board SUB1. Therefore, the stiffener ring 4 is arranged along the peripheral portion of the top surface 2t.

[0043] In BGA-type semiconductor devices, a cover member called a lid is placed to cover the semiconductor chip. The lid is placed on the wiring substrate to cover the semiconductor chip, and is therefore adhered not only to the wiring substrate but also to the semiconductor chip. Therefore, the adhesive strength between the lid and the wiring substrate depends not only on the strength of the adhesive layer that bonds the lid to the wiring substrate, but also on the strength of the lid fixed to the wiring substrate via the semiconductor chip.

[0044] On the other hand, because the stiffener ring 4 of this embodiment is an annular member, the stiffener ring 4 and the semiconductor chip CHP1 are spaced apart from each other. That is, the stiffener ring 4 is disposed on the wiring board SUB1 so as not to cover the semiconductor chip CHP1. In this case, the fixing strength between the semiconductor chip CHP1 and the wiring board SUB1 does not contribute to the adhesive strength between the stiffener ring 4 and the wiring board SUB1. In order for the stiffener ring 4 to suppress warpage deformation of the wiring board SUB1, the stiffener ring 4 must be firmly fixed to the wiring board SUB1, so the adhesive strength of the adhesive layer is an important factor.

[0045] Since the stiffener ring 4 is an annular member, the back surface 3b of the semiconductor chip CHP1 remains exposed even after the stiffener ring 4 is mounted on the wiring board SUB1. In this case, for example, a heat sink for heat dissipation having a size larger than the size of the upper surface 2t of the wiring board SUB1 can be brought into direct contact with the back surface 3b of the semiconductor chip CHP1.

[0046] One possible method for improving the adhesive strength between the stiffener ring 4 and the wiring board SUB1 is to place an adhesive layer around the entire periphery of the stiffener ring 4. However, there are cases where it is preferable not to place an adhesive layer between the stiffener ring 4 and the wiring board SUB1.

[0047] For example, from the viewpoint of reducing the amount of adhesive layer used and suppressing the manufacturing cost of the semiconductor device PKG1, it is preferable that there is a space between the stiffener ring 4 and the wiring substrate SUB1 where no adhesive layer is disposed.

[0048] Alternatively, in the manufacturing process of the semiconductor device PKG1, a cleaning process may be performed to remove flux components after forming solder balls. In this case, the cleaning liquid will flow onto the upper surface 2t (see FIG. 3) as well as the lower surface 2b of the wiring substrate SUB1 (see FIG. 3). From the viewpoint of preventing the cleaning liquid that has flowed onto the upper surface 2t from accumulating, it is preferable that there be a space between the stiffener ring 4 and the wiring substrate SUB1 where no adhesive layer is disposed. This is because the cleaning liquid is discharged through the space where no adhesive layer is disposed, thereby preventing the cleaning liquid from accumulating.

[0049] In light of the above, the inventors of the present application have studied a fixing method in which the stiffener ring 4 and the wiring board SUB1 are fixed to the wiring board SUB1 via multiple adhesive layers, and the multiple adhesive layers are spaced apart from one another. Details will be described below.

[0050] <Layout of components mounted on the top surface of the wiring board> Next, the layout of multiple components mounted on the upper surface 2t of the wiring board SUB1 will be described. FIG. 4 is a transparent plan view showing the adhesive layer between the stiffener ring and the wiring board, seen through the stiffener ring shown in FIG. 1. In FIG. 4, the outline of the stiffener ring 4 shown in FIG. 1 is indicated by a dotted line. FIG. 5 is an explanatory diagram schematically showing the relationship between the direction in which the wiring board deforms and the stiffener ring mounted on the wiring board. Note that FIG. 5 is a cross-sectional view taken along the extension direction of the extension portion 4e1 shown in FIG. 4. FIG. 6 is a plan view showing the state in which the stiffener ring and adhesive layer shown in FIG. 1 have been removed. Note that in FIG. 6, the outline of the area where the adhesive layer BND shown in FIG. 4 is disposed and the edge of the area where the stiffener ring 4 is disposed are indicated by a two-dot chain line.

[0051] 1, the top surface 2t of the wiring board SUB1 has a side 2s1, a side 2s2 opposite to the side 2s1, a side 2s3 intersecting with the sides 2s1 and 2s2, and a side 2s4 opposite to the side 2s3. The top surface 2t also has an angle 2c1 at the intersection of the side 2s1 and the side 2s3, an angle 2c2 at the intersection of the side 2s1 and the side 2s4, an angle 2c3 at the intersection of the side 2s2 and the side 2s3, and an angle 2c4 at the intersection of the side 2s2 and the side 2s4.

[0052] Furthermore, because the top surface 2t is a quadrangle, two diagonal lines can be drawn, although they are not visible lines but virtual lines. That is, on the top surface 2t, a diagonal line 2d1 can be drawn connecting the intersection point (corner 2c1) of side 2s1 and side 2s3 and the intersection point (corner 2c4) of side 2s2 and side 2s4. Also, on the top surface 2t, a diagonal line 2d2 can be drawn connecting the intersection point (corner 2c2) of side 2s1 and side 2s4 and the intersection point (corner 2c3) of side 2s2 and side 2s3. In the example shown in FIG. 1, sides 2s1 and 2s2 are sides that extend along the X direction, and sides 2s3 and 2s4 are sides that extend along the Y direction.

[0053] In a plan view, the stiffener ring 4 includes an extending portion 4e1 extending along side 2s1, an extending portion 4e2 extending along side 2s2, an extending portion 4e3 extending along side 2s3, and an extending portion 4e4 extending along side 2s4. The stiffener ring 4 also includes a corner 4c1 connected between the extending portions 4e1 and 4e3, a corner 4c2 connected between the extending portions 4e1 and 4e4, a corner 4c3 connected between the extending portions 4e2 and 4e3, and a corner 4c4 connected between the extending portions 4e2 and 4e4.

[0054] 1, corners 4c1 and 4c4 overlap with diagonal line 2d1 in plan view, and when diagonal line 2d2 is drawn, corners 4c2 and 4c3 overlap with diagonal line 2d2.

[0055] As shown in Figure 3, the stiffener ring 4 is fixed to the upper surface 2t of the wiring board SUB1 via multiple adhesive layers (adhesive layers BND3 and BND4 are shown in Figure 3) that are arranged between the stiffener ring 4 and the upper surface 2t of the wiring board SUB1 and spaced apart from each other.

[0056] Furthermore, because the top surface 2t of the wiring board SUB1 is rectangular, two center lines can be drawn on the top surface 2t, although they are imaginary lines and not actually visible, as shown in Fig. 4. That is, a center line 2CL1 can be drawn on the top surface 2t, connecting the center of the side 2s1 and the center of the side 2s2. Furthermore, a center line 2CL2 can be drawn on the top surface 2t, connecting the center of the side 2s3 and the center of the side 2s4.

[0057] As shown in Figure 4, in this embodiment, the multiple adhesive layers BND include an adhesive layer BND1 arranged at a position overlapping with the extension portion 4e1 (see Figure 1) and arranged at a position overlapping with the center line 2CL1, an adhesive layer BND2 arranged at a position overlapping with the extension portion 4e2 (see Figure 1) and arranged at a position overlapping with the center line 2CL1, an adhesive layer BND3 arranged at a position overlapping with the extension portion 4e3 (see Figure 1) and arranged at a position overlapping with the center line 2CL2, and an adhesive layer BND4 arranged at a position overlapping with the extension portion 4e4 (see Figure 1) and arranged at a position overlapping with the center line 2CL2.

[0058] The multiple adhesive layers BND also include an adhesive layer BND5 arranged at a position overlapping the corner 4c1 and also arranged at a position overlapping the diagonal line 2d1, an adhesive layer BND6 arranged at a position overlapping the corner 4c2 and also arranged at a position overlapping the diagonal line 2d2, an adhesive layer BND7 arranged at a position overlapping the corner 4c3 and also arranged at a position overlapping the diagonal line 2d2, and an adhesive layer BND8 arranged at a position overlapping the corner 4c4 and also arranged at a position overlapping the diagonal line 2d1.

[0059] According to the study by the inventors of the present application, from the viewpoint of suppressing warpage deformation of the wiring board SUB1, it is preferable to arrange adhesive layers BND in at least eight places as shown in FIG.

[0060] 5, when the wiring board SUB1 warps, the center of the upper surface 2t becomes convex. In other words, the wiring board SUB1 deforms so that the height of the peripheral edge portion becomes lower than the height of the central portion of the upper surface 2t.

[0061] If the stiffener ring 4 has sufficiently high rigidity and does not deform, a force that suppresses warpage of the wiring board SUB1 is applied via the adhesive layer BND that is bonded between the stiffener ring 4 and the wiring board SUB1. From the viewpoint of effectively suppressing warpage, it is preferable that adhesive layers BND be disposed in the portion with the smallest amount of deformation and the portion with the largest amount of deformation.

[0062] According to this embodiment, adhesive layers BND are arranged in eight locations as shown in FIG. 4, so that when the wiring board SUB1 warps and deforms, the portions with the smallest amount of deformation and the portions with the largest amount of deformation are bonded together.

[0063] The inventors of the present application experimentally confirmed the warpage suppression effect of the wiring board SUB1 according to the embodiment shown in FIG. 4, and found that when the adhesive layer BND is arranged in the eight locations shown in FIG. 4, the same degree of deformation suppression effect can be obtained as when the adhesive layer BND is arranged around the entire periphery of the stiffener ring 4.

[0064] On the other hand, when focusing on the amount of adhesive layer BND used, the total volume of the eight adhesive layers BND from adhesive layer BND1 to adhesive layer BND8 is less than half the volume when adhesive layers BND are arranged around the entire circumference of stiffener ring 4.

[0065] Therefore, it has been found that, according to this embodiment, it is possible to ensure adhesive strength capable of suppressing warpage deformation of the wiring board SUB1, and also to reduce the amount of adhesive layer BND used.

[0066] 4 overlaps with the diagonal line 2d1 or the diagonal line 2d2. When considering warpage deformation along each side of the rectangular top surface 2t, the amount of adhesive layer BND can be reduced by arranging the adhesive layer BND at a position overlapping with the diagonal line 2d1 or the diagonal line 2d2.

[0067] 4 has both the function of an adhesive layer BND for suppressing warpage deformation along the extension direction of the extending portion 4e1 and the function of an adhesive layer BND for suppressing warpage deformation along the extension direction of the extending portion 4e3. In this case, the amount of adhesive layer BND used can be reduced compared to the case where adhesive layers BND are arranged at three locations along the extension direction of the extending portion 4e1 and the extension direction of the extending portion 4e3.

[0068] 4, the following can be expressed from the viewpoint of the small amount of adhesive layer BND used: Adhesive layer BND1 extends in the X direction. The length L1 of adhesive layer BND1 in the X direction is shorter than the separation distance G15 between adhesive layer BND1 and adhesive layer BND5 in the X direction and the separation distance G16 between adhesive layer BND1 and adhesive layer BND6 in the X direction.

[0069] Furthermore, the length L2 of the adhesive layer BND2 in the X direction is shorter than the separation distance G27 between the adhesive layer BND2 and the adhesive layer BND7 in the X direction and the separation distance G28 between the adhesive layer BND2 and the adhesive layer BND8 in the X direction. Furthermore, the length L3 of the adhesive layer BND3 in the Y direction orthogonal to the X direction is shorter than the separation distance G35 between the adhesive layer BND3 and the adhesive layer BND5 in the Y direction and the separation distance G37 between the adhesive layer BND3 and the adhesive layer BND7 in the Y direction. Furthermore, the length L4 of the adhesive layer BND4 in the Y direction is shorter than the separation distance G46 between the adhesive layer BND4 and the adhesive layer BND6 in the Y direction and the separation distance G48 between the adhesive layer BND4 and the adhesive layer BND8 in the Y direction.

[0070] Furthermore, in the case of the example of this embodiment, from the viewpoint of the small amount of adhesive layer BND used, another expression can be made as follows. That is, the adhesive layer BND1 has a region R1 on the top surface 2t of the wiring board SUB1 that overlaps with the stiffener ring 4 in a plan view. Region R1 has a region R2 where the wiring board SUB1 and the stiffener ring 4 (see FIG. 1) face each other with a plurality of adhesive layers BND (see FIG. 4) interposed therebetween, and a region R3 where the wiring board SUB1 and the stiffener ring 4 face each other without the plurality of adhesive layers BND interposed therebetween. Of region R1, the area of ​​region R2 (more specifically, the total area of ​​the eight regions R2 shown in FIG. 6) is smaller than the area of ​​region R3. The area of ​​region R3 can be defined as the difference between the total area of ​​region R1 and the total area of ​​the plurality of regions R2.

[0071] In the present embodiment, the adhesive layer BND is disposed in eight locations that are particularly important from the viewpoint of suppressing warpage deformation of the wiring board SUB1, and therefore, as described above, the amount of adhesive layer BND used can be reduced. That is, according to this embodiment, the amount of adhesive layer BND used can be reduced, thereby suppressing the manufacturing cost of the semiconductor device PKG1. Alternatively, in the above-described method for manufacturing a semiconductor device, the following can be said from the viewpoint of preventing the residue of cleaning liquid used to remove flux components. That is, according to this embodiment, the cleaning liquid is discharged through a space where no adhesive layer BND is disposed (a space above region R3 shown in FIG. 6). This makes it possible to suppress the stagnation of cleaning liquid.

[0072] <Modification of adhesive layer layout> Next, a description will be given of a modified example of the layout of the adhesive layer BND shown in Fig. 4. Fig. 7 is a plan view showing a modified example of Fig. 4.

[0073] 7 differs from the semiconductor device PKG1 shown in Fig. 4 in the shape of the adhesive layers BND, among the plurality of adhesive layers BND, that are arranged at positions that overlap with the corners of the stiffener ring 4. More specifically, among the plurality of adhesive layers BND, adhesive layer BND5 arranged at a position that overlaps with corner 4c1 of the stiffener ring 4, adhesive layer BND6 arranged at a position that overlaps with corner 4c2 of the stiffener ring 4, adhesive layer BND7 arranged at a position that overlaps with corner 4c3 of the stiffener ring 4, and adhesive layer BND8 arranged at a position that overlaps with corner 4c4 of the stiffener ring 4 are each formed to have an L shape.

[0074] The adhesive layer BND5 has a portion positioned to overlap the corner 4c1 of the stiffener ring 4, a portion positioned to overlap the extension 4e1 connected to the corner 4c1, and a portion positioned to overlap the extension 4e3 connected to the corner 4c1.

[0075] Similarly, the adhesive layer BND6 has a portion positioned to overlap the corner 4c2 of the stiffener ring 4, a portion positioned to overlap the extension 4e1 connected to the corner 4c2, and a portion positioned to overlap the extension 4e4 connected to the corner 4c2.

[0076] Similarly, the adhesive layer BND7 has a portion positioned to overlap the corner 4c3 of the stiffener ring 4, a portion positioned to overlap the extension 4e2 connected to the corner 4c3, and a portion positioned to overlap the extension 4e3 connected to the corner 4c3.

[0077] Similarly, the adhesive layer BND8 has a portion positioned to overlap the corner 4c4 of the stiffener ring 4, a portion positioned to overlap the extension 4e2 connected to the corner 4c4, and a portion positioned to overlap the extension 4e4 connected to the corner 4c4.

[0078] In the modified example shown in Fig. 7, the areas of the adhesive layers BND arranged at positions overlapping the corners of the stiffener ring 4 that adhere to the wiring board SUB1 can be increased. In the example shown in Fig. 7, the contact areas of the adhesive layers BND5, BND6, BND7, and BND8 with the wiring board SUB1 are larger than the contact area of ​​the adhesive layer that has the largest contact area with the wiring board SUB1 among the adhesive layers BND1, BND2, BND3, and BND4. In the example shown in Fig. 7, the contact areas of the adhesive layers BND5, BND6, BND7, and BND8 with the wiring board SUB1 are equal to one another.

[0079] As explained using FIG. 5, the wiring board SUB1 deforms so that the height of its peripheral edge becomes lower than the height of the center of the top surface 2t. As a result, an external force acts on the peripheral edge of the wiring board SUB1 in a direction that increases the distance between the stiffener ring 4 and the wiring board SUB1. Each of the adhesive layers BND5, BND6, BND7, and BND8 shown in FIG. 7 is provided to resist the force that acts in a direction that increases the distance between the stiffener ring 4 and the wiring board SUB1. Increasing the adhesive strength of each of the adhesive layers BND5, BND6, BND7, and BND8 increases the effect of suppressing warpage.

[0080] In this modified example, the adhesive strength of each of the adhesive layers BND5, BND6, BND7, and BND8 is strengthened by increasing the area where each of the adhesive layers BND5, BND6, BND7, and BND8 adheres to the wiring board SUB1.

[0081] From the viewpoint of suppressing the stagnation of the cleaning liquid, the shapes of the adhesive layers BND5, BND6, BND7, and BND8 shown in FIG. 7 are more likely to cause stagnation of the cleaning liquid than the shapes of the adhesive layers BND5, BND6, BND7, and BND8 shown in FIG. 4.

[0082] Therefore, from the viewpoint of suppressing the accumulation of the cleaning liquid, it is preferable that the planar shape of each of the adhesive layers BND5, BND6, BND7, and BND8 is circular or elliptical, as shown in FIG.

[0083] Except for the above-mentioned differences, the semiconductor device PKG2 shown in Fig. 7 is the same as the semiconductor device PKG1 described with reference to Fig. 1 to Fig. 6. Therefore, a duplicated description will be omitted.

[0084] <Modification of stiffener ring shape> Next, modifications of the semiconductor device described with reference to Fig. 1 to Fig. 6 will be described. First, modifications of the stiffener ring shown in Fig. 1 will be described. Fig. 8 is a plan view showing a semiconductor device which is a modification of Fig. 1. Fig. 9 is an explanatory diagram of the semiconductor device shown in Fig. 8. Fig. 10 is a transparent plan view showing the adhesive layer between the stiffener ring and the wiring substrate through the stiffener ring shown in Fig. 8.

[0085] The semiconductor device PKG3 shown in FIGS. 8 to 10 differs from the semiconductor device PKG1 described with reference to FIGS. 1 to 6 in the following points.

[0086] As shown in Fig. 9, the stiffener ring 4A of the semiconductor device PKG3 differs from the stiffener ring 4 of the semiconductor device PKG1 shown in Fig. 3 in that it is thicker. In the example shown in Fig. 9, the thickness T4 of the stiffener ring 4A is larger than the thickness T2 of the wiring substrate SUB1. By increasing the thickness T4 of the stiffener ring 4A, the rigidity of the stiffener ring 4A can be improved. Increasing the rigidity of the stiffener ring 4A is preferable because the stiffener ring 4A itself is less likely to deform even if a strong external force is applied to the stiffener ring 4A.

[0087] However, even if the rigidity of the stiffener ring 4A is improved, if the stiffener ring 4A and the wiring board SUB1 are not firmly fixed together, it is not possible to prevent deformation of the wiring board SUB1. Therefore, even when a thick stiffener ring 4A like the stiffener ring 4A of this modified example is used, in order to prevent deformation of the wiring board SUB1, as already explained, it is necessary to arrange multiple adhesive layers BND in appropriate positions and ensure the adhesive strength between the stiffener ring 4A and the wiring board SUB1.

[0088] Note that the embodiment in which the stiffener ring is thicker than the wiring substrate is not limited to this modification. For example, as a modification of the stiffener ring 4 shown in Fig. 3, the stiffener ring 4 may be thicker than the wiring substrate SUB1 including the core insulating layer 2CR.

[0089] 8, in the semiconductor device PKG3, the stiffener ring 4A has a planar shape that is different from that of the stiffener ring 4 shown in Fig. 1. Specifically, the stiffener ring 4A has planar shapes of corners 4c1, 4c2, 4c3, and 4c4 that are different from those of the stiffener ring 4 shown in Fig. 1.

[0090] Corner portions 4c1, 4c2, 4c3, and 4c4 of stiffener ring 4A extend in directions intersecting the X and Y directions, respectively. The angle formed between the extension direction of corner portions 4c1, 4c2, 4c3, and 4c4 and the X direction is, for example, 45 degrees. Similarly, the angle formed between the extension direction of corner portions 4c1, 4c2, 4c3, and 4c4 and the Y direction is, for example, 45 degrees.

[0091] Although corners 4c1, 4c2, 4c3, and 4c4 extend in directions intersecting the X and Y directions, respectively, the extension distances of the corners are not long. For example, the extension distances of corners 4c1, 4c2, 4c3, and 4c4 are shorter than the extension distances of extension portions 4e1, 4e2, 4e3, and 4e4.

[0092] As shown in Fig. 8, the stiffener ring 4A formed so that each corner is inclined with respect to each of the X and Y directions may be called a tapered shape or a chamfered shape. In this case, each corner can be called a tapered portion or a chamfered portion.

[0093] In this modified example, as shown in Fig. 8, the exposed area of ​​the top surface 2t of the wiring substrate SUB1 is larger near each of the four corners 2c1, 2c2, 2c3, and 2c4 than in the example shown in Fig. 1. Identification marks used in the manufacturing process, etc., may be placed around the corners of the top surface 2t. Increasing the exposed area from the stiffener ring 4A around the corners of the top surface 2t as in this modified example can improve the visibility of the marks.

[0094] In addition, in the case of this modified example, since the four corners of the stiffener ring 4A are tapered, the planar shapes of the adhesive layers BND5, BND6, BND7, and BND8 shown in Figure 10 are different from those of the embodiment shown in Figure 4.

[0095] 10 , in a plan view, each of the adhesive layers BND5 and BND8 has a length BL1 in a direction intersecting the diagonal line 2d1 that is longer than a length BL2 in a direction along the diagonal line 2d1. Furthermore, each of the adhesive layers BND6 and BND7 has a length BL3 in a direction intersecting the diagonal line 2d2 that is longer than a length BL4 in a direction along the diagonal line 2d2. Increasing the lengths BL1 and BL3 increases the bonding area between the adhesive layer BND and the wiring substrate SUB1. Furthermore, in this modification, even if the lengths BL1 and BL3 are increased, each of the multiple adhesive layers BND can be prevented from protruding outside the position where it overlaps with the stiffener ring 4 in a plan view.

[0096] The layout of the adhesive layer BND in the semiconductor device PKG3 shown in FIG. 10 can be expressed as follows. That is, each of the adhesive layers BND5 and BND8 faces the semiconductor chip CHP1 in a plan view and has a long side LS1 extending in a direction intersecting the diagonal line 2d1. Each of the adhesive layers BND6 and BND7 faces the semiconductor chip CHP1 in a plan view and has a long side LS2 extending in a direction intersecting the diagonal line 2d2. In this case, compared to the shapes of the adhesive layers BND5, BND6, BND7, and BND8 shown in FIG. 7, the structure is less likely to cause the cleaning liquid to stagnate. Therefore, compared to the semiconductor device PKG2 described using FIG. 7, it can be said that the semiconductor device PKG3 of this modification has a structure that can prevent the cleaning liquid from stagnating.

[0097] Furthermore, the semiconductor device PKG3 shown in Figure 10 is similar to the semiconductor device PKG2 described using Figure 7 in that the multiple adhesive layers BND arranged at positions overlapping the corners of the stiffener ring 4A can increase the area of ​​adhesion to the wiring substrate SUB1.

[0098] That is, the contact area of ​​each of adhesive layers BND5, BND6, BND7, and BND8 with wiring board SUB1 is larger than the contact area of ​​the adhesive layer that has the largest contact area with wiring board SUB1 among adhesive layers BND1, BND2, BND3, and BND4. In the example shown in Fig. 10, the contact areas of adhesive layers BND5, BND6, BND7, and BND8 with wiring board SUB1 are equal to one another.

[0099] Fig. 11 is a transparent plan view showing a modification of Fig. 10. In the semiconductor device PKG4 shown in Fig. 11, the planar shapes of adhesive layers BND5, BND6, BND7, and BND8, which are arranged at the four corners of the stiffener ring 4A among the multiple adhesive layers BND, are different from those of the semiconductor device PKG3 shown in Fig. 10.

[0100] Specifically, in a plan view, each of the adhesive layers BND5, BND6, BND7, and BND8 is triangular. Note that, although each corner of the triangle is rounded as shown in Fig. 11, if the rounded portions are considered to be corners, the shape can be considered to be a triangle.

[0101] In the case of the semiconductor device PKG4, the contact areas of the adhesive layers BND5, BND6, BND7, and BND8 with the wiring board SUB1 are even larger than those of the semiconductor device PKG3 shown in FIG. 10. As described above, from the viewpoint of preventing warpage of the wiring board SUB1, it is effective to improve the adhesive strength between the stiffener ring 4A and the wiring board SUB1 at the corners of the stiffener ring 4A. Therefore, from the viewpoint of preventing warpage of the wiring board SUB1, the semiconductor device PKG4 is even more preferable than the semiconductor device PKG3.

[0102] On the other hand, from the viewpoint of reducing the amount of adhesive layer BND, the semiconductor device PKG3 shown in FIG. 10 is more preferable.

[0103] Except for the above-mentioned differences, the semiconductor device PKG3 shown in Figures 8 to 10 and the semiconductor device PKG4 shown in Figure 11 are the same as the semiconductor device PKG1 described with reference to Figures 1 to 6. Therefore, a duplicated description will be omitted.

[0104] <Other variations> Fig. 12 is a plan view showing another modified example of Fig. 1. In Fig. 12, the outlines of multiple adhesive layers BND arranged between the stiffener ring 4 and the wiring board SUB1 are shown by dotted lines. The semiconductor device PKG5 shown in Fig. 12 differs from the semiconductor device PKG1 shown in Fig. 1 in that a semiconductor chip CHP1 and an electronic component CD1 are mounted on the upper surface 2t of the wiring board SUB1.

[0105] More specifically, in a plan view, an electronic component CD1 mounted on a wiring substrate SUB1 is disposed between the semiconductor chip CHP1 and the stiffener ring 4. In the example shown in Fig. 12, a plurality of electronic components CD1 are mounted between the semiconductor chip CHP1 and the stiffener ring 4.

[0106] Each of the electronic components CD1 is a surface-mount chip component and is mounted on the wiring board SUB1 via solder. Each of the electronic components CD1 includes, for example, a capacitor, an inductor, or a resistor. In recent years, with the increasing sophistication of semiconductor devices, a plurality of electronic components CD1 are sometimes mounted on the top surface 2t of the wiring board SUB1 in addition to the semiconductor chip CHP1.

[0107] In this way, when the electronic component CD1 is mounted on the wiring board SUB1, the size of the upper surface 2t of the wiring board SUB1 may increase. When the size of the upper surface 2t increases, the above-mentioned warpage deformation becomes more likely to occur. This is because, as the distance from the center to the periphery of the upper surface 2t increases, the stress applied due to thermal effects increases.

[0108] The techniques already described using Figures 1 to 11, or the techniques related to the manufacturing method of a semiconductor device described below, are particularly effective when applied to semiconductor devices having wiring substrates with large upper surfaces 2t that are prone to warping deformation.

[0109] When the size of the top surface 2t increases, the size of the stiffener ring 4 also increases, and therefore the amount of adhesive layer BND used also increases when the adhesive layer BND is disposed around the entire periphery of the stiffener ring 4. As described above, according to the embodiment already described, the amount of adhesive layer BND used can be reduced and the occurrence of warpage deformation can be prevented, and therefore this is particularly effective when applied to semiconductor devices with a large size of the top surface 2t.

[0110] The semiconductor device PKG5 shown in Fig. 12 is similar to the semiconductor device PKG1 shown in Fig. 1 except for the above-mentioned differences. Therefore, a duplicated description will be omitted. However, although the semiconductor device PKG5 has been described as a modified example of the semiconductor device PKG1, it can be applied in combination with the semiconductor device PKG2 described using Fig. 7, the semiconductor device PKG3 described using Figs. 8 to 10, or the semiconductor device PKG4 described using Fig. 11.

[0111] <Method of manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device will be described. In the following, as a representative example, the method for manufacturing the semiconductor device PKG1 explained using Figures 1 to 6 will be mainly described, and then, in principle, only the differences will be described for modified examples. Figure 13 is an explanatory diagram showing an example of the flow of an assembly process for a semiconductor device according to one embodiment.

[0112] <Wiring board preparation process> In the wiring board preparation step shown in Fig. 13, the wiring board SUB1 shown in Fig. 4 is prepared. The wiring board SUB1 prepared in this step is formed with the components of the wiring board SUB1 described with reference to Figs. 1 to 3. However, at the stage of this step, the wiring board SUB1 is prepared before the semiconductor chip CHP1 and the stiffener ring 4 are mounted thereon.

[0113] Incidentally, in the wiring board preparation step, there is a case where a wiring board 20 is prepared, which is a so-called multi-cavity board provided with a plurality of device forming portions 21, as shown in Fig. 14. The wiring board 20 has a plurality of device forming portions 21 and a cut portion 22 surrounding each of the plurality of device forming portions 21. Fig. 14 is a plan view showing a modified example of the wiring board prepared in the wiring board preparation step shown in Fig. 13.

[0114] The following description will be given using an example of preparing the substrate SUB1 shown in FIGS. 1 to 6 in the wiring substrate preparation process. When preparing the substrate shown in FIG. 14 in this process, the following description of the sides and corners of the periphery of the top surface 2t can be interpreted as the sides and corners of the periphery of the device formation portion 21. That is, the top surface 2t of each of the multiple device formation portions 21 forms a quadrangle in a plan view. Although these are virtual lines rather than visible lines, the top surface 2t of each of the multiple device formation portions 21 includes a side 2s1, a side 2s2 opposite to the side 2s1, a side 2s3 intersecting with the sides 2s1 and 2s2, and a side 2s4 opposite to the side 2s3. Although they are imaginary points and not visible lines, the top surface 2t of each of the multiple device formation portions 21 has corner 2c1, which is the intersection of side 2s1 and side 2s3, corner 2c2, which is the intersection of side 2s1 and side 2s4, corner 2c3, which is the intersection of side 2s2 and side 2s3, and corner 2c4, which is the intersection of side 2s2 and side 2s4.

[0115] Furthermore, because the top surface 2t of the device formation unit 21 is a rectangle, two diagonal lines can be drawn, though they are not visible lines but virtual lines. That is, on the top surface 2t of the device formation unit 21, a diagonal line 2d1 can be drawn connecting the intersection (corner 2c1) of the side 2s1 and the side 2s3 and the intersection (corner 2c4) of the side 2s2 and the side 2s4. Also, on the top surface 2t, a diagonal line 2d2 can be drawn connecting the intersection (corner 2c2) of the side 2s1 and the side 2s4 and the intersection (corner 2c3) of the side 2s2 and the side 2s3. In the example shown in FIG. 1, the sides 2s1 and 2s2 are sides extending along the X direction, and the sides 2s3 and 2s4 are sides extending along the Y direction.

[0116] Similarly, because the top surface 2t of the device formation section 21 is rectangular, two center lines can be drawn, though they are not visible lines but imaginary lines, as shown in Fig. 14. That is, a center line 2CL1 can be drawn on the top surface 2t, connecting the center of the side 2s1 and the center of the side 2s2. Furthermore, a center line 2CL2 can be drawn on the top surface 2t of the device formation section 21, connecting the center of the side 2s3 and the center of the side 2s4.

[0117] <Semiconductor chip preparation process> 13, the semiconductor chip CHP1 shown in Figures 1, 3, and 4 is prepared. The structure of the semiconductor chip CHP1 has already been described, so a duplicated description will be omitted.

[0118] <Semiconductor chip mounting process> Next, in the semiconductor chip mounting process shown in FIG. 13, the semiconductor chip CHP1 is mounted on the upper surface 2t of the wiring board SUB1 as shown in FIG. 3. In the semiconductor chip mounting process, the semiconductor chip CHP1 is mounted on the wiring board SUB1 so that its surface 3t faces the upper surface 2t of the wiring board SUB1. Each of the electrodes 3PD of the semiconductor chip CHP1 is positioned to face each of the pads 2PD of the wiring board SUB1. After the semiconductor chip CHP1 is placed on the wiring board SUB1, a reflow process is performed, thereby electrically connecting the electrodes 3PD and the pads 2PD via the protruding electrodes 3BP. This type of connection method is called a flip-chip connection method, and the semiconductor chip mounting process of this embodiment is called a face-down mounting method in which the surface 3t of the semiconductor chip CHP1 faces the upper surface 2t of the wiring board SUB1.

[0119] When multiple electronic components CD1 are mounted on the upper surface 2t of the wiring board SUB1, as in the semiconductor device PKG5 described with reference to Fig. 12, an electronic component mounting step is performed to mount the multiple electronic components CD1 on the upper surface 2t of the wiring board SUB1. Each of the multiple electronic components CD1 shown in Fig. 12 is electrically connected to a terminal (not shown) of the wiring board SUB1 via, for example, a solder material. In this case, the reflow treatment of the semiconductor chip CHP1 and the reflow treatment of the multiple electronic components CD1 can be performed simultaneously.

[0120] Although not shown in Figure 13, if the protruding electrode 3BP shown in Figure 3 or the solder material (not shown) for mounting the electronic component CD1 contains a flux component that activates the solder component, a cleaning process may be carried out after the reflow process to remove any residue of the flux component.

[0121] <Sealing process> Next, in the sealing step shown in FIG. 13, as shown in FIG. 4, underfill resin UF is supplied between the semiconductor chip CHP1 and the wiring board SUB1, and the plurality of protruding electrodes 3BP are sealed in a state in which they are insulated from one another.

[0122] <Stiffener ring installation process> Next, in the stiffener ring mounting step shown in Fig. 13, the stiffener ring 4 is mounted on the upper surface 2t of the wiring board SUB1 as shown in Fig. 1, Fig. 3, and Fig. 4. As shown in Fig. 13, the stiffener ring mounting step includes an adhesive application step, a stiffener ring bonding step, and an adhesive application step.

[0123] Fig. 15 is a plan view showing a state in which adhesive has been applied onto the wiring board in the adhesive application step shown in Fig. 13. In the adhesive application step, as shown in Fig. 15, adhesive bnd is applied to a plurality of locations in region R1 of the top surface 2t, which is the region where the stiffener ring 4 (see Fig. 1) is to be mounted.

[0124] Of the upper surface of the wiring board SUB1, region R1 includes an extending portion R11 extending along side 2s1, an extending portion R12 extending along side 2s2, an extending portion R13 extending along side 2s3, and an extending portion R14 extending along side 2s4. Region R1 also includes a corner R15 connected between extending portion R11 and extending portion R13, a corner R16 connected between extending portion R11 and extending portion R14, a corner R17 connected between extending portion R12 and extending portion R13, and a corner R18 connected between extending portion R12 and extending portion R14.

[0125] 1, corners R15 and R18 overlap with diagonal line 2d1 in plan view. Also, when diagonal line 2d2 is drawn, corners R16 and R17 overlap with diagonal line 2d2.

[0126] In addition, in the adhesive application process, the multiple adhesives bnd applied to region R1 so as to be spaced apart from each other include adhesive bnd1 arranged at a position overlapping extension portion R11 and also arranged at a position overlapping center line 2CL1, adhesive bnd2 arranged at a position overlapping extension portion R12 and also arranged at a position overlapping center line 2CL1, adhesive bnd3 arranged at a position overlapping extension portion R13 and also arranged at a position overlapping center line 2CL2, and adhesive bnd4 arranged at a position overlapping extension portion R14 and also arranged at a position overlapping center line 2CL2.

[0127] The multiple adhesives bnd include adhesive bnd5 arranged at a position overlapping corner R15 and also arranged at a position overlapping diagonal line 2d1, adhesive bnd6 arranged at a position overlapping corner R16 and also arranged at a position overlapping diagonal line 2d2, adhesive bnd7 arranged at a position overlapping corner R17 and also arranged at a position overlapping diagonal line 2d2, and adhesive bnd8 arranged at a position overlapping corner R18 and also arranged at a position overlapping diagonal line 2d1.

[0128] 15, the following can be expressed from the perspective of the small amount of adhesive bnd used: adhesive bnd1 extends in the X direction. The length L1 of adhesive bnd1 in the X direction is shorter than the separation distance G15 between adhesive bnd1 and adhesive bnd5 in the X direction and the separation distance G16 between adhesive bnd1 and adhesive bnd6 in the X direction.

[0129] Furthermore, the length L2 of adhesive bnd2 in the X direction is shorter than the separation distance G27 between adhesive bnd2 and adhesive bnd7 in the X direction and the separation distance G28 between adhesive bnd2 and adhesive bnd8 in the X direction. Furthermore, the length L3 of adhesive bnd3 in the Y direction, which is perpendicular to the X direction, is shorter than the separation distance G35 between adhesive bnd3 and adhesive bnd5 in the Y direction and the separation distance G37 between adhesive bnd3 and adhesive bnd7 in the Y direction. Furthermore, the length L4 of adhesive bnd4 in the Y direction is shorter than the separation distance G46 between adhesive bnd4 and adhesive bnd6 in the Y direction and the separation distance G48 between adhesive bnd4 and adhesive bnd8 in the Y direction.

[0130] Furthermore, in the case of the example of this embodiment, the amount of adhesive bnd used can be expressed as follows in terms of the small amount of adhesive bnd used. That is, in region R1, the area of ​​the region to which the multiple adhesive bnds are applied in the adhesive application step is smaller than the area of ​​the region to which the multiple adhesive bnds are not applied. Note that regions R2 and R3 described using FIG. 6 each indicate the region after the stiffening bonding step and the adhesive curing step shown in FIG. 13 are completed. Therefore, the area of ​​the region to which the multiple adhesive bnds are applied in the adhesive application step is even smaller than region R2 shown in FIG. 6. Furthermore, the area of ​​the region to which the multiple adhesive bnds are not applied is even larger than region R3 shown in FIG. 6.

[0131] Next, in the stiffener ring bonding step shown in Fig. 13, the stiffener ring 4 (see Fig. 1) is placed on the region R1 shown in Fig. 15, and the stiffener ring 4 is bonded via a plurality of adhesive layers bnd. In this step, each of the plurality of adhesive layers bnd applied to the region R1 is sandwiched between the lower surface of the stiffener ring 4 and the upper surface 2t of the wiring substrate SUB1 and spread out to the periphery. As a result, the shape of the plurality of adhesive layers bnd takes on the shape of the plurality of adhesive layers BND shown in Fig. 4.

[0132] Next, in the adhesive curing step shown in FIG. 13, the adhesive bnd (see FIG. 15) is cured to form a plurality of spaced-apart adhesive layers BND (see FIG. 4). This step fixes the stiffener ring 4 (see FIG. 1) onto the wiring board SUB1. Each of the plurality of adhesives bnd shown in FIG. 15 is, for example, an organic adhesive containing a silicone-based thermosetting resin component. In this case, in the adhesive curing step, the wiring board SUB1 to which the stiffener ring 4 (see FIG. 1) is adhered is placed in a heating furnace (not shown) and heated (cure baked), thereby hardening each of the plurality of adhesives bnd. Each of the plurality of adhesives bnd may be an organic adhesive containing an epoxy-based thermosetting resin component. Here, epoxy-based organic adhesives are harder than silicone-based organic adhesives. Therefore, compared to using a silicone-based organic adhesive, the stiffener ring 4 can be fixed more firmly to the wiring board SUB1, thereby further suppressing warpage of the wiring board SUB1.

[0133] <Solder ball formation process> Next, in the solder ball forming step shown in FIG. 13, a plurality of solder balls SB are formed on the lower surface 2b of the wiring board SUB1 as shown in FIG.

[0134] In this process, multiple solder balls SB (see FIGS. 2 and 4) are bonded to multiple lands 2LD formed on the underside of the wiring board SUB1 shown in FIG. 3. After placing solder material on each of the multiple lands 2LD exposed on the underside of the wiring board SUB1, a reflow process is performed. The solder material contains, for example, a flux component that can improve the activity of the solder. When the solder material applied to the lands 2LD is heated, the flux component that seeps out from the solder material activates the surface of the solder material, allowing the solder material to be bonded to the lands 2LD. Furthermore, the surface tension of the solder material causes the solder material to be formed into a ball shape, resulting in multiple solder balls SB as shown in FIG. 2.

[0135] The flux components contained in the solder material may remain as residue around the solder balls SB after the reflow process. In this case, it is preferable to remove the flux component residue by performing the cleaning step shown in FIG.

[0136] <Cleaning process> Next, the wiring board SUB1 is cleaned in the cleaning process shown in FIG. 13. In the cleaning process, a cleaning liquid is sprayed onto the wiring board SUB1 to remove flux and other substances adhering to the wiring board SUB1 or the solder balls SB. At this time, even if the cleaning liquid is sprayed onto the lower surface 2b of the wiring board SUB1 shown in FIG. 3, there is a possibility that the cleaning liquid will find its way onto the upper surface 2t of the wiring board SUB1. Also, as shown in FIG. 1, the upper surface 2t of the wiring board SUB1 is exposed in the space inside the stiffener ring 4. Therefore, there is a possibility that the cleaning liquid will adhere to the space surrounded by the stiffener ring 4. If the cleaning liquid remains, there is a possibility that electrical malfunctions will occur. For this reason, it is preferable to completely remove any cleaning liquid adhering to the wiring board SUB1 during the cleaning process.

[0137] <Cleaning solution removal process> 13, the cleaning liquid that has adhered to the wiring substrate SUB1 in the above-described cleaning process is removed. As described above, in the cleaning process, there is a possibility that the cleaning liquid will adhere to the space surrounded by the stiffener ring 4 shown in FIG.

[0138] However, in the present embodiment, the plurality of adhesive layers BND are arranged spaced apart from one another, so that the cleaning liquid can be removed from the gaps between adjacent adhesive layers BND. Therefore, compared to the studied example in which adhesive layers BND are arranged around the entire periphery of the stiffener ring 4, the cleaning liquid is easier to remove.

[0139] In the cleaning liquid removal step, the method for removing the cleaning liquid is not particularly limited, but examples thereof include a method of blowing air (hot or cold air) onto the wiring substrate SUB1, a method of rotating the wiring substrate SUB1 to dissipate the cleaning liquid by centrifugal force, or a method of allowing it to dry naturally.

[0140] 7, there is a possibility that the cleaning liquid will accumulate on the inner surfaces (surfaces facing the semiconductor chip CHP1) of the L-shaped adhesive layers BND5, BND6, BND7, and BND8. However, in the cases of each embodiment other than the semiconductor device PKG2, the structure is such that it is easy to prevent the cleaning liquid from accumulating.

[0141] The cleaning liquid removal step can be considered as part of the cleaning step shown in FIG.

[0142] <Singulation process> When using the wiring substrate 20 described with reference to FIG. 14, a singulation step is performed after the cleaning step (more specifically, after the cleaning liquid removal step), as indicated by the dotted lines in FIG. 13. In the singulation step, the wiring substrate 20 is cut along the cutting portions 22 shown in FIG. 14 to separate the plurality of device forming portions 21. The cutting method is not particularly limited, and an example is a method of cutting the wiring substrate 20 by cutting using a dicing blade (not shown). Note that if the wiring substrate SUB1 shown in FIGS. 1 to 6 is prepared in the wiring substrate preparation step shown in FIG. 13, the singulation step can be omitted. This is because the wiring substrate SUB1 shown in FIGS. 1 to 6 corresponds to one device forming portion 21 shown in FIG. 14.

[0143] <Modification of adhesive application process> Next, a modified example of the adhesive application step described with reference to Fig. 15 will be described. In the respective manufacturing methods of the semiconductor device PKG2 shown in Fig. 7, the semiconductor device PKG3 shown in Fig. 10, and the semiconductor device PKG4 shown in Fig. 11, the shape of the adhesive applied in the adhesive application step is different. However, in all cases, the area of ​​the adhesive in a plan view is smaller than the area of ​​the adhesive layer BND shown in Fig. 7, Fig. 10, or Fig. 11. This is because, in each of the manufacturing methods of the semiconductor device, in the stiffener bonding step described above, the adhesive is sandwiched between the stiffener and the wiring substrate and spread out.

[0144] For example, in the manufacturing method of the semiconductor device PKG3 shown in Fig. 10, a plurality of adhesives bnd are applied as shown in Fig. 16. Fig. 16 is a plan view showing a modification of Fig. 15. In the example shown in Fig. 16, the length BL1 of each of the adhesives bnd5 and bnd8 applied in the adhesive application step in a direction intersecting the diagonal line 2d1 is longer than the length BL2 of each of the adhesives bnd6 and bnd7 applied in the adhesive application step in a direction intersecting the second diagonal line is longer than the length of each of the adhesives bnd6 and bnd7 in a direction intersecting the second diagonal line.

[0145] 16, in the adhesive application step, the multiple adhesives bnd are applied as follows: Adhesives bnd1 and bnd2 are each applied so as to extend in the X direction; Adhesives bnd3 and bnd4 are each applied so as to extend in the Y direction that intersects with the X direction; Adhesives bnd5 and bnd8 are each applied so as to extend in a direction that intersects with the diagonal line 2d1; and Adhesives bnd6 and bnd7 are each applied so as to extend in a direction that intersects with the diagonal line 2d2.

[0146] In addition, in the example shown in FIG. 16, the application area of ​​each of adhesives bnd5, bnd6, bnd7, and bnd8 is larger than the application area of ​​the adhesive with the largest application area among adhesives bnd1, bnd2, bnd3, and bnd4.

[0147] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0148] 3, the thickness of the stiffener ring 4 may be smaller than not only the thickness T2 of the wiring board SUB1 but also the thickness of the core insulating layer 2CR that constitutes the wiring board SUB1. However, in order to more reliably prevent warpage deformation of the wiring board SUB1, it is preferable to use a stiffener ring whose rigidity is improved by increasing the thickness of the adhesive layers BND in addition to arranging them at appropriate positions. [Explanation of symbols]

[0149] 2b,2Cb Bottom surface 2c1,2c2,2c3,2c4 angle 2CL1,2CL2 Center line 2CP conductor pattern 2CR Core insulation layer (insulation layer, core material, core insulation layer) 2Ct,2t top surface 2D wiring 2d1,2d2 diagonals 2e insulating layer 2LD Land 2PD pad (terminal) 2s1, 2s2, 2s3, 2s4 sides 2THW through-hole wiring 2v via wiring 3b Back side (main side, bottom side) 3BP protruding electrode (bump electrode) 3PD electrodes (pads, electrode pads, bonding pads) 3t surface (main surface, top surface) 4,4A Stiffening 4c1,4c2,4c3,4c4,R15,R16,R17,R18 Corner 4e1,4e2,4e3,4e4,R11,R12,R13,R14 Extension part 20,SUB1 wiring board 21 Device Formation Department 22 Cut section BL1, BL2, BL3, BL4, L1, L2, L3, L4 length bnd,bnd1,bnd2,bnd3,bnd4,bnd5,bnd6,bnd7,bnd8 adhesive BND,BND1,BND2,BND3,BND4,BND5,BND6,BND7,BND8 Adhesive layer CD1 Electronic Components CHP1 semiconductor chip G15,G16,G27,G28,G35,G37,G46,G48 Separation distance LS1, LS2 long side PKG1, PKG2, PKG3, PKG4, PKG5 Semiconductor device R1,R2,R3 area SB solder ball (solder material, external terminal, electrode, external electrode) SR1, SR2 insulating film T2, T4 thickness UF underfill resin (insulating resin) WL1,WL2,WL3,WL4,WL5,WL6,WL7,WL8 wiring layers

Claims

1. a wiring substrate having an upper surface and a lower surface opposite to the upper surface; a semiconductor chip mounted on the upper surface of the wiring substrate; a stiffener ring fixed to the upper surface of the wiring board; Including, the top surface includes a first side, a second side opposite to the first side, a third side intersecting the first side and the second side, and a fourth side opposite to the third side; In a plan view, the stiffener ring is arranged so as to continuously surround the periphery of the semiconductor chip, and includes a first extending portion extending along the first side, a second extending portion extending along the second side, a third extending portion extending along the third side, a fourth extending portion extending along the fourth side, a first corner portion connected to the first extending portion and the third extending portion, a second corner portion connected to the first extending portion and the fourth extending portion, a third corner portion connected to the second extending portion and the third extending portion, and a fourth corner portion connected to the second extending portion and the fourth extending portion, when a first diagonal line is drawn connecting an intersection point between the first side and the third side and an intersection point between the second side and the fourth side, the first corner and the fourth corner overlap with the first diagonal line, when a second diagonal line is drawn connecting an intersection point between the first side and the fourth side and an intersection point between the second side and the third side, the second corner portion and the third corner portion overlap with the second diagonal line, the stiffener ring is fixed to the upper surface of the wiring substrate via a plurality of adhesive layers disposed between the stiffener ring and the upper surface of the wiring substrate and spaced apart from one another; The plurality of adhesive layers are a first adhesive layer that is arranged at a position overlapping the first extension portion and that is arranged at a position overlapping with a first center line that connects a center of the first side and a center of the second side; a second adhesive layer disposed at a position overlapping the second extension portion and at a position overlapping the first center line when the first center line is drawn; a third adhesive layer that is arranged at a position overlapping the third extension portion and that is arranged at a position overlapping with a second center line that connects the center of the third side and the center of the fourth side; a fourth adhesive layer disposed at a position overlapping the fourth extension portion and at a position overlapping the second center line when the second center line is drawn; a fifth adhesive layer disposed at a position overlapping the first corner portion and at a position overlapping the first diagonal line when the first diagonal line is drawn; a sixth adhesive layer disposed at a position overlapping the second corner portion and at a position overlapping the second diagonal line when the second diagonal line is drawn; a seventh adhesive layer disposed at a position overlapping the third corner portion and at a position overlapping the second diagonal line when the second diagonal line is drawn; an eighth adhesive layer disposed at a position overlapping the fourth corner portion and at a position overlapping the first diagonal line when the first diagonal line is drawn; The semiconductor device includes:

2. In claim 1, The thickness of the stiffener ring is greater than the thickness of the wiring substrate.

3. In claim 1, each of the fifth adhesive layer and the eighth adhesive layer has a length in a direction intersecting the first diagonal line longer than a length in a direction along the first diagonal line in a plan view; The sixth adhesive layer and the seventh adhesive layer each have a length in a direction intersecting the second diagonal that is longer than a length in a direction along the second diagonal.

4. In claim 1, the first adhesive layer extends in a first direction; A semiconductor device, wherein the length of the first adhesive layer in the first direction is shorter than the distance between the first adhesive layer and the fifth adhesive layer in the first direction and the distance between the first adhesive layer and the sixth adhesive layer in the first direction.

5. In claim 4, a length of the second adhesive layer in the first direction is shorter than a distance between the second adhesive layer and the seventh adhesive layer in the first direction and a distance between the second adhesive layer and the eighth adhesive layer in the first direction; a length of the third adhesive layer in a second direction perpendicular to the first direction is shorter than a distance between the third adhesive layer and the fifth adhesive layer in the second direction and a distance between the third adhesive layer and the seventh adhesive layer in the second direction; A semiconductor device, wherein the length of the fourth adhesive layer in the second direction is shorter than the distance between the fourth adhesive layer and the sixth adhesive layer in the second direction and the distance between the fourth adhesive layer and the eighth adhesive layer in the second direction.

6. In claim 1, the upper surface of the wiring substrate has a first region that overlaps with the stiffener ring in a plan view; a second region of the first region, in which the wiring substrate and the stiffener ring face each other via the plurality of adhesive layers, has an area smaller than a third region of the first region, in which the wiring substrate and the stiffener ring face each other without the plurality of adhesive layers therebetween.

7. In claim 1, A semiconductor device, wherein the contact area of ​​each of the fifth adhesive layer, the sixth adhesive layer, the seventh adhesive layer, and the eighth adhesive layer with the wiring substrate is larger than the contact area of ​​the adhesive layer among the first adhesive layer, the second adhesive layer, the third adhesive layer, and the fourth adhesive layer that has the largest contact area with the wiring substrate.

8. In claim 1, each of the fifth adhesive layer and the eighth adhesive layer faces the semiconductor chip in a plan view and has a long side extending in a direction intersecting the first diagonal line; A semiconductor device, wherein each of the sixth adhesive layer and the seventh adhesive layer faces the semiconductor chip in a planar view and has a long side extending in a direction intersecting the second diagonal line.

9. In claim 1, The semiconductor chip has a first surface, a plurality of protruding electrodes formed on the first surface, and a second surface opposite the first surface, and is mounted on the wiring board via the plurality of protruding electrodes so that the first surface faces the top surface of the wiring board.

10. In claim 1, A semiconductor device, wherein a plurality of solder balls are formed on the lower surface of the wiring substrate.

11. In claim 1, In a plan view, an electronic component mounted on the wiring substrate is disposed between the semiconductor chip and the stiffener ring.

12. (a) mounting a semiconductor chip on an upper surface of a wiring substrate; (b) mounting a stiffener ring on the top surface of the wiring substrate; and The step (b) comprises: (b1) applying adhesive to a plurality of locations in a first region of the upper surface, the first region being a region where the stiffener ring is to be mounted; (b2) placing the stiffener ring on the first region and adhering the stiffener ring via the adhesive; (b3) curing the adhesive to form a plurality of spaced-apart adhesive layers to secure the stiffener ring to the wiring substrate; Including, the top surface of the wiring substrate includes a first side, a second side opposite to the first side, a third side intersecting the first side and the second side, and a fourth side opposite to the third side; The first region of the upper surface of the wiring substrate continuously surrounds a periphery of a region on which the semiconductor chip is mounted, and the first region includes a first extending portion extending along the first side, a second extending portion extending along the second side, a third extending portion extending along the third side, a fourth extending portion extending along the fourth side, a first corner portion connected to the first extending portion and the third extending portion, a second corner portion connected to the first extending portion and the fourth extending portion, a third corner portion connected to the second extending portion and the third extending portion, and a fourth corner portion connected to the second extending portion and the fourth extending portion, when a first diagonal line is drawn connecting an intersection point between the first side and the third side and an intersection point between the second side and the fourth side, the first corner and the fourth corner overlap with the first diagonal line, when a second diagonal line is drawn connecting an intersection point between the first side and the fourth side and an intersection point between the second side and the third side, the second corner portion and the third corner portion overlap with the second diagonal line, In the step (b1), the adhesives applied to the first region so as to be spaced apart from each other are a first adhesive disposed at a position overlapping the first extension portion and, when a first center line is drawn connecting a center of the first side and a center of the second side, disposed at a position overlapping the first center line; a second adhesive disposed at a position overlapping the second extension portion and at a position overlapping the first center line when the first center line is drawn; a third adhesive disposed at a position overlapping the third extension portion and, when a second center line is drawn connecting the center of the third side and the center of the fourth side, at a position overlapping the second center line; a fourth adhesive disposed at a position overlapping the fourth extension portion and at a position overlapping the second center line when the second center line is drawn; a fifth adhesive disposed at a position overlapping the first corner portion and at a position overlapping the first diagonal line when the first diagonal line is drawn; a sixth adhesive disposed at a position overlapping the second corner portion and at a position overlapping the second diagonal line when the second diagonal line is drawn; a seventh adhesive disposed at a position overlapping the third corner portion and at a position overlapping the second diagonal line when the second diagonal line is drawn; an eighth adhesive disposed at a position overlapping the fourth corner portion and at a position overlapping the first diagonal line when the first diagonal line is drawn; A method for manufacturing a semiconductor device, comprising:

13. In claim 12, A method for manufacturing a semiconductor device, wherein the stiffener ring has a thickness greater than a thickness of the wiring substrate.

14. In claim 12, each of the fifth adhesive and the eighth adhesive applied in the step (b1) has a length in a direction intersecting the first diagonal line longer than a length in a direction along the first diagonal line in a plan view; A method for manufacturing a semiconductor device, wherein the sixth adhesive and the seventh adhesive applied in step (b1) each have a length in a direction intersecting the second diagonal that is longer than the length in a direction along the second diagonal.

15. In claim 12, the first adhesive applied in the step (b1) extends in a first direction, a method for manufacturing a semiconductor device, wherein after the step (b1), the length of the first adhesive in the first direction is shorter than the distance between the first adhesive and the fifth adhesive in the first direction and the distance between the first adhesive and the sixth adhesive in the first direction.

16. In claim 15, After the step (b1), a length of the second adhesive in the first direction is shorter than a distance between the second adhesive and the seventh adhesive in the first direction and a distance between the second adhesive and the eighth adhesive in the first direction; a length of the third adhesive in a second direction perpendicular to the first direction is shorter than a distance between the third adhesive and the fifth adhesive in the second direction and a distance between the third adhesive and the seventh adhesive in the second direction; A method for manufacturing a semiconductor device, wherein the length of the fourth adhesive in the second direction is shorter than the distance between the fourth adhesive and the sixth adhesive in the second direction and the distance between the fourth adhesive and the eighth adhesive in the second direction.

17. In claim 12, A method for manufacturing a semiconductor device, wherein an area of ​​the first region to which the adhesive is applied in the step (b1) is smaller than an area of ​​a region to which the adhesive is not applied in the step (b1).

18. In claim 12, A method for manufacturing a semiconductor device, wherein the application area of ​​each of the fifth adhesive, the sixth adhesive, the seventh adhesive, and the eighth adhesive is larger than the application area of ​​the adhesive with the largest application area among the first adhesive, the second adhesive, the third adhesive, and the fourth adhesive.

19. In claim 12, In the step (b1), each of the first adhesive and the second adhesive is applied so as to extend in a first direction; the third adhesive and the fourth adhesive are applied so as to extend in a second direction intersecting the first direction, the fifth adhesive and the eighth adhesive are applied so as to extend in a direction intersecting the first diagonal line, the sixth adhesive and the seventh adhesive are applied so as to extend in a direction intersecting the second diagonal line.

20. In claim 12, (c) after the step (b), forming a plurality of solder balls on a lower surface of the wiring substrate opposite to the upper surface; (d) after the step (c), cleaning the wiring substrate.

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