Frequency monitoring device and frequency monitoring method

Abstract

To provide a frequency monitoring device and a frequency monitoring method for further improving the detection accuracy of an overfrequency in an AC fundamental wave frequency.SOLUTION: The frequency monitoring device includes a frequency detection unit, a frequency / period conversion unit, a filter unit, a period / frequency conversion unit, and an overfrequency detection unit. The frequency detection unit calculates a first estimated frequency of the AC component within a predetermined period. The frequency period conversion unit calculates a period by a reciprocal operation on the first estimated frequency. The filter unit calculates a value in which the fluctuation of the period is reduced. The period frequency conversion unit calculates a second estimated frequency by a reciprocal operation on a value obtained by reducing the variation of the period. The overfrequency detection unit determines the second estimated frequency on the basis of a predetermined determination criterion defined to detect an overfrequency.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a frequency monitoring device and a frequency monitoring method. [Background technology]

[0002] There are frequency monitoring devices that evaluate the quality of AC power and monitor the operating status of drive devices using the actually detected fundamental frequency of AC voltage. There has been a demand for improved detection accuracy of over-frequency in the fundamental frequency of AC. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6270987 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a frequency monitoring device and a frequency monitoring method that improve the accuracy of detecting over-frequency in the fundamental frequency of AC. [Means for solving the problem]

[0005] A frequency monitoring device according to an embodiment includes a frequency detection unit, a frequency-period conversion unit, a filter unit, a period-frequency conversion unit, and an over-frequency detection unit. The frequency detection unit calculates a first estimated frequency of an AC component within a predetermined period. The frequency-period conversion unit calculates the period by performing an inverse operation on the first estimated frequency. The filter unit calculates a value obtained by reducing fluctuations in the period. The period-frequency conversion unit calculates a second estimated frequency by performing an inverse operation on the value obtained by reducing fluctuations in the period. The over-frequency detection unit determines the second estimated frequency based on predetermined criteria established to detect over-frequency. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of a drive system according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating the function of a filter circuit according to an embodiment. [Figure 3] FIG. 2 is a configuration diagram of a frequency detection unit according to the embodiment. [Figure 4] FIG. 2 is a diagram for explaining frequency estimation according to the embodiment. [Figure 5A] 10A and 10B are diagrams for explaining frequency detection when there is an influence of waveform distortion according to the embodiment. [Figure 5B] FIG. 10 is a diagram for explaining frequency detection when there is an influence of waveform distortion according to a comparative example. [Figure 6] 5A and 5B are diagrams for explaining frequency detection values ​​based on the time constant of a filter according to the embodiment. [Figure 7] FIG. 2 is a diagram for explaining frequency detection according to the embodiment. [Figure 8] FIG. 10 is a configuration diagram of a drive system according to a second embodiment. [Figure 9] FIG. 10 is a diagram for explaining frequency estimation according to the second embodiment. [Figure 10] FIG. 10 is a diagram for explaining frequency estimation according to a modified example of the second embodiment. [Figure 11] FIG. 2 is a diagram for explaining an example of the configuration of a frequency monitoring device according to each embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a frequency monitoring device and a frequency monitoring method according to an embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Duplicate descriptions of those components may be omitted. Electrical connection may simply be referred to as "connected."

[0008] (First embodiment) 1 is a diagram showing the configuration of a drive system 10 according to the first embodiment. Note that the same parts are given the same reference numerals, and redundant explanations will be omitted where appropriate, with differences being mainly described below.

[0009] The drive system 10 includes a frequency monitoring device 1, an inverter device 2, an electric motor 3, and a DC power supply 4. For example, the drive system 10 is a speed sensorless drive system in which a speed sensor cannot be attached.

[0010] The DC power supply 4 is connected to the inverter device 2. The DC power supply 4 supplies DC power to the inverter device 2. The DC power supply 4 may be any device that outputs DC power, such as a generator, a battery, or a power conversion device.

[0011] The inverter device 2 is a power conversion device that converts DC power supplied from a DC power source 4 into three-phase AC power. An electric motor 3 is connected to the AC side of the inverter device 2. The inverter device 2 controls the driving of the electric motor 3 by outputting the converted AC power to the electric motor 3. The inverter device 2 performs VVVF (variable voltage variable frequency) control to maintain a constant V / F (voltage / frequency) ratio of the electric motor 3. The V / F ratio is the ratio between voltage and frequency for maintaining a constant magnetic flux of the electric motor 3. In the following explanation, a case where the frequency is fixed may be exemplified for simplicity, but the present invention is not limited to this.

[0012] The frequency monitoring device 1 is a device configured with hardware independent of, for example, the inverter device 2 and the electric motor 3. The frequency monitoring device 1 is connected to an electrical path through which AC power is supplied from the inverter device 2 to the electric motor 3 by wiring that takes in the inter-phase voltage of the three-phase AC voltage output from the inverter device 2. The frequency monitoring device 1 is connected to a control device 8 of the inverter device 2 by a transmission path that transmits information. The frequency monitoring device 1 detects the inter-phase voltage output from the inverter device 2 and monitors the state of the inverter device 2. Note that the frequency monitoring device 1 may also monitor the state of the inverter device 2 by detecting the inter-phase voltage output from the inverter device 2 and transmitting and receiving information to and from the control device 8.

[0013] The inverter device 2 includes an inverter circuit 7 and a control device 8.

[0014] The inverter circuit 7 is an electric circuit that converts DC power supplied from the DC power supply 4 into three-phase AC power. The inverter circuit 7 is composed of semiconductor elements such as switching elements. The inverter circuit 7 performs power conversion by being controlled by PWM (pulse width modulation).

[0015] The control device 8 is a device built into the inverter device 2. The control device 8 receives various information and controls the drive system 10. The control device 8 mainly drives the electric motor 3 by controlling the AC power output from the inverter circuit 7. Specifically, the control device 8 outputs a gate signal to drive the switching elements of the inverter circuit 7, thereby controlling the AC power output from the inverter circuit 7. In this way, the electric motor 3 is driven.

[0016] The control device 8 includes an operation sequence execution unit 31, a motor control unit 32, and a gate block command unit .

[0017] The operation sequence execution unit 31 receives information ascertaining the states of the electric motor 3 and the inverter circuit 7, and a fault signal NG detected by the frequency monitoring device 1, from the electric motor control unit 32. Based on this received information, the operation sequence execution unit 31 determines the control to be performed on the inverter circuit 7 and the electric motor 3 in accordance with a predetermined operation sequence. The operation sequence execution unit 31 outputs various information to the electric motor control unit 32 in order to execute the control determined by the operation sequence. When the operation sequence execution unit 31 receives a fault signal NG from the frequency monitoring device 1, it performs control to limit or stop the operation of the inverter circuit 7 and the electric motor 3 in accordance with the operation sequence.

[0018] The motor control unit 32 receives information such as voltage or current from various sensors provided in the inverter circuit 7 or the electric motor 3, and determines the state of the inverter circuit 7 or the electric motor 3. In order to execute the control determined by the operation sequence execution unit 31, the motor control unit 32 controls the output power of the inverter circuit 7 based on the determined state to drive the electric motor 3. The motor control unit 32 outputs information required for the operation sequence of the operation sequence execution unit 31 to the operation sequence execution unit 31.

[0019] When the gate block command unit 34 receives the fault signal NG detected by the frequency monitoring device 1, it gate blocks the switching elements of the inverter circuit 7. As a result, the conversion operation of the inverter circuit 7 stops.

[0020] The frequency monitoring device 1 includes a voltage detector 5 and a monitoring circuit 6 .

[0021] The voltage detector 5 detects, for example, a voltage between two of the three phases of the AC voltage output from the inverter device 2 (inter-phase voltage), and outputs the detected voltage to the monitoring circuit 6. The voltage detector 5 includes a filter circuit 11 and an insulating circuit 12.

[0022] FIG. 2 is a schematic diagram showing the function of the filter circuit 11. The filter circuit 11 shapes a square-wave voltage into a sine-wave voltage. The voltage waveform output from the PWM-controlled inverter circuit 7 is a single-pulse or multi-pulse square wave. The waveform shown here is an example, and the voltage waveform may be a waveform output from a two-level, three-level, or five-level inverter device 2. By passing the output voltage of the inverter circuit 7 through the filter circuit 11, the waveform input to the filter circuit 11 is shaped from a square wave to a sine wave. The sine-wave voltage output from the filter circuit 11 is output to the monitoring circuit 6 via the isolation circuit 12. By using the isolation circuit 12, the monitoring circuit 6 is isolated from the main circuit of the drive system 10.

[0023] The monitoring circuit 6 monitors the drive system 10 based on, for example, the output voltage detected by the voltage detector 5 .

[0024] The monitoring circuit 6 includes a frequency detection unit 13 , a frequency-to-period conversion unit 14 , a filter unit 15 , a period-to-frequency conversion unit 16 , an over-frequency detection setting unit 17 , an over-frequency detection unit 20 , and a fault detection unit 25 .

[0025] The frequency detection unit 13 calculates a first estimated frequency f1 based on the voltage waveform detected by the voltage detector 5.

[0026] The frequency detection unit 13 according to the embodiment will be described with reference to FIG. FIG. 3 is a configuration diagram of a frequency detection unit according to the embodiment.

[0027] The frequency detection unit 13 includes, for example, a detection cycle setting unit 131, an inversion number detection unit 132, a reference time determination unit 133, a counting unit 134, a frequency detection unit main body 135, and a dead band setting unit 136. The detection cycle setting unit 131 sets data specifying the length of the detection cycle in the storage unit. The reversal number detection unit 132 counts the number of reversal events, in which the instantaneous value of the AC component switches between positive and negative within a predetermined period, based on the voltage waveform. The reference time determination unit 133 selects a specific reversal event from among a plurality of reversal events in a predetermined cycle according to a predetermined rule, and determines the reference time of the selected reversal event. The counter 134 counts the number of pulses in a clock signal that includes a pulse train with a predetermined repetition period, and outputs the count result. The frequency detection unit main body 135 calculates the difference between a "current reference time," which is a reference time for the current cycle of a predetermined period, and a "previous reference time," which is a reference time for the previous cycle of the predetermined period. The frequency detection unit main body 135 calculates a first estimated frequency f1 of the AC component based on the difference between the "current reference time" and the "previous reference time," the number of previous reversal events in the previous cycle, and the standard length of a half cycle of the AC component. The dead band setting unit 136 is provided before the input of the inversion number detection unit 132, and removes the ripple component of the AC signal detected by the voltage detector 5 using a predetermined hysteresis characteristic to generate the above AC component. The reason for the hysteresis characteristic described above is that the waveform of the detected AC signal contains ripples, and without hysteresis, false detection would occur near the zero crossing. By providing a hysteresis characteristic using two threshold levels, the "H → L transition level" and the "L → H transition level," if the noise amplitude level is relatively small it does not exceed the threshold level and is not detected as the number of positive / negative inversions. This causes the signal (comparator output signal) that is the result of determining the amplitude level to invert every 180 degrees.

[0028] For example, the AC waveform shown in FIG. 2 has no noticeable distortion and is a sinusoidal waveform. The monitoring circuit 6 measures the times T1 and T2 between the zero crossing points of the sine wave as shown in FIG. However, depending on the situation, it may be observed that the AC voltage does not reverse every 180 degrees.

[0029] Frequency detection according to the embodiment will be described with reference to FIGS. 4, 5A, and 5B. Fig. 4 is a diagram for explaining frequency detection according to the embodiment. Fig. 5A is a diagram for explaining frequency detection when there is an influence of waveform distortion according to the embodiment. Fig. 5B is a diagram for explaining frequency detection when there is an influence of waveform distortion according to a comparative example.

[0030] Depending on the state of the device and the environment in which it is used, distortions such as those shown in Figures 5A and 5B may remain. Figures 5A and 5B show two cycles of an AC waveform, and show an example in which noise exceeding the hysteresis width is detected at the timing of the transition from the first cycle to the second cycle within that range.

[0031] When such amplitude noise is superimposed, distortion can remain. When identifying periods where the amplitude is positive and periods where it is negative, a phase inversion of positive and negative occurs, and the positive and negative identification results become discontinuous. This phenomenon is called "pulse splitting." A specific model of this phenomenon is shown in Figures 5A and 5B. 5A and 5B indicates that the waveform of the output signal from the filter section 15 changes due to differences in the characteristics of the filter section 15, which will be described later.

[0032] The explanation will be continued by returning to Fig. 4. Fig. 4 shows the relationship between the frequency detection unit 13, frequency-to-period conversion unit 14, filter unit 15, and period-to-frequency conversion unit 16 of the monitoring circuit 6. The frequency detection unit 13 calculates the first estimated frequency f1 from the measured times T1 and T2 using the following equation: The frequency detection unit 13 outputs the calculated first estimated frequency f1 to the over-frequency detection unit 20.

[0033] f1=1 / (T1+T2) [Hz]

[0034] The above formula is for one period of the voltage waveform shown in FIG. 2, and may be changed depending on the number of periods of the voltage waveform included in the frequency measurement period.

[0035] The frequency period converter 14 is disposed after the frequency detector 13. The frequency period converter 14 generates period information based on the first estimated frequency f1 generated by the frequency detector 13.

[0036] For example, the frequency period converter 14 includes a limiter 141 and a reciprocal calculator 142 . The limiter 141 is set with a lower limit value LL and an upper limit value UL for the input first estimated frequency f1. The lower limit value LL of the limiter 141 is set to avoid 0 and values ​​near 0. An over-frequency discrimination setting value OFTH is defined to identify an abnormal increase in the first estimated frequency f1. The upper limit value UL of the limiter 141 is set with a value determined based on the over-frequency discrimination setting value OFTH. A frequency corresponding to the over-frequency discrimination setting value is called an "over-frequency." For example, the upper limit value UL of the limiter 141 is set with a value that exceeds the over-frequency discrimination setting value OFTH. The value of the upper limit value UL of the limiter 141 may be a frequency that is higher than the rated frequency by approximately twice the difference between the rated frequency and the over-frequency. The reciprocal calculation unit 142 (first reciprocal calculation unit) calculates the reciprocal of the output value of the limiter 141.

[0037] The filter unit 15 is disposed after the frequency period conversion unit 14. A filter time constant for defining low-pass characteristics is preset in the filter unit 15. The filter unit 15 receives the output from the frequency period conversion unit 14, i.e., data indicating a period, as input. As described above, the filter unit 15 performs filtering on the period. For example, the time constant of the filter should be determined to be such that an abnormal value is not erroneously detected when pulse splitting occurs, etc. When pulse splitting occurs, the output value of the limiter 141 in the preceding stage is limited to the upper limit value UL. The characteristics of the filter unit 15 can be equivalent to a first-order lag characteristic defined by a time constant. However, without being limited to this, a general method may be applied to realize the desired characteristics of the filter unit 15.

[0038] FIG. 6 is a diagram for explaining frequency detection values ​​based on the time constant of a filter according to the embodiment. As shown in the voltage waveform in the upper part, a state in which a period in which a sine wave with distortion is observed is sometimes observed interspersed between periods in which a sine wave without distortion is observed. A frequency is detected in accordance with this voltage waveform and supplied to filter unit 15. If excessive waveform distortion occurs, the input signal to filter unit 15 changes in a step-like manner. For example, during a period in which excessive waveform distortion is detected, the input signal to filter unit 15 changes in a step-like waveform that has gone all the way up to the upper limit value UL of limiter 141. The following shows an example of the output waveform of the filter unit 15 when the upper limit value UL of the limiter 141 is set to the same as the overfrequency. The output waveforms are shown side by side, with three waveforms for which the filter time constant is changed, and a comparative example in which the filter is disabled. The resulting waveform changes depending on whether or not filtering is performed and the filter time constant.

[0039] For example, the following shows a method for determining the time constant of the filter unit 15 when the upper limit value UL of the limiter 141 is set to be the same as the overfrequency. In this case, for the allowable time X [s] from the detection of an overfrequency by the frequency detection unit 13 until the overfrequency detection unit 20 performs comparison processing, it is advisable to set the time constant of the filter unit 15 to a value (approximately 50%) that takes into account the processing time Y [s] and that allows for a margin of error. If the upper limit value UL of the limiter 141 is set to a value greater than the above-mentioned overfrequency, such as twice the overfrequency, the output value of the filter unit 15 tends to increase. Therefore, it is advisable to also increase the time constant so as to suppress the increasing tendency of the output value of the filter unit 15.

[0040] Adding such a filter unit 15 delays the time it takes for the over-frequency state to be identified by the over-frequency detection unit 20. Even when pulse splitting as described above occurs, in order to prioritize not falsely detecting an over-frequency state, it is advisable to use filter processing with a time constant suited to the required conditions.

[0041] The above description of when limiter 141 functions exemplifies a case where the detected frequency value becomes an abnormal value, which occurs when pulse splitting occurs, but filter unit 15 functions effectively even when the detected frequency value fluctuates even when pulse splitting does not occur. For example, providing filter unit 15 can reduce fluctuations in the period value corresponding to each frequency estimate.

[0042] 4, the explanation will be continued. The period-to-frequency converter 16 is disposed after the filter unit 15. The period-to-frequency converter 16 generates frequency information based on the period generated by the filter unit 15.

[0043] For example, the periodic frequency converter 16 includes a limiter 161 and a reciprocal calculator 162 . The limiter 161 is set with a lower limit value LL and an upper limit value UL for the period generated by the filter unit 15. The lower limit value LL of the limiter 161 is set to avoid 0 and values ​​near 0. The upper limit value UL of the limiter 161 is set to a large value, for example, the maximum positive value that can be set, to increase the calculation accuracy. By setting the upper limit value UL of the limiter 161 to a large value, the accuracy of the calculation results near 0 in the subsequent stage can be increased.

[0044] Returning to FIG. 1 mentioned above, the explanation will be continued. The over-frequency detection setting unit 17 sets an over-frequency discrimination set value OFTH, which is a threshold value for detecting an excessive increase in the output frequency f of the inverter device 2. The over-frequency detection setting unit 17 outputs the over-frequency discrimination set value OFTH to the over-frequency detection unit 20.

[0045] The over-frequency detection unit 20 compares the second estimated frequency f2 based on the frequency information generated by the period-to-frequency conversion unit 16 with the over-frequency discrimination setting value OFTH set in the over-frequency detection setting unit 17, and determines whether the second estimated frequency f2 is higher than the over-frequency discrimination setting value OFTH. The over-frequency detection unit 20 outputs a signal to the fault detection unit 25 based on the determination result. For example, if the second estimated frequency f2 is higher than the over-frequency discrimination setting value OFTH, the over-frequency detection unit 20 outputs a signal indicating '1' indicating an over-frequency abnormality. If the second estimated frequency f2 is equal to or lower than the over-frequency discrimination setting value OFTH, the over-frequency detection unit 20 outputs a signal indicating '0' indicating normality to the fault detection unit 25.

[0046] The fault detection unit 25 detects a fault based on the signal received from the over-frequency detection unit 20. The fault detection unit 25 determines that a fault has occurred if the received signal indicates '1' (i.e., a signal indicating an abnormality). When the fault detection unit 25 detects a fault, it controls the relay 26 and outputs a fault signal NG from the relay 26 to the inverter device 2.

[0047] (Overview of operation) A method for reducing the influence of noise in frequency estimation according to the embodiment will be described. The method for reducing the influence of noise in the embodiment described above is combined with several methods described below.

[0048] 1. Noise superimposed on the AC voltage waveform is reduced by the filter circuit 11 of the voltage detector 5. 2. After performing the above "1.", the frequency detection unit 13 of the monitoring circuit 6 reduces the influence of residual noise by identifying and quantizing the intensity value of the AC voltage waveform using a threshold value with hysteresis. Note that the noise superimposed on the AC voltage waveform that has been noise-reduced by the filter circuit 11 is reduced and used. 3. The frequency detection unit 13 of the monitoring circuit 6 derives an estimated value of the frequency of the AC voltage waveform after carrying out the above steps "1." and "2." using a predetermined method. 4. The monitoring circuit 6 reduces the variation in the estimated value of the frequency in "3." above by using a calculation process to be described later.

[0049] (Explanation of the calculation process to reduce the variation in estimated frequency) As mentioned above, if there is residual noise as described in "2." above, the quantization results of the AC voltage waveform may vary. Therefore, we will consider noise countermeasures that can be applied when there is residual noise that exceeds the hysteresis width. For example, it is recommended to combine the following several techniques with the noise countermeasures in the embodiments.

[0050] A: The counter 134 of the frequency detector 13 outputs the count result of the number of pulses of the clock signal. The inversion count detector 132 of the frequency detector 13 counts the number of inversion events, in which the instantaneous value of the AC component switches between positive and negative, within an evaluation period (a predetermined cycle) based on the voltage waveform during the evaluation period. The frequency detector main body 135 calculates a first estimated frequency f1 of the AC component based on the difference between the "current reference time" and the "previous reference time," the number of previous inversion events in the previous cycle, and the standard length of a half cycle of the AC component. As a result, the frequency evaluation period extends from the "current reference time" to the "previous reference time." This extends the counting period compared to when the frequency is estimated every half cycle of the AC, reducing the effects of variation caused by discretization.

[0051] B: In some cases, it may be determined that there was a clear misjudgment in the counting of the number of reversal events based on the period value resulting from the above "A." In such cases, the limiter 141 of the frequency-period converter 14 replaces the value of the first estimated frequency f1 with the upper limit value UL of the limiter 141, which is a predetermined fixed value. This reduces the influence of the misjudgment in the output of the limiter 141 that is influenced by the residual noise.

[0052] C: The reciprocal calculation unit 142 of the frequency-period conversion unit 14 calculates the reciprocal of the first estimated frequency f1 or the upper limit value UL of the limiter 141 in "3." above, and converts it into a period. This enables smoothing processing using the period.

[0053] D: Filtering by the filter unit 15 is applied to the smoothing process using the period. This filtering can be performed using a low-pass filter (LPF), a moving average, or the like, and can reduce sudden fluctuations that may occur in the magnitude of the first estimated frequency f1.

[0054] E: Estimate the frequency using the period data smoothed in "D." above.

[0055] F: The voltage waveform in "A" above may contain ripples. As already explained, implementing a dead band set by the hysteresis width can help reduce the ripples in the voltage waveform.

[0056] (Regarding period and frequency detection values) With reference to FIG. 7, frequency detection according to the embodiment will be described. FIG. 7 is a diagram for explaining frequency detection according to the embodiment. In the timing chart of FIG. 7, from the top, the output voltage (INV voltage) of the inverter device 2, the zero-cross detection result (zero-cross detection), the reference clock, the value of the internal counter, and the like are written. The horizontal axis indicates the passage of time.

[0057] The output voltage of the inverter device 2 is detected as, for example, a sinusoidal AC voltage waveform. The AC voltage waveform shown in this figure is an example of an ideal waveform. Every time the AC voltage waveform passes through 0V potential, a pulse is generated as a result of the zero-cross detection. The value of the internal counter is recorded in synchronization with the pulse resulting from the zero-cross detection.

[0058] A detection period (e.g., X [ms]) longer than the period of the AC voltage waveform is used to identify a specific zero-cross detection result within the detection period. This specific zero-cross detection result corresponds to the last zero-cross detection within the detection period. In the internal counter stage shown in the figure, identification information such as "X," "A," "B," "C," or "D" is assigned to points based on the specific zero-cross detection result.

[0059] Using points within each detection period, the number of pulses of the reference clock within the time between the points is counted to obtain the "count number."

[0060] The detection frequency calculation formula is as follows:

[0061]

number

[0062] In the above formula, n is the number of zero counts detected, fc is the reference clock frequency, f is the detection frequency, and (Cm-Cm-1) is the number of counts.

[0063] The example shown in FIG. 7 is a case where there is no error in detecting the zero crossing when the detection frequency (inverter frequency) f=50 Hz.

[0064] Using this example, a specific value is assigned to the detection frequency calculation formula and verified.

[0065] Since one period T = 1 / 50 = 0.02 s, the half period T / 2 = 0.02 / 2 = 0.01 s.

[0066] The count number is the number of pulses of the reference clock, so the pulse width per count is 1 / (33×10 6 )=3.03×10 -8 Assume that the reference clock fc is approximately 33 MHz.

[0067] The section (XA) relating to the first detection cycle is 1.5 cycles. The number of counts during that time is 0.03 / (3.03×10 -8 ) = 990,000 counts.

[0068] Using the above values, the detection frequency f is calculated.

[0069] f=3 / 990000×33×10 6 / 2=50

[0070] As described above, the detection frequency f can be calculated using the detection frequency calculation formula. However, the above calculation is based on the assumption that there is no error in detecting the zero crossing. If there is an error in the zero cross detection, the count number will change, and the error will have an effect on the detection frequency calculated using the detection frequency calculation formula.

[0071] In this embodiment, the above detection frequency calculation formula is used to calculate the first estimated frequency f1. This first estimated frequency f1 may be affected by residual noise as described above. Therefore, as shown in the above embodiment, it is advisable to reduce the influence of residual noise by performing processing by the monitoring circuit 6.

[0072] (Reducing the variability in detected period and frequency values) If the number of pulses within a given period of a pulse train of a clock signal that is repeated at a given cycle is uniform, the length of the given period can be determined with the precision of the pulse width from the product of the width of a unit pulse and the number of pulses. For example, the repetition period of a predetermined period is measured and the results are called the measurement period.Furthermore, the frequency is calculated from each measurement period, and the calculated frequencies are averaged to calculate the average frequency.The average period is calculated by averaging each measurement period. In this case, the average period and average frequency are shown when there is no fluctuation in the measurement period and it is uniform (always 1.0).

[0073] Measurement period 1.0 [pu] 1.0 [pu] 1.0 [pu] 1.0 [pu] Average period T=1.0 [pu] Average frequency F=1 / T=1.0 [pu]

[0074] The above calculation results in no variation or error in either the average period or the average frequency.

[0075] Unlike the above case, the average period and average frequency are shown when the measurement period fluctuates and is not uniform. For example, suppose the measurement period is a repetition of 1.1 and 0.9.

[0076] Measurement period 1.1 [pu] 0.9 [pu] 1.1 [pu] 0.9 [pu] Average period T=((1.1+0.9)) / 2=1.0 [pu] Average frequency F=((1 / 1.1+1 / 0.9)) / 2=1.01 [pu]

[0077] According to the above calculation results, there is no error in the average period, but there is an error of +1.0% in the average frequency.

[0078] Generally, if the period is a repetition of (+x) [pu] and (-x) [pu], the tendency will be as follows.

[0079] Average period T=([(1+x)+(1-x)]) / 2=1.0 [pu] Average frequency F=((1 / (1+x)+1 / (1-x))) / 2=1 / ((1-x^2)) [pu]≒1+x^2 [pu]

[0080] Analytically, this average frequency can be approximated as:

[0081] F=1+x^2 [pu]

[0082] According to the above calculation results, there is no error in the average period, but the average frequency has an error of (+x^2) [pu], which causes it to always shift higher. Therefore, when detecting the frequency from the measured period, if the period fluctuates, the value of the "average frequency" in the above calculation method will become higher.

[0083] To improve this, in the embodiment, a filter process is performed on the period to smooth the variation in each measurement period, and the estimated frequency is calculated based on the smoothed period value, thereby reducing the effect of variation in the measurement frequency.

[0084] According to this embodiment, the frequency monitoring device 1 includes a frequency detection unit 13, a frequency-period conversion unit 14, a filter unit 15, a period-frequency conversion unit 16, and an over-frequency detection unit 20. The frequency detection unit 13 calculates a first estimated frequency of an AC component within a predetermined period. The frequency-period conversion unit 14 calculates the period by performing an inverse operation on the first estimated frequency. The filter unit 15 calculates a value obtained by reducing fluctuations in the period. The period-frequency conversion unit 16 calculates a second estimated frequency by performing an inverse operation on the value obtained by reducing fluctuations in the period. The over-frequency detection unit 20 determines the second estimated frequency based on predetermined criteria established to detect over-frequency. This makes it possible to further improve the accuracy of detecting over-frequency at the fundamental frequency of AC.

[0085] The limiter 141 (first limiter) of the frequency-to-period converter 14 outputs an output value other than 0 at least when the value of the first estimated frequency is 0. The reciprocal calculator 142 may calculate the reciprocal of the first estimated frequency f1 using the output value from the limiter 141. This allows the calculation of the reciprocal of the first estimated frequency f1 to be successful.

[0086] The limiter 141 has a lower limit LL and an upper limit UL, both set to positive values, for the range of the output value of the previous stage. The upper limit UL of the limiter 141 is set higher than a threshold value (e.g., an overfrequency discrimination set value OFTH) for determination based on a predetermined determination criterion, and is set within a range that will prevent erroneous determination based on the predetermined determination criterion.

[0087] The limiter 161 (second limiter) of the period-to-frequency converter 16 outputs an output value other than 0 when at least the value obtained by reducing the fluctuation in the period is 0. The reciprocal calculation unit 162 (second reciprocal calculation unit) may use the output value from the previous stage adjusted by the limiter 161 to calculate the second estimated frequency f2.

[0088] The dead band setting unit 136 is configured to generate an AC component by removing the ripple component of the detected AC signal using a predetermined hysteresis characteristic, thereby reducing the influence of the ripple component.

[0089] (Second embodiment) The second embodiment will be described with reference to FIGS. Fig. 8 is a diagram for explaining frequency detection according to the second embodiment, and Fig. 9 is a diagram for explaining frequency estimation according to the second embodiment.

[0090] FIG. 8 shows a frequency monitoring device 1A that replaces the frequency monitoring device 1. The frequency monitoring device 1A includes a monitoring circuit 6A that replaces the monitoring circuit 6 of the frequency monitoring device 1. The monitoring circuit 6A includes a second normalization processing unit 19 in addition to the configuration of the monitoring circuit 6 described above, and includes a frequency detection unit 13A instead of the frequency detection unit 13.

[0091] The frequency detection unit 13A includes a first normalization processing unit 137 in addition to the components of the frequency detection unit 13. The components of the frequency detection unit 13A correspond to the components of the frequency detection unit 13 except for the addition of the first normalization processing unit 137.

[0092] First normalization processing unit 137 of frequency detection unit 13A is disposed between the output of counting unit 134 in frequency detection unit 13A and the input of frequency detection unit main body 135. First normalization processing unit 137 normalizes the output data of counting unit 134 based on a predetermined standard and outputs the normalized data. The normalization processing by first normalization processing unit 137 is processing to scale the output data of counting unit 134. This processing allows the number of pulses to be converted to a number smaller than the actually counted number.

[0093] The second normalization processing unit 19 is disposed between the periodic frequency conversion unit 16 and the over-frequency detection unit 20. The second normalization processing unit 19 adjusts the output data of the periodic frequency conversion unit 16 based on a predetermined criterion and outputs the adjusted data. The adjustment process by the second normalization processing unit 19 is a process of adjusting the scaling of the output data of the periodic frequency conversion unit 16. The adjustment process by the second normalization processing unit 19 may be set to cancel the scaling correction caused by the normalization process by the first normalization processing unit 137 described above. Although the frequency detection unit 13A temporarily converts the number of pulses to a number smaller than the actually counted number of pulses, this process can also adjust the number of pulses to the same scaling as the actually counted number of pulses.

[0094] When the various data used in the above processing are represented as fixed-length binary data, it is recommended to perform positional adjustment by division or multiplication by a power of 2. During the processing, instead of performing a division operation, a logical shift operation is performed on all bits of the binary data in the direction of the lower bits to obtain the quotient of the division result. It is also recommended to assign 0 to the most significant bit in conjunction with the logical shift operation in the direction of the lower bits. Alternatively, instead of performing a multiplication operation, a logical shift operation can be performed on all bits of the binary data in the direction of the most significant bit to obtain the product of the multiplication results. Note that it is advisable to assign 0 to the least significant bit in conjunction with the logical shift operation in the direction of the most significant bit.

[0095] For example, by representing the data output from counting unit 134 as "fixed-length binary data," it is possible to count clock pulses within a range of approximately twice the number indicated by the most significant digit of this "fixed-length binary data."

[0096] It is advisable to adjust the range of the data values ​​output from the counting unit 134 to a number of digits that matches the expected fundamental frequency (fundamental period) of the AC.

[0097] For example, the shift amount for the logical shift operation may be determined as follows:

[0098] If the fundamental frequency is relatively low (low frequency), increase the shift amount beyond the reference value. If the fundamental frequency is within the standard range (medium frequency), the shift amount is set to the standard value. If the fundamental frequency is relatively high (high frequency), reduce the shift amount below the reference value.

[0099] A more specific example of values ​​will be described below. If the fundamental frequency of the AC is 100 Hz or less, the first normalization processing unit 137 performs a logical shift operation to shift the value one bit downward, thereby converting the count value of the clock pulses to half its value. If the fundamental frequency of the AC is greater than 100 Hz and equal to or less than 200 Hz, the first normalization processing unit 137 performs a logical shift operation to shift the count value two bits downward, thereby converting the count value of the clock pulses to a quarter value. If the fundamental frequency of the AC is greater than 200 Hz and equal to or less than 300 Hz, the first normalization processing unit 137 performs a logical shift operation to shift the count value three bits downward, thereby converting the count value of the clock pulses to one-eighth of its original value. As described above, by performing logical shift operations in which the shift amount is determined according to the range of the fundamental wave frequency of the AC, it is possible to compress the range in which the values ​​resulting from the logical shift operations are dispersed.

[0100] After filtering the period and converting it to a frequency, the second normalization unit 19 performs a logical shift operation to shift all bits toward higher order by the number of bits corresponding to the shift amount. This allows the range indicated by the processing result of the second normalization unit 19 to be restored to the same range as the count value of the clock pulses.

[0101] As shown above, a frequency monitoring device 1A is shown. The frequency monitoring device 1A (frequency monitoring device) includes a monitoring circuit 6A, which replaces the monitoring circuit 6 of the frequency monitoring device 1, and includes a first normalization processing unit 137 (normalization unit) and a second normalization processing unit 19 (adjustment unit). The first normalization processing unit 137 (normalization unit) normalizes the AC component according to the rank of the frequency or period of the AC component. The second normalization processing unit 19 (adjustment unit) adjusts the second estimated frequency f2 according to the rank. The over-frequency detection unit 20 then determines the adjusted second estimated frequency f2. This allows the AC voltage waveform to be normalized to a value appropriate for the frequency range (range) and processed.

[0102] (Modification of the second embodiment) A modification of the second embodiment will be described with reference to FIG. FIG. 10 is a diagram for explaining frequency estimation according to a modification of the second embodiment. In the above embodiment, the shift amount of the logical shift calculation is predetermined. In this modified example, the shift amount of the logical shift calculation is adjusted depending on the driving situation.

[0103] For example, if the frequency adjustment range for VVVF control is set relatively wide, it may cross the frequency classifications exemplified in the above embodiment. Even in cases such as VVVF control in which the AC fundamental frequency changes during variable frequency operation, it is advisable to determine the frequency range of the AC voltage waveform based on the command frequency and normalize it to an appropriate value according to the determined frequency range. The frequency monitoring device 1A can perform VVVF control in response to a request from the control device 8 using the shift amount of the logical shift calculation.

[0104] (Configuration example of frequency monitoring device 1 of each embodiment) Next, with reference to FIG. 11, an example of the configuration of the frequency monitoring device 1 (1A) will be described. FIG. 11 is a diagram for explaining an example of the configuration of the frequency monitoring device 1 according to each embodiment.

[0105] The frequency monitoring device 1 includes, for example, a processing unit 811, a communication processing unit 812, an input / output unit 813, and a storage unit 814. For example, the processing unit 811, the communication processing unit 812, the input / output unit 813, and the storage unit 814 are connected via a bus or the like.

[0106] The communication processing unit 812 communicates with the control device 8 of the higher-level device and acquires various information, which can be supplied to the processing unit 811 .

[0107] The storage unit 814 is realized by a ROM, a RAM, a HDD, a flash memory, etc. The storage unit 814 is allocated a storage area for storing various setting information and programs for functioning the frequency monitoring device 1, basic programs such as an OS, application programs, etc.

[0108] The input / output unit 813 includes, for example, a voltage detector 5 and a relay 26, and receives information on the output state of the inverter circuit 7 (such as line voltage) as input information, and outputs the result of an over-frequency determination. The input / output unit 813 may include, for example, a display unit such as a liquid crystal display that displays various information, and an operation detection unit. The display unit and operation detection unit may be configured as a touch panel that combines them.

[0109] The processing unit 811 detects the frequency from an AC waveform based on the line voltage and performs a predetermined determination process to detect an over-frequency state. The processing unit 811 outputs the result of the determination as to whether or not an over-frequency state exists via the input / output unit 813.

[0110] The processing unit 811 executes a software program including the above functions. Processing unit 811 executes a software program to implement some or all of its functions. The software program for implementing the functions of processing unit 811 may be stored in storage unit 814 in advance, or may be downloaded to storage unit 814 from an external device or portable storage medium (not shown), or via a communication line.

[0111] The functions described herein and performed by the components of the frequency monitoring device 1 may be implemented in circuitry or processing circuitry. The circuitry or processing circuitry may include general-purpose processors, application-specific processors, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), central processing units (CPUs), graphics processing units (GPUs), conventional circuits, and / or combinations thereof, programmed to perform the described functions. Processors that perform the above functions include transistors and other circuits and are considered circuitry or processing circuitry. The processor for performing the above functions may include or be a programmable processor that executes a program stored in memory and / or a programmable device that can be reconfigured by data stored in memory. In this specification, a circuit, unit, or means is hardware that is programmed to realize or performs the described functions, which may be any hardware disclosed herein or any hardware known to be programmed to realize or perform the described functions. If the hardware is a processor that is considered to be a type of circuitry, the circuitry, means, or unit is a combination of hardware and software used to configure the hardware and / or processor.

[0112] According to at least one of the above-described embodiments, the frequency monitoring device includes a frequency detection unit, a frequency-period conversion unit, a filter unit, a period-frequency conversion unit, and an over-frequency detection unit. The frequency detection unit calculates a first estimated frequency of an AC component within a predetermined period. The frequency-period conversion unit calculates the period by performing an inverse operation on the first estimated frequency. The filter unit calculates a value in which fluctuations in the period have been reduced. The period-frequency conversion unit calculates a second estimated frequency by performing an inverse operation on the value in which fluctuations in the period have been reduced. The over-frequency detection unit determines the second estimated frequency based on predetermined criteria set for detecting over-frequencies. This can further improve the accuracy of detecting over-frequencies at the fundamental frequency of AC.

[0113] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0114] For example, the frequency monitoring device 1 and the inverter device 2 may be configured separately or integrated. The functional units that control various processes of the frequency monitoring device 1 and the inverter device 2 may be configured separately or integrated. In the latter case, a common processor may perform part of the respective processes or the above. [Explanation of symbols]

[0115] 1 Frequency monitoring device 2. Inverter device 5 Voltage detector 6 Monitoring circuit 8 Control Device 10 Drive System 11 Filter Circuit 12. Isolation Circuits 13 Frequency detection section 14 Frequency-to-periodic converter 15 Filter section 16 Periodic frequency converter 17 Over-frequency detection setting section 20 Over-frequency detection section

Claims

1. a frequency detection unit that calculates a first estimated frequency of an AC component within a predetermined period; a frequency-period converter that calculates a period by performing an inverse operation on the first estimated frequency; a filter unit that calculates a value that reduces fluctuations in the period; a period-to-frequency converter that calculates a second estimated frequency by performing an inverse operation on the value obtained by reducing the fluctuation of the period; an over-frequency detection unit that determines the second estimated frequency based on a predetermined determination criterion that is set to detect an over-frequency; A frequency monitoring device comprising:

2. The frequency-to-period converter a first limiter that outputs an output value other than 0 when at least the value of the first estimated frequency becomes 0; a first reciprocal calculation unit that calculates the reciprocal of the first estimated frequency using the output value from the first limiter; The frequency monitoring device of claim 1 .

3. the first limiter has a lower limit value and an upper limit value of the range of the output value each set to a positive value; The upper limit is set higher than the threshold value for determination based on the predetermined determination criterion, and is determined within a range in which erroneous determination based on the predetermined determination criterion does not occur.

3. The frequency monitoring device according to claim 2.

4. The periodic frequency conversion unit a second limiter that outputs an output value other than 0 when at least the value obtained by reducing the fluctuation of the period is 0; a second reciprocal calculation unit that calculates the second estimated frequency using the output value adjusted by the second limiter; The frequency monitoring device of claim 1 .

5. The frequency detection unit an inversion number detection unit that counts the number of inversion events in which the instantaneous value of the AC component switches between positive and negative within a predetermined period; a reference time determination unit that selects a specific reversal event from among a plurality of reversal events in the predetermined period according to a predetermined rule, and determines a reference time of the selected reversal event; a frequency detection unit that calculates a first estimated frequency of the AC component based on a difference between a current reference time that is the reference time of a current cycle of the predetermined period and a previous reference time that is the reference time of a previous cycle of the predetermined period, the number of previous reversal events in the previous cycle, and a standard length of a half cycle of the AC component; The frequency monitoring device of claim 1 .

6. a normalization unit that normalizes the AC component according to a rank of a frequency or a period of the AC component; an adjustment unit that adjusts the second estimated frequency in accordance with the rank; Equipped with The over-frequency detection unit determining the adjusted second estimated frequency The frequency monitoring device according to claim 1 .

7. a dead band setting unit that generates the AC component by removing the ripple component of the detected AC signal using a predetermined hysteresis characteristic; The frequency monitoring device of claim 1 .

8. calculating a first estimated frequency of the AC component within a predetermined period; calculating a period by performing an inverse operation on the first estimated frequency; Calculate the value that reduces the periodic fluctuation, calculating a second estimated frequency by performing an inverse operation on the value obtained by reducing the fluctuation of the period; Determining the second estimated frequency based on predetermined criteria established to detect over-frequency. A frequency monitoring method including:

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