Semiconductor device

Abstract

To provide a semiconductor device which can be easily miniaturized. To provide a semiconductor device which can be highly integrated.SOLUTION: The first insulating layer has an opening, the first conductive layer is positioned along the opening, the third insulating layer is positioned along the first conductive layer, and the second conductive layer is positioned in a recessed portion of the third insulating layer. The second insulating layer is positioned over the second conductive layer and has a slit reaching the second conductive layer, the third conductive layer is positioned over the second insulating layer, the semiconductor layer includes a portion in contact with a side surface of the third conductive layer, a portion in contact with a side surface of the second insulating layer inside the slit, and a portion in contact with an upper surface of the second conductive layer inside the slit, the fourth insulating layer covers the semiconductor layer inside the slit, the fourth conductive layer covers the fourth insulating layer inside the slit, the second conductive layer includes first to third layers, a top surface of the first layer has a depressed portion, the second layer is positioned in the depressed portion of the first layer, and the third layer is positioned over the first layer and the second layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used as semiconductor devices. A CPU is a collection of semiconductor elements that have been processed from a semiconductor wafer and have semiconductor integrated circuits (at least transistors and memories) formed into chips, and on which electrodes serving as connection terminals are formed.

[0004] A CPU, memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] In recent years, along with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner. Patent Document 4 also discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537 [Non-patent literature]

[0009] [Non-Patent Document 1] Takashi Koida, "High Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be easily miniaturized. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device in which a wiring load is reduced. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that exhibits favorable electrical characteristics. Another object is to provide a semiconductor device with high operating speed. Another object is to provide a semiconductor device with high productivity.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0013] One embodiment of the present invention includes a capacitor, a transistor on the capacitor, a first insulating layer, and a second insulating layer on the first insulating layer. The capacitor includes a first conductive layer, a second conductive layer, and a third insulating layer. The transistor includes a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, and a fourth insulating layer. The first insulating layer has an opening, and the first conductive layer is located along the opening. The third insulating layer is located along the first conductive layer. The second conductive layer is located in a recess of the third insulating layer. The second insulating layer is located on the second conductive layer and reaches the second conductive layer. a third conductive layer located on the second insulating layer; a semiconductor layer having a portion contacting a side surface of the third conductive layer, a portion contacting a side surface of the second insulating layer inside the slit, and a portion contacting an upper surface of the second conductive layer inside the slit; a fourth insulating layer covering the semiconductor layer inside the slit; the fourth conductive layer covering the fourth insulating layer inside the slit; the second conductive layer having first to third layers, the first layer having a recess on its upper surface, the second layer located in the recess of the first layer, and the third layer located on the first and second layers.

[0014] In the above, it is preferable that the height of the upper surface of the first layer and the height of the upper surface of the second layer are approximately the same.

[0015] In the above, it is preferable that the lower surface of the third layer contacts the upper surface of the first layer and the upper surface of the second layer.

[0016] In the above, it is preferable that the third insulating layer and the second conductive layer have substantially the same top surface shape.

[0017] Furthermore, in the above, it is preferable that the device has a connection electrode and a fifth conductive layer, the slit extends in a first direction, the fourth conductive layer extends in the first direction inside the slit, the fifth conductive layer is located on the fourth conductive layer and extends in a second direction intersecting the first direction, and the connection electrode contacts the upper surface of the third conductive layer and the lower surface of the fifth conductive layer.

[0018] In the above, it is preferable that the semiconductor layer contains a first metal oxide, the third layer contains a second metal oxide, and the first metal oxide and the second metal oxide each contain indium.

[0019] In the above, it is preferable that the first layer contains tungsten and the second layer contains titanium nitride. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a semiconductor device that can be easily miniaturized can be provided. Alternatively, a semiconductor device that enables high integration can be provided. Alternatively, a semiconductor device with reduced wiring load can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, a semiconductor device that exhibits favorable electrical characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided. Alternatively, a semiconductor device with high productivity can be provided.

[0021] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0023] [Figure 1] 1A and 1B are diagrams showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a diagram illustrating a configuration example of a semiconductor device. [Figure 3] FIG. 3 is a diagram illustrating a configuration example of a semiconductor device. [Figure 4] FIG. 4 is a diagram illustrating a configuration example of a semiconductor device. [Figure 5]FIG. 5 is a diagram illustrating a configuration example of a semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating a configuration example of a semiconductor device. [Figure 7] FIG. 7 is a diagram illustrating a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating a configuration example of a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating a configuration example of a semiconductor device. [Figure 14] 14A to 14C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 15] 15A to 15C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 16] 16A to 16C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 17] 17A and 17B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 18] 18A and 18B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 19] 19A and 19B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 20] 20A and 20B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 21] 21A and 21B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 22]22(A) and 22(B) are diagrams illustrating the carrier concentration dependence of Hall mobility, and Fig. 22(C) is a cross-sectional view illustrating an indium oxide film. [Figure 23] FIG. 23 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 24] 24A to 24H are diagrams illustrating examples of circuit configurations of memory cells. [Figure 25] 25A and 25B are perspective views illustrating a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a block diagram illustrating the CPU. [Figure 27] 27(A) and 27(B) are perspective views of the semiconductor device. [Figure 28] 28(A) and 28(B) are perspective views of the semiconductor device. [Figure 29] 29(A) and 29(B) are diagrams showing configuration examples of electronic components. [Figure 30] 30(A) to 30(C) are diagrams showing examples of the configuration of a mainframe computer. [Figure 31] Fig. 31(A) is a diagram showing an example of the configuration of space equipment, and Fig. 31(B) is a diagram showing an example of the configuration of a storage system. [Figure 32] FIG. 32 is a cross-sectional STEM image according to Example 1. [Figure 33] 33(A) and (B) are cross-sectional STEM images according to Example 1. [Figure 34] FIG. 34 is a graph according to the first embodiment. [Figure 35] FIG. 35 is a graph according to the first embodiment. [Figure 36] FIG. 36 is a graph according to the first embodiment. [Figure 37] FIG. 37 is a graph according to the first embodiment. [Figure 38] Fig. 38(A) is a perspective schematic diagram of a memory cell array, and Fig. 38(B) is a diagram explaining the manufacturing process of the memory cell. [Figure 39]Fig. 39(A) is a schematic plan view of a memory cell, Fig. 39(B) is an equivalent circuit diagram of the memory cell, and Fig. 39(C) and Fig. 39(D) are schematic cross-sectional views of the memory cell. [Figure 40] Fig. 40(A) is a schematic plan view of a memory cell, Fig. 40(B) is an equivalent circuit diagram of the memory cell, and Fig. 40(C) and Fig. 40(D) ​​are schematic cross-sectional views of the memory cell. [Figure 41] 41(A) and 41(B) are graphs according to the second embodiment. [Figure 42] FIG. 42 is a graph according to the second embodiment. [Figure 43] 43(A) and 43(B) are graphs according to the second embodiment. [Figure 44] FIG. 44 is a graph according to the second embodiment. [Figure 45] FIG. 45 is a diagram showing the circuit configuration used in the simulation. [Figure 46] FIG. 46 is a circuit diagram of a sense amplifier circuit. [Figure 47] 47(A) and 47(B) are timing charts according to the second embodiment. [Figure 48] 48(A) and 48(B) are graphs according to the second embodiment. [Figure 49] Figure 49 is a photograph of the appearance of a DRAM chip. [Figure 50] Figure 50 is a cross-sectional STEM image of a DRAM chip. [Figure 51] 51(A) and 51(B) are block diagrams of a DRAM chip. [Figure 52] 52(A) and (B) are diagrams according to the second embodiment. [Figure 53] 53(A) and 53(B) are timing charts for a DRAM chip. [Figure 54] Fig. 54(A) is a schematic diagram for explaining a delay circuit, and Fig. 54(B) is a timing chart of the delay circuit. [Figure 55]FIG. 55 is a graph illustrating the simulation results of the delay circuit. [Figure 56] FIG. 56 is a graph according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0029] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0030] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0031] In this specification, the term "electrical connection" does not include cases where two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film.

[0032] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0033] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.

[0034] In the following, expressions indicating directions such as "upper" and "lower" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a surface to be formed, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the surface to be formed may be expressed as "lower" and the laminate side as "upper."

[0035] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as one.

[0036] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0037] Unless otherwise specified, in this specification, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0038] (Embodiment 1) In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. The semiconductor device exemplified below can be applied to a memory device.

[0039] A semiconductor device according to one embodiment of the present invention includes a plurality of memory cells, each of which includes one transistor and one memory element. The memory element can be any of various elements capable of retaining stored data, such as a capacitor, a variable resistance element, a ferroelectric element, a charge trap element, or a floating gate element.

[0040] In a transistor included in a memory cell, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in a height direction. In other words, it can be said that the channel length direction has a component in a height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0041] More specifically, an insulating layer functioning as a spacer is provided above a lower electrode, which is one of a source electrode and a drain electrode, and an upper electrode, which is the other of the source electrode and the drain electrode, is provided above the insulating layer. A slit extending in a first direction and reaching the lower electrode is provided in the insulating layer. The slit has a side surface approximately perpendicular to the substrate surface. The semiconductor layer has a portion contacting the side surface of the upper electrode, a portion contacting the side surface of the insulating layer inside the slit, and a portion contacting the upper surface of the lower electrode inside the slit. A gate insulating layer is provided inside the slit to cover the semiconductor layer. A gate electrode is provided inside the slit to cover the gate insulating layer.

[0042] The semiconductor layer is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor properties. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in a vertical transistor according to one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can form a low-resistance region without doping with such impurities and can provide good connection with the source and drain electrodes. Therefore, a transistor having a three-dimensional structure according to one embodiment of the present invention can be manufactured with high yield.

[0043] The capacitor of the memory cell can be provided below the transistor. For example, the capacitor may be formed in a vertical hole-shaped opening provided in an insulating layer. By stacking the transistor and the capacitor, memory cells can be arranged at high density. The capacitor can be a so-called MIM (Metal-Insulator-Metal) capacitor having a dielectric between a pair of electrodes. In this case, it is preferable that the lower electrode of the transistor also serves as the upper electrode of the capacitor.

[0044] Here, the lower electrode of the transistor preferably includes a first layer having a recess formed therein that overlaps the opening, a second layer provided to fill the recess in the first layer, and a third layer formed on the first and second layers. This configuration allows the top surfaces of the first and second layers to be planarized, making the heights of the top surfaces of the first and second layers approximately the same. Furthermore, the surface on which the third layer is to be formed can be planarized, making the shape of the third layer flat. This prevents the third layer from having a locally thin film thickness. Therefore, when the slit is formed, the slit can be prevented from penetrating the third layer. This allows the semiconductor layer to be in contact with the third layer but not the first layer.

[0045] The third layer in contact with the semiconductor layer preferably contains a conductive metal oxide (oxide conductor). Using a metal oxide for the conductive film in contact with the metal oxide-containing semiconductor layer is preferable because it can reduce the contact resistance between them and the wiring load. It is particularly preferable for the third layer to contain the same metal element as the metal element contained in the semiconductor layer, because this can further reduce the contact resistance. Specifically, it is preferable for the semiconductor layer and the third layer to contain one or more of In, Sn, Zn, Ga, and Ti. Furthermore, a low-resistance metal material can be used for the first layer. This can reduce both the contact resistance and the wiring resistance, thereby further reducing the wiring load.

[0046] A more specific example will be described below with reference to the drawings.

[0047] [Configuration example] FIG. 1(A) shows a schematic top view of a semiconductor device 50. FIGS. 2 and 3 show schematic cross-sectional views taken along the cutting lines AB and CD shown in FIG. 1(A), respectively. FIG. 4 shows a perspective view of the semiconductor device 50. Some components (such as insulating layers) are omitted from FIG. 4. Arrows indicating the X, Y, and Z directions are shown in each figure. Here, the X, Y, and Z directions intersect with one another; for example, the X, Y, and Z directions are perpendicular to one another.

[0048] The semiconductor device 50 has a configuration in which a plurality of memory cells 15 are arranged in the X and Y directions. In the semiconductor device 50, conductive layers 26 functioning as bit lines extend in the X direction, and conductive layers 23 functioning as word lines extend in the Y direction. As shown in FIG. 2, the memory cell 15 has a transistor 10 and a capacitance element 30 therebelow.

[0049] FIG. 1B shows a circuit diagram corresponding to the semiconductor device 50. FIG. 1B shows a plurality of wirings BL that function as bit lines, a plurality of wirings WL that intersect the bit lines at right angles and function as word lines, and wirings CL. While FIG. 1B shows an example in which the wirings CL are parallel to the wirings WL, they may also be parallel to the wirings BL or arranged in a lattice pattern. Alternatively, the wirings CL may be flat (or plate-shaped) conductive films.

[0050] The memory cell 15 includes one transistor 10 and one capacitor 30. The transistor 10 has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor 30. The other electrode of the capacitor 30 is connected to a wiring CL.

[0051] The wiring BL functions as a wiring for writing and reading data. The wiring WL functions as a wiring for controlling the on / off (conducting state or non-conducting state) of the transistor 10 functioning as a switch. The wiring CL functions as a constant potential line connected to the capacitor 30.

[0052] 2, the transistor 10 and the capacitor 30 are provided over an insulating layer 11 that is provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0053] The transistor 10 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other. Here, the conductive layer 24 has a stacked structure including a conductive layer 24a1, a conductive layer 24a2 on the conductive layer 24a1, and a conductive layer 24b located on the conductive layer 24a1 and the conductive layer 24a2. Note that hereinafter, the conductive layers 24a1 and 24a2 may be collectively referred to as the conductive layer 24a. In addition, an example is shown in which the conductive layer 25 includes a conductive layer 25a and a conductive layer 25b located thereon.

[0054] The capacitor 30 is provided on a conductive layer 55 that functions as a wiring CL. The capacitor 30 includes a conductive layer 51 that functions as a lower electrode, a conductive layer 24 that functions as an upper electrode, and an insulating layer 52 that is disposed between the conductive layer 51 and the conductive layer 24 and functions as a dielectric. Thus, the conductive layer 24 preferably serves as both the lower electrode of the transistor 10 and the upper electrode of the capacitor 30. This simplifies the manufacturing process and reduces manufacturing costs. As shown in FIG. 2 and other figures, when the conductive layer 24 has a stacked structure of conductive layers 24a and 24b, the lower conductive layer 24a can function as the upper electrode of the capacitor 30. In this case, the upper conductive layer 24b can also function as a connection electrode for connecting the conductive layer 24a and the semiconductor layer 21.

[0055] A conductive layer 55 is provided on the insulating layer 11. Here, an example is shown in which the conductive layer 55 has a two-dimensional flat (plate-like) shape, but it may also have a wiring (line-like shape) extending in the X direction, Y direction, or other direction. Alternatively, it may have a lattice-like shape that combines two or more portions extending in different directions.

[0056] An insulating layer functioning as a protective insulating layer can be provided between the insulating layer 11 and the conductive layer 55. Alternatively, the insulating layer 11 may function as the protective insulating layer. The insulating layer has a function of preventing impurities such as hydrogen from diffusing into the semiconductor layer 21 from the insulating layer 11 or from below the insulating layer 11. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0057] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0058] An insulating layer 46 is provided on the conductive layer 55. The insulating layer 46 functions as an interlayer insulating layer. The insulating layer 46 has a plurality of openings 40 that reach the conductive layer 55, and one capacitor element 30 is provided for each opening 40. The openings 40 are preferably formed in the shape of a vertical hole with a large aspect ratio. By forming the openings 40 deep, the area where the pair of electrodes of the capacitor element 30 face each other can be increased, thereby increasing the capacitance.

[0059] The conductive layer 51 is provided along the opening 40. Specifically, the conductive layer 51 has a portion provided along the side surface of the insulating layer 46 at the opening 40 and a portion in contact with the upper surface of the conductive layer 55. In other words, the conductive layer 51 has a cylindrical (also called cup-like) shape with a bottom and a recess. The conductive layer 51 is provided individually for each memory cell 15, and the respective conductive layers 51 are connected by the conductive layer 55.

[0060] The insulating layer 52 is provided along the conductive layer 51. Specifically, the insulating layer 52 has a portion provided along the recess of the conductive layer 51, a portion in contact with the upper surface of the conductive layer 51, and a portion in contact with the upper surface of the insulating layer 46. The insulating layer 52 does not need to be formed individually for each memory cell 15, and can be formed integrally. However, the present invention is not limited to this, and the insulating layer 52 can also be configured to be provided individually for each memory cell 15.

[0061] The conductive layer 24 is formed by filling the recessed portion of the insulating layer 52. Alternatively, the conductive layer 24 can be said to be provided so as to fill the recessed portion of the conductive layer 51 with the insulating layer 52 interposed therebetween. Alternatively, the conductive layer 24 can be said to have a portion provided on the insulating layer 46 with the insulating layer 52 interposed therebetween. The conductive layer 24 is provided individually for each memory cell 15.

[0062] Although FIGS. 1A and 4 show an example in which the outline of the conductive layer 51 in a plan view (the outline of the opening 40) is circular, this is not limiting. Therefore, the horizontal cross-sectional shape of the conductive layer 51 is not limited to a circular ring shape, but may be any shape as long as it is annular. For example, the outline shape and horizontal cross-sectional shape of the conductive layer 51 in a plan view are not limited to a circle, but may be an ellipse, a rectangle with rounded corners, or the like. They may also be regular polygons such as an equilateral triangle, a square, or a regular pentagon, or polygons other than regular polygons. Furthermore, a concave polygon, such as a star-shaped polygon, with at least one interior angle exceeding 180 degrees, can increase capacitance. Other shapes include a polygon with rounded corners and a closed curve combining straight and curved lines.

[0063] 2 and the like is a so-called cylinder-type or trench-type capacitive element. The configuration of the capacitive element 30 is not limited to this, and for example, a pillar-type capacitive element may also be used.

[0064] 2 and 4 show an example in which the bottom of the conductive layer 51 is rounded (has a concave curved surface). Furthermore, the bottom of the insulating layer 52 provided along the conductive layer 51 and the bottom of the conductive layer 24 provided along the insulating layer 52 also have a rounded shape (a convex curved surface). In this way, by configuring the conductive layer 51, which forms the surface on which the insulating layer 52 is formed, to have no corners, it is possible to prevent the insulating layer 52 from becoming locally thin. Furthermore, since the bottom of the conductive layer 51 has no corners, it is possible to prevent local concentration of the electric field. This makes it possible to suppress leakage current of the capacitance element, thereby improving reliability.

[0065] Furthermore, a rounded recess is provided on the top surface of conductive layer 55, and the bottom of conductive layer 51 is provided to be coupled to this recess. With this configuration, the contact area between conductive layer 55 and conductive layer 51 is increased, and the contact resistance therebetween can be reduced. The recess in conductive layer 55 can be formed by etching a portion of the top of conductive layer 55 when forming an opening in insulating layer 46.

[0066] The conductive layer 24a1 is preferably made of a conductive material having a lower resistance than the conductive layer 24b. In particular, it is preferable that the conductive layer 24a1 contains a metal material. By using a metal material having a lower resistance than the conductive layer 24b for the conductive layer 24a1, it is possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring. For example, the conductive layer 24a1 can be made of a conductive material containing tungsten, copper, or aluminum.

[0067] Since the conductive layer 24a1 is formed by filling the opening 40, which has a high aspect ratio, a recess may be formed on the upper surface of the conductive layer 24a1, particularly in the region overlapping with the opening 40 and in the vicinity thereof. As shown in FIG. 2, the conductive layer 24a2 is formed by filling the recess of the conductive layer 24a1.

[0068] The conductive layer 24a2 is preferably made of a conductive material. The conductive film that will become the conductive layer 24a2 preferably has a function of preventing oxidation of the conductive film that will become the conductive layer 24a1 during the manufacturing process. For example, a conductive nitride can be used as such a conductive film. For example, the conductive layer 24a2 can be made of a conductive nitride such as titanium nitride, a nitride containing titanium and aluminum, tantalum nitride, or a nitride containing tantalum and aluminum.

[0069] The upper surfaces of the conductive layers 24a1 and 24a2 are preferably flattened. For example, it is preferable that the heights of the upper surfaces of the conductive layers 24a1 and 24a2 are approximately the same. With this configuration, the conductive layer 24b provided on the conductive layers 24a1 and 24a2 can also be made flat. This prevents unevenness from being formed on the conductive layer 24b, which would otherwise result in locally thin regions. This prevents the formation of slits 20 penetrating the conductive layer 24b and reaching the conductive layer 24a.

[0070] The conductive layer 24b is preferably made of a conductive metal oxide (oxide conductor). The conductive layer 24b, which is in contact with the metal oxide-containing semiconductor layer 21, is preferably made of a conductive metal oxide, because this reduces the contact resistance between them and the wiring load. It is particularly preferable for the conductive layer 24b to contain the same metal element as the metal element contained in the semiconductor layer 21, because this further reduces the contact resistance. Specifically, it is preferable for both the semiconductor layer 21 and the conductive layer 24b to contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. For example, the conductive layer 24b can be made of a conductive oxide such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, or Ga-Zn oxide.

[0071] It is preferable that conductive layer 24b contacts conductive layer 24a1. As shown in Fig. 2, it is preferable that the lower surface of conductive layer 24b contacts the upper surface of conductive layer 24a1 and the upper surface of conductive layer 24a2. By adopting a structure in which conductive layer 24b contacts conductive layer 24a1, which has a lower electrical resistance, it is possible to further reduce the load on the wiring.

[0072] An insulating layer 41 is provided above the conductive layer 24 and the insulating layer 52. The insulating layer 41 has a strip-shaped slit 20 extending in the Y direction. It is preferable that the side surface of the insulating layer 41 within the slit 20 is approximately perpendicular to the substrate surface. It is preferable that the height of the insulating layer 41 is greater than the width of the slit 20 in the X direction.

[0073] In this specification, "two surfaces are perpendicular" means that the interior angle between them is 80 degrees or more and 100 degrees or less. "Two surfaces are approximately perpendicular" means that the interior angle between them is 60 degrees or more and 120 degrees or less (including perpendicular). "Two surfaces are parallel" means that the interior angle between them is -10 degrees or more and 10 degrees or less. "Two surfaces are approximately parallel" means that the interior angle between them is -30 degrees or more and 30 degrees or less (including parallel).

[0074] Conductive layer 25 is provided on insulating layer 41. Here, an example is shown in which conductive layer 25 has a laminated structure of conductive layer 25a and conductive layer 25b above conductive layer 25a. Furthermore, conductive layer 25 is provided with a slit that overlaps with slit 20, and conductive layer 25 is divided into two at the slit. In other words, a pair of conductive layers 25 is provided on insulating layer 41 so as to sandwich one slit 20 therebetween. Furthermore, as shown in FIG. 4, island-shaped conductive layers 25 are arranged at equal intervals along the extension direction of slit 20.

[0075] The semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have portions located inside the slit 20. The semiconductor layer 21 and the insulating layer 22 are provided along the side surface of the insulating layer 41 and the upper surface of the conductive layer 24 inside the slit 20. The conductive layer 23 is provided so as to fill the recessed portion of the insulating layer 22.

[0076] The semiconductor layer 21 has a portion in contact with the side surface of the conductive layer 25, a portion in contact with the side surface of the insulating layer 41 in the slit 20, and a portion in contact with the top surface of the conductive layer 24b. Here, it is preferable to use a conductive metal oxide similar to the conductive layer 24b for one of the conductive layers 25a and 25b of the conductive layer 25. It is also preferable to use a low-resistance metal material for the other. By stacking a conductive film with low contact resistance with the semiconductor layer 21 and a conductive film with low wiring resistance, it is possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the wiring load. In the following, an example is shown in which a conductive metal oxide is used for the conductive layer 25b and a metal material is used for the conductive layer 25a. However, it is also possible to use a conductive metal oxide for the conductive layer 25a and a metal material for the conductive layer 25b.

[0077] Of the conductive layers 25a and 25b, the conductive film using a conductive metal oxide is preferably configured to further reduce contact resistance by containing the same metal element as the metal element contained in the semiconductor layer 21. Specifically, it is preferable that either the conductive layer 25a or the conductive layer 25b and the semiconductor layer 21 contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti.

[0078] In the transistor 10, the source electrode and the drain electrode are located at different heights, so that a current flows in the semiconductor in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, or the like. Since the transistor 10 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (Lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0079] Furthermore, the channel length of the transistor 10 can be precisely controlled by adjusting the thickness of the insulating layer 41, which functions as a spacer. This significantly reduces the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. This allows for the realization of transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0080] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a high on-state current and an extremely low off-state current can be realized at low cost. Unless otherwise specified, the following describes a configuration example in which an oxide semiconductor is used for the semiconductor layer 21.

[0081] 2 shows an example in which the upper surface of the region of the conductive layer 24b overlapping with the slit 20 has a rounded recess (concave surface). As a result, inside the slit 20, the bottoms of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are each provided along the concave surface of the conductive layer 24b, and have a rounded protrusion (convex surface). This makes it possible to realize a configuration in which the electric field is less likely to concentrate, similar to the conductive layer 51 of the capacitance element 30. As a result, a transistor with low leakage current and high reliability can be realized.

[0082] It is preferable that the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have flattened upper portions and that the heights of their upper surfaces (e.g., heights from the substrate surface) are approximately the same. Furthermore, it is preferable that the heights of the upper surfaces of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are approximately the same as the height of the upper surface of the conductive layer 25 (specifically, the conductive layer 25b). With this configuration, the conductive layer 25 and the conductive layer 23 do not overlap in a planar view, thereby reducing the parasitic capacitance between the conductive layer 25 and the conductive layer 23. This makes it possible to realize a semiconductor device capable of high-speed operation.

[0083] An insulating layer 43 is provided in contact with the upper surface of the conductive layer 25, the upper surface of the semiconductor layer 21, the upper surface of the insulating layer 22, and the upper surface of the conductive layer 23. The insulating layer 43 functions as a barrier film that prevents impurities such as hydrogen from diffusing into the semiconductor layer 21 from above. For example, a film through which hydrogen is less likely to diffuse than in a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0084] Furthermore, the insulating layer 43 preferably includes a stack of an insulating film functioning as a barrier film and an insulating film having a function of capturing or fixing hydrogen, which is located closer to the semiconductor layer 21 than the insulating film. This allows hydrogen that may diffuse into the semiconductor layer 21 due to heat or the like applied during the manufacturing process of the transistor 10 or the memory cell 15 to be captured or fixed by the insulating film, thereby reducing the concentration of hydrogen in the semiconductor layer 21. This makes it possible to realize a highly reliable transistor 10 or semiconductor device 50 with good electrical characteristics. As the insulating film that captures or fixes hydrogen, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, a hafnium zirconium oxide film, or the like is preferably used.

[0085] An insulating layer 44 that functions as an interlayer insulating film is provided on the insulating layer 43. The insulating layer 44 does not have to be provided if it is not necessary.

[0086] A conductive layer 26 functioning as a bit line is provided on the insulating layer 44. A plug 27 is provided through an opening in the insulating layer 44 and the insulating layer 43 to connect the conductive layer 25 and the conductive layer 26. The plug 27 contacts the upper surface of the conductive layer 25 and the lower surface of the conductive layer 26. This allows the conductive layer 26 to connect the multiple conductive layers 25 arranged in the X direction across the slit 20. Furthermore, as shown in FIG. 2, by forming an opening extending to the conductive layer 25b, the plug 27 can be provided so as to contact the conductive layer 25a. This configuration allows the plug 27 to be connected to the conductive layer 25a, which has a lower resistance, thereby reducing the wiring resistance.

[0087] Here, the semiconductor device 50 preferably has a layer in which the memory cells 15 are provided and a layer in which the functional circuits are provided stacked. The functional circuits may include, for example, a drive circuit for driving the memory cells 15, an arithmetic circuit, a power supply circuit, etc. The drive circuit may include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This not only reduces the footprint of the semiconductor chip including the semiconductor device 50, but also shortens the wiring length compared to when the functional circuits and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

[0088] 5 shows an example in which a layer 80 in which a memory cell 15 is provided and a layer 60 in which a transistor 90 constituting a functional circuit is provided are arranged below the layer 80. In this example, one of a source electrode and a drain electrode of the transistor 90 is connected to a conductive layer 26 that functions as a bit line.

[0089] The transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. The substrate 91 can typically be made of single-crystal silicon. Alternatively, the substrate 91 can be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, the substrate 91 can be a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.

[0090] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and a low-resistance region 95a and a low-resistance region 95b functioning as a source region and a drain region. The transistor 90 can be either a p-channel type or an n-channel type. An element isolation layer 98 is provided in the substrate 91 between two adjacent transistors 90.

[0091] The transistor 90 has a semiconductor region 92 in which a channel is formed that has a convex shape (fin shape). Although not shown in Fig. 5, a conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 in the Y direction via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0092] An insulating layer 96 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 96, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 88 is provided covering the conductive layer 81 and the insulating layer 87, an insulating layer 45 is provided on the insulating layer 88, and an insulating layer 11 is provided on the insulating layer 45. A plug 82 is provided inside an opening provided in the insulating layer 96 and the insulating layer 86, and the plug 82 connects the conductive layer 81 to the low-resistance region 95b. A conductive layer 84 is provided on the insulating layer 45, and a plug 83 is provided inside an opening provided in the insulating layer 45 and the insulating layer 88, connecting the conductive layer 84 to the conductive layer 81. The conductive layer 84 and the conductive layer 26 are connected via a plug 85 provided inside an opening provided in each insulating layer between them. This connects one of the source and drain of the transistor 90 to the conductive layer 26.

[0093] Although an example in which the conductive layer 81 is provided as a wiring layer on the layer 60 has been shown, the present invention is not limited to this. For example, the layer 60 may have a structure in which interlayer insulating layers and wiring layers are alternately stacked on top of each other (also referred to as a multi-layer wiring layer).

[0094] 5, an insulating layer 47 is provided on the layer 80. That is, the layer 80 is disposed between the insulating layers 45 and 47.

[0095] The above-described films having a barrier property against hydrogen can be used for the insulating layers 45 and 47. In particular, a silicon nitride film or a silicon nitride oxide film is preferably used.

[0096] Furthermore, the insulating layer 45 and the insulating layer 47 preferably have a stacked structure in which an insulating film functioning as the above-described barrier film and an insulating film having a function of capturing or fixing hydrogen are stacked inside the insulating film (on the transistor 10 side). For example, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, a hafnium zirconium oxide film, or the like is preferably used.

[0097] This makes it possible to suppress the diffusion of hydrogen from the outside into the region sandwiched between insulating layers 45 and 47. Furthermore, it is possible to reduce the hydrogen concentration inside this region. This effectively reduces the amount of hydrogen that can diffuse into semiconductor layer 21 of transistor 10, thereby realizing a highly reliable transistor 10.

[0098] 6 shows an example in which layers 80 each having a memory cell 15 are stacked. In FIG. 6, an example in which three layers 80 (layers 80[1] to [3] from the substrate 91 side) are stacked is shown, but two layers or four or more layers may be stacked.

[0099] The plug 85 connects the conductive layer 84 and the conductive layer 26 of the layer 80[1]. The plug 89 connects the conductive layers 26 of the two layers 80 together. As a result, the three conductive layers 26 of the layers 80[1] to 80[3] are connected to one of the source and drain of the transistor 90.

[0100] The insulating layer 47 is provided on the layer 80[3]. However, the present invention is not limited to this, and an insulating layer 47 may be provided for each layer 80.

[0101] Although the configuration shown here is one in which the layer 80 is stacked directly on the substrate 91 on which the transistor 90 is provided, this is not limiting. For example, the substrate 91 on which the transistor 90 is provided and the substrate on which the memory cell 15 is provided may be bonded together. For example, the two substrates may be bonded together by direct bonding (hybrid bonding) using a direct bonding technique, such as Cu-Cu bonding. Alternatively, a method may be used in which two or more layers are bonded together with their insulating surfaces facing each other, and then through-hole electrodes are formed to connect the electrodes provided on each layer. In particular, the use of direct bonding or through-hole electrodes allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at high density, which is preferable because it increases the amount of data transmitted between layers.

[0102] When bonding two layers, any of the following methods can be used: CoC (Chip on Chip) bonding, CoW (Chip on Wafer) bonding, and WoW (Wafer on Wafer) bonding. WoW bonding is highly productive because it bonds wafers together, but it can reduce yields because all chips, including both good and bad, must be bonded together. On the other hand, CoW bonding, which bonds chips to wafers, and CoC bonding, which bonds chips together, are inferior to WoW bonding in terms of productivity, but their ability to bond good chips together significantly improves yields. CoC bonding is also less productive than the other two methods, but is highly versatile because it can bond two layers even when the sizes are significantly different.

[0103] A wiring layer such as an interposer may be provided between the two layers, which eliminates the need to align the positions of bonding electrodes between two adjacent layers, allowing for greater freedom in the design of each layer and enabling the realization of a higher performance semiconductor device.

[0104] 7 shows an example in which a layer 60 having a memory cell 16 that can be used as a DRAM (Dynamic Random Access Memory) is stacked with a layer 80. The memory cell 16 has a transistor 90 and a capacitor 70.

[0105] One of a source electrode and a drain electrode of the transistor 90 is connected to a bit line, and the other is connected to a capacitor 70. The capacitor 70 includes a conductive layer 71, a conductive layer 73, and an insulating layer 72 sandwiched between them. Figure 7 shows a structure including a pillar-shaped conductive layer 71, and the insulating layer 72 and conductive layer 73 provided to cover the conductive layer 71.

[0106] 7 shows an example in which a common bit line is connected to two transistors 90. With this configuration, memory cells can be arranged at high density.

[0107] 7 shows an example in which layer 80 is laminated directly on layer 60, but layers 60 and 80 may be fabricated separately and then bonded together. In this case, the order in which layers 60 and 80 are laminated does not matter, and layer 60 may be laminated on layer 80. Furthermore, the orientation of layers 80 and 60 does not matter, and the bonding surface may be the substrate side (the surface to be formed on), or the surface opposite the substrate side.

[0108] [About the components] <substrate> Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of other substrates include an insulating substrate with a conductive layer or semiconductor layer, a semiconductor substrate with a conductive layer or insulating layer, and a conductive substrate with a semiconductor layer or insulating layer. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor, a resistor, a switch element (including a transistor), a light-emitting element, a memory element, and the like.

[0109] Semiconductor layer The semiconductor layer 21 preferably includes a metal oxide (oxide semiconductor).

[0110] Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0111] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and compositions close to these. Note that a close composition includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0112] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0113] The semiconductor layer 21 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, or In-Ga-Al-Zn oxide. Ga-Zn oxide may also be used. Materials that do not contain Zn, such as indium oxide, are preferred because they enhance compatibility with LSI manufacturing processes. On the other hand, materials that contain Zn are preferred because they facilitate high crystallinity.

[0114] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0115] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0116] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). It is particularly preferable to form the metal oxide film by ALD, which has excellent coating properties. When forming the metal oxide by sputtering, the composition of the formed metal oxide film may differ from that of the target. In particular, the zinc content in the formed metal oxide film may decrease to about 50% of that of the target.

[0117] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then X , A Y , A Z When the content of metal element X is X / (A X +A Y +A Z ) In addition, the ratio of the number of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is B X :B Y :B Z When the content of the metal element X is expressed as B X / (B X +B Y +B Z ) can be shown as

[0118] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0119] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0120] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. In other words, a transistor with a small threshold voltage variation in NBTIS (Negative Bias Temperature Illumination Stress) testing can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, which can reduce the threshold voltage variation in the NBTIS testing of the transistor.

[0121] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0122] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical properties and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0123] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) for the second layer, i.e., the side closer to the gate electrode, than for the first layer. This allows for a normally-off transistor with a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than the second layer may be used for the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0124] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby achieving a transistor with a high on-current and high reliability.

[0125] The differences in mobility and conductivity described above can be expressed, for example, by differences in the indium content. Furthermore, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect mobility and conductivity. Examples of high-mobility materials include materials with an atomic ratio of In:Ga:Zn=4:2:3 and its vicinity, materials with an atomic ratio of In:Zn=1:1 and its vicinity, materials with an atomic ratio of In:Zn=2:1 and its vicinity, materials with an atomic ratio of In:Zn=4:1 and its vicinity, and materials with an atomic ratio of In:Sn:Zn=40:X:10 (where X is 0.1 or more and 5 or less, typically X=1) and its vicinity. On the other hand, materials with lower mobility or conductivity compared to the above-mentioned materials include materials with an atomic ratio of In:Ga:Zn=1:3:2 and its vicinity, materials with an atomic ratio of In:Ga:Zn=1:3:4 and its vicinity, materials with an atomic ratio of In:Ga:Zn=2:2:1 and its vicinity, materials with an atomic ratio of In:Ga:Zn=1:1:1 and its vicinity, and materials with an atomic ratio of In:Ga:Zn=1:1:2 and its vicinity.

[0126] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystal (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0127] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0128] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has a significantly smaller source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can retain charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0129] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0130] A semiconductor device according to one embodiment of the present invention can also be applied to, for example, a display device. To increase the light emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher source-drain breakdown voltage than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light emission luminance of the light-emitting device.

[0131] When the transistor operates in the saturation region, OS transistors can reduce the change in source-drain current relative to a change in gate-source voltage compared to Si transistors. Therefore, by using OS transistors as the drive transistors in pixel circuits, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0132] As described above, by using an OS transistor for the drive transistor included in the pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission brightness," "multiple gradations," and "suppression of the effects of manufacturing variations in light-emitting devices."

[0133] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0134] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0135] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0136] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable to the semiconductor layer of a transistor include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0137] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0138] <Gate insulating layer> The insulating layer 22 functions as a gate insulating layer of the transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least a film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. In addition, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0139] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials having a high relative dielectric constant, and preferably by using a laminate structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order. Alternatively, the insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By laminating an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0140] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0). X Metal oxides with Y (yttrium) added to HfZrO can also be used. XThe addition of Y to the compound can enhance the ferroelectricity.

[0141] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0142] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0143] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0144] When the insulating layer 22 has a three-layer structure, it is preferable that an insulating film made of a material through which oxygen easily diffuses is used for the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen is used for the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen is used for the film located between them. Silicon oxide or silicon oxynitride can be used as the material through which oxygen easily diffuses. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0145] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0146] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, followed by an insulating film made of a material through which oxygen easily diffuses, an insulating film having a function of capturing or fixing hydrogen, and an insulating film having a barrier property against hydrogen and oxygen, in order from the side closer to the semiconductor layer 21. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, oxygen can be prevented from being released from the semiconductor layer 21. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21.

[0147] When the insulating layer 22 has a laminated structure, each insulating film is preferably a thin film. For example, by making the thickness of the insulating layer 22 1 nm to 20 nm, preferably 3 nm to 10 nm, the subthreshold swing value (also referred to as the S value) of the transistor can be reduced. Furthermore, the thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0148] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0149] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Furthermore, oxygen when described as corresponding substances refers to at least one of, for example, oxygen atoms, oxygen molecules, etc.

[0150] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include insulating films containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and the insulating films can be used in a single layer or a stacked layer. Specifically, examples of materials that can be used for the insulating film that has a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0151] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0152] Examples of insulating film materials capable of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, silicon may be added to these oxides to achieve an amorphous structure. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Metal oxides may have crystalline regions and / or grain boundaries.

[0153] <Conductive layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0154] As the conductive film in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferable.

[0155] Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide materials such as In-Ga-Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0156] For example, the conductive layer 24 and the conductive layer 25 can each have a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0157] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element, may be used. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0158] Furthermore, the conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 described above.

[0159] The conductive layer 23, the conductive layer 24, and the conductive layer 25 also function as wirings, and therefore are preferably formed by stacking low-resistance conductive materials. For example, the conductive layer 24a1, the conductive layer 24a2, and the conductive layer 25b can also be formed using the low-resistance conductive material that can be used for the conductive layer 23. Note that the conductive layer 24a2 may be formed using a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material.

[0160] <Insulating layer> The insulating layer 41 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0161] The insulating layer 41 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. The insulating layer 41 can be an oxide insulating film that can be used for the above gate insulating layer.

[0162] Furthermore, since the insulating layer 41 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a higher film formation rate than other insulating layers. For example, the insulating layer 41 may be a silicon oxide film (also called a TEOS film) formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) using a plasma CVD method. This can improve productivity.

[0163] The insulating layer 11, the insulating layer 42, the insulating layer 44, the insulating layer 46, and the insulating layer 47 each function as an interlayer insulating layer. The insulating layer 11, the insulating layer 42, the insulating layer 44, the insulating layer 46, and the insulating layer 47 can be made of the same insulating material as can be used for the insulating layer 41.

[0164] The insulating layer 52 functions as a dielectric for the capacitive element 30. The insulating layer 52 can be made of the same insulating material as the insulating layer 22. For example, an insulating material made of a high-k material that can be used for the insulating layer 22 can be used. It is also preferable to use a laminated structure of a high-k material with a high relative dielectric constant and a material with a higher dielectric strength than the high-k material. By using the ferroelectric material for the insulating layer 52, the capacitive element 30 can be a ferroelectric capacitor, thereby realizing a nonvolatile memory device. A resistance-change memory element utilizing the colossal electric-field-induced resistance change (CER) effect can also be used as the capacitive element 30.

[0165] This concludes the description of the components.

[0166] [Variations] An example in which the configuration is partially different from the above configuration example will be described below. Note that the same reference numerals are used to designate the same parts as those described above, and the description thereof will be omitted.

[0167] [Variation 1] The configuration shown in FIG. 8 differs from the above-described configuration example mainly in that the shapes of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are different.

[0168] 8, semiconductor layer 21 has a portion that contacts the upper surface of conductive layer 25b. Insulating layer 22 is provided to cover semiconductor layer 21, and has a portion that overlaps conductive layer 25b with semiconductor layer 21 interposed therebetween. Therefore, in the configuration shown in FIG. 8, semiconductor layer 21 and insulating layer 22 do not have flattened upper surfaces.

[0169] The upper surface of conductive layer 23 is positioned lower than the height of the upper surface of conductive layer 25b. This makes it possible to reduce the parasitic capacitance between conductive layer 23 and conductive layer 26 and the parasitic capacitance between conductive layer 23 and conductive layer 25. For example, if the upper part of conductive layer 23 is removed by etching instead of planarization, the height of the upper surface of conductive layer 23 can be lowered by performing over-etching.

[0170] Here, if the height of the upper surface of conductive layer 23 is made lower than the height of the lower surface of conductive layer 25, a so-called offset region can be formed in which a gate electric field is not applied to semiconductor layer 21. On the other hand, if the height of the upper surface of conductive layer 23 is made higher than the lower surface of conductive layer 25, no offset region is formed, and a transistor with a high on-current can be realized. The height of the upper surface of conductive layer 23 can be adjusted according to the required transistor characteristics.

[0171] [Variation 2] The configuration shown in FIG. 9 differs from the above-described configuration example mainly in that the shape of the conductive layer 51 of the capacitive element 30 is different and that the insulating layer 41 has a laminated structure.

[0172] 9, the upper end of the conductive layer 51 is located below the upper surface of the insulating layer 46, and the upper ends of the conductive layer 51 and the insulating layer 46 each have a rounded shape. By configuring the conductive layer 51 and the insulating layer 46, which form the surface on which the insulating layer 52 is to be formed, to have no corners, the coverage of the insulating layer 52 is improved and it is possible to prevent the insulating layer 52 from becoming locally thin. This makes it possible to suppress the leakage current of the capacitor element 30, thereby improving reliability.

[0173] 9 shows an example in which the insulating layer 41 has a laminated structure in which an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c are laminated in this order from the insulating layer 52 side.

[0174] The semiconductor layer 21 is provided in contact with the inner wall of the insulating layer 41 within the slit 20. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c that have a barrier property against oxygen. This makes it possible to confine oxygen contained in the insulating layer 41b in a region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. Furthermore, it is possible to prevent oxygen in the insulating layer 41b from being desorbed and reduced during the process. This makes it possible to more efficiently supply oxygen to the semiconductor layer 21.

[0175] The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b is a region with reduced oxygen vacancies and can be considered an i-type region. On the other hand, the portion that is not in contact with the insulating layer 41b is preferably an n-type region that contains many carriers. That is, the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b can be called a channel formation region, and the region outside of that can be called a low-resistance region (also called a source region or a drain region).

[0176] The insulating layer 41b is preferably a film containing as little hydrogen as possible because it is in contact with the semiconductor layer 21. Carriers are generated when oxygen vacancies in the semiconductor layer 21 combine with hydrogen, which may affect the threshold voltage of the transistor 10, for example. Therefore, an insulating film other than an oxide insulating film through which hydrogen does not easily diffuse may be used as the insulating layer 41b. For example, a single layer of an insulating film having a barrier property against hydrogen and oxygen may be used as the insulating layer 41.

[0177] Because the semiconductor layer 21 and the insulating layer 22 are formed along the inner walls of the slits 20 in the insulating layer 41, the thickness of these portions may be thin depending on the film formation method. For example, with film formation methods such as sputtering or plasma CVD, films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface. On the other hand, with film formation methods such as atomic layer deposition (ALD) or thermal CVD, films of uniform thickness can be formed regardless of the angle of the surface on which they are formed. For example, when the angle of the sidewalls of the slits 20 in the insulating layer 41 relative to the substrate surface is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0178] The insulating layer 41b can be used as an interlayer insulating film. For example, it is preferable to form the insulating layer 41b by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. This can suppress the supply of hydrogen to the semiconductor layer 21, thereby stabilizing the electrical characteristics of the transistor 10.

[0179] The insulating layer 41b is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the above gate insulating layer can be used as the insulating layer 41b.

[0180] Furthermore, since the insulating layer 41b functions as an interlayer insulating layer, it is preferable to use a film formation method that allows for film formation at a higher film formation rate than other insulating layers. For example, an insulating film formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) by plasma CVD may be used as the insulating layer 41. This can improve productivity.

[0181] It is preferable that the insulating layers 41a and 41c are made of films that do not easily diffuse hydrogen. By sandwiching the insulating layer 41b between the insulating layers 41a and 41c, which do not easily diffuse hydrogen, it is possible to prevent external hydrogen from entering the insulating layer 41b that contacts the semiconductor layer 21.

[0182] For example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used for the insulating layer 41a and the insulating layer 41c. Silicon nitride and silicon nitride oxide in particular have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and are therefore suitable for use as the insulating layer 41a and the insulating layer 41c.

[0183] [Variation 3] Alternatively, the memory cell 15 may have a structure as shown in FIGS.

[0184] 10 and 11, the conductive layer 55 may have a stacked structure of a conductive layer 55a and a conductive layer 55b on the conductive layer 55a. The conductive layer 55a is provided along the opening in the insulating layer 53, and the conductive layer 55b is provided to fill the recess of the conductive layer 55a. The conductive layer 55a may be made of a conductive material that is resistant to oxidation and maintains low electrical resistance even when oxidized, which can be used for the conductive layer 24a2, etc. The conductive layer 55b may be made of a low-resistance conductive material that can be used for the conductive layer 24a1, etc.

[0185] As shown in FIGS. 10 and 11, the conductive layer 55 can be provided extending in the Y direction to function as wiring.

[0186] As shown in FIGS. 10 and 11 , the insulating layer 46 may have a stacked structure of an insulating layer 46a, an insulating layer 46b on the insulating layer 46a, and an insulating layer 46c on the insulating layer 46b. The insulating layer 46a may be made of the same material and have the same structure as the insulating layer 41a, the insulating layer 46b may be made of the same material and have the same structure as the insulating layer 41b, and the insulating layer 46c may be made of the same material and have the same structure as the insulating layer 41c. Furthermore, a sidewall-shaped insulating layer 48 may be provided in contact with the sidewall of the opening 40. The insulating layer 48 may be made of the same material as the insulating layers 41a and 41c. By using films that are less susceptible to hydrogen diffusion for the insulating layers 41a, 41c, and 48, hydrogen contained in the insulating layer 41b can be prevented from diffusing into the semiconductor layer 21 via the capacitor element 30.

[0187] 10 and 11, the conductive layer 24a1 can also have a laminated structure. The conductive layer 24a1 preferably has a lower layer made of a conductive material that is resistant to oxidation and maintains low electrical resistance even when oxidized, and an upper layer made of a low-resistance conductive material. For example, the conductive layer 24a1 can have a laminated structure made of a titanium nitride film and a tungsten film on the titanium nitride film.

[0188] As shown in FIGS. 10 and 11 , the conductive layer 24b, the conductive layer 24a1, and the insulating layer 52 may be configured so that their top surface shapes are generally the same. Here, it is preferable that the side surfaces of the conductive layer 24b, the side surfaces of the conductive layer 24a1, and the side surfaces of the insulating layer 52 are flush with each other. That is, it is preferable that the conductive layer 24b, the conductive layer 24a1, and the insulating layer 52 are etched using the same mask pattern. When attempting to provide a plug 85 penetrating multiple interlayer films, as in the configuration shown in FIG. 5 , the presence of the insulating layer 52 may make etching more difficult. In contrast, by forming the insulating layer 52 in an island shape as described above, it is not necessary to etch the insulating layer 52 when providing the plug 85. This improves the productivity of semiconductor devices.

[0189] As shown in FIGS. 10 and 11, the insulating layer 41a can also be formed so that its upper surface is flat. In this case, the insulating layer 41a is formed so as to fill the region that does not overlap with the conductive layer 24, and the insulating layer 41a is subjected to CMP processing to flatten the upper surface of the insulating layer 41a. With this structure, the structure above the insulating layer 41a is not affected by steps caused by the structure of the conductive layer 24, thereby improving the productivity of the semiconductor device. In this case, as shown in FIGS. 10 and 11, the film thickness of the insulating layer 41a in the region that overlaps with the insulating layer 46 is thicker than the film thickness of the insulating layer 41a in the region that overlaps with the conductive layer 24.

[0190] 10 and 11, a structure in which part of the semiconductor layer 21, part of the insulating layer 22, and part of the conductive layer 23 are located on the conductive layer 25 may also be used. In this case, the semiconductor layer 21 and the insulating layer 22 may be provided overlapping the conductive layer 25. Furthermore, as shown in FIG. 11, it is preferable that the semiconductor layer 21 be provided on and in contact with the conductive layer 24b and not extend beyond the conductive layer 24b. This allows the semiconductor layer 21 to be in contact with the insulating layer 41a, preventing oxygen from being extracted from the semiconductor layer 21 by the insulating layer 41a. However, the present invention is not limited to this, and a structure in which the semiconductor layer 21 covers the conductive layer 24b and is in contact with the upper surface of the insulating layer 41a may also be used.

[0191] 10, it is preferable to make the portion of conductive layer 23 above conductive layer 25 smaller than semiconductor layer 21, so that the area where conductive layer 23 overlaps the upper surface of conductive layer 25 is small. With this configuration, the parasitic capacitance of conductive layer 23 and conductive layer 25 can be reduced. Also, as shown in FIG. 10, a recess may be formed in the center of conductive layer 23b, and insulating layer 43 and insulating layer 44 may be formed up to the inside of this recess. Alternatively, only insulating layer 43 may be formed in this recess.

[0192] 10 and 11, the conductive layer 23 may have a stacked structure of a conductive layer 23a and a conductive layer 23b on the conductive layer 23a. The conductive layer 23a may be made of a conductive material that is resistant to oxidation and maintains low electrical resistance even when oxidized, which can be used for the conductive layer 24a2, etc. The conductive layer 23b may be made of a low-resistance conductive material that can be used for the conductive layer 24a1, etc.

[0193] [Variation 4] 2 and other figures show a configuration in which a plurality of transistors 10 are arranged in a slit 20 extending in the Y direction, but the present invention is not limited to this. For example, as shown in Figures 12 and 13, an opening 20a may be formed in the insulating layer 41, and one transistor 10 may be provided in the opening 20a.

[0194] The opening 20a is formed in the insulating layer 41 and the conductive layer 25. Like the opening 40, the opening 20a is preferably a vertical hole with a large aspect ratio. A plurality of the openings 20a are preferably arranged in the Y direction. With this configuration, a plurality of transistors 10 can be arranged in the Y direction, similar to the structure shown in FIG. 2.

[0195] 12 and 13, the conductive layer 25 is not divided by the opening 20a. That is, the conductive layer 25 is provided extending in the X direction and functions as a bit line.

[0196] 12 and 13, the semiconductor layer 21 can also be provided extending in the X direction. The semiconductor layer 21 may be provided on the conductive layer 25, and within the opening 20a, it is provided along the opening 20a. In the configuration shown in FIG. 2 and other figures, the semiconductor layer 21 is processed into an island shape within the slit 20 to isolate the semiconductor layer 21 from the semiconductor layer 21 of an adjacent transistor 10. In contrast, in the configuration shown in FIGS. 12 and 13, the semiconductor layer 21 can be processed outside the opening 20a, eliminating the need for highly accurate processing. This improves the productivity of the semiconductor device.

[0197] 13, the insulating layer 22 can be formed to cover the outer side surfaces of the semiconductor layer 21 and the outer side surfaces of the conductive layer 25. In the example shown in FIG.

[0198] 12 and 13, the upper portion of the conductive layer 23 may be positioned in an opening provided in the insulating layer 44, so that the upper surfaces of the insulating layer 44 and the conductive layer 23 are flush with each other. A portion of the insulating layer 43 may be provided between the insulating layer 44 and the conductive layer 23. Preferably, a conductive layer 29 is provided on the conductive layer 23 and the insulating layer 44. The conductive layer 29 extends in the Y direction and is connected to the conductive layer 23. That is, the conductive layer 29 functions as a word line. The conductive layer 29 may be made of the same material as the conductive layer 26.

[0199] By providing the conductive layer 29 as described above, the distance between the conductive layer 29 and the conductive layer 25 can be increased, and the parasitic capacitance between the conductive layer 29 and the conductive layer 25 can be reduced. In addition, by providing the conductive layer 23 as described above, the overlapping area between the conductive layer 23 and the conductive layer 25 can be reduced, and the parasitic capacitance between the conductive layer 23 and the conductive layer 25 can be reduced.

[0200] The above is a description of the modified example.

[0201] [Example of manufacturing method] An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below, taking as an example a semiconductor device including the memory cell 15 exemplified in the above structure example.

[0202] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0203] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0204] Sputtering methods include RF sputtering, which uses a high-frequency power source for sputtering; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferred for film formation using insulating targets. DC sputtering is primarily used for film formation using conductive targets. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0205] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0206] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0207] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0208] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. ALD, in particular, has excellent step coverage and thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0209] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0210] In the ALD method, films of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, films of any composition can be formed by controlling the number of cycles of each precursor. Also, like the CVD method, films with continuously changing compositions can be formed.

[0211] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0212] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0213] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as light for exposure. Instead of light for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0214] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0215] 14(A) to 21(B) are schematic cross-sectional views corresponding to each step in the fabrication method exemplified below. In each figure, the cross section corresponding to FIG. 2 is shown on the left side of the dashed dotted line, and the cross section corresponding to FIG. 3 is shown on the right side.

[0216] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0217] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0218] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which insulating layer 11 is to be formed is not flat, a planarization process may be performed after insulating layer 11 is formed so that the upper surface of insulating layer 11 becomes flat.

[0219] Next, a conductive film that will become the conductive layer 55 is formed on the insulating layer 11. The conductive film can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. Next, a resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching, thereby forming the conductive layer 55. The conductive layer 55 can be formed in a plate-like, line-like, or lattice-like shape.

[0220] Subsequently, an insulating film may be formed to cover the conductive layer 55, and then planarization may be performed until the upper surface of the conductive layer 55 is exposed. This allows the conductive layer 55 to be embedded in an insulating layer (not shown). Note that although an example in which an insulating layer (not shown) is formed after the conductive layer 55 has been shown here, the conductive layer 55 and the insulating layer may also be formed by forming an insulating film, forming an opening (or a recess) in the insulating film for embedding the conductive layer 55, forming a conductive film that will become the conductive layer 55, and then performing planarization until the surface of the insulating film is exposed. For the planarization, for example, CMP (Chemical Mechanical Polishing), dry etching, or the like may be used.

[0221] Subsequently, the insulating layer 46 is formed on the conductive layer 55 (FIG. 14(A)). The insulating layer 46 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0222] In addition, when the conductive layer 55 is not embedded in an insulating layer (not shown), after the insulating layer 46 is formed, an uneven shape reflecting the shape of the conductive layer 55 may be formed on the upper surface of the insulating layer 46. In this case, it is preferable to perform a planarization treatment on the upper surface of the insulating layer 46.

[0223] Next, an opening 40 is formed in the insulating layer 46, reaching the conductive layer 55 (FIG. 14(B)). At this time, a part of the upper surface of the conductive layer 55 may be etched. It is preferable to perform etching so that a curved surface is formed on the upper part of the conductive layer 55.

[0224] Next, a conductive film 51f that will become the conductive layer 51 is formed to cover the upper surface of the insulating layer 46, the side surfaces of the insulating layer 46 in the opening 40, and the upper surface of the conductive layer 55 (FIG. 14(C)). The conductive film 51f can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoint of coverage, it is particularly preferable to form the conductive film 51f by a CVD method.

[0225] A sacrificial layer is formed on the conductive film so as to cover the recess of the opening 40, and a planarization process is performed until the upper surface of the insulating layer 46 is exposed. The sacrificial layer is then removed, thereby forming a conductive layer 51 that is located only inside the opening 40 (Figure 15(A)).

[0226] Here, during the planarization process or removal of the sacrificial layer, the height of the upper surface of the conductive layer 51 may become lower than the upper surface of the insulating layer 46. Also, the corners of the upper end of the conductive layer 51 and the upper end of the opening 40 of the insulating layer 46 may be scraped and rounded. This results in the configuration shown in FIG.

[0227] Next, an insulating layer 52 is formed along the surfaces of the insulating layer 46 and the conductive layer 51. The insulating layer 52 can be formed by a film formation method such as sputtering, ALD, or CVD, but ALD is preferable from the viewpoint of coverage. Next, a conductive film 24a1f that will become the conductive layer 24a1 is formed on the insulating layer 52 so as to fill the recess in the opening 40 of the insulating layer 46 (FIG. 15(B)). The conductive film 24a1f can be formed by a film formation method such as sputtering, ALD, or CVD. A CVD method (metal CVD) that has high embeddability is preferably used to form the conductive film 24a1f. By using such a method, the conductive film 24a1f can be formed by filling the opening 40, which has a high aspect ratio.

[0228] Next, a conductive film 24a2f that will become the conductive layer 24a2 is formed on the conductive film 24a1f (FIG. 15(C)). The conductive film 24a2f can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. As described above, it is preferable to use a conductive film that has the function of suppressing oxidation of the conductive film 24a1f, such as a conductive nitride, for the conductive film 24a2f. The conductive film 24a2f preferably fills a recess formed in the upper surface of the conductive film 24a1f at a position that overlaps with the opening 40. Because the recess in the upper surface of the conductive film 24a1f is shallower than the opening 40, it is preferable to use a CVD method (metal CVD method) or an ALD method for forming the conductive film 24a1f. Furthermore, if a metal CVD method or the like is used to form the conductive film 24a1f, the unevenness of the upper surface of the conductive film 24a1f may become large, resulting in a decrease in flatness of the upper surface. In this case as well, the unevenness on the upper surface of the conductive film 24a1f can be filled in with the conductive film 24a2f.

[0229] Next, CMP processing is performed until at least a portion of the upper surface of conductive film 24a1f is exposed (FIG. 16(A)). As a result, a portion of conductive film 24a2f remains in the recessed portion of the upper surface of conductive film 24a1f, forming conductive layer 24a2. As shown in FIG. 16(A), the upper surfaces of conductive film 24a1f and conductive layer 24a2 that have been subjected to CMP processing have high flatness. The heights of the upper surfaces of conductive film 24a1f and conductive layer 24a2 are approximately the same.

[0230] Next, a conductive film 24bf, which will become the conductive layer 24b, is formed on the conductive film 24a1f and the conductive layer 24a2 (FIG. 16(B)). The conductive film 24bf can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. As described above, the upper surfaces of the conductive film 24a1f and the upper surface of the conductive layer 24a2, i.e., the surfaces on which the conductive film 24bf is formed, have high flatness, and therefore the flatness of the conductive film 24bf can be improved.

[0231] Next, a resist mask is formed on the conductive film 24bf, and unnecessary portions of each conductive film are removed by etching to form the conductive layer 24 including the conductive layer 24a1, the conductive layer 24a2, and the conductive layer 24b (FIG. 16(C)). At this point, the capacitor element 30 can be formed. Here, it is preferable that the lower surface of the conductive layer 24b contacts the upper surface of the conductive layer 24a1 and the upper surface of the conductive layer 24a2. By configuring the conductive layer 24b to contact the conductive layer 24a1, which has a lower electrical resistance, the conductivity can be improved.

[0232] When forming the capacitor element 30 shown in FIGS. 10 and 11 , the insulating layer 52 may be formed in an island shape to match the conductive layer 24. Forming the insulating layer 52 in an island shape prevents the insulating layer 52 from excessively expanding. As described above, a high-k material is preferably used for the insulating layer 52, but such materials may be difficult to etch. When attempting to form a plug 85 penetrating multiple interlayer films, as in the configuration shown in FIG. 5 , the presence of the insulating layer 52 increases the difficulty of etching. In contrast, forming the insulating layer 52 in an island shape as described above eliminates the need to etch the insulating layer 52 when forming the plug 85. This improves the productivity of semiconductor devices. Furthermore, the insulating layer 52 and the conductive layer 24 can be collectively etched using the same mask pattern, thereby improving the productivity of semiconductor devices.

[0233] Subsequently, an insulating layer 41 is formed to cover the conductive layer 24, and a planarization process is performed on the upper surface of the insulating layer 41. The insulating layer 41 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0234] The insulating layer 41 is preferably an oxide film containing a large amount of oxygen to the extent that oxygen is released by heating, and a small amount of hydrogen. The insulating layer 41 can be formed by a film formation method such as PECVD, sputtering, or ALD, but is preferably formed by sputtering. In particular, by forming the insulating layer 41 using a gas containing oxygen instead of a gas containing hydrogen, an insulating film containing an extremely small amount of hydrogen and an excess amount of oxygen can be formed. By forming the insulating layer 41 in this manner, oxygen can be supplied from the insulating layer 41 to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0235] Subsequently, heat treatment may be performed. The heat treatment is preferably performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 and the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0236] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 41 and the like as much as possible.

[0237] A process for supplying oxygen may be performed after the insulating layer 41 is formed, so that oxygen can be supplied from the insulating layer 41 to the semiconductor film 21f later by heat or the like applied after the semiconductor film 21f is formed.

[0238] Examples of treatments for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) by sputtering in an oxygen-containing atmosphere. The formed oxide film may be removed immediately or may be left as is. Note that the oxygen-containing atmosphere includes not only oxygen gas (O2) but also atmospheres containing gases of oxygen-containing compounds such as ozone (O3) and dinitrogen monoxide (NO).

[0239] Next, a conductive film 25af that will become the conductive layer 25a and a conductive film 25bf that will become the conductive layer 25b are stacked and formed (FIG. 17(A)) on the insulating layer 41. The conductive films 25af and 25bf can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0240] Next, a resist mask is formed on the conductive film 25bf, and unnecessary portions of each conductive film are removed to form the conductive layer 25a and the conductive layer 25b. Next, an insulating film that will become the insulating layer 42 is formed, and a planarization process is performed until the top surface of the conductive layer 25b is exposed, thereby forming the insulating layer 42 (FIG. 17(B)). This allows the conductive layer 25a and the conductive layer 25b to be embedded in the insulating layer 42.

[0241] Next, a resist mask is formed on the conductive layer 25b and the insulating layer 42, and a slit 20 is formed in the conductive layer 25b, the conductive layer 25a, the insulating layer 42, and the insulating layer 41 (FIG. 18(A)). When forming the slit 20, it is preferable to etch a portion of the conductive layer 24b located at the bottom of the slit 20 to form a recess in the conductive layer 24b. At this time, it is preferable to perform etching so that a concave curved surface is formed on the upper part of the conductive layer 24b. Furthermore, as shown on the right side of FIG. 18(A), it is preferable that a concave curved surface is also formed on the upper surface of the insulating layer 41 located at the bottom of the slit 20 in the portion where the conductive layer 24b is not provided.

[0242] Here, by forming the conductive layer 24b in a highly flat shape as described above, it is possible to prevent the formation of an opening in the conductive layer 24b that reaches the conductive layer 24a by the etching, which prevents the semiconductor layer 21 containing metal oxide, which is formed in a later step, from coming into contact with the highly conductive conductive layer 24a2 and extracting oxygen from the semiconductor layer 21 into the conductive layer 24a2.

[0243] When forming the slits 20, it is preferable to process the slits 20 by anisotropic dry etching so that the side walls of the slits 20 (the side surfaces of the conductive layers 25b, 25a, insulating layer 42, and insulating layer 41) are approximately perpendicular to the surface on which they are formed. Depending on the processing conditions, the side walls of the slits 20 may be inclined with respect to the direction perpendicular to the surface on which they are formed, resulting in a tapered shape.

[0244] Subsequently, a semiconductor film 21f that becomes the semiconductor layer 21 is formed to cover the upper and side surfaces of the conductive layer 25b, the side surfaces of the conductive layer 25a, the side surfaces and upper surface of the insulating layer 41, and the upper surface of the conductive layer 24b.

[0245] The semiconductor film 21f may be a metal oxide (oxide semiconductor) film having semiconductor properties. The metal oxide film may be formed by a suitable method such as sputtering, CVD, MBE, PLD, or ALD. The metal oxide film is preferably formed in contact with the substantially vertical side surfaces of the insulating layer 41. Therefore, the metal oxide film is preferably formed by a method with good coverage, and more preferably by ALD.

[0246] The metal oxide film preferably has crystallinity. In particular, the metal oxide film of one embodiment of the present invention preferably contains a metal oxide having a CAAC structure.

[0247] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0248] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity after each metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0249] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering can be used for each. In particular, forming the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also called "mixing"). This is particularly suitable when the element contained in the layer constituting the surface to be formed inhibits crystallization of the metal oxide (for example, when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. While a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited to this. The same process can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0250] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0251] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0252] When performing a treatment to enhance the crystallinity of a metal oxide film, the temperature of the heat treatment (or the temperature of the substrate) is preferably set to room temperature (e.g., 25°C) or higher, 100°C to 700°C, 100°C to 600°C, or 300°C to 450°C. By setting the temperature within the above range, deformation (distortion or warpage) of the substrate can be significantly reduced even when the heat treatment is performed. Furthermore, the release of hydrogen in the metal oxide film as hydrogen molecules or water molecules can be promoted.

[0253] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0254] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0255] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0256] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0257] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0258] The conditions for forming the metal oxide film include a substrate temperature of room temperature or higher and 250° C. or lower, preferably room temperature or higher and 200° C. or lower, and more preferably room temperature or higher and 140° C. or lower. For example, a substrate temperature of room temperature or higher and lower than 140° C. is preferred because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0259] When using the ALD method, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it not only exhibits high step coverage but also allows for low-temperature film formation.

[0260] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0261] For example, when forming an In-Ga-Zn oxide film, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and a gallium- and zinc-containing precursor.

[0262] Examples of precursors that can be used that contain indium include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0263] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0264] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0265] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0266] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, it is also possible to deposit a film whose composition changes continuously. It is also possible to deposit two or more films with different compositions consecutively.

[0267] After the metal oxide film is formed, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, preferably 250°C to 650°C, more preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0268] The gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment is set to 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, moisture and the like can be prevented from being incorporated into the metal oxide film as much as possible.

[0269] Although the semiconductor film 21f is shown as a single layer in the drawings, it may have a multilayer structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by the sputtering method. Note that the semiconductor film 21f may have a multilayer structure of four or more layers.

[0270] Next, a resist mask 61 is formed on the semiconductor film 21f (FIG. 18(B)). At this time, in order to suppress variations in the thickness of the resist mask 61, an organic or inorganic material formed by a coating method may be provided between the resist mask 61 and the semiconductor film 21f as a planarizing film that fills the slits 20. More specifically, a coating type insulating film such as an SOC (Spin On Carbon) film or an SOG (Spin On Glass) film may be used.

[0271] Next, the portions of the semiconductor film 21f that are not covered by the resist mask 61 are removed by etching, and then the resist mask 61 is removed, thereby forming the semiconductor layer 21 (FIG. 19(A)). When etching the semiconductor layer 21, it is difficult to remove the portions that contact the side surfaces of the insulating layer 41 by anisotropic dry etching alone, so it is preferable to perform etching by combining isotropic dry etching and wet etching. Alternatively, the regions of the semiconductor film 21f that are not covered by the resist mask 61 may be treated in advance to modify part of the semiconductor film 21f so that it becomes easier to etch. Examples of such treatment include plasma treatment, doping (including ion implantation), and wet treatment.

[0272] Subsequently, the insulating layer 22 is formed to cover the semiconductor layer 21 and the insulating layer 41. The insulating layer 22 can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable that the insulating layer 22 be provided on the surface of the vertical portion of the semiconductor layer 21 with as uniform a thickness as possible. For this reason, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. Note that when the sidewalls of the insulating layer 41 are tapered, the insulating layer 22 can be formed by a film formation method such as sputtering or CVD.

[0273] Next, a conductive film 23f, which will later become the conductive layer 23, is formed to cover the insulating layer 22 (FIG. 19(B)). The conductive film 23f can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoint of coverage, it is particularly preferable to form the conductive film 23f by a CVD method.

[0274] Next, a planarization process is performed on the conductive film 23f, the insulating layer 22, and the semiconductor layer 21 (FIG. 20(A)). The planarization process is performed until the upper surface of the conductive layer 25b is exposed. As a result, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 located inside the slit 20 are formed. Furthermore, as a result of the planarization process, the heights of the upper surfaces of the conductive layer 25b, the conductive layer 23, the insulating layer 22, and the semiconductor layer 21 are approximately the same (for example, the height from the substrate surface).

[0275] At this point, transistor 10 can be formed.

[0276] Subsequently, an insulating layer 43 is formed to cover the conductive layer 25b, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 (FIG. 20(B)). Subsequently, an insulating layer 44 is formed on the insulating layer 43. The insulating layers 43 and 44 can be formed by a CVD method, an ALD method, a sputtering method, or the like, respectively.

[0277] Next, an opening reaching the conductive layer 25a is formed in the insulating layer 44, the insulating layer 43, and the conductive layer 25b. Thereafter, a conductive film is formed to fill the opening, and a planarization process is performed until the upper surface of the insulating layer 44 is exposed, thereby forming the plug 27 (FIG. 21(A)).

[0278] Subsequently, a conductive film is formed on the insulating layer 44 and the plugs 27, and unnecessary portions are removed by etching to form the conductive layer 26 (FIG. 21(B)).

[0279] Through the above steps, a semiconductor device including a memory cell 15 including the transistor 10 and the capacitor 30 can be manufactured.

[0280] The above is a description of an example of the manufacturing method.

[0281] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0282] (Embodiment 2) In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0283] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0284] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0285] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 22(A) shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO X ), and FIG. 22(B) is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0286] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 22(B). On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 22(A) (see Non-Patent Document 1). This tendency is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is, and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that the characteristics of indium oxide shown in Figure 22(A) are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 22(A).

[0287] In Figure 22(A), the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1 × 10 15 cm -3 The range includes, for example, 1×10 14 cm -3 That's it, 1 x 10 18 cm -3 By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm 2 It is expected that the efficiency can be increased to about / (V·s).

[0288] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0289] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. 20 cm -3 The range includes, for example, 1×10 19 cm -3 That's it, 1 x 10 22 cm -3 By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 -4 It is expected that the resistance can be reduced to Ω·cm or less.

[0290] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains the same element as the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0291] In this way, the low-carrier-concentration region of indium oxide is used as the channel region of a transistor, while the high-carrier-concentration region is used as the source and drain regions. In other words, indium oxide can be considered an oxide capable of valence electron control. Note that IGZO can sometimes develop strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. However, unlike IGZO, indium oxide can be valence-controlled, eliminating the need for strain within the film as in IGZO. Minimizing strain within the film is expected to improve reliability. For example, by creating regions within the indium oxide film with carrier concentrations in the range R1 and the range R2 shown in Figure 22(A), a so-called nin junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon-based transistors is generally known. However, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0292] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) a high on-current (in other words, high mobility); (2) a low off-current; (3) a normally-off state; (4) high reliability; and (5) a high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, a low off-current, and is normally-off. The transistor has high mobility and is different from a normally-on transistor.

[0293] Note that a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in Figure 22(B), in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in Figure 22(A), the lower the carrier concentration, the higher the hole mobility. When Ef = Ei, the hole mobility is maximized. That is, a transistor containing indium oxide can achieve high field-effect mobility by achieving Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0294] Normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated using the constant current method. Vsh is the difference between the tangent of the maximum slope when the drain current (Id) in the Id-Vg characteristics of the transistor is expressed logarithmically and Id=1 pA (1×10 -12 A) is the gate voltage (Vg) at the intersection with the line A), or the Vg at the intersection between the line extrapolated from the two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive, the transistor can be considered to be normally off.

[0295] Furthermore, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef=Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef=Ei can be obtained.

[0296] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0297] The above film configuration can also be considered as a stacked configuration of a film capable of supplying oxygen to the indium oxide film from the indium oxide film side (e.g., a silicon oxide film), a film capable of gettering hydrogen (e.g., a hafnium oxide film), and a film suppressing the penetration of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that minimizes the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to an i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0298] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also referred to as microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0299] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0300] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), or a combination of these methods may be used.

[0301] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis changes continuously around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0302] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

[0303] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can act as a scattering source for carriers, which can result in a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably has a concentration of each of these impurities of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and the like are elements that can be contained in the film formation gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0304] The indium oxide film in the channel formation region may contain elements that can form the same trivalent cations as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such elements include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist primarily as trivalent cations in oxides, allowing the carrier concentration of indium oxide to be maintained low.

[0305] Furthermore, the indium oxide film in this specification has a high film density. Table 1 shows the film density of an indium oxide film (In2O3 here) applicable to one embodiment of the present invention.

[0306] [Table 1]

[0307] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is an SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the indium oxide film is formed. Sample 1, Sample 4, and Sample 5 are not heat treated (as-depo), Sample 2 is baked at 350°C in a CDA atmosphere, Sample 3 is baked at 650°C in a CDA atmosphere, and Sample 6 is baked at 250°C in a vacuum atmosphere.

[0308] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used for the heat treatment (condition 3) after the indium oxide film formation contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60°C or less, preferably −100°C or less, as the atmosphere.

[0309] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, resulting in a higher purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. 3 The theoretical film density of an indium oxide film is 7.18 g / cm 3 In this specification, the range of the film density of the indium oxide film is 6.70 g / cm 3 More than 7.18g / cm 3Preferably, it is 6.90 g / cm or less. 3 More than 7.18g / cm 3 More preferably, it is 7.00 g / cm or less. 3 More than 7.18g / cm 3 The following is the result.

[0310] The film density can be evaluated using, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, if the film density is high, the transmission electron (TE) image will be dense (dark), and if the film density is low, the transmission electron (TE) image will be pale (bright).

[0311] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm 2 / (V·s) or more, preferably 100 cm 2 / (V·s) or more, preferably 150 cm 2 / (V·s) or more, more preferably 200 cm 2 / (V·s) or more, more preferably 250 cm 2 / (V·s) or more.

[0312] One of the features of indium oxide films is that they have higher oxygen permeability (diffusibility) than IGZO films. As shown in Figure 22(C), X Oxygen (O) that diffuses into the indium oxide film passes through the indium oxide film and is released as oxygen molecules (O2). It may also react with hydrogen contained in the film and be released as water molecules (H2O). In addition, oxygen vacancies (V O ) exists, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen diffuses easily in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0313] As described above, an indium oxide film is more likely to reduce oxygen vacancies in the film than an IGZO film, and therefore, by applying such an indium oxide film to a transistor, a transistor with extremely high reliability can be realized.

[0314] Furthermore, as shown in Figure 22(C), the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and is released as hydrogen molecules (H2). Alternatively, hydrogen reacts with oxygen contained in the film and is released as water molecules.

[0315] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0316] Table 2 shows the effective masses of single-crystal indium oxide (here, In2O3) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, it is possible to realize transistors with high field-effect mobility and high frequency characteristics (also called f characteristics). Furthermore, because the effective mass of holes is large, it is possible to realize transistors with extremely small off-current. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1 × 10 -15 A) or less, or 1aA (1×10 -18 A) or less, and under room temperature (25°C) -18 A) or less, or 1zA (1 x 10 -21Furthermore, as shown in Table 2, indium oxide has a smaller effective mass for electrons and a larger effective mass for holes than silicon, which may enable the realization of a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0317] [Table 2]

[0318] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0319] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) to the crystals of the seed layer is calculated as Δa = ((L1 - L2) / L2) × 100. Here, L1 is the length or lattice constant of the unit lattice vector of the crystals of the formed film, and L2 is the length or lattice constant of the unit lattice vector of the crystals of the seed layer.

[0320] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0321] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0322] The crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film with hexagonal or trigonal crystal structure can be used underneath an indium oxide film with cubic crystal structure. For example, by using a

[0001] crystal orientation on the surface of the seed layer and a

[0111] crystal orientation on the underside of the indium oxide film, the crystal orientation requirements for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include the wurtzite structure, YbFe2O4 structure, Yb2Fe3O7 structure, and modified structures thereof. An example of a crystal with the YbFe2O4 structure or Yb2Fe3O7 structure is IGZO. Note that indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Note that silicon crystals have a diamond structure. As described above, indium oxide and silicon have similar properties in terms of single crystals. However, when comparing indium oxide and silicon in terms of whether they can form single crystals on an insulating film, they have different properties.

[0323] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0324] (Embodiment 3) In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0325] Fig. 23 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 23 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 23 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0326] The memory cell 15 exemplified in the above embodiment can be applied to the memory cell 950 .

[0327] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0328] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0329] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0330] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0331] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0332] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0333] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0334] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0335] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 23, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, it is preferable to provide a power switch for each power domain.

[0336] Other examples of the configuration of a memory cell that can be applied to the memory cell 950 will be described with reference to FIGS.

[0337] In the following, when two components are said to be connected, this includes being electrically connected via a circuit element (such as a transistor, switch, diode, or resistor). Electrical connection means that a current can flow between the two components. Note that when two components are connected via a switch or transistor, this is also included in the term "electrical connection," because a current can flow when these are in the on state.

[0338] [DOSRAM] 24A shows an example of a circuit configuration of a memory cell of a DRAM. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0339] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0340] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. A second terminal of the capacitance element CA is connected to the wiring CAL.

[0341] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0342] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitance element CA into a conductive state (a state in which current can flow).

[0343] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 24B can also be used. The memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0344] In the memory cell 952, the potential written via the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0345] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0346] [NOSRAM] 24C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and elsewhere, a memory device having a gain cell type memory cell in which an OS transistor is used as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0347] A first terminal of transistor M2 is connected to a first terminal of capacitance element CB, a second terminal of transistor M2 is connected to line WBL, and a gate of transistor M2 is connected to line WOL. A second terminal of capacitance element CB is connected to line CAL. A first terminal of transistor M3 is connected to line RBL, a second terminal of transistor M3 is connected to line SL, and a gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0348] The line WBL functions as a write bit line, the line RBL functions as a read bit line, and the line WOL functions as a word line. The line CAL functions as a line for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the line CAL.

[0349] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0350] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of the transistor M3, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0351] Further, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 24(D). The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0352] 24(E) is an example of a memory cell 955 in which the capacitor CB and the wiring CAL are omitted from the memory cell 953. Also, FIG. 24(F) is an example of a memory cell 956 in which the capacitor CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the degree of integration of the memory cells can be increased.

[0353] Note that it is preferable to use an OS transistor for at least the transistor M2, and particularly preferable to use an OS transistor for the transistors M2 and M3.

[0354] Since the OS transistor has an extremely small off-state current, written data can be retained for a long time by the transistor M2, thereby reducing the frequency of refreshing the memory cells. Alternatively, the refresh operation of the memory cells can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be retained in the memory cells 953, 954, 955, and 956.

[0355] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one aspect of NOSRAM.

[0356] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, which increases the degree of freedom in circuit design.

[0357] Furthermore, when an OS transistor is used as the transistor M3, the memory cell can be configured using only n-type transistors.

[0358] 24G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0359] A first terminal of the transistor M4 is connected to a first terminal of the capacitor CC, a second terminal of the transistor M4 is connected to the wiring BIL, and a gate of the transistor M4 is connected to the wiring WOL. A second terminal of the capacitor CC is connected to a first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to a first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitor CC. A second terminal of the transistor M6 is connected to the wiring BIL, and a gate of the transistor M6 is connected to the wiring RWL.

[0360] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low level potential.

[0361] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0362] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0363] It is preferable to use an OS transistor for at least the transistor M4.

[0364] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0365] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be configured using only n-type transistors.

[0366] [OS-SRAM] FIG. 24H shows an example of an SRAM (Static Random Access Memory) using OS transistors. In this specification and elsewhere, an SRAM using OS transistors is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 24H is a memory cell of an SRAM that can be backed up.

[0367] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0368] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. A gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. A gate of transistor M8 is connected to wiring WOL.

[0369] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0370] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0371] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0372] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0373] The wiring VDL is a wiring that applies a high level potential, and the wiring GNDL is a wiring that applies a low level potential.

[0374] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0375] In the memory cell 958, the transistors MS1 and MS2 form an inverter loop, and therefore an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL, turning off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0376] The data read will now be described. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. Also, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. In the wirings BIL and BILB, the potentials change from the precharged potentials to the potentials of the first terminals of the capacitors CD2 and CD1, respectively, so that the potentials held in the memory cells can be read from the potential of the wiring BIL or wiring BILB.

[0377] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held for a long time by the transistors M7 to M10, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0378] Note that Si transistors may be used as the transistors MS1 to MS4.

[0379] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 25(A), the driver circuit 910 and the memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and the memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 25(B), the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0380] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0381] Fig. 26 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in Fig. 26 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0382] The arithmetic device 960 shown in FIG. 26 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. A rewritable ROM and a ROM interface may be provided. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0383] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.

[0384] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0385] It is also possible to use only the memory array 920 as a cache without providing the cache 999.

[0386] The arithmetic device 960 shown in FIG. 26 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 26 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0387] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.

[0388] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates an address for a register 996 and performs read and write operations on the register 996 depending on the state of the arithmetic unit 960.

[0389] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0390] In the arithmetic unit 960 shown in FIG. 26, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0391] The memory array 920 and the arithmetic device 960 can be provided overlapping each other. Figures 27(A) and (B) show perspective views of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic device 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic device 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the layer 930 are shown separately in Figure 27(B).

[0392] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0393] The layer 930 having the memory array and the arithmetic device 960 may be stacked by stacking the layer 930 having the memory array directly on the arithmetic device 960 (also called monolithic stacking), or by forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding). The former method does not require consideration of misalignment during bonding, and therefore not only can it reduce the chip size but also the manufacturing cost.

[0394] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also called a level 1 cache), the memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and is accessed least frequently. Furthermore, the memory array 920L1 has the smallest capacity and is accessed most frequently.

[0395] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0396] 27(B), a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0397] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0398] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0399] Whether the memory array 920 functions as a cache or a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0400] The semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache and the other part to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

[0401] Furthermore, a layer 930 having one memory array 920 may be provided overlapping the arithmetic device 960. Figure 28A shows a perspective view of a semiconductor device 970B.

[0402] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 28(A) shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0403] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if you want to increase the capacity of the L1 cache, you can achieve this by increasing the area of ​​the area L1. This configuration makes it possible to improve the efficiency of calculation processing and increase the processing speed.

[0404] Moreover, a plurality of memory arrays may be stacked. Figure 28(B) shows a perspective view of the semiconductor device 970C.

[0405] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0406] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0407] (Fourth embodiment) In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0408] [Electronic Components] FIG. 29(A) shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 29(A) has semiconductor device 710 inside mold 711. FIG. 29(A) omits some parts in order to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0409] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0410] Furthermore, by configuring on-chip memory, the size of connection wiring can be reduced compared to technologies that use through-electrodes such as TSV, and it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0411] Furthermore, it is preferable that the memory cell arrays included in the storage layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By configuring the memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used in the storage layer 716, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.

[0412] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0413] 29(B) shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

[0414] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0415] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 732. For example, a silicon interposer or a resin interposer can be used for the interposer 731.

[0416] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, with a silicon interposer, TSVs can also be used as through electrodes.

[0417] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0418] Furthermore, SiPs and MCMs that use silicon interposers are less likely to experience a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0419] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required to accommodate the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the terminal pitch becomes an issue, making it difficult to provide the large number of interconnects required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may also be used that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0420] A heat sink (heat sink) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0421] Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate. FIG. 29(B) shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0422] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0423] [Large computer] 30A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0424] 30(B) shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, which are each connected to the motherboard 5630.

[0425] Fig. 30(C) shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, an electronic component 5626, an electronic component 5627, an electronic component 5628, a connection terminal 5629, etc., which are mounted on the board 5622. Note that Fig. 30(C) illustrates components other than the electronic component 5626, the electronic component 5627, and the electronic component 5628.

[0426] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0427] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0428] The electronic component 5626 has terminals (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminals into sockets (not shown) provided on the board 5622.

[0429] The electronic component 5627 and the electronic component 5628 have a plurality of terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0430] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0431] [Space equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0432] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0433] 31A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that in FIG. 31A, a planet 6804 is shown in space.

[0434] 31A, a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0435] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0436] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is recommended to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may also be called a solar cell module.

[0437] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0438] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. Note that a semiconductor device including an OS transistor according to one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0439] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0440] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0441] As described above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.

[0442] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage devices and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0443] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0444] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0445] Figure 31(B) shows a storage system applicable to a data center. The storage system 6000 shown in Figure 31(B) has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0446] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0447] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0448] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0449] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, thereby lowering power consumption.Furthermore, by using a stacked memory cell array, miniaturization is possible.

[0450] Note that the application of a semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of a semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO). Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming due to its low power consumption.

[0451] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Example]

[0452] In this example, a sample including an OS transistor and a capacitor was fabricated, and a cross section was observed. In addition, the electrical characteristics of the OS transistor were evaluated.

[0453] In this example, as Sample 1A, a semiconductor device was fabricated, which included a layer 60 including a Si transistor and a layer 80 located on the layer 60 and having a memory cell 15, as shown in FIG. 5 . In Sample 1A, the memory cell 15 had a structure including a capacitor 30 and a transistor 10, similar to the structure shown in FIGS. 10 and 11 . The memory cells 15 were arranged in a matrix on the XY plane shown in FIGS. 10 and 11 , with the conductive layer 26 functioning as a wiring extending in the X direction and the conductive layer 55 and conductive layer 23 functioning as wiring extending in the Y direction. For details of the capacitor 30 and the transistor 10 of Sample 1A, see the descriptions of FIGS. 10 and 11 .

[0454] The memory cell according to this embodiment will be described in detail below.

[0455] As shown in Figures 10 and 11, a conductive layer 55 was formed in the opening of the insulating layer 53. A silicon oxide film formed by sputtering was used as the insulating layer 53. The conductive layer 55 had a laminated structure of a conductive layer 55a and a conductive layer 55b. The conductive layer 55a was a laminated film of a tantalum nitride film formed by sputtering and a titanium nitride film formed by CVD. The conductive layer 55b was a tungsten film formed by CVD.

[0456] An insulating layer 46 having an opening 40 was formed on the insulating layer 53. An insulating layer 48 was formed in contact with the sidewall of the opening 40. The insulating layer 46 had a stacked structure of insulating layers 46a, 46b, and 46c. The insulating layer 46a was a silicon nitride film formed by the PEALD method. The insulating layer 46b was a silicon oxide film formed by the sputtering method. The insulating layer 46c was a silicon nitride film formed by the sputtering method. The insulating layer 48 was a silicon nitride film formed by the PEALD method.

[0457] A conductive layer 51 was formed along the opening 40, an insulating layer 52 was formed along the conductive layer 51, and the recesses in the insulating layer 52 were filled to form the conductive layer 24. The conductive layer 51 was a titanium nitride film formed by CVD. The insulating layer 52 was a laminated film of a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film formed by thermal ALD. The conductive layer 24a1 was a laminated film of a titanium nitride film and a tungsten film formed by CVD. The conductive layer 24a2 was a titanium nitride film formed by CVD. The conductive layer 24b was an In-Sn-Si oxide film formed by sputtering.

[0458] The conductive layer 24 was fabricated using the steps shown in FIGS. 15(B) to 16(C). First, a conductive film 24a1f was formed, and then a conductive film 24a2f was formed on the conductive film 24a1f. Next, CMP processing was performed until the conductive film 24a1f was exposed, filling the recesses in the conductive film 24a1f to form a conductive layer 24a2. Next, a conductive film 24bf was formed, and the conductive films 24a1f and 24bf were processed to form the conductive layers 24a1 and 24b. Here, the insulating layer 52 was also formed to have the same top surface shape as the conductive layers 24a1 and 24b.

[0459] An insulating layer 41 was formed on the conductive layer 24. The insulating layer 41 had a laminated structure of insulating layers 41a, 41b, and 41c. The insulating layer 41a was a laminated film of a silicon nitride film formed by the PEALD method and a silicon nitride film formed by the sputtering method. After the insulating layer 41a was formed, a CMP process was performed to flatten the upper surface of the insulating layer 41a. The insulating layer 41b was a silicon oxide film formed by the sputtering method. The insulating layer 41c was a silicon nitride film formed by the sputtering method. Here, the thickness of the insulating layer 41 on the conductive layer 24 was set to 115 nm.

[0460] Conductive layer 25 was formed on insulating layer 41. Slits 20 were formed in insulating layer 41 and conductive layer 25. Conductive layer 25 had a laminated structure of conductive layer 25a and conductive layer 25b. Conductive layer 25a was a tungsten film formed by sputtering. Conductive layer 25b was an In-Sn-Si oxide film formed by sputtering.

[0461] A semiconductor layer 21 was formed along the slit 20. The semiconductor layer 21 was a laminated film of a crystalline In2O3 film formed by thermal ALD and an In-Ga-Zn oxide film formed by sputtering. The In2O3 film had a thickness of 5 nm. The In-Ga-Zn oxide film had a thickness of 5 nm and was formed using a target with an atomic ratio of In:Ga:Zn = 1:1:1.2. The semiconductor layer 21 was formed in an island shape within the slit 20. Here, the width of the semiconductor layer 21 in the Y direction was set to 400 nm.

[0462] An insulating layer 22 was formed along the semiconductor layer 21, and a conductive layer 23 was formed along the insulating layer 22. The conductive layer 23 had a laminated structure of a conductive layer 23a and a conductive layer 23b. The insulating layer 22 was a laminated film of an aluminum oxide film formed by a thermal ALD method, a silicon oxide film formed by a PEALD method, a hafnium oxide film formed by a thermal ALD method, and a silicon nitride film formed by a PEALD method. The conductive layer 23a was a titanium nitride film formed by a CVD method. The conductive layer 23b was a tungsten film formed by a CVD method. Here, the conductive layer 23, the insulating layer 22, and the semiconductor layer 21 were formed so that portions thereof were located on the conductive layer 25.

[0463] An insulating layer 43 was formed to cover the conductive layer 23, and an insulating layer 44 was formed on the insulating layer 43. The insulating layer 43 was made of silicon nitride formed by the PEALD method. The insulating layer 44 was made of a laminated film of a silicon oxide film and a silicon nitride film formed by the sputtering method. Furthermore, a plug 27 was formed to penetrate the insulating layer 43 and the insulating layer 44 and to contact the conductive layer 25, and a conductive layer 26 was formed to contact the upper surface of the plug 27.

[0464] In this manner, a sample 1A including the transistor 10 having a channel width of 800 nm and a channel length of 115 nm and the capacitor 30 was fabricated.

[0465] [Cross-section observation] Cross-sectional STEM images of the prepared samples were taken using a scanning transmission electron microscope (STEM). Phase contrast images were taken using a Hitachi High-Technologies "HD-2700" microscope with an accelerating voltage of 200 kV.

[0466] Cross-sectional STEM images of Sample 1A are shown in Fig. 32, Fig. 33(A), and Fig. 33(B). Fig. 32 is an overall image of the cross section, Fig. 33(A) is an enlarged view of the memory cell 15, and Fig. 33(B) is an enlarged view of the transistor 10.

[0467] 32, in sample 1A, Si transistors are formed in a layer 60, and multi-layer wiring is formed on the Si transistors. On layer 60, a layer 80 including memory cells 15 is formed.

[0468] As shown in FIG. 33A, in the memory cell 15, a capacitive element 30 and a transistor 10 on the capacitive element 30 are formed.

[0469] As shown in Figure 33(B), in the conductive layer 24, a conductive layer 24a2 is formed so as to fill the recesses of the conductive layer 24a1. The upper surface of the conductive layer 24a1 is highly uneven and has low flatness. In contrast, by providing the conductive layer 24a2, the flatness of the upper surface of the conductive layer 24a2 and the exposed upper surface of the conductive layer 24a1 is increased. This increases the flatness of the surface on which the conductive layer 24b is to be formed, allowing the conductive layer 24b to be formed flat.

[0470] The side surfaces of the conductive layer 24 and the insulating layer 52 are roughly aligned, and the conductive layer 24 and the insulating layer 52 are formed in the same pattern. The conductive layer 23 has a recess in the slit 20, and the recess is filled with the insulating layer 43 and the insulating layer 44. The conductive layer 23, the insulating layer 22, and a part of the semiconductor layer 21 are formed above the conductive layer 25.

[0471] [Evaluation of transistor electrical characteristics] The Id-Vgs characteristics of 40 transistors included in Sample 1 A were measured. Here, Vgs refers to the voltage between the gate and source, and may be referred to as the gate voltage Vgs hereinafter.

[0472] In the measurements, the drain voltage Vds was set to 1.2 V, and the gate voltage Vgs was swept from -4 V to +4 V in 0.1 V steps. The measurement temperature was room temperature (27°C). Figure 34 shows the Id-Vgs characteristics of the transistor. In Figure 34, the vertical axis represents the drain current Id [A], and the horizontal axis represents the gate voltage Vgs [V].

[0473] As shown in Figure 34, it was confirmed that all of the transistors included in Sample 1A exhibited good electrical characteristics. Specifically, the transistors included in Sample 1A had a median threshold voltage (Vth) of 0.04 V, a standard deviation of the threshold voltage of 57 mV, a median S value of 76 mV / dec, and a median transconductance of 143 μS. Here, the threshold voltage (Vth) is the value of the gate voltage Vgs when the drain current Id becomes 1 pA.

[0474] 35 shows the results of investigating the temperature dependence of the Id-Vgs characteristics of the transistor included in Sample 1A. As shown in FIG. 35, the Id-Vgs characteristics were measured at temperatures of -40°C, -25°C, 27°C, 85°C, and 110°C. In the measurement of the Id-Vgs characteristics shown in FIG. 35, Id=1.0×10 -12A is the lower limit of measurement. As shown in Figure 35, it was confirmed that sample 1A exhibited good electrical characteristics over a wide temperature range. Under all temperature conditions, the off-state current was lower than 1 pA, which is the lower limit of measurement. This means that the transistor included in sample 1A has an off-state leakage current that is much lower than that of a Si transistor.

[0475] [Evaluation of off-state current] In this section, the off-state current of a transistor is evaluated. Sample 1B was prepared to evaluate the off-state current of the transistor.

[0476] Sample 1B includes a DUT (Device Under Test) to be evaluated for off-state current. Because the off-state current of an OS transistor is extremely small, 19,800 transistors connected in parallel were prepared as the DUT in this example.

[0477] The transistors included in the DUT of Sample 1B can be configured similarly to the transistors included in Sample 1A described above. That is, in the DUT, the off-state current is amplified to a detectable value by setting the total channel width to 15.84 mm.

[0478] As a comparative example, a reference sample was prepared in which the DUT included a silicon transistor (Si-FET) with W (channel width) / L (channel length)=120 nm / 60 nm.

[0479] To evaluate the off-current of the transistor included in the DUT of Sample 1B, -2.0 V was applied to the gate terminal of the DUT transistor, 0 V to the source terminal, and 0.8 V to the drain terminal. Next, the drain terminal was left floating, and the change in the potential of the drain terminal over time was observed via a source follower circuit. The off-current Ioff of the DUT transistor was calculated from the pre-measured parasitic capacitance of the drain terminal and the change in potential of the drain terminal over the measurement time. To evaluate the off-current of the transistor included in the reference sample, 0 V was applied to the gate and source terminals of the DUT transistor, and 1.2 V was applied to the drain terminal.

[0480] FIG. 36 shows an Arrhenius plot of the calculated off-state currents of the transistors included in Sample 1B and the reference sample. In FIG. 36, the horizontal axis represents the reciprocal of temperature T (1000 / T) [1 / K], and the vertical axis represents the off-state current Ioff [A / μm] per 1 μm of channel width. The circular plots represent the calculated off-state currents of the transistors included in Sample 1B, plotting the calculated off-state currents at 110°C, 100°C, and 85°C. The triangular plots represent the calculated off-state currents of the silicon transistors, plotting the calculated off-state currents at 150°C, 100°C, and 27°C. The solid line represents the regression line obtained from the calculated off-state currents of the transistors included in Sample 1B, and the dashed line represents the regression line obtained from the calculated off-state currents of the silicon transistors.

[0481] 36, the off-state current per 1 μm of channel width of the transistor included in Sample 1B was 2.0 zA / μm under an environment of 27° C. (extrapolated). This value was smaller by 10 orders of magnitude than the off-state current of a silicon transistor under an environment of 27° C. This confirmed that the off-state current of an OS transistor is small and has little temperature dependence.

[0482] [Estimated write speed assuming DOSRAM] In this section, an estimate of the write speed will be described assuming a 1T1C type DOSRAM in which a capacitance element Cs of 5.9 fF is connected to the transistor 10 of sample 1A.

[0483] A wiring WL is connected to the gate terminal of the transistor 10, a wiring BL is connected to the drain terminal, and one of the electrodes of the capacitance element Cs is connected to the source terminal. Here, the node where the source terminal and one of the electrodes of the 5.9 fF capacitance element are connected is called a retention node SN.

[0484] The time from when a voltage Vwl that turns on the transistor 10 is applied to the wiring WL and a voltage of 1.2 V is applied to the wiring BL until the potential of the holding node SN becomes 0.96 V (80% of the potential of the wiring BL, 1.2 V) is defined as the write time t w The write time t w can be expressed by the following formula:

[0485]

number

[0486] where I SN is the current value of the holding node SN, and V SN is the potential of the storage node SN, and Cs is the capacitance value of the capacitive element Cs. The above calculations were performed using the results of Id-Vs measurements of the transistor 10 at -40°C.

[0487] The threshold voltage Vth and S value were calculated from the results of Id-Vgs measurement of the transistor 10 at 85° C. The current value in the off state was extrapolated from the threshold voltage Vth and S value, and the corresponding potential was set to Voff. The time it takes for the potential of the retention node SN to fluctuate by 0.1 V was calculated to obtain the data retention time t ret It was decided.

[0488] Data retention time t when voltage Vwl is set to 2.5V, 2.6V, and 2.7V ret and the write time t w The correlation between the data retention time t ret [sec], and the vertical axis represents the write time t w The dashed line in Figure 37 represents t ret =0.64sec.

[0489] As shown in Figure 37, the data retention time t ret Even if we set = 0.64 sec, the writing time at -40°C t wThe write speed was approximately 0.9 to 3.3 nsec. Even assuming a data retention time that is significantly longer than that of silicon transistors, it was confirmed that the write speed is fast.

[0490] The configurations, structures, or methods described in this embodiment can be used in appropriate combination with the configurations, structures, or methods described in other embodiment modes. [Example]

[0491] In this example, evaluation results of a DRAM-type memory cell 800 fabricated by stacking a transistor TrN, which is a VFET, on a capacitance element VC, and a DRAM chip 850 configured including a plurality of such memory cells 800 will be described.

[0492] 38(A) shows a perspective schematic diagram of a memory cell array in which memory cells 800 are arranged in a matrix of 2 rows and 2 columns. Fig. 38(B) shows the manufacturing process of the memory cell 800. All process temperatures are 400°C or less.

[0493] 39(A) is a schematic plan view of memory cell 800, and FIG. 39(B) is an equivalent circuit diagram of memory cell 800. FIG. 39(C) is a schematic cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 39(A). FIG. 39(D) is a schematic cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 39(A). Note that in the schematic perspective views, schematic plan views, and schematic cross-sectional views, some components may be omitted to make the configuration easier to understand.

[0494] As shown in the equivalent circuit diagram of Figure 39(B), one of the source and drain of transistor TrN is connected to one electrode of capacitance element VC, and the other is connected to bit line BL. Also, the gate of transistor TrN is connected to word line WL. When memory cell 800 is driven, a fixed potential is supplied to the other electrode of capacitance element VC.

[0495] [Memory cell manufacturing process] A memory cell 800 in which a transistor TrN is stacked on a capacitance element VC was fabricated in the following manner.

[0496] First, a conductive layer 811 was formed on a substrate, an insulating layer was formed on the conductive layer 811, and a portion of the insulating layer was removed to form an opening 812 in a region overlapping with the conductive layer 811 (capacitor hole formation). Next, a conductive layer 813, an insulating layer 814, and a conductive layer 815 were formed in this order (bottom electrode formation, insulator deposition, top electrode formation), each having a region overlapping with the inner wall and bottom of the opening 812. The conductive layer 813 has a region that contacts the conductive layer 811 at the bottom of the opening 812. The conductive layer 815 has a region that overlaps with the conductive layer 813 via the insulating layer 814. The insulating layer 814 has a region that extends beyond the opening 812. The region where the conductive layer 815 and the conductive layer 813 overlap with the insulating layer 814 interposed therebetween functions as a capacitor element VC.

[0497] Next, a conductive layer 816 covering the opening 812 is formed on the insulating layer 814 and the conductive layer 815. The conductive layer 816 has a region in contact with the conductive layer 815. The conductive layer 816 also functions as one of the source electrode or drain electrode of the transistor TrN, which is a VFET (Lower S / D electrode formation). The conductive layer 816 also functions as a retention node SN that retains the charge supplied to the memory cell 800.

[0498] Next, an insulating layer having a thickness of 105 nm was formed on the conductive layer 816 (S / D spacer deposition (thickness=105 nm)), and a conductive layer 817 was formed on the insulating layer (Upper S / D electrode formation). The thickness of the insulating layer determines the distance from the source electrode to the drain electrode of the transistor TrN. In other words, the channel length of the transistor TrN, which is a VFET, is determined. The conductive layer 817 also functions as the other of the source electrode or drain electrode of the transistor TrN, which is a VFET. The conductive layer 817 also functions as the bit line BL.

[0499] Next, parts of the insulating layer and the conductive layer 817 were removed to form an opening 818 with a diameter of 60 nm in a region overlapping with the conductive layer 816 (Channel hole formation (60 nmφ)). Next, an oxide semiconductor layer 819 was formed having a region overlapping with the inner wall and bottom of the opening 818 (OS island formation). In the transistor TrN, crystalline indium oxide (also referred to as "IO") was used as the oxide semiconductor layer 819. The oxide semiconductor layer 819 has a region in contact with the conductive layer 816 and a region in contact with the conductive layer 817.

[0500] Assuming that the shape of the opening 818 in plan view is circular and the diameter is a, the channel width W of the transistor TrN can be expressed as W=a×pi.

[0501] Next, an insulating layer 820 was formed on the oxide semiconductor layer 819 (gate insulator deposition). The insulating layer 820 has a region overlapping the inner wall of the opening 818 via the oxide semiconductor layer 819. Next, a sacrificial layer having a region filling the opening 818 was formed on the opening 818 (dummy gate formation), and an insulating layer covering the sacrificial layer (insulator deposition) was formed. Next, CMP processing was performed on the insulating layer to reduce unevenness on the upper part of the insulating layer and simultaneously expose the upper part of the sacrificial layer. Next, the sacrificial layer was removed (dummy gate etching), and a conductive layer 821 was formed (gate metal formation). The conductive layer 821 has a region overlapping the oxide semiconductor layer 819 via the insulating layer 820 inside the opening 818. The conductive layer 821 functions as the gate electrode of the transistor TrN.

[0502] Next, a conductive layer 822 having an area in contact with the conductive layer 821 and functioning as a word line WL was formed on the conductive layer 821. In addition, a protective layer to prevent the intrusion of impurity elements from the outside, an interlayer insulating layer, a via layer, and the like (passivation, interlayer, via, and wiring formations) were formed above the conductive layer 822. In this manner, the memory cell 800 was fabricated.

[0503] In the memory cell 800 shown in this embodiment, the distance from the upper surface of the insulating layer 820 to the word line WL is set to 65 nm. Since the transistor TrN has a structure in which the gate electrode is pulled up (also called a "GE pulled-up structure"), the parasitic capacitance generated between the gate electrode and the other of the source electrode or the drain electrode is reduced. Therefore, the parasitic capacitance generated between the word line WL and the bit line BL can be reduced.

[0504] For comparison with memory cell 800, a memory cell 801 without a GE pull-up structure was separately fabricated. FIG. 40(A) is a schematic plan view of memory cell 800, and FIG. 40(B) is an equivalent circuit diagram of memory cell 800. FIG. 40(C) is a schematic cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 40(A). FIG. 40(D) ​​is a schematic cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 40(A).

[0505] The memory cell 801 has a configuration in which a transistor TrC, which is a VFET, is stacked on a capacitance element VC. That is, the memory cell 801 has a configuration in which the transistor TrN of the memory cell 800 is replaced with the transistor TrC.

[0506] The transistor TrC is a VFET similar to the transistor TrN, but does not undergo the formation of a sacrificial layer, the formation of an insulating layer on the sacrificial layer, the CMP process, the removal of the sacrificial layer, or the formation of a conductive layer 822 that functions as the word line WL. Therefore, in the memory cell 801, the conductive layer 821 also functions as the word line WL. That is, since the distance from the top surface of the insulating layer 820 to the word line WL is 0 nm, the capacitance generated between the word line WL and the bit line BL is larger than that of the memory cell 800. The transistor TrC is a transistor with a larger capacitance between the gate electrode and the other of the source electrode and the drain electrode than the transistor TrN. That is, the transistor TrC is a transistor with a larger parasitic capacitance of the gate electrode than the transistor TrN.

[0507] [Transistor parasitic capacitance] The magnitude of the parasitic capacitance generated in each of transistors TrN and TrC was investigated. For each of transistors TrN and TrC, 20,000 transistors with a channel length L of 105 nm and a channel width W of 60 nmφ were fabricated and connected in parallel, and CV measurements were performed. Figure 41(A) shows the results of the parasitic capacitance measurements. Figure 41(A) shows the capacitance values ​​of the parasitic capacitance between the gate electrode and the other of the source electrode or drain electrode (WL-BL), the parasitic capacitance between the gate electrode and one of the source electrode or drain electrode (WL-SN), the parasitic capacitance between the source electrode and drain electrode (BL-SN), and the parasitic capacitance between the gate electrode and the substrate (WL-Sub).

[0508] 41(A) shows that the parasitic capacitance (WL-BL) between the gate electrode and the other of the source electrode and the drain electrode is dominant in both transistors TrN and TrC. Furthermore, it was found that the total parasitic capacitance can be reduced by 63.2% by adopting the GE pull-up structure.

[0509] [Sheet resistance of word line WL] 41B shows the measurement results of the sheet resistance of the conductive layer 822 functioning as the word line WL of the memory cell 800 and the conductive layer 821 functioning as the word line WL of the memory cell 801. The sheet resistance of the conductive layer 821 was 161.3 Ω / sq. The sheet resistance of the conductive layer 822 was 7.9 Ω / sq, which was 95.1% lower than that of the conductive layer 821. This is because the memory cell 801, which does not employ a GE pull-up structure, has a structure that serves both as a gate electrode and a word line WL, making it difficult to use a low-resistance material for the conductive layer 821 having a region buried in the opening 818.

[0510] On the other hand, in the memory cell 800 employing the GE pull-up structure, the conductive layer 822 functioning as the word line WL can be formed after forming the conductive layer 821 that functions as the gate electrode and is buried in the opening 818. For this reason, a low-resistance material can be used for the conductive layer 822.

[0511] [Transistor Id-Vgs characteristics] Next, the Id-Vgs characteristics of the transistor TrN were measured under a room temperature environment. The measurement results are shown in Fig. 42. In Fig. 42, the horizontal axis represents the gate voltage (Vgs) and the vertical axis represents the drain current (Id).

[0512] The transistor TrN used in the measurement had a channel length L of 105 nm and a channel width of 60 nmφ. In Figure 42, characteristics 831 and 832 show the Id-Vgs characteristics of the transistor TrN using IO for the oxide semiconductor layer 819. Characteristics 833 and 834 show the Id-Vgs characteristics of the transistor TrN using indium-gallium-zinc oxide (CAAC) with a c-axis aligned crystal (CAAC) structure (also referred to as "CAAC-IGZO") for the oxide semiconductor layer 819. Characteristics 831 and 833 are Id-Vgs characteristics when the drain voltage (Vds) is 0.1 V, and characteristics 832 and 834 are Id-Vgs characteristics when Vds is 1.2 V.

[0513] The Id-Vgs characteristics of the transistor TrN using IO for the oxide semiconductor layer 819 indicate that the threshold voltage (Vth) is 0.4 V, indicating enhancement-type characteristics. The transistor TrN using IO for the oxide semiconductor layer 819 also exhibits a transconductance (gm) of 47.6 μS, a subthreshold swing value (SS) of 91.0 mV / dec, and an on-current of 112.2 μA / μm when the gate voltage exceeds Vth by 1 V.

[0514] The transistor TrN using CAAC-IGZO for the oxide semiconductor layer 819 had enhancement-type characteristics with a Vth of 0.45 V. The transistor TrN using CAAC-IGZO for the oxide semiconductor layer 819 had a gm of 4.7 μS, an SS value of 91.0 mV / dec, and an on-state current of 13.5 μA / μm when Vgs exceeded Vth by 1 V.

[0515] The off-state current of both transistors TrN was the lower limit of measurement (1×10 -13 It was found that the on-state current of the transistor TrN using IO for the oxide semiconductor layer 819 when the gate voltage exceeded Vth by 1 V was 8.3 times higher than that of the transistor TrN using CAAC-IGZO for the oxide semiconductor layer 819.

[0516] [Temperature dependence of gm and Vth] The temperature dependence of gm and Vth was evaluated for each of the transistor TrN using IO for the oxide semiconductor layer 819 and the transistor TrN using CAAC-IGZO for the oxide semiconductor layer 819. Figure 43A shows the temperature dependence of gm for each transistor. The horizontal axis of Figure 43A represents temperature, and the vertical axis represents the relative value of gm when the maximum value of the measurement results is set to 1.

[0517] The rate of change in gm due to temperature change was 7% for the transistor TrN using IO for the oxide semiconductor layer 819, and 41% for the transistor TrN using CAAC-IGZO for the oxide semiconductor layer 819.

[0518] 43(B) shows the temperature dependence of the Vth variation of each transistor. The horizontal axis of FIG. 43(B) represents temperature, and the vertical axis represents the variation in Vth (ΔVth) when Vth at 125°C is used as the reference.

[0519] The amount of change in Vth due to temperature change was 0.22 V for the transistor TrN using IO for the oxide semiconductor layer 819, and 0.31 V for the transistor TrN using CAAC-IGZO for the oxide semiconductor layer 819.

[0520] 43A and 43B show that the temperature dependence of both gm and Vth of the transistor TrN using IO for the oxide semiconductor layer 819 is smaller than that of the transistor TrN using CAAC-IGZO for the oxide semiconductor layer 819.

[0521] [Arrhenius plot of leakage current] Figure 44 shows an Arrhenius plot of the leakage current (off current) of the transistor TrN and the leakage current of the capacitor VC per memory cell 800. Measurements were performed using a dedicated circuit designed to measure leakage current. In an environment of 125°C, the leakage current of the transistor TrN was 238 zA / cell, and the leakage current of the capacitor VC was a low value of 46 zA / cell.

[0522] [Read and write time simulation results] The data read time and data write time of the memory cell 800 and the memory cell 801 were confirmed by Spice simulation.

[0523] The circuit configuration used in the simulation is shown in Figure 45. In the simulation, a configuration (VFET / VC) was assumed in which a word line WL driver and sense amplifier circuit 841 made of Si CMOS were combined with a capacitance element VC and a VFET transistor TrN. Note that a word line selection signal WL_IN is input to the input of the word line WL driver.

[0524] The simulation was performed assuming a memory cell array including memory cells arranged in 32 rows and 256 columns. Specifically, for one memory cell MC (memory cell 800 or memory cell 801) consisting of a VFET and a VC, a parasitic capacitance C3 and a parasitic resistance R3 equivalent to 32 memory cells MC were added to the bit line BL and the inverted bit line BLB (32 in series). In addition, a parasitic capacitance C2 and a parasitic resistance R2 equivalent to 256 word lines WL were added to the word line WL of one memory cell MC (256 in series).

[0525] In addition, a parasitic capacitance C4 of the sense amplifier circuit 841 is added to each of the bit line BL and the inverted bit line BLB. Also, a parasitic capacitance C1 and a parasitic resistance R1 of the word line WL driver output section are added to the word line WL of one memory cell MC.

[0526] The parasitic capacitance of the memory cell MC was calculated by three-dimensional electromagnetic field analysis of the layer structure and layout of the fabricated memory cell 800. The parasitic resistance of the memory cell MC was calculated with reference to the measurement results shown in FIG.

[0527] The simulation was performed for a transistor TrN with a GE pull-up structure (with pull-up) and a transistor TrC without a GE pull-up structure (without pull-up), for the cases where the oxide semiconductor layer 819 was IO and CAAC-IGZO.

[0528] Tables 3 and 4 show the various parameters used in the simulation.

[0529] [Table 3]

[0530] [Table 4]

[0531] In the simulation, the sheet resistance (Rs of WL) of the word line WL was set to two levels: 161.3 Ω / sq and 7.9 Ω / sq. The parasitic resistance R1 was set to 340 Ω, the parasitic capacitance C1 was set to 37 fF, and the parasitic capacitance C4 was set to 4 fF. The parasitic resistance R2 was set to two levels: 302.5 Ω / cell and 14.8 Ω / cell, and the parasitic capacitance C2 was set to two levels: 0.38 fF / cell and 0.15 fF / cell. The parasitic resistance R1 was set to 25.9 Ω / cell. The parasitic capacitance C3 was set to two levels: 0.36 fF / cell and 0.16 fF / cell. The simulation was performed using the parameter combinations shown in Tables 3 and 4 as type 1 to type 5.

[0532] 46 shows a circuit diagram of the sense amplifier circuit 841. In addition to the bit line BL and the inverted bit line BLB, the sense amplifier circuit 841 is connected with wiring EQB, wiring SAP, wiring SAN, wiring VPRE, wiring EQ, wiring DBL, wiring DBLB, and wiring CSEL.

[0533] 47A shows a timing chart of a data read operation of the memory cell 800 and the memory cell 801. FIG. 47B shows a timing chart of a data write operation of the memory cell 800 and the memory cell 801.

[0534] 47A, time Tr is the time required for charge sharing between the retention node SN of the selected memory cell and the bit line BL. Time Trs is the time required for the sense amplifier circuit 841 to amplify the voltage of the bit line BL. In this embodiment, Read Time is defined as the sum of time Tr and time Trs.

[0535] 47B, time Tw is the time it takes for the voltage of the line DBL to be written to the storage node SN of memory cell 800 or memory cell 801 and for the voltage of the storage node SN to reach 80% of the voltage of the line DBL. Time Twl is the falling edge time of WL_IN. In this embodiment, Write Time is defined as the sum of time Tw and time Twl.

[0536] The simulation results for read time are shown in Figure 48(A). It was found that read time could be reduced by 25% for type 2, 40% for type 3, 63% for type 4, and 81% for type 5 compared to type 1.

[0537] The simulation results for write time are shown in Figure 48(B). It was found that the write time could be reduced by 35% for types 2 and 3, 54% for type 4, and 89% for type 5 compared to type 1.

[0538] From the simulation results, it was confirmed that the use of the GE pull-up structure reduces both the read time and the write time. Furthermore, it was confirmed that the use of IO for the oxide semiconductor layer 819 reduces both the read time and the write time. Furthermore, it was confirmed that the application of both the GE pull-up structure and IO can further enhance the reduction in both the read time and the write time. In other words, it was found that the adoption of the GE pull-up structure and the use of IO for the oxide semiconductor layer 819 improves the access speed of the DRAM memory cell.

[0539] [DRAM chip] A DRAM chip 850 was fabricated by stacking a memory cell 800 having a GE pull-up structure on a Si CMOS. The transistor TrN of the memory cell 800 had a channel length L of 105 nm and a channel width W of 60 nmφ, and an IO was used as the oxide semiconductor layer 819. The sheet resistance of the word line WL was set to 7.9 Ω / sq. The capacitance element VC had an opening 812 with a diameter of 80 nmφ and a capacitance value of 2.3 fF.

[0540] A photograph of the appearance of the DRAM chip 850 is shown in Figure 49. The external size of the fabricated DRAM chip 850 is 4 mm x 4 mm. The DRAM chip 850 has a memory and SA array containing multiple memory cell arrays and multiple sense amplifier circuits, and a control circuit (controller) that controls the operations of these.

[0541] 50 shows a cross-sectional STEM image of a portion of the fabricated DRAM chip 850. The fabricated DRAM chip 850 has a FEOL (Front End Of Line) formed with Si CMOS of a technology node of 55 nm, a wiring layer 861 including six conductive layers formed thereon, and one layer of VFET / VC, which is the memory cell 800, formed thereon.

[0542] 51(A) and 51(B) show block diagrams of a fabricated DRAM chip 850. As shown in FIG. 51(A), the DRAM chip 850 has an input / output circuit 862, a control circuit 864, and 16 banks 860. Also, as shown in FIG. 51(B), each bank 860 has a sense amplifier array 851 including a plurality of sense amplifier circuits, a memory cell array 855 including a plurality of memory cells 800, a data sense amplifier circuit 852, a sense amplifier driver circuit 853, and a word line driver circuit 854. The sense amplifier array 851, the data sense amplifier circuit 852, the sense amplifier driver circuit 853, the word line driver circuit 854, the input / output circuit 862, the control circuit 864, and the like are formed of Si CMOS, which is an FEOL. Also, a memory cell array 855 including a plurality of memory cells 800 is formed above the Si CMOS. Although FIG. 51A shows a configuration in which the control circuit 864 is provided outside the bank 860, a configuration in which part or all of the control circuit 864 is provided inside the bank 860 is also possible.

[0543] In addition to the data (DATA) input and output, the bank 860 is supplied with a data output control signal (signal RE_EN), a sense amplifier control signal (signal SA_EN), a precharge control signal (signal EQ_EN), a column selection control signal (signal CSEL_EN), memory address information Addr, a word line control signal (signal WL_EN), and the like via a control circuit 864 (From / To Controller). In addition, the control circuit 864 can output each signal in synchronization with a clock signal (signal CLK).

[0544] Figure 52(A) shows a shmoo plot of the Read Time, which is obtained by varying the voltage supplied to the word line WL (WL Supply Voltage) from 1.5 V to 2.3 V in 0.1 V steps and varying the Read Time from 2.5 ns to 20 ns in 2.5 ns steps in a room temperature environment.

[0545] In the Shmoo plot of Figure 52(A), if the pass ratio of the DRAM chip 850 is 99% or more, it is marked as Pass, and if not, it is marked as Fail. The pass ratio refers to the percentage of memory cells that can be used to read or write data out of all memory cells under evaluation.

[0546] From FIG. 52(A), it is clear that a stable data read operation can be achieved when the voltage supplied to the word line WL is 2.0 V or more and the read time is 5.0 ns or more.

[0547] Figure 52(B) shows a shmoo plot of the write time, which is obtained by varying the voltage supplied to the word line WL from 1.5 V to 2.3 V in 0.1 V steps and varying the write time from 5.5 ns to 23 ns in 2.5 ns steps in a room temperature environment.

[0548] In the shmoo plot of FIG. 52(B), if the pass ratio of the DRAM chip 850 in a room temperature environment is 99% or more, it is marked as Pass, and if not, it is marked as Fail.

[0549] From FIG. 52(B), it is clear that a stable data write operation can be achieved when the voltage supplied to the word line WL is 1.9 V or more and the write time is 5.5 ns or more.

[0550] Here, a timing chart of the read operation in measuring the Read Time of FIG. 52(A) is shown in FIG. 53(A). As shown in FIG. 53(A), in the read operation, signals WL_EN, SA_EN, EQ_EN, CSEL_EN, and RE_EN were input to each circuit of bank 860. Each signal was controlled in synchronization with signal CLK. Therefore, the rising and falling edges of each signal were synchronized with the rising edges of signal CLK.

[0551] As shown in Figure 53(A), the number of cycles required for one read operation C1 is 9. Here, the read time in this read operation (hereinafter referred to as read time T1) is defined as the time from when signal WL_EN turns on to when signal SA_EN turns on. As shown in Figure 53(A), read time T1 corresponds to one cycle of signal CLK. In the above read operation, the frequency of signal CLK was set to 200 MHz, so read time T1 was 5 ns.

[0552] Note that the read time can be further shortened by performing the read operation without synchronizing with the signal CLK. For example, the signals WL_EN, SA_EN, EQ_EN, CSEL_EN, and RE_EN can be generated based on a delayed signal of the signal CLK. A timing chart of the read operation in this case is shown in FIG. 53(B). As shown in FIG. 53(B), the pulse widths of the signals WL_EN, SA_EN, EQ_EN, CSEL_EN, and RE_EN are shorter than those of the signals in FIG. 53(A), but the on-off sequence is the same as in FIG. 53(A). As a result, the number of cycles required for one read operation C2 according to FIG. 53(B) is one. Therefore, the read time T2 can be shorter than the read time T1.

[0553] A delay circuit 866 shown in Fig. 54(A) can be used to delay the signal CLK. As shown in Fig. 54(A), the delay circuit 866 has a plurality of buffer circuits 868 connected in series. The multi-stage buffer circuits 868 can also be configured to be connected to each other using a multiplexer or the like.

[0554] As shown in Fig. 54(B), signal IN input to delay circuit 866 passes through multi-stage buffer circuits 868 and is output as signal OUT delayed by delay time Td. The delay time Td of signal OUT can also be adjusted by appropriately selecting the number of buffer circuit stages. In this way, signals WL_EN, SA_EN, EQ_EN, CSEL_EN, and RE_EN shown in Fig. 53(B) can be generated based on signal IN and signal OUT with the delay time Td adjusted.

[0555] Figure 55 shows the results of a Spice simulation performed on a delay circuit 866 having 31 stages of buffer circuits 868. In Figure 55, the horizontal axis represents the number of stages of the buffer circuits set, and the vertical axis represents the delay time Td [ns]. Note that not all of the buffer circuits 868 have the same delay time, and some buffer circuits 868 have different delay times.

[0556] As shown in Fig. 55, by setting the number of stages of the buffer circuit 868 from 1 to 31, the delay time Td can be adjusted in the range of about 0.2 ns to about 12 ns. Therefore, as shown in Fig. 53(B), the on and off of each signal can be precisely controlled.

[0557] Figure 56 shows the measurement results of the data retention time of the DRAM chip 850 in an environment of 125°C. The horizontal axis of Figure 56 shows the retention time in logarithm, and the vertical axis shows the pass ratio, which indicates the percentage of memory cells that are able to continuously retain data compared to all memory cells evaluated.

[0558] Measurements were performed by storing different data between adjacent memory cells for one bit of data (data 1 and data 0). The fabricated DRAM chip 850 maintained a pass ratio of over 99% even after a retention time of 100 seconds in an environment of 125°C. A retention time of 100 seconds is approximately 1,563 times longer than the refresh cycle of a typical DRAM, which is 64 ms. Therefore, the fabricated DRAM chip 850 can reduce the refresh cycle and reduce standby power consumption. It was found that the fabricated DRAM chip 850 is a memory device capable of high-speed access and long-term data retention.

[0559] Table 5 shows the performance of the fabricated DRAM chip 850.

[0560] [Table 5]

[0561] The configurations, structures, or methods described in this embodiment can be used in appropriate combination with the configurations, structures, or methods described in other embodiment modes. [Explanation of symbols]

[0562] 10: transistor, 11: insulating layer, 15: memory cell, 16: memory cell, 20: slit, 20a: opening, 21: semiconductor layer, 21f: semiconductor film, 22: insulating layer, 23: conductive layer, 23a: conductive layer, 23b: conductive layer, 23f: conductive film, 24: conductive layer, 24a: conductive layer, 24a1: conductive layer, 24a2: conductive layer, 24a1f: conductive film, 24a2f: conductive film, 24b: conductive layer, 24bf: conductive film, 25: conductive layer, 25a: conductive layer, 25af: conductive film, 25b: conductive layer, 25bf: conductive film, 26: conductive layer, 27: plug, 29: conductive layer, 30: capacitance element, 40: Opening, 41: insulating layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 46a: insulating layer, 46b: insulating layer, 46c: insulating layer, 47: insulating layer, 48: insulating layer, 50: semiconductor device, 51: conductive layer, 51f: conductive film, 52: insulating layer, 53: insulating layer, 55: conductive layer, 55a: conductive layer, 55b: conductive layer, 60: layer, 61: resist mask, 70: capacitor element, 71: conductive layer, 72: insulating layer, 73: conductive layer, 80: layer, 81: conductive layer, 82: plug, 83: plug, 84: conductive layer, 85: Plug, 86: insulating layer, 87: insulating layer, 88: insulating layer, 89: plug, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 96: insulating layer, 98: element isolation layer, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device , 800: memory cell, 801: memory cell, 811: conductive layer, 812: opening, 813: conductive layer, 814: insulating layer, 815: conductive layer, 816: conductive layer, 817: conductive layer, 818: opening, 819: oxide semiconductor layer, 820: insulating layer, 821: conductive layer, 822: conductive layer, 831: characteristics, 832: characteristics, 833: characteristics, 834: characteristics, 841: sense amplifier circuit, 850: DRAM chip, 851: sense amplifier array, 852: data detection amplifier circuit, 853: sense amplifier drive circuit, 854: word line drive circuit, 855: memory cell array, 860: bank,861: wiring layer, 862: input / output circuit, 864: control circuit, 866: delay circuit, 868: buffer circuit, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941 : row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: large scale computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5 627: Electronic components, 5628: Electronic components, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6000: Storage system, 6001: Host, 6001sb: Server, 6002: Storage control circuit, 6003: Storage, 6003md: Storage device, 6800: Satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device,

Claims

1. a capacitor element, a transistor on the capacitor element, a first insulating layer, and a second insulating layer on the first insulating layer; the capacitive element includes a first conductive layer, a second conductive layer, and a third insulating layer; the transistor includes the second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, and a fourth insulating layer; the first insulating layer has an opening; the first conductive layer is located along the opening; the third insulating layer is located along the first conductive layer; the second conductive layer is located within a recess in the third insulating layer; the second insulating layer is located on the second conductive layer and has a slit reaching the second conductive layer; the third conductive layer is located on the second insulating layer; the semiconductor layer has a portion in contact with a side surface of the third conductive layer, a portion in contact with a side surface of the second insulating layer inside the slit, and a portion in contact with a top surface of the second conductive layer inside the slit; the fourth insulating layer covers the semiconductor layer inside the slit; the fourth conductive layer covers the fourth insulating layer inside the slit; the second conductive layer has first to third layers, the first layer has a recess on its upper surface; the second layer is located within a recess in the first layer; the third layer is located on the first layer and the second layer; Semiconductor device.

2. In claim 1, the height of the top surface of the first layer and the height of the top surface of the second layer are approximately the same; Semiconductor device.

3. In claim 2, a lower surface of the third layer contacting an upper surface of the first layer and an upper surface of the second layer; Semiconductor device.

4. In claim 1, the third insulating layer and the second conductive layer have substantially the same top surface shape; Semiconductor device.

5. In claim 1, a connection electrode and a fifth conductive layer; the slit extends in a first direction; the fourth conductive layer extends in the first direction within the slit, the fifth conductive layer is located on the fourth conductive layer and extends in a second direction intersecting the first direction; the connection electrode is in contact with an upper surface of the third conductive layer and a lower surface of the fifth conductive layer; Semiconductor device.

6. In any one of claims 1 to 5, the semiconductor layer comprises a first metal oxide; the third layer comprises a second metal oxide; the first metal oxide and the second metal oxide each contain indium; Semiconductor device.

7. In claim 6, the first layer comprises tungsten; the second layer comprises titanium nitride; Semiconductor device.

Images