Display panel and electronic device including the same

Abstract

To provide a display panel capable of preventing color mixture between adjacent pixels and preventing reduction in luminance while improving contact reliability.SOLUTION: In an embodiment, the display panel may further include a pixel defining layer on the driving device layer, the pixel defining layer defining a first opening exposing at least a portion of the first lower electrode, a first connection electrode on the pixel defining layer, the first connection electrode being electrically connected to the pixel driver and the first upper electrode, and a separator on the pixel defining layer. The separator may include a first separator adjacent to the first light emitting device and a second separator spaced apart from the first light emitting device with the first separator interposed therebetween, and a spacing part may be provided between the first separator and the second separator. The first separator includes a first side adjacent to the first light emitting device and a second side adjacent to the spacing part. The first connection electrode is disposed on at least a portion of the first side surface and is not disposed on the second side surface.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a display panel having improved contact reliability and preventing color mixing, and an electronic device including the same. [Background technology]

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, personal computers, navigation systems, game consoles, etc. include display panels for displaying images. The display panels include light-emitting elements and circuits for driving the light-emitting elements. The light-emitting elements included in the display panel emit light in response to a voltage applied from the circuit to generate images. Research into the connection between the light-emitting elements and the circuits has been ongoing to improve the reliability of display panels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2022-0165818 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide a display panel in which contact reliability is improved, color mixing between adjacent pixels is prevented, and a decrease in brightness is prevented. [Means for solving the problem]

[0005] A display panel according to an embodiment of the present invention includes: a driving element layer including a pixel driving unit; a first light emitting element including a first lower electrode disposed on the driving element layer; a first intermediate layer disposed on the first lower electrode and including at least a first light emitting layer; and a first upper electrode disposed on the first intermediate layer; a pixel defining layer disposed on the driving element layer and defining a first opening exposing at least a portion of the first lower electrode; a first connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving unit and the first upper electrode; and a separator disposed on the pixel defining layer. The separator includes a first separator adjacent to the first light emitting element and a second separator spaced apart from the first light emitting element across the first separator, and a separation portion is provided between the first separator and the second separator. The first separator has a first side adjacent to the first light emitting element and a second side adjacent to the separation portion. The first connecting electrode is disposed on at least a portion of the first side and not on the second side.

[0006] According to an embodiment of the present invention, the display panel further includes a second light-emitting element disposed on the driving element layer, the second light-emitting element including a second lower electrode, a second intermediate layer disposed on the second lower electrode and including at least a second light-emitting layer, and a second upper electrode disposed on the second intermediate layer. The second separator may be disposed between the second light-emitting element and the first separator in a plane.

[0007] A second opening exposing at least a portion of the second lower electrode may be defined in the pixel defining layer, and the display panel may further include a second connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the second upper electrode.

[0008] The second separator may include a third side adjacent to the second light emitting element and a fourth side adjacent to the separation portion. The second connecting electrode may be disposed on at least a portion of the third side and not on the fourth side. Neither the first connecting electrode nor the second connecting electrode may be disposed on the separation portion.

[0009] The first intermediate layer may further include a first functional layer, which may include a first intermediate functional layer disposed on the first lower electrode and a second intermediate functional layer disposed on the first light-emitting layer, and the first light-emitting layer may be disposed between the first intermediate functional layer and the second intermediate functional layer.

[0010] The display panel according to an embodiment of the present invention may further include a first dummy layer disposed on the first separator and including the same material as the first functional layer, and a second dummy layer disposed on the first dummy layer and including the same material as the first upper electrode, and the first connecting electrode may be in contact with the second dummy layer.

[0011] A display panel according to one embodiment of the present invention may further include a first additional dummy layer disposed in the separation portion and containing the same material as the first functional layer, and a second additional dummy layer disposed on the first additional dummy layer and containing the same material as the first upper electrode.

[0012] The first connecting electrode may have a ring shape surrounding the first opening.

[0013] In a first contact region adjacent to the first separator, the lower surface of the first upper electrode may contact the upper surface of the first connecting electrode.

[0014] The first connecting electrode may include a first connecting portion disposed in the first contact region, a second connecting portion disposed on the first side surface of the first separator, and a third connecting portion disposed on the top surface of the separator.

[0015] The first upper electrode may include a first upper electrode portion in contact with an upper surface of the first connecting portion and a second upper electrode portion in contact with a side surface of the second connecting portion.

[0016] The display panel according to an embodiment of the present invention may further include an additional separator disposed in the spaced apart portion, the additional separator being spaced apart from the first separator and the second separator.

[0017] A through hole may be defined in the pixel defining layer, and the first connecting electrode may be connected to the pixel driving part through the through hole.

[0018] The first intermediate layer may overlap the through hole.

[0019] In an intermediate region disposed between the first separator and the first light emitting element, the first intermediate layer may be disposed between the first connecting electrode and the first upper electrode.

[0020] A display panel according to an embodiment of the present invention includes a driving element layer including a pixel driving unit, a first light emitting element disposed on the driving element layer and including a first lower electrode, a first intermediate layer disposed on the first lower electrode and including at least a first light emitting layer, and a first upper electrode disposed on the first intermediate layer, a second light emitting element disposed on the driving element layer and including a second lower electrode, a second intermediate layer disposed on the second lower electrode and including at least a second light emitting layer, and a second upper electrode disposed on the second intermediate layer, and a second light emitting element disposed on the driving element layer and including at least a second light emitting layer. a pixel defining layer defining a first opening exposing a portion of the second lower electrode and a second opening exposing at least a portion of the second lower electrode, a first connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the first upper electrode, a second connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the second upper electrode, and a separator disposed on the pixel defining layer and including a first separator adjacent to the first light emitting element and a second separator spaced from the first separator and adjacent to the second light emitting element, wherein a distance between the first separator and the second separator is smaller than a distance between the first connecting electrode and the second connecting electrode.

[0021] The first intermediate layer may further include a first functional layer. The first functional layer may include a first intermediate functional layer disposed on the first lower electrode and a second intermediate functional layer disposed on the first light-emitting layer, and the first light-emitting layer may be disposed between the first and second intermediate functional layers. The second intermediate layer may further include a second functional layer. The second functional layer may include a third intermediate functional layer disposed on the second lower electrode and a fourth intermediate functional layer disposed on the second light-emitting layer, and the second light-emitting layer may be disposed between the third and fourth intermediate functional layers.

[0022] The display panel according to an embodiment of the present invention may further include a first dummy layer disposed on the first separator and including the same material as the first functional layer, a second dummy layer disposed on the first dummy layer and including the same material as the first upper electrode, a third dummy layer disposed on the second separator and including the same material as the second functional layer, and a fourth dummy layer disposed on the second dummy layer and including the same material as the third upper electrode. The first connecting electrode may be in contact with the second dummy layer, and the second connecting electrode may be in contact with the fourth dummy layer.

[0023] A separation distance between the second dummy layer and the fourth dummy layer may be smaller than a separation distance between the first connecting electrode and the second connecting electrode.

[0024] The first connecting electrode and the second connecting electrode may not be disposed in a spaced apart portion between the first separator and the second separator.

[0025] A display panel according to one embodiment of the present invention may further include a first additional dummy layer disposed between the first separator and the second separator and containing the same material as the first functional layer and the second functional layer, respectively, and a second additional dummy layer disposed on the first additional dummy layer and containing the same material as the first upper electrode and the second upper electrode, respectively.

[0026] According to an embodiment of the present invention, an electronic device includes: a driving element layer including a pixel driving unit; a first light emitting element disposed on the driving element layer, the first light emitting element including a first lower electrode, a first intermediate layer disposed on the first lower electrode and including at least a first light emitting layer, and a first upper electrode disposed on the first intermediate layer; a second light emitting element disposed on the driving element layer, the second lower electrode, a second intermediate layer disposed on the second lower electrode and including at least a second light emitting layer, and a second upper electrode disposed on the second intermediate layer; a pixel defining layer disposed on the driving element layer, the pixel defining layer defining a first opening exposing at least a portion of the first lower electrode and a second opening exposing at least a portion of the second lower electrode; a connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving unit; and a separator disposed on the pixel defining layer, the separator including a first separator adjacent to the first light emitting element and a second separator spaced apart from the first separator, and a separator provided between the first separator and the second separator. The connecting electrode is not disposed between the first separator and the second separator. [Effects of the Invention]

[0027] As described above, in the display panel of one embodiment, the connection electrodes electrically connected to the cathodes of the light-emitting elements and the pixel driving circuits are contacted in areas adjacent to the separators provided to separate the pixels and at the sides of the separators, thereby achieving connection over a relatively wide area and improving contact reliability. Meanwhile, the display panel of one embodiment includes a plurality of separators provided between adjacent pixels and spacers provided therebetween, thereby preventing leakage current from occurring between adjacent pixels. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 2a] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 2b] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 2c] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 3a] 1 is a plan view showing a simplified display panel according to an embodiment of the present invention; [Figure 3b] 1 is a plan view showing a simplified display panel according to an embodiment of the present invention; [Figure 4a] 1 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 4b] 1 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 4c] 1 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 4d] 1 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 5] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 7a] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 7b] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 8a] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 8b] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention; [Figure 8c] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0029] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on," "coupled," or "bonded" to another component, it means that it may be directly positioned, coupled, or bonded to the other component, or that a third component may be disposed therebetween.

[0030] The same reference numerals refer to the same elements. In the drawings, the thickness, proportions, and dimensions of the elements are exaggerated for the purpose of effectively explaining the technical content. "And / or" includes all combinations of one or more elements defined by the associated elements.

[0031] Terms such as "first" and "second" are used to describe various components, but the components are not limited to these terms. These terms are used only to distinguish one component from another. For example, a first component may be designated as a "second component" without departing from the scope of the present invention, and similarly, a second component may be designated as a "first component." A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0032] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0033] It should be understood that the terms "comprise" or "have" and the like specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth above in the specification, but do not preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] The terms "part" and "unit" refer to a software component or hardware component that performs a specific function. Hardware components include, for example, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). A software component refers to executable code and / or data used by executable code in an addressable storage medium. Thus, software components include, for example, object-oriented software components, class components, and operation components, and include processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the present invention belongs. Furthermore, terms that are the same as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless explicitly defined herein.

[0036] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0037] FIG. 1 is a block diagram of a nail display device DD according to an embodiment of the present invention.

[0038] Referring to FIG. 1, the display device DD may include a display panel DP, panel drivers SDC, EDC, DDC, a power supply unit PWS, and a timing controller TC. In this embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In the following embodiments, an organic light-emitting display panel will be used as an example for detailed description. The panel drivers SDC, EDC, DDC may include a scan driver SDC, an emission driver EDC, and a data driver DDC.

[0039] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, luminescence lines ESL1 to ESLn, and data lines DL1 to DLm. The display panel DP may include a plurality of pixels connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, the luminescence lines ESL1 to ESLn, and the data lines DL1 to DLm (where m and n are integers greater than 1).

[0040] For example, a pixel PXij (where i and j are integers greater than 1) located on the ith horizontal line (or ith line) and jth vertical line (or jth pixel column) may be connected to the ith first scan line (or write scan line) GWLi, the ith second scan line (or compensation scan line) GCLi, the ith third scan line (or first initialization scan line) GILi, the ith fourth scan line (or second initialization scan line) GBLi, the ith fifth scan line (or reset scan line) GRLi, the jth data line DLj, and the ith emission line ESLi.

[0041] The pixel PXij may include a plurality of light-emitting elements, a plurality of transistors, and a plurality of capacitors, and may be supplied with a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (or reference voltage) VREF, a fourth power supply voltage (or first initialization voltage) VINT1, a fifth power supply voltage (or second initialization voltage) VINT2, and a sixth power supply voltage (or compensation voltage) VCOMP via a power supply unit PWS.

[0042] The first and second power supply voltages VDD and VSS are set to have voltage values ​​such that a current flows through the light emitting device to emit light. For example, the first power supply voltage VDD may be set to a voltage higher than the second power supply voltage VSS.

[0043] The third power supply voltage VREF may be a voltage for initializing the gate of the driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to implement a predetermined gray level by using a voltage difference with the data signal. To this end, the third power supply voltage VREF may be set to a predetermined voltage within the voltage range of the data signal.

[0044] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage higher than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. That is, the fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF by the threshold voltage of the driving transistor, but the present invention is not limited thereto.

[0045] The fifth power supply voltage VINT2 may be a voltage for initializing the cathode of the light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or may be set to a voltage similar to or the same as the third power supply voltage VREF, but is not limited thereto. The fifth power supply voltage VINT2 may be set to a voltage similar to or the same as the first power supply voltage VDD.

[0046] The sixth power supply voltage VCOMP may provide a predetermined current to the drive transistor when compensating for the threshold voltage of the drive transistor.

[0047] 1 shows that the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, and VCOMP are all supplied from the power supply unit PWS, but the present invention is not limited thereto. For example, the first power supply voltage VDD and the second power supply voltage VSS may all be supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied depending on the structure of the pixel PXij.

[0048] In the embodiment of the present invention, the signal lines connected to the pixels PXij can be variously set in accordance with the circuit structure of the pixels PXij.

[0049] The scan driver SDC receives a first control signal SCS from the timing controller TC and can supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0050] The scan signal may be set to a voltage that turns on the transistor to which the scan signal is supplied. For example, the scan signal supplied to a P-type transistor may be set to a logic low level, and the scan signal supplied to an N-type transistor may be set to a logic high level. Hereinafter, "a scan signal is supplied" may be interpreted as meaning that the scan signal is supplied to a logic level that turns on the transistor controlled by the scan signal.

[0051] 1, for convenience of explanation, the scan driver SDC is shown as a single configuration, but the present invention is not limited to this. According to an embodiment, a plurality of scan drivers may be included to supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn, respectively.

[0052] The light emitting driver EDC may provide light emitting signals to the light emitting lines ESL1 to ESLn in response to the second control signal ECS. For example, the light emitting signals may be sequentially provided to the light emitting lines ESL1 to ESLn.

[0053] The transistors connected to the light emitting lines ESL1 to ESLn of the present invention may be N-type transistors. In this case, the light emitting signals supplied to the light emitting lines ESL1 to ESLn may be set to a gate open voltage. The transistors receiving the light emitting signals may be turned off when the light emitting signals are supplied, and may be turned on otherwise.

[0054] The second control signal ECS includes a light emission start signal and a clock signal, and the light emission driver EDC may be implemented as a shift register that sequentially shifts the pulsed light emission start signal using the clock signal to sequentially generate and output the pulsed light emission signals.

[0055] The data driver DDC may receive a third control signal DCS and video data RGB from the timing controller TC. The data driver DDC may convert the digital video data RGB into an analog data signal (i.e., data voltage). The data driver DDC may provide data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0056] The third control signal DCS may include a data enable signal instructing output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register that shifts the horizontal start signal in synchronization with the data clock signal to generate a sampling signal, a latch that latches image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data (e.g., digital data) into an analog data signal, and a buffer (or amplifier) ​​that outputs the data signal to the data lines DL1 to DLm.

[0057] The power supply unit PWS may supply a first power supply voltage VDD, a second power supply voltage VSS, and a third power supply voltage VREF to the display panel DP for driving the pixels PXij, and may also supply at least one of a fourth power supply voltage VINT1, a fifth power supply voltage VINT2, and a sixth power supply voltage VCOMP to the display panel DP.

[0058] As an example, the power supply unit PWS may supply a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VREF, a fourth power supply voltage VINT1, a fifth power supply voltage VINT2, and a sixth power supply voltage VCOMP to the display panel DP via a first power supply line VDL (see FIG. 2a), a second power supply line VSL (see FIG. 2a), a third power supply line VRL (or a reference voltage line, see FIG. 2a), a fourth power supply line VIL1 (or a first initialization voltage line, see FIG. 2a), a fifth power supply line VIL2 (or a second initialization voltage line, see FIG. 2a), and a sixth power supply line VCL (or a compensation voltage line, see FIG. 2a), respectively, which are not shown.

[0059] The power supply unit PWS may be implemented as a power management integrated circuit, but is not limited to this.

[0060] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal. The first control signal SCS may be supplied to the scan driver SDC, the second control signal ECS may be supplied to the emission driver EDC, the third control signal DCS may be supplied to the data driver DDC, and the fourth control signal PCS may be supplied to the power driver PDC. The timing controller TC may rearrange the input image data IRGB in accordance with the arrangement of the pixels PXij in the display panel DP to generate image data RGB (or frame data).

[0061] Meanwhile, the scan driver SDC, emission driver EDC, data driver DDC, power supply PWS, and / or timing controller TC may be formed directly on the display panel DP or provided as separate driver chips and connected to the display panel DP. At least two of the scan driver SDC, emission driver EDC, data driver DDC, power supply PWS, and timing controller TC may be provided as a single driver chip. For example, the data driver DDC and timing controller TC may be provided as a single driver chip.

[0062] Although the display device DD according to one embodiment has been described with reference to FIG. 1, the display device of the present invention is not limited thereto. Signal lines may be added or omitted depending on the pixel configuration. Furthermore, the connection relationship between a pixel and a signal line may be changed. When one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0063] 2a, 2b, and 2c are equivalent circuit diagrams of pixels according to an embodiment of the present invention, each of which exemplarily illustrates an equivalent circuit diagram of a pixel (PXij, PXij-1, PXij-2) connected to an i-th first scan line GWLi (hereinafter referred to as the first scan line) and a j-th data in DLj (hereinafter referred to as the data line).

[0064] 2a, the pixel PXij may include a light emitting element LD and a pixel driving circuit PDC, The light emitting element LD is connected between the first power line VDL and the pixel driving circuit PDC.

[0065] The pixel driver PDC may be connected to a plurality of scan lines GWLi, GCLi, GILi, GBLi, GRLi, data lines DLj, light emitting lines ESLi, and a plurality of power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The pixel driver PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8, a first capacitor C1, and a second capacitor C2. Hereinafter, the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8 will be described as being N-type. However, the present invention is not limited to this embodiment. Some of the first to eighth transistors T1 to T8 may be N-type transistors and the rest may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be P-type transistors.

[0066] The gate of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power supply line VDL to the second power supply line VSL via the light emitting element LD in response to the voltage of the first node N1. In this case, the first power supply voltage VDD may be set to a voltage having a higher potential than the second power supply voltage VSS.

[0067] In this specification, "electrically connected between a transistor and a signal line or between transistors" means "the source, drain, and gate of a transistor are integral with the signal line or are connected via a connecting electrode."

[0068] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 may be turned on when the write scan signal GW is supplied to the write scan line GWLi to electrically connect the data line DLj to the first node N1.

[0069] The third transistor T3 may be coupled between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be coupled to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through an i-th fifth scan line GRLi (hereinafter, a reset scan line). When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to provide the reference voltage VREF to the first node N1.

[0070] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. A first electrode of the fourth transistor T4 may be connected to the third node N3, and a second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 that provides the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. A gate of the fourth transistor T4 may receive a first initialization scan signal GI through an i-th third scan line GILi (hereinafter, referred to as the first initialization scan line). The fourth transistor T4 may be turned on when the first initialization scan signal GI is provided to the first initialization scan line GILi, and may provide the first initialization voltage VINT1 to the third node N3.

[0071] The fifth transistor T5 may be connected between the compensation power line VCL and the second node N2. A first electrode of the fifth transistor T5 receives the compensation voltage VCOMP through the compensation voltage line VCL, and a second electrode of the fifth transistor T5 is connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 may receive a compensation scan signal GC through an i-th second scan line GCLi (hereinafter, the compensation scan line). The fifth transistor T5 may be turned on when the compensation scan signal GC is supplied to the compensation scan line CGLi, and may provide the compensation voltage VCOMP to the second node N2, thereby compensating the threshold voltage of the first transistor T1 during the compensation period.

[0072] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. Specifically, the gate of the sixth transistor T6 may receive an emission signal EM via an i-th emission line ESLi (hereinafter, emission line). A first electrode of the sixth transistor T6 may be connected to the cathode of the light emitting element LD via a fourth node N4, and a second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1 via a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. When an emission signal EM is provided to the emission line ESLi, the sixth transistor T6 may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0073] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. A first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the seventh transistor T7 may receive the second power voltage VSS through the second power line VSL. A gate of the seventh transistor T7 may be electrically connected to the light emitting line ESLi. The seventh transistor T7 may be referred to as a second light emitting control transistor. When an light emitting signal EM is provided to the light emitting line ESLi, the seventh transistor T7 is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0074] Meanwhile, in this embodiment, the sixth transistor T6 and the seventh transistor T7 are connected to the same emission line ESLi and turned on by the same emission signal EM, but this is shown for illustrative purposes only, and the sixth transistor T6 and the seventh transistor T7 may be turned on independently by different signals that are distinct from each other. Also, in the pixel driver PDC according to an embodiment of the present invention, either the sixth transistor T6 or the seventh transistor T7 may be omitted.

[0075] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter, the second initialization scan line), a first power supply connected to the second initialization voltage node VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to a second initialization scan signal GB transmitted via the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0076] Meanwhile, in this embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be operated simultaneously by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be turned on / off simultaneously by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be provided as a substantially single scan line. As a result, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 may be performed at the same timing. However, this is merely an example and is not limited to any one embodiment.

[0077] Furthermore, according to the present invention, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 can be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be provided as a substantially single power supply voltage line. In this case, the cathode initialization operation and the compensation operation of the driving transistor can be performed using a single power supply voltage, which can simplify the design of the driving unit. However, this is shown by way of example only, and one embodiment of the present invention is not limited to any one embodiment.

[0078] The first capacitor C1 may be disposed between the first node N1 and the second node N2. The first capacitor C1 may store a difference voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0079] The second capacitor C2 may be disposed between the third node N3 and the second power supply VSL. That is, one electrode of the second capacitor C2 may be coupled to the first power supply line VSL, which is supplied with the first power supply VSS, and the other electrode of the second capacitor C2 may be coupled to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power supply VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor. The second capacitor C2 may have a higher storage capacitance than the first capacitor C1. As a result, the second capacitor C2 may minimize a voltage change at the third node N3 in response to a voltage change at the first node N1.

[0080] In this embodiment, the light emitting element LD may be connected to the pixel driver PDC through a fourth node N4. The light emitting element LD may include an anode connected to the first power line VDL and a cathode opposite the anode. In this embodiment, the light emitting element LD may be connected to the pixel driver PDC through the cathode. That is, in the pixel PXij according to the present invention, the connection node between the light emitting element LD and the pixel driver PDC may be the fourth node N4, which may correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Therefore, the potential of the fourth node N4 may substantially correspond to the cathode potential of the light emitting element LD.

[0081] Specifically, the anode of the light emitting element LD is connected to the first power line VDL and receives the first power voltage VDD, and the cathode is connected to the first transistor T1 via the sixth transistor T6. That is, in this embodiment, in which the first to eighth transistors T1 to T8 are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is the driving transistor, may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if degradation of the light emitting element LD occurs, the influence on the transistors constituting the pixel driver PDC, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. That is, the amount of change in driving current due to degradation of the light emitting element LD may be reduced, and image retention of the display panel due to increased use time may be reduced, thereby improving the lifespan.

[0082] Alternatively, as shown in FIG. 2b, pixel PXij-1 may include a pixel driver PDC-1 including two transistors T1 and T2 and a first capacitor C1. The pixel driver PDC-1 is connected to the light emitting element LD, the write scan line GWLi, the data line DLj, and the second power line VSL. The pixel driver PDC-1 shown in FIG. 2b may correspond to the pixel driver PDC shown in FIG. 2a with the third to eighth transistors T3 to T8 and the second capacitor C2 omitted.

[0083] Each of the first and second transistors T1 and T2 may be an N-type or P-type transistor. In this embodiment, the first and second transistors T1 and T2 are N-type transistors.

[0084] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 may be connected to the light emitting element LD via the second node N2 and to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0085] The second transistor T2 may include a gate receiving a write scan signal GW via a write scan line GWLi, a first electrode coupled to the data line DLj, and a second electrode coupled to the first node N1, and may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted via the write scan line GWLi.

[0086] The first capacitor C1 may include an electrode coupled to the first node N1 and an electrode coupled to the third node N3, and may store a data signal DATA transmitted to the first node N1.

[0087] The light emitting element LD may include an anode and a cathode. In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving unit PDC-1 via the second node N2. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-1.

[0088] In this embodiment, the first and second transistors T1 and T2 are N-type transistors, and the second node N2, to which the cathode of the light emitting element LD and the pixel driver PDC-1 are connected, may correspond to the drain of the first transistor T1. That is, the gate-source voltage Vgs of the first transistor T1 due to the light emitting element LD may be prevented. As a result, the amount of change in driving current due to degradation of the light emitting element LD may be reduced, and image retention of the display panel due to increased use time may be reduced, thereby improving the lifespan of the display panel.

[0089] Alternatively, as shown in FIG. 2c, pixel PXij-2 may include a pixel driver PDC-2 including six transistors T1, T2, T3, T4a, T5a, T6a, and two first capacitors C1, C2.

[0090] The pixel driving unit PDC-2 may be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first light emitting line ESL1i (hereinafter referred to as the first light emitting line), the i-th second light emitting line ESL2i (hereinafter referred to as the second light emitting line), the data line DLj, the first power supply line VDL, the second power supply line VSL, the third power supply line VRL, and the initialization voltage line VIL.

[0091] The pixel driver PDC-2 shown in Figure 2c may have a structure similar to that of the pixel driver PDC shown in Figure 2a, with the fourth transistor T4 and the fifth transistor T5 omitted. The area of ​​the pixel driver PDC-2 shown in Figure 2c is smaller than the area of ​​the pixel driver PDC shown in Figure 2a, which may make it easier to achieve high resolution.

[0092] The first and sixth transistors T1, T2, T3, T4a, T5a, and T6a may be N-type or P-type transistors. In this embodiment, the first and sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors.

[0093] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 may be connected to the light emitting element LD via the second node N2 and to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0094] The second transistor T2 may include a gate receiving a write scan signal GW via a write scan line GWLi, a first electrode coupled to the data line DLj, and a second electrode coupled to the first node N1, and may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted via the write scan line GWLi.

[0095] The third transistor T3 may be coupled between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be coupled to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through a reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to provide the reference voltage VREF to the first node N1.

[0096] The fourth transistor T4a may be connected between the first transistor T1 and the light emitting element LD. More specifically, the gate of the fourth transistor T4a may receive a first light emitting signal EM1 via a first light emitting line ESLi. A first electrode of the fourth transistor T4a may be connected to the cathode of the light emitting element LD via a fourth node N4, and a second electrode of the fourth transistor T4a may be connected to the first electrode of the first transistor T1 via a second node N2. The fourth transistor T4a may be referred to as a first light emitting control transistor. When the first light emitting signal EM1 is provided to the first light emitting line ESL1i, the fourth transistor T4a may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0097] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. A first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the fifth transistor T5a may receive the second power supply voltage VSS through the second power line VSL. A gate of the fifth transistor T5a may be electrically connected to the second light-emitting line ESL2i. The fifth transistor T5a may be referred to as a second light-emitting control transistor. When a second light-emitting signal EM2 is provided to the second light-emitting line ESL2i, the fifth transistor T5a is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0098] Meanwhile, in this embodiment, the fourth transistor T4a and the fifth transistor T5a are connected to first and second light-emitting lines ESL1i and ESL2i, respectively, and are turned on via first and second light-emitting signals EM1 and EM2, respectively. That is, the fourth transistor T4a and the fifth transistor T5a may be turned on independently. However, this is merely an example and is not limiting. For example, in this embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to the same light-emitting line and controlled by the same light-emitting signal. In addition, in the pixel driver PDC-2 according to this embodiment, either the fourth transistor T4a or the fifth transistor T5a may be omitted.

[0099] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. That is, the sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may supply the initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0100] The first capacitor C1 may be disposed between the first node N1 and the second node N2. The first capacitor C1 may store a difference voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0101] The second capacitor C2 may be disposed between the third node N3 and the second power supply VSL. That is, one electrode of the second capacitor C2 may be coupled to the first power supply line VSL, which is supplied with the first power supply VSS, and the other electrode of the second capacitor C2 may be coupled to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power supply VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor.

[0102] The light emitting element LD may include an anode and a cathode. In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving unit PDC-2 via a fourth node N4. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1 via a fourth transistor T4a. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-2.

[0103] In this embodiment, where the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors, the potential of the third node N3, which corresponds to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting device LD. Therefore, even if the light emitting device LD deteriorates, the influence on the transistors constituting the pixel driver PDC-2, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. In other words, the amount of change in driving current due to deterioration of the light emitting device LD may be reduced, and image retention of the display panel due to increased use time may be reduced, thereby improving the lifespan of the display panel.

[0104] Meanwhile, Figures 2a, 2b, and 2c show circuits for pixel drivers PDC, PDC-1, and PDC-2 according to an embodiment of the present invention, and the display panel according to an embodiment of the present invention is not limited to any one embodiment, and the number and arrangement of transistors and the number and arrangement of capacitors can be designed in various ways as long as they are circuits connected to the cathode of the light emitting element LD.

[0105] 3A and 3B are plan views each showing a simplified display panel according to an embodiment of the present invention, with some components omitted. The following description will be given with reference to FIGS. 3A and 3B.

[0106] 3a, a display panel DP according to an embodiment is divided into a display area DA and a peripheral area (or non-display area) NDA. The display area DA may include a plurality of light emitting portions EP.

[0107] The light-emitting portions EP may be areas that are respectively illuminated by the pixels PXij (see FIG. 1). More specifically, each light-emitting portion EP may correspond to a light-emitting opening OP-PDL (see FIG. 5) described later. The light-emitting opening OP-PDL may be referred to as an opening or an aperture.

[0108] The peripheral area NDA may be disposed adjacent to the display area DA. In this embodiment, the peripheral area NDA is illustrated as surrounding the edge of the display area DA. However, this is merely an example, and the peripheral area NDA may be disposed on one side of the display area DA or may be omitted.

[0109] In this embodiment, the scan driver SDC and the data driver DDC may be mounted on the display panel DP. In one embodiment, the scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the peripheral area NDA. The scan driver SDC may overlap in plan with at least some of the light emitting units EP disposed in the display area DA. By disposing the scan driver SDC in the display area DA, the area of ​​the peripheral area NDA may be reduced compared to conventional display panels in which the scan driver is disposed in the peripheral area, making it easier to implement a display device with a thin bezel.

[0110] 3a, the scan driver SDC may be provided in two separate parts. The two scan drivers SDC may be spaced apart on either side of the center of the display area DA. Alternatively, the number of scan drivers SDC may be greater than two, and the present invention is not limited to any one embodiment.

[0111] 3A shows an example of a display panel, and the data driver DDC may be disposed in the display area DA. In this case, a portion of the light emitting unit EP disposed in the display area DA may overlap the data driver DDC on a plane.

[0112] In one embodiment, the data driver DDC may be provided in the form of a separate driver independent of the display panel DP and connected to the display panel DP, but this is merely an example, and the data driver DDC may be formed in the same process as the scan driver SDC to configure the display panel DP, and is not limited to any one embodiment.

[0113] As shown in Figure 3b, the display panel DP may have a length in the first direction DR1 that is longer than the length in the second direction DR2. A plurality of pixels PX11 to PXnm are exemplarily shown arranged in n rows and m columns in the display area DA. In this embodiment, the display panel DP may include a plurality of pixel drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 are exemplarily shown to include a first scan driver SDC1 and a second scan driver SDC2 that are spaced apart from each other in the first direction.

[0114] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to other parts of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0115] For ease of explanation, pads PD of the data lines DL1 to DLm are shown in Figure 3b. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driver DDC (see Figure 3a) via the pads PD.

[0116] According to the present invention, the pads PD may be divided and arranged at positions spaced apart from each other across the display area DA in the peripheral area NDA. For example, some of the pads DP may be arranged on the upper side, i.e., adjacent to the first scan line GL1 of the scan lines GL1 to GLn, and other pads DP may be arranged on the lower side, i.e., adjacent to the last scan line GLn of the scan lines GL1 to GLn. In this embodiment, the pads PD connected to odd-numbered data lines among the data lines DL1 to DLm may be arranged on the upper side, and the pads PD connected to even-numbered data lines among the data lines DL1 to DLm may be arranged on the lower side.

[0117] Although not shown, the display panel DP may include a plurality of upper data drivers connected to the pads PD arranged on the upper side and / or a plurality of lower data drivers connected to the pads PD arranged on the lower side. However, this is an exemplary explanation, and the display panel DP may include one upper data driver connected to the pads PD arranged on the upper side and / or one lower data driver connected to the pads PD arranged on the lower side. The pad PD according to an embodiment of the present invention may be arranged on only one side of the display panel DP and connected to a single data driver, and is not limited to any one embodiment.

[0118] Also, as described in Figure 3a, the display panel DP in Figure 3b may also have scan drivers and / or data drivers arranged in the display area DA, and as a result, some of the light-emitting units arranged in the display area DA may overlap the scan drivers and / or data drivers in a plane.

[0119] 4a to 4d are enlarged plan views of a partial area of ​​a display panel according to an embodiment of the present invention.

[0120] 4a exemplarily shows two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. Referring to FIG. 4a, the first row Rk light emitting unit includes light emitting units constituting the first row, first column light emitting unit UT11 and the first row, second column light emitting unit UT12, and the second row Rk+1 light emitting unit includes light emitting units constituting the second row, first column light emitting unit UT21 and the second row, second column light emitting unit UT22.

[0121] Each of the light-emitting portions EP1, EP2, and EP3 may correspond to a light-emitting opening OP-PDL (see FIG. 5) described later. That is, each of the light-emitting portions EP1, EP2, and EP3 may be an area from which light is emitted by the light-emitting element described above. Each of the light-emitting portions EP1, EP2, and EP3 may correspond to a unit that configures an image displayed on the display panel DP (see FIG. 1). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by a light-emitting opening OP-PDL described later, in particular, an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0122] The light-emitting units EP1, EP2, and EP3 may include a first light-emitting unit EP1, a second light-emitting unit EP2, and a third light-emitting unit EP3. The first light-emitting unit EP1, the second light-emitting unit EP2, and the third light-emitting unit EP3 may emit light of different colors. For example, the first light-emitting unit EP1 may emit red light, the second light-emitting unit EP2 may emit green light, and the third light-emitting unit EP3 may emit blue light, but the color combination is not limited to this. Furthermore, at least two of the first to third light-emitting units EP1, EP2, and EP3 may emit light of the same color. For example, the first to third light-emitting units EP1, EP2, and EP3 may all emit blue light or all emit white light.

[0123] The third light-emitting unit EP3, which displays light emitted by a third light-emitting element among the first to third light-emitting units EP1, EP2, and EP3, may include two sub-light-emitting units EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is merely an example, and the third light-emitting unit EP3 may be provided in a single pattern having an integrated shape like the first and second light-emitting units EP1 and EP2, or either one of the first and second light-emitting units EP1 and EP2 may have a spaced-apart sub-light-emitting unit, and the present invention is not limited to any one embodiment.

[0124] The first row Rk light-emitting unit may include first to third light-emitting units EP1, EP2, EP3 that constitute the first row and first column light-emitting unit UT11, and first to third light-emitting units EP1, EP2, EP3a that constitute the first row and second column light-emitting unit UT12, and the second row Rk+1 light-emitting unit may include first to third light-emitting units EP1, EP2, EP3a that constitute the second row and first column light-emitting unit UT21, and first to third light-emitting units EP1, EP2, EP3 that constitute the second row and second column light-emitting unit UT22.

[0125] In one embodiment of the present invention, the light emitting units constituting the first row, first column light emitting unit UT11 and the light emitting units constituting the second row, second column light emitting unit UT22 may have substantially the same shape. Also, the light emitting units constituting the first row, second column light emitting unit UT12 and the light emitting units constituting the second row, first column light emitting unit UT21 may have substantially the same shape. The light emitting units constituting the first row, first column light emitting unit UT11 may have a different shape from the light emitting units constituting the first row, second column light emitting unit UT12. For example, a portion of the light emitting unit Rk in the first row and a portion of the light emitting unit RK+1 in the second row may have symmetrical shapes.

[0126] In one embodiment of the present invention, the third light-emitting part EP3a of the second row, first column light-emitting unit UT21 and the third light-emitting part EP3 of the first row, first column light-emitting unit UT11 may have a shape and arrangement that is line-symmetrical with respect to the axis aligned with the first direction DR1, and the third light-emitting part EP3 of the second row, second column light-emitting unit UT22 and the third light-emitting part EP3a of the first row, second column light-emitting unit UT12 may have a shape and arrangement that is line-symmetrical with respect to the axis aligned with the first direction DR1, but this is merely an example and is not limiting.

[0127] Figure 4b shows light emitting portions arranged in a row. For ease of explanation, Figure 4b also shows a plurality of upper electrodes EL21, EL22, and EL23, a plurality of circuit driving units PDC1, PDC2, and PDC3, first to third connecting electrodes CNE1, CNE2, and CNE3, and a separator SPR. Figure 4c shows the separator SPR, a plurality of light emitting portions EP1, EP2, and EP3 arranged in an area defined by the separator SPR, and a plurality of connecting electrodes CNE1, CNE2, and CNE3, which are included in the display panel configuration.

[0128] 4a to 4c, the top electrodes EL21, EL22, and EL23 may be electrically disconnected by being separated from one another by separators SPR. In this embodiment, one light-emitting unit UT11 may include three light-emitting portions EP1, EP2, and EP3. Accordingly, the light-emitting unit UT11 may include three top electrodes EL21, EL22, and EL23 (hereinafter referred to as first to third cathodes), three pixel driving portions PDC1, PDC2, and PDC3, and three connecting electrodes CNE1, CNE2, and CNE3. However, this is merely an example, and the number and arrangement of the light-emitting portions included in the light-emitting unit UT11 may be variously designed and is not limited to any one embodiment.

[0129] The separator SPR includes a first separator SPR1 adjacent to the first light-emitting portion EP1 and a second separator SPR2 adjacent to the second light-emitting portion EP2. The separator SPR may further include a third separator SPR3 adjacent to the third light-emitting portion EP3. The first separator SPR1, the second separator SPR2, and the third separator SPR3 may each have a shape that surrounds at least a portion of the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3, respectively.

[0130] A spacing portion SPP may be provided between two adjacent separators SPR. A spacing portion SPP may be provided between the first separator SPR1 and the second separator SPR2, between the second separator SPR2 and the third separator SPR23, and between the third separator SPR3 and the first separator SPR1. As shown in FIG. 4c, a first spacing portion SPP1 may be provided between the first separator SPR1 and the second separator SPR2, a second spacing portion SPP2 may be provided between the second separator SPR3 and the first separator SPR1, and a third spacing portion SPP3 may be provided between the second separator SPR2 and the third separator SPR3. The spacing portion SPP provided between two adjacent separators may prevent a short circuit from occurring between adjacent light emitting portions EP1, EP2, and EP3. The specific shapes of the separator SPR and the separating portion SPP will be described in more detail later in the description regarding FIG. 6 and the like.

[0131] The first to third pixel driving units PDC1, PDC2, and PDC3 are electrically connected to the first to third light emitting elements LD1, LD2, and LD3, respectively, including the first to third light emitting units EP1, EP2, and EP3. In this specification, "connected" refers not only to being connected by direct physical contact but also to being electrically connected.

[0132] Also, as shown in FIG. 4b, each area where the first to third pixel driving units PDC1, PDC2, and PDC3 are defined on a plane may correspond to a unit in which transistors and capacitor elements constituting the pixel driving unit PDC (see FIG. 2a) for driving the light emitting element of the pixel are repeatedly arranged.

[0133] The first to third pixel driving units PDC1, PDC2, and PDC3 may be sequentially arranged along the first direction DR1. Meanwhile, the arrangement positions of the first to third pixel driving units PDC1, PDC2, and PDC3 may be designed independently of the positions and shapes of the first to third light emitting units EP1, EP2, and EP3.

[0134] For example, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged in areas defined by the separators SPR, i.e., at positions different from the positions where the first to third cathodes EL21, EL22, and EL23 are arranged, or may be designed to have shapes and areas different from the shapes of the first to third cathodes EL21, EL22, and EL23. Alternatively, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged to overlap the positions where the first to third light emitting units EP1, EP2, and EP3 are located, respectively, and may be designed to have shapes having areas similar to the areas defined by the separators SPR, for example, the first to third cathodes EL21, EL22, and EL23.

[0135] In this embodiment, the first to third pixel driving circuits PDC1, PDC2, and PDC3 are each shown as a rectangle, the first to third light emitting circuits EP1, EP2, and EP3 are each arranged in a different shape with a smaller area, and the first to third cathodes EL21, EL22, and EL23 are shown as irregular shapes that are arranged at positions overlapping the first to third light emitting circuits EP1, EP2, and EP3.

[0136] 4b, the first pixel driver PDC1 may be disposed at a position where it partially overlaps with the first light emitter EP1, the second light emitter EP2, and other adjacent light emitting units. The second pixel driver PDC2 may be disposed at a position where it overlaps with the first light emitter EP1, the second light emitter EP2, and the third cathode EL23. The third pixel driver PDC3 may be disposed at a position where it overlaps with the third light emitter EP3. However, this is merely an example, and the positions and arrangements of the first to third pixel drivers PDC1, PDC2, and PDC3 may be designed in various shapes and arrangements independent of the first to third light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0137] The light emitting unit UT11 may include first to third connecting electrodes CNE1, CNE2, and CNE3. The first connecting electrode CNE1 may electrically connect the first light emitting element LD1 forming the first light emitting portion EP1 (or the first light emitting portion EP1 is defined) to the first pixel driving part PDC1, the second connecting electrode CNE2 may electrically connect the second light emitting element LD2 forming the second light emitting portion EP2 to the second pixel driving part PDC2, and the third connecting electrode CNE3 may electrically connect the third light emitting element LD3 forming the third light emitting part EP3 to the third pixel driving part PDC3.

[0138] In detail, the first to third connecting electrodes CNE1, CNE2, and CNE3 may electrically connect the first to third cathodes EL21, EL22, and EL23 to the first to third pixel driving parts PDC1, PDC2, and PDC3 in one-to-one correspondence, respectively.

[0139] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel definition layer PDL (see FIG. 5 ), which will be described later. The first to third connecting electrodes CNE1, CNE2, and CNE3 may have a ring shape surrounding the corresponding first to third light emitting portions EP1, EP2, and EP3. In this embodiment, the first to third connecting electrodes CNE1, CNE2, and CNE3 each have a closed line ring shape, but this is not limiting. For example, at least some of the first to third connecting electrodes CNE1, CNE2, and CNE3 may have a ring shape with a broken portion.

[0140] The annular shape of the first to third linking electrodes CNE1, CNE2, and CNE3 may improve the degree of freedom in the positions at which the first to third linking electrodes CNE1, CNE2, and CNE3 are connected to the first to third pixel driving units PDC1, PDC2, and PDC3. That is, by arranging the first to third connection units CE1, CE2, and CE3 corresponding to any positions of the annular first to third linking electrodes CNE1, CNE2, and CNE3, respectively, the first to third linking electrodes CNE1, CNE2, and CNE3 can be connected to the first to third pixel driving units PDC1, PDC2, and PDC3 via the first to third connection units CE1, CE2, and CE3. For example, the first connecting electrode CNE1 may be connected to the first pixel driver PDC1 via the first connector CE1, the second connecting electrode CNE2 may be connected to the second pixel driver PDC2 via the second connector CE2, and the third connecting electrode CNE3 may be connected to the third pixel driver PDC3 via a connecting wire CN3 (including the third connector CE3 and the driving connector CD3). That is, additional connecting wires connected to the first and second connecting electrodes CNE1 and CNE2 may be omitted.

[0141] One connecting wire CN3 may electrically connect the third pixel driver PDC3 and the third light emitting element LD3 constituting the third light emitting unit EP3. Specifically, the connecting wire CN3 may correspond to a node (see the fourth node N4 in FIG. 2a, the second node N2 in FIG. 2b, or the fourth node N4 in FIG. 2c) at which the light emitting element LD (see FIG. 2a) is connected to the pixel driver (PDC in FIG. 2a, PDC-1 in FIG. 2b, or PDC-2 in FIG. 2c).

[0142] The connecting wire CN3 may include a third connecting part CE3 and a driving connecting part CD3, where the third connecting part CE3 may be provided on one side of the connecting wire CN3 and the driving connecting part CD3 may be provided on the other side of the connecting wire CN3.

[0143] The driving connection part CD3 may be a part of the connecting wire CN3 that is connected to the pixel driving part PDC3. In this embodiment, the driving connection part CD3 may be connected to one electrode of a transistor constituting the pixel driving part PDC3. Specifically, the driving connection part CD3 may be connected to the drain of the sixth transistor T6 shown in FIG. 2a, the drain of the first transistor T1 shown in FIG. 2b, or the drain of the fourth transistor T4a shown in FIG. 2c. Thus, the position of the driving connection part CD3 may correspond to the position of a transistor physically connected to the connecting wire CN3 in the pixel driving part. The third connection part CE3 may be a part of the connecting wire CN3 that is connected to the third light emitting element LD3. In this embodiment, the third connection part CE3 may be connected to the third connecting electrode CNE3.

[0144] The first linking electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light-emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second linking electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light-emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third linking electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light-emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0145] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be spaced apart from one another. For example, gaps GP1, GP2, and GP3 between adjacent connecting electrodes among the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with separators SPR. For example, first edges EG11, EG21, and EG31 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may not be covered by separators SPR, and second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with separators SPR. Alternatively, second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be covered by separators SPR. It can be said that the gaps GP are formed, for example, between adjacent connecting electrodes CNE. 4c, the gap GP can be said to be formed between the outer edge of one of adjacent connecting electrodes CNE and the outer edge of the other connecting electrode CNE. For example, the gap GP can be said to be formed between the second edge EG12 of the first connecting electrode CNE1 and the second edge EG22 of the second connecting electrode CNE2. The gap GP can also be said to be formed between the second edge EG22 of the second connecting electrode CNE2 and the second edge EG32 of the third connecting electrode CNE3. The gap GP can also be said to be formed between the second edge EG12 of the first connecting electrode CNE1 and the second edge EG12 of the third connecting electrode CNE3.

[0146] In one embodiment of the present invention, the first to third connection parts CE1, CE2, and CE3 may be arranged at positions that do not overlap the first to third light emitting parts EP1, EP2, and EP3 in a plan view. For example, a light emitting opening OP-PDL (see FIG. 5) and a through hole OP-P (see FIG. 5) spaced apart from the light emitting opening OP-PDL may be defined in the pixel defining layer PDL.

[0147] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third connection portions CE1, CE2, and CE3 may be arranged corresponding to the first to third through holes OP-P1, OP-P2, and OP-P3, respectively. The light-emitting opening OP-PDL may include a first light-emitting opening OP-PDL1, a second light-emitting opening OP-PDL2, and a third light-emitting opening OP-PDL3. The first to third light-emitting portions EP1, EP2, and EP3 may be defined corresponding to the first to third through holes OP-P1, OP-P2, and OP-P3, respectively. Therefore, the first to third connection portions CE1, CE2, and CE3 may be arranged at positions spaced apart from the first to third through holes OP-P1, OP-P2, and OP-P3.

[0148] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on the pixel defining layer PDL (see FIG. 5). When viewed from above, the first connecting electrode CNE1 may surround the first light-emitting opening OP-PDL1, the second connecting electrode CNE2 may surround the second light-emitting opening OP-PDL2, and the third connecting electrode CNE3 may surround the third light-emitting opening OP-PDL3.

[0149] According to one embodiment of the present invention, the driving connection part CD3, which is the position where the connecting line CN3 is connected to the transistor TR (see FIG. 5) of the third pixel driving part PDC3, may be defined at a position that does not overlap with the third connection part CE3 on a plane, and may be arranged at a position that overlaps with the third light emitting part EP3.

[0150] The first to third cathodes EL21, EL22, and EL23 may be connected to the first to third connecting electrodes CE1, CE2, and CE3. For example, the bottom surfaces of the first to third cathodes EL21, EL22, and EL23 may be connected to (or in contact with) the top surfaces of the first to third connecting parts CE1, CE2, and CE3, respectively. This may further improve the contact reliability (or connection stability) between the first to third cathodes EL21, EL22, and EL23 and the first to third connecting parts CE1, CE2, and CE3.

[0151] Furthermore, connection regions where the first to third cathodes EL21, EL22, and EL23 are connected to the first to third connecting portions CE1, CE2, and CE3 may surround at least a portion of the first to third light-emitting openings OP-PDL1, OP-PDL2, and OP-PDL3, respectively. The first to third cathodes EL21, EL22, and EL23 may be connected to the first to third connecting portions CE1, CE2, and CE3 in regions adjacent to the separator SPR, and each of the contact regions may be defined adjacent to the separator SPR. That is, the first to third cathodes EL21, EL22, and EL23 may be connected to the first to third connecting portions CE1, CE2, and CE3 not at specific points but over a relatively wide region, for example, a region similar in shape to the first to third connecting portions CE1, CE2, and CE3, respectively. That is, the area of ​​the connection contact is increased, and the connection may be maintained stably.

[0152] FIG. 4d shows the separator SPR, the light-emitting portions EP1, EP2, and EP3, and the lower electrode EL1.

[0153] 4d, the lower electrode EL1 (hereinafter referred to as the anode) of the light emitting element LD1 (see FIG. 5) according to an embodiment of the present invention may be provided in common to the first to third light emitting portions EP1, EP2, and EP3. That is, the anode EL1 may be formed as a single layer across the entire display area DA, whereby the anode EL1 layer may be disposed overlapping the separator SPR. Alternatively, the anode EL1 of each light emitting element LD1 may be formed as independent conductive patterns spaced apart from each other and electrically connected to each other via another conductive layer, whereby the anode EL1 pattern may be disposed without overlapping the separator SPR.

[0154] As described above, the first power supply voltage VDD (see FIG. 2a) is applied to the anode EL1, and a common voltage may be provided to all the light emitting units. The anode EL1 may be connected to the first power supply line VDL (see FIG. 2a) that provides the first power supply voltage VDD in the peripheral area NDA, or may be connected to the first power supply line VDL (see FIG. 2a) in the display area DA, and is not limited to any one embodiment.

[0155] Meanwhile, a plurality of openings may be defined in the anode EL1 according to the present invention, and the openings may penetrate the anode EL1 layer. The openings in the anode EL1 layer may be positioned so as not to overlap the light-emitting portion EP (see FIG. 3a) and may be defined so as to overlap the separator SPR. The openings may facilitate the discharge of gas generated from organic layers disposed below the anode EL1, such as the sixth insulating layer 60 (see FIG. 5) described below. This may allow sufficient discharge of gas from organic layers disposed below the light-emitting element during the manufacturing process of the display panel, thereby reducing the amount of gas discharged from the organic layers after manufacturing and slowing the rate at which the light-emitting element deteriorates.

[0156] 5 is a cross-sectional view of a display panel DP according to an embodiment of the present invention, taken along line II' of FIG.

[0157] 5 exemplarily illustrates the components, arrangements, and connections of components arranged in a cross section of a region where the first light-emitting element LD1 included in the first light-emitting unit EP1 in FIG. 4a is arranged, but similar descriptions may be applied to the cross sections of a region where the second light-emitting element LD2 included in the second light-emitting unit EP2 is arranged and the cross sections of a region where the third light-emitting element LD3 included in the third light-emitting unit EP3 is arranged. Also, for convenience of explanation, the first light-emitting element LD1 and the components included therein shown in FIG. 5 are described as the components of the "light-emitting element LD1," and similar descriptions may be applied to the second light-emitting element LD3 and the third light-emitting element LD3 and the components included therein.

[0158] 5, the display panel DP in one embodiment may include a base layer BS, a driving element layer DDL, a light-emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL. However, this is just an example, and in one embodiment, the display panel DP may not include the sensing layer ISL.

[0159] The driving element layer DDL may include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, and 60 to constitute a pixel driving unit PDC.

[0160] The base layer BS is a member that provides a base surface on which the pixel driving units PDC are disposed. The base layer BS may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The base layer BS may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0161] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0162] The polymer resin layer may include a polyimide-based resin. The polymer resin layer may also include at least one of an acrylic resin, a methacrylic resin, a polyisoprene-based resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In this specification, a "XX-based" resin refers to a resin containing a functional group of "XX."

[0163] The insulating layer, conductive layer, and semiconductor layer disposed on the base layer BS may be formed by coating, deposition, etc. Then, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned through multiple lithography processes to form holes in the insulating layer, or semiconductor patterns, conductive patterns, signal lines, etc.

[0164] The driving element layer DDL may include first to sixth insulating layers 10, 20, 30, 40, 50, and 60 sequentially stacked on the base layer BS, and a pixel driving unit PDC. Figure 5 shows one transistor TR and first and second capacitors C1 and C2 of the pixel driving unit PDC.

[0165] The transistor TR corresponds to a transistor connected to the light emitting element LD1 via the intermediate connecting electrode CN and the connecting electrode CNE1, i.e., a connecting transistor connected to a node corresponding to the cathode of the light emitting element LD1 (the fourth node N4 in FIG. 2a, the second node N2 in FIG. 2b, or the fourth node N4 in FIG. 2c), and more specifically, may correspond to the sixth transistor T6 in FIG. 2a, the first transistor T1 in FIG. 2b, or the fourth transistor T4a in FIG. 2c. Meanwhile, although not shown, other transistors constituting the pixel driving unit PDC may have the same structure as the transistor TR (hereinafter, referred to as the connecting transistor) shown in FIG. 5. However, this is merely an illustrative example, and the other transistors constituting the pixel driving unit PDC may have a different structure from the connecting transistor TR, and the present invention is not limited to any one embodiment.

[0166] A first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 is illustrated as a single-layer silicon oxide layer. Meanwhile, insulating layers described below may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited to this.

[0167] Meanwhile, the first insulating layer 10 may cover the lower conductive layer BCL. That is, the display panel DP may further include a lower conductive layer BCL disposed overlapping the connection transistor TR. The lower conductive layer BCL may block the electrical potential caused by polarization of the base layer BS from affecting the connection transistor TR. The lower conductive layer BCL may also block light incident on the connection transistor TR from below. At least one of an inorganic barrier layer and a buffer layer may further be disposed between the lower conductive layer BCL and the base layer BS.

[0168] The lower conductive layer BCL may include a reflective metal, such as titanium (Ti), molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0169] In this embodiment, the lower conductive layer BCL may be connected to the source of the connection transistor TR (or transistor) via the source electrode W1. In this case, the lower conductive layer BCL may be synchronized with the source of the transistor TR. However, this is an exemplary illustration, and the lower conductive layer BCL may be connected to the gate of the transistor TR and synchronized with the gate. Alternatively, the lower conductive layer BCL may be connected to another electrode and independently applied with a static voltage or pulse signal. Alternatively, the lower conductive layer BCL may be provided in a form isolated from other conductive patterns. The lower conductive layer BCL according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0170] A transistor TR may be disposed on the first insulating layer 10. The connecting transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, without being limited thereto, the semiconductor pattern SP may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0171] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR, which are differentiated by their respective degrees of conductivity. The channel region CR may overlap with the gate electrode GE in a plan view. The source region SR and the drain region DR may be separated from each other with the channel region CR interposed therebetween. If the semiconductor pattern SP is an oxide semiconductor, the source region SR and the drain region DR may each be a reduced region. As a result, the source region SR and the drain region DR have a relatively higher reduced metal content than the channel region CR. Alternatively, if the semiconductor pattern SP is polycrystalline silicon, the source region SR and the drain region DR may each be a highly doped region.

[0172] The source region SR and the drain region DR have relatively high conductivity compared to the channel region CR. The source region SR may correspond to the source electrode of the connection transistor TR, and the drain region DR may correspond to the drain electrode of the connection transistor TR. As shown in FIG. 5, a separate source electrode pattern W1 and a drain electrode pattern W2 may be further provided, connected to the source region SR and the drain region DR, respectively. In particular, each of the separate source electrode pattern W1 and the drain electrode pattern W2 may be integrally formed with one of the lines constituting the pixel driving unit (see PDC in FIG. 2a, PDC-1 in FIG. 2b, or PDC-2 in FIG. 2c), and is not limited to any one embodiment.

[0173] The second insulating layer 20 may overlap multiple pixels in common and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 is a single silicon oxide layer.

[0174] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR. The gate electrode GE may also be disposed above the semiconductor pattern SP. However, this is merely an example, and the gate electrode GE may also be disposed below the semiconductor pattern SP, and is not limited to any one embodiment.

[0175] The gate electrode GE may include, but is not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or alloys thereof.

[0176] A third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0177] Among the plurality of conductive patterns W1, W2, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart with a first insulating layer 10 and a second insulating layer 20 interposed therebetween.

[0178] In one embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BCL may have an integral shape, and the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0179] A third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may overlap the second capacitor electrode CPE2 on a plane while being spaced apart from the second capacitor electrode CPE2 with the third insulating layer 30 interposed therebetween. The third capacitor electrode CPE3 may constitute a second capacitor C2 together with the second capacitor electrode CPE2.

[0180] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0181] A source electrode pattern W1 and a drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to a source region SR of the connection transistor TR through a first contact hole CNT1, and the source region SR of the source electrode pattern W1 and the semiconductor pattern SP may function as the source of the connection transistor TR. The drain electrode pattern W2 may be connected to a drain region DR of the connection transistor TR through a second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may function as the drain of the connection transistor TR. A fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0182] An intermediate connecting electrode CN may be disposed on the fifth insulating layer 50. The intermediate connecting electrode CN may electrically connect the pixel driver PDC and the light emitting element LD1. That is, the intermediate connecting electrode CN may electrically connect the connection transistor TR and the light emitting element. The intermediate connecting electrode CN may be a connection node connecting the pixel driver PDC and the first light emitting element LD1. That is, the intermediate connecting electrode CN may correspond to the fourth node N4 (see FIG. 2a) shown in FIG. 2a, the second node N2 (see FIG. 2b) shown in FIG. 2b, or the fourth node N4 (see FIG. 2c) shown in FIG. 2c.

[0183] A sixth insulating layer 60 may be disposed on the intermediate connecting electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and cover at least a portion of the intermediate connecting electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a common general-purpose polymer such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), PMMA (polymethyl methacrylate), or PS (polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0184] The sixth insulating layer 60 may have a through hole OP-60 exposing at least a portion of the intermediate connecting electrode CN. The intermediate connecting electrode CN may be connected to the connecting electrode CNE1 through a portion exposed from the sixth insulating layer 60, and thus may be electrically connected to the light emitting element LD1. That is, the intermediate connecting electrode CN, together with the connecting electrode CNE1, may electrically connect the connecting transistor TR and the light emitting element LD1. In this specification, a region where the intermediate connecting electrode CN and the connecting electrode CNE1 are connected may be referred to as a connection region CNA. The connection region CNA may be defined by the through hole OP-60. Meanwhile, in the display panel DP according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted or may be provided in plural, and is not limited to any one embodiment. If the sixth insulating layer 60 is omitted, the intermediate connecting electrode CN may also be omitted.

[0185] The intermediate connecting electrode CN may include a first layer L1, a second layer L2, and a third layer L3 stacked in sequence along the third direction DR3. The second layer L2 may include a different material from the first layer L1. Also, the second layer L2 may include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. Also, the second layer L2 may have a relatively thicker thickness than the third layer L3. The second layer L2 may include a highly conductive material. In one embodiment, the second layer L2 may include aluminum (Al).

[0186] The light emitting element layer LDL may be disposed on the driving element layer DDL. The light emitting element layer LDL may include a pixel defining film PDL, a light emitting element LD1, and a separator SPR.

[0187] The pixel-defined membrane PDL can be an organic layer, and can include, for example, common general-purpose polymers such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), PMMA (polymethyl methacrylate), and PS (polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0188] In one embodiment, the pixel definition layer PDL has a light-absorbing property and may have, for example, a blocking color. That is, the pixel definition layer PDL may include a black component (black coloring agent). The black component may include a black dye or a black pigment. The black component may include carbon black, a metal such as chromium, or an oxide thereof. The pixel definition layer PDL may correspond to a light-blocking pattern having a light-blocking property.

[0189] An opening OP-PDL (hereinafter referred to as a light-emitting opening) exposing at least a portion of a lower electrode EL11 (described later) may be defined in the pixel defining layer PDL. A plurality of light-emitting openings OP-PDL may be provided and arranged corresponding to each light-emitting element. All components of the light-emitting element LD1 may be arranged to overlap in the light-emitting opening OP-PDL, and the light-emitting opening OP-PDL may be an area in which holes emitted by the light-emitting element LD1 are substantially displayed. As a result, the shape of the light-emitting portion EP1 (see FIG. 4a) may substantially correspond to the shape of the light-emitting opening OP-PDL on a plane. Meanwhile, the area corresponding to the light-emitting portion EP1, i.e., the area defined by the light-emitting opening OP-PDL, may be referred to as a light-emitting area EA1.

[0190] A connecting electrode CNE1 may be disposed on the pixel defining layer PDL. The connecting electrode CNE1 may electrically connect the pixel driver PDC and the light emitting element LD1. That is, the pixel driver PDC may be electrically connected to the light emitting element LD1 via the intermediate connecting electrode CN and the connecting electrode CNE1. The connecting electrode CNE1 may correspond to the first connecting electrode CNE1 shown in FIG. 4a. The second connecting electrode CNE2 (see FIG. 4a) and the third connecting electrode CNE3 (see FIG. 4a) may also have a structure similar to that of the first connecting electrode CNE1.

[0191] The connecting electrode CNE1 may include a first edge EG1c adjacent to the light-emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The upper electrode EL21 of the light-emitting element LD1 may contact the connecting electrode CNE1 in a region adjacent to the second edge EG2c. In the case of FIG. 4c, the first edge EG1c corresponds to the first edges EG11, EG21, and EG31, and the second edge EG2c corresponds to the second edges EG12, EG22, and EG32.

[0192] The connecting electrode CNE1 may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the material constituting the connecting electrode CNE1 is not limited to the above examples. For example, the connecting electrode CNE1 may include a metal material.

[0193] A through hole OP-P spaced apart from the light emitting opening OP-PDL may be defined in the pixel defining layer PDL. A plurality of through holes OP-P may be provided and disposed corresponding to each light emitting element. The size of the through hole OP-P defined in the pixel defining layer PDL may be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connecting electrode CNE1 may be disposed in the through hole OP-P and the through hole OP-60 and connected to the intermediate connecting electrode CN.

[0194] The light-emitting element LD1 can include a lower electrode EL11, an intermediate layer IML1, and an upper electrode layer EL21.

[0195] The lower electrode EL11 may be a semi-transmissive, transmissive, or reflective electrode. According to one embodiment of the present invention, the lower electrode EL11 may include a reflective layer made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the lower electrode EL11 may include an ITO / Ag / ITO stacked structure.

[0196] In this embodiment, the lower electrode EL11 may be the anode of the light emitting element LD1. That is, the lower electrode EL11 may be connected to the first power supply line VDL (see FIG. 2a) and may receive the first power supply voltage VDD (see FIG. 2a). The lower electrode EL11 may be connected to the first power supply line VDL in the display area DA (see FIG. 2a or FIG. 3b) or may be connected to the first power supply line VDL in the peripheral area NDA. In the latter case, the first power supply line VDL may be disposed in the peripheral area NDA (see FIG. 3a or FIG. 3b), and the lower electrode EL11 may extend to the peripheral area NDA.

[0197] 5, the bottom electrode EL11 overlaps the light emitting opening OP-PDL but does not overlap the separator SPP1, but as described above in FIG. 4d, the bottom electrode EL11 of the light emitting element may have a single shape with a mesh or lattice shape in which openings are defined in some areas. In other words, as long as the same first power supply voltage VDD can be applied to the bottom electrode EL11 of each of the light emitting elements, the shape of the bottom electrode EL11 may be various and is not limited to any one embodiment.

[0198] The intermediate layer IML1 may be disposed between the lower electrode EL11 and the upper electrode layer EL21. The intermediate layer IML1 may include an emitting layer EML1 and a functional layer FNL1. The light emitting device LD1 may include the intermediate layer IML1 with various structures and is not limited to any one embodiment. For example, the functional layer FNL1 may be provided as a plurality of layers, or as two or more layers spaced apart with the emitting layer EML1 sandwiched therebetween.

[0199] The functional layer FNL1 may be disposed between the bottom electrode EL11 and the top electrode layer EL21. In this embodiment, the emitting layer EML1 is shown to be inserted within the functional layer FNL1. In other words, it can be understood that the emitting layer EML1 is disposed between the first intermediate functional layer FNL11 (see FIG. 6) and the second intermediate functional layer FNL12 (see FIG. 6), which will be described later.

[0200] The functional layer FNL1 can control charge transfer between the bottom electrode EL11 and the top electrode layer EL21. For example, the functional layer FNL1 can include a hole injection / transport material and / or an electron injection / transport material. The functional layer FNL1 can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0201] The emitting layer EML1 may include an organic emitting material. Alternatively, the emitting layer EML1 may include an inorganic emitting material or may be a mixed layer of an organic emitting material and an inorganic emitting material. In this embodiment, the emitting layers EML1 included in adjacent emitting units EP (see FIG. 3a) may include emitting materials that display different colors. For example, the emitting layer EML1 included in each emitting unit EP may provide any one of blue, red, and green light. However, the emitting layers EML1 disposed in all emitting units EP may include emitting materials that display the same color. In this case, the emitting layer EML1 may provide blue light or white light.

[0202] The upper electrode EL21 may be disposed on the intermediate layer IML1. As described above, the upper electrode EL21 may be connected to the connecting electrode CNE1 and electrically connected to the pixel driver PDC. That is, the upper electrode EL21 may be electrically connected to the connecting transistor TR via the connecting electrode CNE1.

[0203] The separator SPR1 may be disposed on the pixel defining layer PDL, on the connecting electrode CNE1 disposed on the pixel defining layer PDL, and on the gaps GP1 to GP3 (see FIG. 4c) between the connecting electrode CNE1 and the adjacent connecting electrode.

[0204] The top electrode EL21 and the functional layer FNL1 may be formed by common deposition on a plurality of pixels using an open mask. In this case, the top electrode EL21 and the functional layer FNL1 may be divided by the separator SPR1. As described above, the separator SPR1 may have a closed line shape surrounding each light-emitting portion, corresponding to each light-emitting portion, thereby allowing the top electrode EL21 and the functional layer FNL1 to have a divided shape for each light-emitting portion. In other words, the top electrode EL21 and the intermediate layer IML may be electrically independent for each adjacent pixel.

[0205] In one embodiment, the separator SPR1 may have an inverse tapered shape. That is, the separator SPR1 may have a shape in which its width increases as it moves away from the top surface of the pixel definition film PDL. The side surfaces SS1 and SS2 (see FIG. 6 ) of the separator SPR1 may have an obtuse taper angle inclined from the top surface of the pixel definition film PDL. However, this is merely an illustrative example. The taper angle of the separator SPR1 may be set in various ways as long as the separator SPR1 can electrically disconnect the upper electrode EL21 for each pixel. For example, the separator SPR1 may have a dual structure with different taper angles. Furthermore, the separator SPR1 may have a chip-like structure and is not limited to any one embodiment. For example, the chip-like structure may be such that the separator SPR1 has chip portions facing each other and spaced apart. Because the chip portions are spaced apart from each other, the upper electrode EL21 may be physically and electrically disconnected at the spaced apart portions. Also, for example, in the example shown in FIG. 5, the separator SPR1 may have a double reverse tapered shape.

[0206] The separator SPR1 may include an insulating material, particularly an organic insulating material. The separator SPR1 may include an inorganic insulating material, may be composed of multiple layers of organic and inorganic insulating materials, or may include a conductive material depending on the embodiment. In other words, the separator SPR1 is not particularly limited to a specific material as long as it can electrically disconnect the upper electrode EL21 for each pixel.

[0207] A dummy layer UP may be disposed on top of the separator SPR1. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR1 and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML1 and may contain the same material as the intermediate layer UP1. The second dummy layer UP2 may be formed in the same process as the upper electrode EL21 and may contain the same material as the intermediate layer UP1. In other words, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the functional layer FNL1 and the upper electrode EL21.

[0208] The upper electrode EL21 is in contact with the connecting electrode CNE1 through a contact region CA1. The contact region CA1 is provided adjacent to the separator SPR1. In the contact region CA1, the upper surface of the connecting electrode CNE1 may be in contact with the lower surface of the upper electrode EL21. Meanwhile, because the separator SPR1 has an inverse tapered shape and the contact region CA1 is provided adjacent to the separator SPR1, at least a portion of the contact region CA1, where the upper electrode EL21 and the connecting electrode CNE1 are in contact, may be disposed below the side surface of the separator SPR1 (first side surface SS1 in the examples of FIGS. 6 and 7a).

[0209] The display panel DP according to one embodiment may include a light-emitting region EA1 in which the light-emitting element LD1 is disposed, and an intermediate region MA1 disposed between the light-emitting region EA1 and the contact region CA1. The intermediate region MA1 may be adjacent to the contact region CA1. The intermediate region MA1 may be a region in which at least a portion of the intermediate layer IML1 is disposed. In the intermediate region MA1, the functional layer FNL1 included in the intermediate layer IML1 may be disposed between the connecting electrode CNE1 and the upper electrode EL21. That is, in the intermediate region MA1, the connecting electrode CNE1 and the upper electrode EL21 may be spaced apart with the functional layer FNL1 sandwiched therebetween.

[0210] In one embodiment of the display panel DP, the functional layer FNL1 and the top electrode EL21 may be formed by a different deposition process. The top electrode EL21 may be formed by a deposition process that allows deposition materials to be deposited at a lower angle of incidence than the deposition process used to form the functional layer FNL1. For example, the functional layer FNL1 may be formed by thermal evaporation, and the top electrode EL21 may be covered by sputtering. As a result, during the process of forming the functional layer FNL1, the material forming the functional layer FNL1 may not penetrate below the side surface of the separator SPR1 (first side surface SS1 in the examples of FIGS. 6 and 7a), exposing a portion of the connecting electrode CNE1. The top electrode EL21 is formed closer to the separator SPR1 than the functional layer FNL1, and the top electrode EL21 may contact the exposed top surface of the connecting electrode CNE1. That is, in the process of forming the functional layer FNL1 and the upper electrode EL21, the contact area CA1 where the upper electrode EL21 and the connecting electrode CNE1 contact each other may be formed depending on the deposition process method.

[0211] 5, a connection region CNA in which the connecting electrode CNE1 is connected to the intermediate connecting electrode CN may be disposed between the light-emitting region EA1 and the contact region CA1. The connection region CNA may overlap the intermediate region MA1. At least a portion of the intermediate layer IML1 may be disposed so as to overlap the connection region CNA. In one embodiment of the display panel DP, the functional layer FNL1 included in the intermediate layer IML may be disposed so as to overlap the connection region CNA.

[0212] According to an embodiment of the present invention, the connecting electrode CNE1 has a shape that surrounds at least a portion of the light-emitting area EA1 in which the light-emitting element LD1 is disposed. Therefore, the degree of freedom in the position at which the connecting electrode CNE1 and the light-emitting element LD1 are connected and the degree of freedom in the position at which the connecting electrode CNE1 and the pixel driving circuit PDC are connected can be improved. Furthermore, the upper surface of the connecting electrode CNE1 can be in contact with the lower surface of the upper electrode EL21 of the light-emitting element LD1 through the contact area CA1 defined adjacent to the separator SPR1. This improves the reliability of the contact between the connecting electrode CNE1 and the upper electrode EL21, and the lower surface of the connecting electrode CNE1 is in contact with the upper surface of the intermediate connecting electrode CN, thereby improving the reliability of the contact. In the display panel DP according to an embodiment, the size of the through holes OP-P and OP-60 for connecting the connecting electrode CNE1 and the intermediate connecting electrode CN can be reduced or minimized through the above-described structure, thereby easily increasing the area or resolution of the light-emitting portion of the display panel DP.

[0213] In one embodiment of the display panel DP, an encapsulation layer ECL may be disposed on the light-emitting element layer LDL. The encapsulation layer ECL may cover the light-emitting element LD1 and the separator SPR1. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked in sequence. However, the encapsulation layer ECL is not limited thereto, and may further include multiple inorganic layers and organic layers. The encapsulation layer ECL may also be a glass substrate.

[0214] The first and second inorganic layers IL1 and IL2 protect the light emitting device LD1 from water and oxygen outside the display panel DP, and the organic layer OL protects the light emitting device LD1 from foreign matter such as particles remaining during the formation of the first inorganic layer IL1. The first and second inorganic layers IL1 and IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer OL may include an acrylic organic layer, but the type of material is not limited to one.

[0215] The sensing layer ISL may sense an external input. In this embodiment, the sensing layer ISL may be formed on the encapsulation layer ECL through a continuous process. In this case, the sensing layer ISL may be expressed as being directly disposed on the encapsulation layer ECL. "Directly disposed" may mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. In other words, no separate adhesive member may be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is merely an example, and in a display panel DP according to an embodiment of the present invention, the sensing layer ISL may be formed separately and then coupled to the display panel DP via an adhesive member, and is not limited to any one embodiment.

[0216] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include first to third sensing insulating layers 71, 72, and 73. However, this is merely an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0217] Each of the first to third sensing insulation layers 71, 72, and 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The first to third sensing insulation layers 71, 72, and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulation layers 71, 72, and 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0218] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing insulating layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0219] The single-layer sensing conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (ITO). Alternatively, the conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, or the like.

[0220] The multi-layered sensing conductive layer may include a metal layer, such as a titanium (Ti) / aluminum (Al) / titanium (Ti) three-layer structure, or the multi-layered conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0221] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor that senses an external input at the sensing electrode ISL. The sensor may be driven by a capacitance method, such as a mutual capacitance method or a self-capacitance method. However, this is an exemplary explanation, and the sensor may be driven by a resistive method, an ultrasonic method, or an infrared method other than the capacitance method, and is not limited to any one embodiment.

[0222] The first and second sensing conductive layers MTL1 and MTL2 may each include a transparent conductive oxide or may have a metal mesh shape made of an opaque conductive material. The first and second sensing conductive layers MTL1 and MTL2 may have various materials and shapes as long as the visibility of the image displayed by the display panel DP is not reduced, and are not limited to any one embodiment.

[0223] FIG. 6 is a cross-sectional view of a display panel DP according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing a portion corresponding to line II-II' in FIG. 4a. FIGS. 7a and 7b are enlarged cross-sectional views showing a portion of a display panel according to an embodiment of the present invention. FIG. 7a shows a cross-section of region AA' in FIG. 6, and FIG. 7b shows a cross-section of region BB' in FIG. 6. FIGS. 7a and 7b show the shapes of portions corresponding to the first separator SPR1 and second separator SPR2 shown in FIG. 6 and the adjacent contact regions CA1 and CA2.

[0224] Figure 6 shows the arrangement structure of two adjacent light-emitting elements LD1 and LD2 and a separator SPR arranged between them, and for convenience of connection, the base layer BS, part of the driving element layer DDL, the sealing layer ECL, and the sensing layer ISL already explained in Figure 5 are not shown.

[0225] Referring to both Figures 5 and 6, a display panel DP according to one embodiment includes a first light-emitting element LD1 and a second light-emitting element LD2 arranged adjacent to each other, and the upper electrodes EL1 and EL2 of the adjacent first light-emitting element LD1 and second light-emitting element LD2 can be separated from each other by a separator SPR and electrically disconnected.

[0226] The separator SPR includes a first separator SPR1 adjacent to the first light-emitting element LD1 and a second separator SPR2 adjacent to the second light-emitting element LD2. The first separator SPR1 and the second separator SPR2 are spaced apart in one direction. In cross section, the first separator SPR1 and the second separator SPR2 are disposed between the first light-emitting element LD1 and the second light-emitting element LD2. The direction in which the first separator SPR1 and the second separator SPR2 are spaced apart is aligned with the direction in which the first light-emitting element LD and the second light-emitting element LD2 are spaced apart. The second separator SPR2 is disposed between the first separator SPR1 and the second light-emitting element LD2, and the first separator SPR1 may be disposed between the second separator SPR2 and the first light-emitting element LD1.

[0227] The connecting electrodes CNE1 and CNE2 connecting the light emitting elements LD1 and LD2 to the pixel driving unit PDC are not disposed in the spacing portion SPP. The connecting electrodes CNE1 and CNE2 may be disposed on a portion of the upper surface of each of the separators SPR1 and SPR2, but do not overlap the spacing portion SPP or a portion of the upper surface of each of the separators SPR1 and SPR2 adjacent to the spacing portion SPP.

[0228] Each of the separators SPR1 and SPR2 may include an outer surface adjacent to the light emitting elements LD1 and LD2 and an inner surface adjacent to the separation portion SPP. The first separator SPR1 may include a first side surface SS1 adjacent to the first light emitting element LD1 and a second side surface SS2 adjacent to the separation portion SPP. The second separator SPR2 may include a third side surface SS3 adjacent to the second light emitting element LD2 and a fourth side surface SS4 adjacent to the separation portion SPP. The second side surface SS2 and the fourth side surface SS4 may face each other with the separation portion SPP therebetween.

[0229] The connecting electrodes CNE1 and CNE2 are disposed on the outer surfaces of the separators SPR1 and SPR2, but not on the inner surfaces of the separators SPR1 and SPR2. In one embodiment, the first connecting electrode CNE1 may be disposed on the first side surface SS1 of the first separator SPR1, but not on the second side surface SS2. The second connecting electrode CNE2 may be disposed on the third side surface SS3 of the second separator SPR2, but not on the fourth side surface SS4.

[0230] In one direction, the separation distance S1 between the separators SPR1 and SPR2 is smaller than the separation distance S2 between the connecting electrodes CNE1 and CNE2 in the same direction. That is, the separation distance S2 between the tip of the first connecting electrode CNE1 and the second connecting electrode CNE2 may be larger than the separation distance S1 between the first separator SPR1 and the second separator SPR2. The separation distance S1 between the first separator SPR1 and the second separator SPR2 may correspond to the width of the separation portion SPP.

[0231] The first light emitting element LD1 may include a first bottom electrode EL11, a first intermediate layer IML1, and a first top electrode EL21. The second light emitting element LD2 may include a second bottom electrode EL12, a second intermediate layer IML2, and a second top electrode EL22.

[0232] The first and second lower electrodes EL11 and EL22 may each be semi-transmissive, transmissive, or reflective. Each of the first and second lower electrodes EL11 and EL22 may include a reflective layer made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, each of the first and second lower electrodes EL11 and EL22 may include an ITO / Ag / ITO stacked structure.

[0233] In this embodiment, the first bottom electrode EL11 may be the anode of the first light emitting element LD1, and the second bottom electrode EL12 may be the anode of the second light emitting element LD2. A first power supply voltage VDD (see FIG. 2a) may be applied to each of the first bottom electrode EL11 and the second bottom electrode EL12.

[0234] The first intermediate layer IML1 may be disposed between the first bottom electrode EL11 and the first top electrode EL21. The first intermediate layer IML1 may include a first light emitting layer EML1 and a first functional layer FNL1. The second intermediate layer IML2 may be disposed between the second bottom electrode EL12 and the second top electrode EL22. The second intermediate layer IML2 may include a second light emitting layer EML2 and a second functional layer FNL2. The first light emitting element LD1 and the second light emitting element LD2 may include intermediate layers IML1 and IML2 of various structures and are not limited to any one embodiment.

[0235] The first functional layer FNL1 may be disposed between the first bottom electrode EL11 and the first top electrode EL21. The first functional layer FNL1 may include a first intermediate functional layer FNL11 disposed between the first electrode EL11 and the first light-emitting layer EML1 and a second intermediate functional layer FNL12 disposed between the first top electrode EL21 and the first light-emitting layer EML1. The second functional layer FNL2 may be disposed between the second bottom electrode EL12 and the second top electrode EL22. The second functional layer FNL2 may include a third intermediate functional layer FNL21 disposed between the second electrode EL12 and the second light-emitting layer EML2 and a fourth intermediate functional layer FNL22 disposed between the second top electrode EL22 and the second light-emitting layer EML2.

[0236] The first functional layer FNL1 and the second functional layer FNL2 can control the movement of charges between the bottom electrodes EL11, EL12 and the top electrodes EL21, EL22. For example, the first intermediate functional layer FNL11 and the third intermediate functional layer FNL21 can contain a hole injection / transport material. The first intermediate functional layer FNL11 and the third intermediate functional layer FNL21 can include at least one of an electron blocking layer, a hole transport layer, and a hole injection layer. The second intermediate functional layer FNL12 and the fourth intermediate functional layer FNL22 can contain an electron injection / transport material. The second intermediate functional layer FNL12 and the fourth intermediate functional layer FNL22 can include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer.

[0237] The first and second light-emitting layers EML1 and EML2 may each contain an organic light-emitting material, or may each contain an inorganic light-emitting material or may be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material.

[0238] The first top electrode EL21 may be disposed on the first intermediate layer IML1. The second top electrode EL22 may be disposed on the second intermediate layer IML2. The first top electrode EL21 and the second top electrode EL22 may be connected to the connecting electrodes CNE1 and CNE2, respectively, as described above, and may be electrically connected to the pixel driving part PDC. That is, the first top electrode EL21 and the second top electrode EL22 may be electrically connected to the connecting transistor TR via the connecting electrodes CNE1 and CNE2, respectively.

[0239] A dummy layer UP may be disposed on the separators SPR1 and SPR2. The dummy layer UP may include a first dummy layer UP1 disposed on the first separator SPR1 and a second dummy layer UP2 disposed on the first dummy layer UP1. The dummy layer UP may include a third dummy layer UP3 disposed on the second separator SPR2 and a fourth dummy layer UP4 disposed on the third dummy layer UP3. The first dummy layer UP1 may be formed in the same process as the first intermediate layer IML1 and may contain the same material as the first dummy layer UP1. The third dummy layer UP3 may be formed in the same process as the second intermediate layer IML2 and may contain the same material as the second dummy layer UP3. In one embodiment, the first dummy layer UP1 and the third dummy layer UP3 may be formed simultaneously during the process of forming the functional layers FNL1 and FNL2. The second dummy layer UP2 may be formed in the same process as the first upper electrode EL21 and may contain the same material as the first dummy layer UP1. The fourth dummy layer UP4 may be formed in the same process as the second upper electrode EL22 and may contain the same material. In one embodiment, the second dummy layer UP2 and the fourth dummy layer UP4 may be formed simultaneously in the process of forming the upper electrodes EL21 and EL22.

[0240] The first dummy layer UP1 may include a 1-1 dummy layer UP1a and a 1-2 dummy layer UP1b. The 1-1 dummy layer UP1a may be formed in the same process as the first intermediate functional layer FNL11, and may contain the same material as the first dummy layer UP1a. The 1-2 dummy layer UP1b may be formed in the same process as the second intermediate functional layer FNL12, and may contain the same material as the second dummy layer UP1b. The third dummy layer UP3 may include a 3-1 dummy layer UP3a and a 3-2 dummy layer UP3b. The 3-1 dummy layer UP3a may be formed in the same process as the third intermediate functional layer FNL21, and may contain the same material as the third dummy layer UP3b. The 3-2 dummy layer UP3b may be formed in the same process as the fourth intermediate functional layer FNL22, and may contain the same material as the fourth dummy layer FNL22.

[0241] As shown in Figures 6, 7a, and 7b, the first separator SPR1 and the second separator SPR2 may each have a double reverse tapered shape. The side surfaces SS1, SS2, SS3, and SS4 of the first separator SPR1 and the second separator SPR2 may each include a first sub-side surface and a second sub-side surface with different taper angles. The first side surface SS1 of the first separator SPR1 may include a first-1 sub-side surface SS1a and a second-1 sub-side surface SS1b with different taper angles. The second side surface SS1 of the first separator SPR1 may include a first-2 sub-side surface SS2a and a second-2 sub-side surface SS2b with different taper angles. The third side surface SS3 of the second separator SPR2 may include a first-3 side surface SS3a and a second-3 side surface SS3b with different taper angles. The four side surfaces SS4 of the second separator SPR2 may include a first-fourth side surface SS4a and a second-fourth side surface SS4b having different taper angles. The second sub-side surfaces SS1b, SS2b, SS3b, and SS4b may be side surfaces adjacent to the top surface of the pixel defining layer PDL, and the first sub-side surfaces SS1a, SS2a, SS3a, and SS4a may be surfaces spaced apart from the top surface of the pixel defining layer PDL with the second sub-side surfaces SS1b, SS2b, SS3b, and SS4b interposed therebetween.

[0242] The taper angles formed by the first sub-side surfaces SS1a, SS2a, SS3a, and SS4a of the first separator SPR1 and the second separator SPR2 with respect to the upper surface of the pixel defining layer PDL may be different from the taper angles formed by the second sub-side surfaces SS1b, SS2b, SS3b, and SS4b. Each of the taper angles may be obtuse. For example, as shown in FIGS. 7a and 7b, the taper angles formed by the first sub-side surfaces SS1a, SS2a, SS3a, and SS4a with respect to the upper surface of the pixel defining layer PDL may be larger than the taper angles formed by the second sub-side surfaces SS1b, SS2b, SS3b, and SS4b with respect to the upper surface of the pixel defining layer PDL. The taper angles are angles formed by the sub-side surfaces with respect to a horizontal plane, e.g., the upper surface of the pixel defining layer PDL.

[0243] 6 and other figures illustrate separators SPR1 and SPR2 having a double inverse tapered shape, but this is not limiting and a display panel according to a later-described embodiment may have a single inverse tapered shape. That is, the side surfaces SS1 to SS4 of separators SPR1 and SPR2 may include a single surface with a constant taper angle.

[0244] The upper electrodes EL21, EL21 are in contact with the connecting electrodes CNE1, CNE1 through contact regions CA1, CA2. The contact regions CA1, CA2 are provided adjacent to the separators SPR1, SPR2. In the contact regions CA1, CA2, the upper surfaces of the connecting electrodes CNE1, CNE2 are in contact with the lower surfaces of the upper electrodes EL21, EL22. Meanwhile, because the separators SPR1, SPR2 have an inverse tapered shape and the contact regions CA1, CA2 are provided adjacent to the separators SPR1, SPR2, at least a portion of the contact regions CA1, CA2 where the upper electrodes EL21, EL22 and the connecting electrodes CNE1, CNE2 contact each other may be disposed below the side surfaces of the outer surfaces of the separators SPR1, SPR2.

[0245] Meanwhile, as described above, the connecting electrodes CNE1, CNE2 are disposed on the outer surfaces of the separators SPR1, SPR2 but not on the inner surfaces of the separators SPR1, SPR2, so the contact areas CA1, CA2 are disposed adjacent to the outer surfaces of the separators SPR1, SPR2 but not adjacent to the inner surfaces. In one embodiment, a first contact area CA1 may be provided adjacent to the first side surface SS1 of the first separator SPR1, and a separation area SPA where no separate connecting electrode is provided adjacent to the second side surface SS2 may be provided. A second contact area CA2 may be provided adjacent to the third side surface SS3 of the second separator SPR2, and a separation area SPA where no separate connecting electrode is provided adjacent to the fourth side surface SS4 may be provided.

[0246] In one embodiment, the display panel may include middle areas MA1 and MA2 adjacent to the contact areas CA1 and CA2. In the middle areas MA1 and MA2, the functional layers FNL1 and FNL2 may be disposed between the connecting electrodes CNE1 and CNE2 and the upper electrodes EL21 and EL22. That is, in the middle areas MA1 and MA1, the connecting electrodes CNE1 and CNE2 and the upper electrodes EL21 and EL22 may be spaced apart with the functional layers FNL1 and FNL2 sandwiched therebetween. A first middle area MA1 may include a first middle functional layer FNL11 and a second middle functional layer FNL12. A third middle functional layer FNL21 and a fourth middle functional layer FNL22 may be disposed in the second middle area MA2.

[0247] An additional dummy layer AP may be provided in the isolation portion SPP. The additional dummy layer AP may include a first additional dummy layer AP1 and a second additional dummy layer AP2. The first additional dummy layer AP1 may be disposed directly on the pixel defining layer PDL. The second additional dummy layer AP2 may be disposed directly on the first additional dummy layer AP1. The region where the additional dummy layer AP is disposed may correspond to the isolation region SPA described above. The first additional dummy layer AP1 may include a first-first additional dummy layer AP1a and a first-second additional dummy layer AP1b.

[0248] In one embodiment, the first additional dummy layer AP1 may be formed simultaneously with the process of forming the functional layers FNL1 and FNL2. The first additional dummy layer AP1 may be formed in the same process as the functional layers FNL1 and FNL2, the first dummy layer UP1, and the third dummy layer UP3, and may contain the same material. The first-first additional dummy layer AP1a may be formed in the same process as the first intermediate functional layer FNL11 and the third intermediate functional layer FNL21, and may contain the same material. The first-second additional dummy layer AP1b may be formed in the same process as the second intermediate functional layer FNL12 and the fourth intermediate functional layer FNL22, and may contain the same material. The second additional dummy layer AP2 may be formed simultaneously with the process of forming the top electrodes EL21 and EL22. The second additional dummy layer AP2 may be formed in the same process as the top electrodes EL21 and EL22, the second dummy layer UP2, and the fourth dummy layer UP4, and may contain the same material. The second additional dummy layer AP2 may be disposed on a portion of the inner surfaces of the separators SPR1 and SPR2. The second additional dummy layer AP2 may be disposed on a portion of each of the second side surface SS2 of the first separator SPR1 and the fourth side surface SS4 of the second separator SPR2.

[0249] The connecting electrodes CNE1, CNE2 include portions disposed in the contact regions CA1, CA2 and portions disposed on the outer surfaces SS1, SS3 of the separators SPR1, SPR2. The connecting electrodes CNE1, CNE2 may include first connecting portions CNE1-1, CNE2-1 disposed in the contact regions CA1, CA2 and second connecting portions CNE1-2, CNE2-2 disposed on the outer surfaces SS1, SS3 of the separators SPR1, SPR2. The second connecting portions CNE1-2, CNE2-2 may contact the outer surfaces SS1, SS3 of the separators SPR1, SPR2. The second connecting portions CNE1-2, CNE2-2 may contact second sub-side surfaces SS1b, SS3b of the outer surfaces SS1, SS3 of the separators SPR1, SPR2 and may contact at least a portion of the first sub-side surfaces SS1a, SS3a.

[0250] The upper electrodes EL21, EL22 may include portions that contact the connecting electrodes CNE1, CNE2 in the contact regions CA1, CA2 and portions that contact portions of the connecting electrodes CNE1, CNE2 arranged on outer surfaces SS1, SS3 of the separators SPR1, SPR2. The upper electrodes EL21, EL22 may include first electrode portions EL21-1, EL22-1 arranged on top of the first connecting portions CNE1-1, CNE2-1, and second upper electrode portions EL21-2, EL22-2 that contact side surfaces of the second connecting portions CNE1-2, CNE2-2.

[0251] In one embodiment, the separators SPR1 and SPR2 are formed first, and then the connecting electrodes CNE1 and CNE2 are formed in a later process, and portions of the connecting electrodes CNE1 and CNE2 may be shaped so that they are not disposed under the separators SPR1 and SPR2 but are disposed along the outer surfaces SS1 and SS3. As a result, the connecting electrodes CNE1 and CNE2 and the top electrodes EL21 and EL22 may additionally contact each other on the outer surfaces SS1 and SS3 of the separators SPR1 and SPR2 in addition to the contact regions CA1 and CA2, thereby increasing the contact area between the connecting electrodes CNE1 and CNE2 and the top electrodes EL21 and EL22. In other words, the area of ​​the connection contact increases, and the connection may be more stable.

[0252] In one embodiment, portions of the connecting electrodes CNE1, CNE2 may be disposed on the separators SPR1, SPR2. The connecting electrodes CNE1, CNE2 may further include third connecting portions CNE1-3, CNE2-3 disposed on portions of the upper surfaces SPR1-U, SPR2-U of the separators SPR1, SPR2. In one embodiment, the second connecting portions CNE1-2, CNE2-2 of the connecting electrodes CNE1, CNE2 may cover the entire outer surfaces SS1, SS3 of the separators SPR1, SPR2 and be connected to the third connecting portions CNE1-3, CNE2-3 disposed on portions of the upper surfaces SPR1-U, SPR2-U of the separators SPR1, SPR2.

[0253] Meanwhile, at least a portion of the second connecting portions CNE1-2, CNE2-2 may not contact the second electrodes EL21, EL2. Unlike the second connecting portions CNE1-2, CNE2-2 that correspond to the entire outer surfaces SS1, SS3 of the separators SPR1, SPR2, the second upper electrode portions EL21-1, EL22-2 may be disposed corresponding to only a portion of the outer surfaces SS1, SS3 of the separators SPR1, SPR2. Some of the side surfaces of the second connecting portions CNE1-2, CNE2-2 may be exposed and not covered by the second upper electrode portions EL21-2, EL22-2.

[0254] The dummy layers UP may be formed not only on the upper surfaces of the separators SPR1 and SPR2 but also on some of the side surfaces SS1 to SS4, since the dummy layers UP may not be in contact with the upper electrodes EL21 and EL22.

[0255] The spacing between dummy layers disposed on different separators SPR1 and SPR2 in one direction may be equal to or smaller than the spacing between the separators SPR1 and SPR2. In one embodiment, the spacing between the first dummy layer UP1 and the third dummy layer UP3 may be equal to or smaller than the spacing S1 between the first separator SPR1 and the second separator SPR2. The spacing between the second dummy layer UP2 and the fourth dummy layer UP4 may be equal to or smaller than the spacing S1 between the first separator SPR1 and the second separator SPR2. The spacing between the first dummy layer UP1 and the third dummy layer UP3 may be equal to or smaller than the spacing S2 between the tip of the first connecting electrode CNE1 and the second connecting portion CNE2. The spacing between the second dummy layer UP2 and the fourth dummy layer UP4 may be equal to or smaller than the spacing S2 between the tip of the first connecting electrode CNE1 and the second connecting portion CNE2.

[0256] Meanwhile, a portion of the dummy layer UP may contact the connecting electrodes CNE1 and CNE2. The second dummy layer UP2 may contact the first connecting insulating layer CNE1 disposed on the first side surface SS1. The fourth dummy layer UP4 may contact the second connecting insulating layer CNE2 disposed on the third side surface SS3. In the display panel according to an embodiment, even if a portion of the dummy layer UP contacts the connecting electrodes CNE1 and CNE2, a separation portion SPP is provided between adjacent separators SPR1 and SPR2, thereby preventing leakage current from occurring between adjacent pixels.

[0257] More specifically, in the display panel according to an embodiment, a transparent conductive oxide (TCO) included in the connecting electrodes CNE1 and CNE2 has excellent deposition characteristics and may be deposited on parts of outer surfaces SS1 and SS3 and upper surfaces SPR1-U and SPR2-U of the separators SPR1 and SPR2. Meanwhile, a separation portion SPP is provided between the separators SPR1 and SPR2, and the connecting electrodes CNE1 and CNE2 are not provided on inner surfaces SS2 and SS4 of the separators SPR1 and SPR2. Therefore, in the display panel according to an embodiment, even if a part of the dummy layer UP contacts the connecting electrodes CNE1 and CNE2, causing leakage current between the dummy layer UP and the connecting electrodes CNE1 and CNE2, a structure in which the electrical connection is interrupted at the inner surfaces SS2 and SS4 is provided, thereby preventing lateral leakage current between pixels.

[0258] Figures 8a to 8c are cross-sectional views of a display panel according to an embodiment of the present invention. Each of Figures 8a to 8c shows a cross section of a display panel according to the embodiment shown in Figure 6 and another embodiment, corresponding to the cross section shown in Figure 6. Meanwhile, the same reference numerals are used for the components already described with reference to Figures 5 and 6, and detailed descriptions thereof will be omitted.

[0259] 8a, unlike the separators SPR1 and SPR2 shown in FIG. 6, the outer surfaces SS1' and SS3' of the separators SPR1' and SPR2' of one embodiment may have a single reverse taper rather than a double reverse taper. As shown in FIG. 8a, the outer surfaces SS1' and SS3' of the separators SPR1' and SPR2' may have a reverse taper with a certain angle. The first separator SPR1' may have a single reverse tapered first side surface SS1', and the second separator SPR2' may have a single reverse tapered third side surface SS3'.

[0260] In one embodiment of the separators SPR1' and SPR2', the outer surfaces SS1' and SS3' and the inner surfaces SS2 and SS4 may have different shapes. As described above, the inner surfaces SS2 and SS4 of the separators SPR1' and SPR2' may have a double reverse tapered shape, while the outer surfaces SS1' and SS2' may have a single reverse tapered shape with a fixed angle. However, this is not limited thereto, and the inner surfaces SS2 and SS4 of the separators SPR1' and SPR2' may also have a single reverse tapered shape with a fixed angle, like the outer surfaces SS1' and SS2'.

[0261] 8b and 8c, in one embodiment, additional separators SPR-ad1 and SPR-ad2 may be provided in the spaced apart portion between separators SPR1 and SPR2. As shown in Fig. 8b, one additional separator SPR-ad1 may be provided in the spaced apart portion. Alternatively, as shown in Fig. 8c, multiple additional separators SPR-ad1 and SPR-ad2 may be provided in the spaced apart portion. A first additional separator SPR-ad1 and subsequent separators SPR-ad2 may be provided in the spaced apart portion.

[0262] The additional separators SPR-ad1 and SPR-ad2 may have the same shape as the separators SPR1 and SPR2. The additional separators SPR-ad1 and SPR-ad2 may have an inverse tapered shape. That is, the additional separators SPR-ad1 and SPR-ad2 may have a shape in which their width increases as they move away from the top surface of the pixel defining film PDL. The additional separators SPR-ad1 and SPR-ad2 may have a double inverse tapered shape. The first additional separator SPR-ad1 may include a first additional side surface SS-ad1 and a second additional side surface SS-ad2 having an inverse tapered shape. The second additional separator SPR-ad2 may include a third additional side surface SS-ad3 and a fourth additional side surface SS-ad4 having an inverse tapered shape.

[0263] The dummy layer UP may be provided not only on the separators SPR1 and SPR2 but also on the additional separators SPR-ad1 and SPR-ad2. The dummy layer UP may include a fifth dummy layer UP5 disposed on the first additional separator SPR-ad1 and a sixth dummy layer UP6 disposed on the fifth dummy layer UP5. The dummy layer UP may include a seventh dummy layer UP7 disposed on the second additional separator SPR-ad2 and an eighth dummy layer UP8 disposed on the seventh dummy layer UP7. In one embodiment, the fifth dummy layer UP5 and the seventh dummy layer UP7 may be formed simultaneously with the process of forming the functional layers FNL1 and FNL2. In one embodiment, the sixth dummy layer UP6 and the eighth dummy layer UP8 may be formed simultaneously with the process of forming the upper electrodes EL21 and EL22.

[0264] The fifth dummy layer UP5 may include a 5-1 dummy layer UP5a and a 5-2 dummy layer UP5b. The 5-1 dummy layer UP5a may be formed in the same process as the first intermediate functional layer FNL11, and may contain the same material as the first dummy layer UP5a. The 5-2 dummy layer UP5b may be formed in the same process as the second intermediate functional layer FNL12, and may contain the same material as the second dummy layer UP5b. The seventh dummy layer UP7 may include a 7-1 dummy layer UP7a and a 7-2 dummy layer UP7b. The 7-1 dummy layer UP7a may be formed in the same process as the third intermediate functional layer FNL21, and may contain the same material as the second dummy layer UP5b. The 7-2 dummy layer UP7b may be formed in the same process as the fourth intermediate functional layer FNL22, and may contain the same material as the second dummy layer UP5b.

[0265] Sub-separation portions may be provided between the separators SPR1, SPR2 and the adjacent additional separators SPR-ad1, SPR-ad2. When one additional separator SPR-ad1 is provided as shown in Fig. 8b, a first sub-separation portion SPP1 may be provided between the first separator SPR1 and the first additional separator SPR-ad1, and a second sub-separation portion SPP2 may be provided between the second separator SPR2 and the first additional separator SPR-ad1. As shown in FIG. 8c, when a first additional separator SPR-ad1 and a second additional separator SPR-ad2 are provided, a first sub-separation portion SPP1 may be provided between the first separator SPR1 and the first additional separator SPR-ad1, a second sub-separation portion SPP2 may be provided between the second separator SPR2 and the second additional separator SPR-ad2, and a third sub-separation portion SPP3 may be provided between the first additional separator SPR-ad1 and the second additional separator SPR-ad2.

[0266] The above-mentioned additional dummy layers may be provided in each of the sub-isolated portions SPP1, SPP2, and SPP3.

[0267] 8b, when one additional separator SPR-ad1 is provided, a first additional dummy layer AP1 and a second additional dummy layer AP2 may be provided in the first sub-isolation portion SPPa1. The first additional dummy layer AP1 may include a first-first additional dummy layer AP1a and a first-second additional dummy layer AP1b. A third additional dummy layer AP3 and a fourth additional dummy layer AP4 may be disposed in the second sub-isolation portion SPPa2. The third additional dummy layer AP3 may include a third-first additional dummy layer AP3a and a third-second additional dummy layer AP3b. The second additional dummy layer AP2 may be disposed on a portion of each of the second side surface SS2 of the first separator SPR1 and the first additional side surface SS-ad1 of the first additional separator SPR-ad1. The fourth additional dummy layer AP4 can be disposed on a portion of each of the fourth side surface SS4 of the second separator SPR2 and the second additional side surface SS-ad2 of the first additional separator SPR-ad1.

[0268] As shown in FIG. 8c, when a first additional separator SPR-ad1 and a second additional separator SPR-ad2 are provided, a first additional dummy layer AP1 and a second additional dummy layer AP2 may be provided in the first sub-isolated portion SPPa1. The first additional dummy layer AP1 may include a first-first additional dummy layer AP1a and a first-second additional dummy layer AP1b. A third additional dummy layer AP3 and a fourth additional dummy layer AP4 may be disposed in the second sub-isolated portion SPPa2. The third additional dummy layer AP3 may include a third-first additional dummy layer AP3a and a third-second additional dummy layer AP3b. A fifth additional dummy layer AP5 and a sixth additional dummy layer AP6 may be disposed in the third sub-isolated portion SPPa3. The fifth additional dummy layer AP5 may include a fifth-first additional dummy layer AP5a and a fifth-second additional dummy layer AP5b. The second additional dummy layer AP2 may be disposed on a portion of the second side surface SS2 of the first separator SPR1 and a portion of the first additional side surface SS-ad1 of the first additional separator SPR-ad1. The fourth additional dummy layer AP4 may be disposed on a portion of the fourth side surface SS4 of the second separator SPR2 and a portion of the fourth additional side surface SS-ad4 of the second additional separator SPR-ad2. The sixth additional dummy layer AP6 may be disposed on a portion of the second additional side surface SS-ad2 of the first additional separator SPR-ad1 and a portion of the third additional side surface SS-ad3 of the second additional separator SPR-ad2.

[0269] The first additional dummy layer AP1, the third additional dummy layer AP3, and the fifth additional dummy layer AP5 are formed simultaneously with the process of forming the functional layers FNL1, FNL2, and may contain the same material as the functional layers FNL1, FNL2. The second additional dummy layer AP2, the fourth additional dummy layer AP4, and the sixth additional dummy layer AP6 are formed simultaneously with the process of forming the top electrodes EL21, EL22, and may contain the same material as the top electrodes EL21, EL22.

[0270] 9 is a diagram illustrating an electronic device according to an embodiment of the present invention. Referring to FIG. 9, an electronic device 1000 according to an embodiment of the present invention may output various information (e.g., images, text, music) through a display module 1140, which may correspond to the display device DD shown in FIG. 1. When the processor 1110 executes an application stored in the memory 1120, the display module 1140 may provide application information to a user through a display panel 1141.

[0271] In some embodiments, the electronic device 1000 may be a smartphone, a camera, a smart TV, a monitor, a smart watch, a tablet, an automobile display, or an AR / VR headset. For example, the electronic device 1000 may be a smartphone including a touch-sensitive display area DA for interaction and a non-display area NDA including sensors and circuits for enhanced functionality. For example, the electronic device 1000 may be a television or monitor including a large display area DA for high-resolution video playback and a non-display area NDA including driver circuits or connection modules for external inputs. For example, the electronic device 1000 may be a smart watch including a display area DA optimized for small, clear images and a non-display area NDA including biometric sensors for health monitoring. In some cases, the electronic device 1000 may be an AR / VR headset.

[0272] In some embodiments, memory 1120 may store information such as software code for operating application programs 1123. Application programs 1123 may include software designed to perform or provide specific tasks to a user. Application programs 1123 may operate under the control of processor 1110 and utilize data stored in memory 1120 to provide a wide range of functionality, such as productivity tools, multimedia streaming and playback, file or email transfer, and communication services. Application programs 1123 interact seamlessly with user interface 1161 or touchscreen 1142, allowing a user to run, navigate, and use the programs through user input such as touch, tab, gesture, or voice interaction.

[0273] When a user selects an application via touch screen 1142 or user interface 1161, processor 1110 may execute application program 1123 corresponding to the application retrieved from memory 1120 to perform the function of the corresponding application. For example, when a user tabs an icon (or a camera application) displayed on display panel 1141 and selects the camera application, processor 1110 activates the camera module. Processor 1110 may transmit image data corresponding to a captured image acquired via the camera module to display module 1140. Display module 1140 may display an image corresponding to the captured image on display panel 1141.

[0274] As another example, when a user wants to make a phone call, if the user tabs a phone icon displayed on display module 1140, processor 1110 may execute a phone application program stored in memory 1120. A phone keypad may be displayed on display panel 1141 so that the user can enter the phone number to call.

[0275] As another example, display module 1140 may be integrated into electronic device 1000, such as a laptop, smart TV, or tablet. A user wishing to access a multimedia streaming application (e.g., to watch a music video or movie) may do so by tabbing over the corresponding icon. This action activates the application, allowing the user to view the streamed content.

[0276] The processor 1110 may include a main processor 1111 and an auxiliary processor 1112. The main processor 1111 may include a central processing unit (CPU), which may further include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0277] The auxiliary processor 1112 may include a controller 1112-1. The controller 1121-1 may include an interface conversion circuit and a timing control circuit. The controller 1121-1 may receive image signals from the main processor 1111, convert the data format of the image signals to conform to the interface specifications with the display module 1140, and output image data. The controller 1112-1 may output various types of control signals necessary to drive the display module 1140. For example, the controller 1112-1 may drive the display module 1140 to display user-selectable icons on the display screen and execute the application program 1123.

[0278] The memory 1120 may store one or more application programs 1123 and various data used by at least one component of the electronic device 1000 (e.g., the processor 1110 or the user interface 1161), as well as input or output data for instructions related thereto. For example, a camera application program, a GPS application program, an augmented reality and virtual reality application program, and other application programs that can be executed by the processor 1110 when a user selects a corresponding icon displayed on the display screen (or display panel 1141) via the touch screen 1142 or the user interface 1161 may be stored. In addition, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include a volatile memory 1121 and a non-volatile memory 1122.

[0279] The display module 1140 can output visual information (images) to a user. The display module 1140 may include a display panel 1141, a gate driver, a source driver, a voltage generating circuit, and a touch screen. The display module 1140 may further include a window, a chassis, and a bracket for protecting the display panel 1141. The display module 1140 may include at least a portion of the configuration of the display device DD shown in FIG. 1.

[0280] The user interface 1161 serves as a medium for interaction between a user and the electronic device 1000. The user interface 1161 may sense pressure from a part of the user's body (e.g., a finger) or input from a pen or mouse, and generate an electrical signal or data value corresponding to the input. The user interface 1161 includes a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0281] Fingerprint sensor 1162 may sense a fingerprint for biometric recognition of a user and may measure one or more biological signals such as blood pressure, hydration, or body mass.

[0282] The input sensors 1163 can sense user interactions including touch, tab, gestures, movements, voice commands, and eye movements. The input sensors 1163 can include image capture, eye tracking, or optical sensors for sensing movements and gestures. The optical sensors can be infrared or semiconductor aperture detectors. The input sensors 1163 can include audio and acoustic sensors, which can be MEMS microphones for voice recognition or sound-based interaction. The audio and acoustic sensors can be located as part of the user interface 1161 or can be integrated into the display panel 1151.

[0283] The digitizer 1164 may generate data values ​​corresponding to the coordinate information of a pen or mouse input to control cursor movement on the screen. The digitizer 1164 may generate data values ​​representing the amount of change in electromagnetic waves caused by the input. The digitizer 1164 may sense input from a manual pen, or may send and receive data via an active pen or remote control.

[0284] At least one of the fingerprint sensor 1162, the input sensor 1163, or the digitizer 1164 may be embodied as a sensor layer formed on the top layer of the display panel 1141 through a process continuous with the process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 1141.

[0285] The user interface 1161 may also include, for example, gesture sensors, gyro sensors to sense rotational movement, acceleration sensors to track translational movement, grip sensors, pressure sensors, proximity sensors, color sensors, infrared (IR) emitters and camera sensors to track gaze direction and eye movement, temperature sensors, or light sensors. For example, the gyro sensors, acceleration sensors, IR emitters, and cameras may be particularly suited for AR / VR headset functionality.

[0286] The touch screen 1142 includes a touch sensor embedded in the semiconductor layer of the display panel 1141 and senses pressure applied to the top layer (screen) of the display panel 1141. The touch sensor may be capacitive or resistive. The touch screen 1142 may serve as the primary interface through which a user may select and explore applications, control the electronic device 1000, and interact with the electronic device 1000.

[0287] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type or a flexible type that can be rolled up or folded. The display module 1140 may further include a support, bracket, heat dissipation member, etc. that support the display panel 1141. The display panel 1141 may be included in the display device DD shown in FIG. 1.

[0288] The power supply module 1150 may provide power to the components of the electronic device 1000. The power supply module 1150 may include a battery that charges the power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power supply module 1150 may include a power management integrated circuit (PMIC). The PMIC may include the display module 1140 and provide optimized power to each of the above-mentioned components.

[0289] Although the present invention has been described above with reference to preferred embodiments, it should be understood by those skilled in the art or those having ordinary skill in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Therefore, the technical scope of the present invention should be determined by the claims, not by the contents of the detailed description of the specification. [Explanation of symbols]

[0290] DP: Display panel DDL: Driver element layer LD1: First light-emitting element PDL: Pixel definition layer CNE1: First connecting electrode PDC: Pixel driving unit SPR: Separator SPR1: First separator SPR2: Second separator SPP: Separator

Claims

1. a driving element layer including a pixel driving unit; a first light-emitting element disposed on the driving element layer and including a first lower electrode; a first intermediate layer disposed on the first lower electrode and including at least a first light-emitting layer; and a first upper electrode disposed on the first intermediate layer; a pixel defining layer disposed on the driving element layer, the pixel defining layer defining a first opening through which at least a portion of the first lower electrode is exposed; a first connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the first upper electrode; a separator disposed on the pixel defining film; the separator includes a first separator adjacent to the first light emitting element and a second separator spaced apart from the first light emitting element with the first separator interposed therebetween, and a spacer is provided between the first separator and the second separator; the first separator includes a first side adjacent to the first light emitting element and a second side adjacent to the spacer; The display panel, wherein the first connecting electrode is disposed on at least a portion of the first side surface and is not disposed on the second side surface.

2. a second light-emitting element disposed on the driving element layer, the second light-emitting element including a second lower electrode; a second intermediate layer disposed on the second lower electrode and including at least a second light-emitting layer; and a second upper electrode disposed on the second intermediate layer; The display panel according to claim 1 , wherein the second separator is disposed between the second light-emitting element and the first separator in a plan view.

3. a second opening is defined in the pixel defining layer to expose at least a portion of the second lower electrode; 3. The display panel of claim 2, further comprising a second connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the second upper electrode.

4. the second separator includes a third side adjacent to the second light emitting element and a fourth side adjacent to the spacer; The display panel of claim 3 , wherein the second connecting electrode is disposed on at least a part of the third side surface and is not disposed on the fourth side surface.

5. The display panel of claim 4 , wherein the first connecting electrodes and the second connecting electrodes are not disposed in the spaced apart portions.

6. the first intermediate layer further comprises a first functional layer; 2. The display panel of claim 1, wherein the first functional layer includes a first intermediate functional layer arranged on the first lower electrode and a second intermediate functional layer arranged on the first light-emitting layer, and the first light-emitting layer is arranged between the first intermediate functional layer and the second intermediate functional layer.

7. a first dummy layer disposed on the first separator and containing the same material as the first functional layer; a second dummy layer disposed on the first dummy layer and containing the same material as the first upper electrode; The display panel of claim 6 , wherein the first connecting electrode is in contact with the second dummy layer.

8. a first additional dummy layer disposed in the separated portion and containing the same material as the first functional layer; The display panel of claim 6 , further comprising: a second additional dummy layer disposed on the first additional dummy layer and containing the same material as the first upper electrode.

9. The display panel according to claim 1 , wherein the first connecting electrode has a ring shape surrounding the first opening.

10. 2. The display panel of claim 1, wherein a lower surface of the first upper electrode contacts an upper surface of the first connecting electrode in a first contact region adjacent to the first separator.

11. The first connecting electrode is a first connecting portion disposed in the first contact region; a second connecting portion disposed on the first side surface of the first separator; The display panel of claim 10 , wherein the first connecting electrode includes a third connecting portion disposed on an upper surface of the separator.

12. The first upper electrode is a first upper electrode portion in contact with an upper surface of the first connecting portion; The display panel of claim 11 , further comprising: a second upper electrode portion in contact with a side surface of the second connecting portion.

13. Further comprising an additional separator disposed in the spaced apart portion, The display panel of claim 1 , wherein the additional separator is spaced apart from the first separator and the second separator.

14. The display panel of claim 1 , wherein the pixel defining layer has a through-hole defined therein, and the first connecting electrode is connected to the pixel driving part through the through-hole.

15. The display panel according to claim 14 , wherein the first intermediate layer overlaps the through-hole.

16. The display panel of claim 1 , wherein the first intermediate layer is disposed between the first connecting electrode and the first upper electrode in an intermediate region disposed between the first separator and the first light emitting element.

17. a driving element layer including a pixel driving unit; a first light-emitting element disposed on the driving element layer and including a first lower electrode; a first intermediate layer disposed on the first lower electrode and including at least a first light-emitting layer; and a first upper electrode disposed on the first intermediate layer; a second light-emitting element disposed on the driving element layer, the second light-emitting element including: a second lower electrode; a second intermediate layer disposed on the second lower electrode, the second intermediate layer including at least a second light-emitting layer; and a second upper electrode disposed on the second intermediate layer; a pixel defining layer disposed on the driving element layer, the pixel defining layer defining a first opening exposing at least a portion of the first lower electrode and a second opening exposing at least a portion of the second lower electrode; a first connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the first upper electrode; a second connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the second upper electrode; a separator disposed on the pixel defining layer and including a first separator adjacent to the first light emitting element, and a second separator spaced apart from the first separator and adjacent to the second light emitting element; a distance between the first separator and the second separator being smaller than a distance between the first connecting electrode and the second connecting electrode;

18. the first intermediate layer further comprises a first functional layer; the first functional layer includes a first intermediate functional layer disposed on the first lower electrode and a second intermediate functional layer disposed on the first light-emitting layer, and the first light-emitting layer is disposed between the first intermediate functional layer and the second intermediate functional layer; the second intermediate layer further comprises a second functional layer; 18. The display panel of claim 17, wherein the second functional layer includes a third intermediate functional layer arranged on the second lower electrode and a fourth intermediate functional layer arranged on the second light-emitting layer, and the second light-emitting layer is arranged between the third intermediate functional layer and the fourth intermediate functional layer.

19. a first dummy layer disposed on the first separator and containing the same material as the first functional layer; a second dummy layer disposed on the first dummy layer and containing the same material as the first upper electrode; a third dummy layer disposed on the second separator and containing the same material as the second functional layer; a fourth dummy layer disposed on the third dummy layer and containing the same material as the second upper electrode; The display panel of claim 18 , wherein the first connecting electrode contacts the second dummy layer, and the second connecting electrode contacts the fourth dummy layer.

20. The display panel of claim 19, wherein a distance between the second dummy layer and the fourth dummy layer is smaller than a distance between the first connecting electrode and the second connecting electrode.

21. The display panel of claim 20 , wherein the first connecting electrode and the second connecting electrode are not disposed in the spaced apart portion between the first separator and the second separator.

22. a first additional dummy layer disposed between the first separator and the second separator and containing the same material as each of the first functional layer and the second functional layer; The display panel of claim 18 , further comprising: a second additional dummy layer disposed on the first additional dummy layer and including the same material as the first upper electrode and the second upper electrode.

23. a processor; a memory in which an application program executed by said processor is stored; a display device; and The display device includes: a driving element layer including a pixel driving unit; a first light-emitting element disposed on the driving element layer and including a first lower electrode; a first intermediate layer disposed on the first lower electrode and including at least a first light-emitting layer; and a first upper electrode disposed on the first intermediate layer; a second light-emitting element disposed on the driving element layer, the second light-emitting element including: a second lower electrode; a second intermediate layer disposed on the second lower electrode, the second intermediate layer including at least a second light-emitting layer; and a second upper electrode disposed on the second intermediate layer; a pixel defining layer disposed on the driving element layer, the pixel defining layer defining a first opening exposing at least a portion of the first lower electrode and a second opening exposing at least a portion of the second lower electrode; a connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving unit; a separator disposed on the pixel defining film; the separator includes a first separator adjacent to the first light emitting element and a second separator spaced apart from the first separator, and a spacer is provided between the first separator and the second separator; The electronic device, wherein the connecting electrode is not disposed between the first separator and the second separator.

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