Semiconductor device

Abstract

To provide a semiconductor device capable of improving dielectric strength.SOLUTION: The semiconductor element A3 includes a first die pad 3, a second die pad 4, a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a plurality of first terminals 51, a plurality of second terminals 52, and a sealing resin 7. The first die pad 3 is provided with a pair of first near-angle portions 362 located on a side facing the second die pad 4 in the first direction x. The pair of first near-angle portions 362 are provided on both sides of the first die pad 3 in the second direction y. As viewed in the thickness direction, each of the pair of first near-angle portions 362 is inclined with respect to the second direction y.SELECTED DRAWING: Figure 28

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device that transmits signals between a plurality of semiconductor elements mounted in one package via an insulating element. [Background technology]

[0002] Semiconductor devices are used in inverter devices used in electric vehicles, hybrid vehicles, home appliances, and the like. The inverter device includes, for example, a semiconductor device and a power semiconductor, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device has a control element and a drive element. In the inverter device, a control signal output from an ECU (Engine Control Unit) is input to the control element of the semiconductor device. The control element converts the control signal into a PWM (Pulse Width Modulation) control signal and transmits it to the drive element. The drive element switches, for example, six power semiconductors at desired timing based on the PWM control signal. The six power semiconductors switch at desired timing to generate three-phase AC power for driving a motor from DC power of an on-board battery. For example, Patent Document 1 discloses an example of a semiconductor device (drive circuit) used in a motor drive device.

[0003] However, the power supply voltage required for the control element may differ from the power supply voltage required for the drive element. In such a case, in a semiconductor device in which multiple semiconductor elements are mounted in a single package, there is a difference in the power supply voltage applied to the two conduction paths, the conduction path to the control element and the conduction path to the drive element, and therefore it is necessary to improve the dielectric strength voltage between these conduction paths. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-155412 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above circumstances, an object of the present invention is to provide a semiconductor device capable of improving the dielectric strength voltage. [Means for solving the problem]

[0006] A first aspect of the present invention provides a semiconductor device comprising: a conductive support member including a first die pad and a second die pad spaced apart in a first direction orthogonal to a thickness direction and having relatively different potentials; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an insulating element conducting to the first semiconductor element and the second semiconductor element and insulating the first circuit and the second circuit from each other; and a first die pad, a second die pad, and a second die pad. and a sealing resin that covers the first semiconductor element, the second semiconductor element, and the insulating element and insulates the first die pad and the second die pad from each other, wherein the first die pad and the second die pad overlap each other when viewed along the first direction, and when viewed along the thickness direction, the periphery of the first die pad has a first near corner portion that includes a first end portion in a second direction that is perpendicular to both the thickness direction and the first direction, and the first near corner portion becomes more distant from the second die pad in the first direction as it moves toward the first end portion in the second direction.

[0007] A second aspect of the present invention provides a semiconductor device comprising: a conductive support member including a first die pad and a second die pad spaced apart in a first direction orthogonal to a thickness direction and having relatively different potentials; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an insulating element conducting to the first semiconductor element and the second semiconductor element and insulating the first circuit and the second circuit from each other; and a protective layer covering the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, and the insulating element and insulating the first die pad and the second die pad from each other. and a sealing resin that surrounds the die pad, wherein the first die pad and the second die pad overlap each other when viewed along the first direction, the first die pad has a first main surface that faces the thickness direction and has the first semiconductor element mounted thereon, and a first back surface that faces the opposite side of the first main surface in the thickness direction, the second die pad has a second main surface that faces the thickness direction and has the second semiconductor element mounted thereon, and a second back surface that faces the opposite side of the second main surface in the thickness direction, and when viewed along a second direction that is orthogonal to both the thickness direction and the first direction, the distance between the first back surface and the second back surface in the first direction is larger than the distance between the first main surface and the second main surface in the first direction.

[0008] A third aspect of the present invention provides a semiconductor device comprising: a first die pad arranged on one side in a first direction orthogonal to a thickness direction; a second die pad arranged on the other side in the first direction with respect to the first die pad, positioned apart from the first die pad in the first direction, and having a potential relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an insulating element mounted on either the first die pad or the second die pad, relaying transmission and reception of signals between the first circuit and the second circuit and insulating the first circuit and the second circuit from each other; and a plurality of first terminals including a portion located on the one side in the first direction with respect to the first die pad, and arranged along a second direction orthogonal to both the thickness direction and the first direction, at least one of which is conductive to the first circuit. a plurality of second terminals including a portion located on the other side in the first direction with respect to the second die pad and arranged along the second direction, at least one of which is conductive to the second circuit; and a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the insulating element, the plurality of first terminals, and a portion of each of the plurality of second terminals, and insulates the first die pad and the second die pad from each other, wherein the sealing resin has a first side surface located on the one side in the first direction, a second side surface located on the other side in the first direction, and a third side surface and a fourth side surface that are located apart from each other in the second direction and connected to the first side surface and the second side surface, a first gate mark having a surface rougher than other regions of the third side surface is formed on the third side surface, and the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction as viewed along the second direction.

[0009] a second die pad disposed on the other side of the first die pad in the first direction, spaced apart from the first die pad in the first direction, and having a potential relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an insulating element mounted on either the first die pad or the second die pad, relaying transmission and reception of signals between the first circuit and the second circuit and insulating the first circuit and the second circuit from each other; a plurality of second terminals arranged along a thickness direction, at least one of which is electrically connected to the second circuit; and a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the insulating element, the plurality of first terminals, and a portion of each of the plurality of second terminals, and insulates the first die pad and the second die pad from each other, wherein the sealing resin has a top surface that faces a side where the first semiconductor element is located with respect to the first die pad in the thickness direction, and a bottom surface that faces an opposite side to the top surface in the thickness direction. a bottom surface, a first side surface located on the one side in the first direction and connected to the top surface and the bottom surface, a second side surface located on the other side in the first direction and connected to the top surface and the bottom surface, and a third side surface located on either side in the second direction and connected to the first side surface and the second side surface, wherein the plurality of first terminals include a first edge terminal exposed from the first side surface and located closest to the third side surface, and the plurality of second terminals include a second edge terminal exposed from the second side surface and located closest to the third side surface,A first creepage distance from the first edge terminal to the second edge terminal along the first side surface, the third side surface, and the second side surface at the shortest distance is shorter than a second creepage distance from the first edge terminal to the second edge terminal along the first side surface, the bottom surface, and the second side surface at the shortest distance.

[0010] A fifth aspect of the present invention provides a semiconductor device comprising: a first die pad disposed on one side in a first direction orthogonal to a thickness direction; a second die pad disposed on the other side in the first direction with respect to the first die pad, spaced apart from the first die pad in the first direction, and having a potential relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an insulating element mounted on either the first die pad or the second die pad, relaying transmission and reception of signals between the first circuit and the second circuit, and insulating the first circuit and the second circuit from each other; a plurality of first terminals including a portion located on the one side in the first direction with respect to the first die pad, and arranged along a second direction orthogonal to both the thickness direction and the first direction, at least one of which is conductive to the first circuit; a plurality of second terminals, at least one of which is electrically connected to the second circuit, the plurality of second terminals including a portion located on the other side of the first direction and arranged along the second direction; and a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the insulating element, the plurality of first terminals, and a portion of each of the plurality of second terminals, and insulates the first die pad and the second die pad from each other, the sealing resin being such that the first semiconductor element is located on the other side of the first direction and the second semiconductor element is located on the other side of the first direction and the insulating element is arranged along the second direction, the plurality of second terminals being electrically connected to the second circuit; The semiconductor device has a top surface facing the side where the conductive element is located, a bottom surface facing the opposite side from the top surface in the thickness direction, and a first side surface located on one side of the first direction and connected to the top surface and the bottom surface, wherein the first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region and from which the multiple first terminals are exposed, and the surface roughness of each of the top surface, the bottom surface, the first region, and the second region is greater than the surface roughness of the third region. [Effects of the Invention]

[0011] According to the semiconductor device of the present invention, it is possible to improve the dielectric strength voltage.

[0012] Other features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a plan view corresponding to FIG. 1, seen through the sealing resin. [Figure 3] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 4] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 5] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 6] FIG. 2 is a front view of the semiconductor device shown in FIG. [Figure 7] FIG. 2 is a rear view of the semiconductor device shown in FIG. [Figure 8] FIG. 2 is a left side view of the semiconductor device shown in FIG. [Figure 9] FIG. 2 is a right side view of the semiconductor device shown in FIG. [Figure 10] FIG. 3 is a cross-sectional view taken along line XX in FIG. 2. [Figure 11] FIG. 11 is a partially enlarged view of FIG. [Figure 12] FIG. 3 is a cross-sectional view taken along line XII-XII in FIG. 2. [Figure 13] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] 2 is a block diagram showing an example of the configuration of a motor driving device using the semiconductor device shown in FIG. 1. FIG. [Figure 16] 2 is a plan view illustrating the types of each of a plurality of first terminals 51 and a plurality of second terminals 52 of the semiconductor device shown in FIG. 1. FIG. [Figure 17] 2 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 20] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 21] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 22] 2 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 23] 2 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 24] 2 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 25] 2 is a plan view illustrating the function and effect of the semiconductor device shown in FIG. 1. FIG. [Figure 26] FIG. 10 is a plan view of a semiconductor device according to a second embodiment of the present invention, seen through a sealing resin. [Figure 27] FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 26. [Figure 28] FIG. 10 is a plan view of a semiconductor device according to a third embodiment of the present invention, seen through a sealing resin. [Figure 29] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment of the present invention. [Figure 30] FIG. 30 is a rear view of the semiconductor device shown in FIG. 29. [Figure 31] FIG. 10 is a plan view of a semiconductor device according to a fifth embodiment of the present invention. [Figure 32] FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 31. [Figure 33] FIG. 33 is a cross-sectional view taken along line XXXIII-XXXIII in FIG. 31. [Figure 34] FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV in FIG. 31. [Figure 35]FIG. 10 is a plan view of a semiconductor device according to a sixth embodiment of the present invention, seen through a sealing resin. [Figure 36] FIG. 13 is a plan view of a semiconductor device according to a seventh embodiment of the present invention, seen through a sealing resin. [Figure 37] FIG. 13 is a plan view of a semiconductor device according to an eighth embodiment of the present invention, seen through a sealing resin. [Figure 38] FIG. 13 is a plan view of a semiconductor device according to a ninth embodiment of the present invention, seen through a sealing resin. [Figure 39] FIG. 23 is a plan view of a semiconductor device according to a tenth embodiment of the present invention, seen through a sealing resin. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the accompanying drawings.

[0015] [First embodiment] A semiconductor device A1 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 14. The semiconductor device A1 includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a conductive support member 2, a plurality of first wires 61, a plurality of second wires 62, a plurality of third wires 63, a plurality of fourth wires 64, and a sealing resin 7. Of these, the conductive support member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, and a plurality of second terminals 52. The semiconductor device A1 is surface-mounted on a wiring board of an inverter device, for example, in an electric vehicle or a hybrid vehicle. The package format of the semiconductor device A1 is a small outline package (SOP). However, the package format of the semiconductor device A1 is not limited to SOP. Here, for ease of understanding, FIG. 2 shows the sealing resin 7 in perspective. In FIG. 2, the transparent sealing resin 7 is indicated by an imaginary line (double-dashed line).

[0016] In the description of the semiconductor device A1, the thickness direction of each of the first die pad 3 and the second die pad 4 is referred to as the "z direction (thickness direction)." The direction perpendicular to the z direction is referred to as the "x direction (first direction)." The direction perpendicular to both the z direction and the x direction is referred to as the "y direction (second direction)." Furthermore, "plan view" refers to a viewpoint along the z direction.

[0017] First semiconductor element 11, second semiconductor element 12, and insulating element 13 are elements that form the functional core of semiconductor device A1. As shown in Fig. 2, in semiconductor device A1, first semiconductor element 11, second semiconductor element 12, and insulating element 13 are each composed of individual elements. In a plan view, first semiconductor element 11, second semiconductor element 12, and insulating element 13 each have a rectangular shape with the long side extending in the y direction.

[0018] The first semiconductor element 11 has a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmitting circuit for transmitting the PWM control signal to the second semiconductor element 12, and a receiving circuit that receives an electrical signal from the second semiconductor element 12.

[0019] The second semiconductor element 12 has a receiving circuit that receives a PWM control signal, a circuit (gate driver) that performs a switching operation of a switching element (such as an IGBT or a MOSFET) based on the PWM control signal, and a transmitting circuit that transmits an electrical signal to the first semiconductor element 11. The electrical signal can be, for example, an output signal from a temperature sensor installed near the motor.

[0020] The isolation element 13 is an element for transmitting PWM control signals and other electrical signals in an isolated state. The isolation element 13 is, for example, an inductive type. An example of an inductive isolation element is an isolation transformer, which transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The isolation element 13 has a substrate made of Si. An inductor made of Cu is formed on the substrate. The inductors include a transmitting inductor and a receiving inductor, which are stacked on top of each other in the thickness direction (z direction) of the isolation element 13. A dielectric layer made of SiO2 or the like is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor. In the semiconductor device A1, the isolation element 13 is shown as being of an inductive type, but it may also be of a capacitive type. An example of the capacitive isolation element 13 is a capacitor. Furthermore, the isolation element 13 may be a photocoupler.

[0021] In semiconductor device A1, second semiconductor element 12 requires a higher voltage than first semiconductor element 11. As a result, a significant potential difference occurs between first semiconductor element 11 and second semiconductor element 12, and therefore, in semiconductor device A1, a first circuit including first semiconductor element 11 and a second circuit including second semiconductor element 12 are insulated by insulating element 13. In other words, insulating element 13 insulates between the first circuit including first semiconductor element 11, which operates at a relatively low voltage, and the second circuit including second semiconductor element 12, which operates at a relatively high voltage. For example, in an inverter device for an electric vehicle or a hybrid vehicle, the power supply voltage required for first semiconductor element 11 is about 5 V, while the power supply voltage required for second semiconductor element 12 is 600 V or higher.

[0022] As shown in FIGS. 2 and 10 , the insulating element 13 is located between the first semiconductor element 11 and the second semiconductor element 12 in the x direction. The first semiconductor element 11 and the insulating element 13 are mounted on a portion of the conductive support member 2 (a first die pad 3 described later). The second semiconductor element 12 is mounted on a portion of the conductive support member 2 (a second die pad 4 described later). A plurality of electrodes 11A are provided on the upper surface (the surface facing the z direction) of the first semiconductor element 11. The plurality of electrodes 11A are electrically connected to a circuit configured in the first semiconductor element 11. Similarly, a plurality of electrodes 12A are provided on the upper surface (the surface facing the z direction) of the second semiconductor element 12. The plurality of electrodes 12A are electrically connected to a circuit configured in the second semiconductor element 12. A plurality of first electrodes 13A and a plurality of second electrodes 13B are provided on the upper surface (the surface facing the z direction) of the insulating element 13. Each of the plurality of first electrodes 13A and the plurality of second electrodes 13B is electrically connected to either the transmitting inductor or the receiving inductor.

[0023] As shown in FIG. 13, in the insulating element 13, the multiple first electrodes 13A are arranged along the y direction. Similarly, the multiple second electrodes 13B are also arranged along the y direction. The insulating element 13 has a passivation film 13C. The passivation film 13C is made of a material containing, for example, polyimide. The passivation film 13C is located on the upper surface of the insulating element 13. The multiple first electrodes 13A and the multiple second electrodes 13B are each exposed from the passivation film 13C. The passivation film 13C includes a first film 13D and a second film 13E. The first film 13D is located between the multiple first electrodes 13A and the multiple second electrodes 13B in the x direction. The second film 13E is the portion of the passivation film 13C excluding the first film 13D. As shown in FIG. 14, the surface roughness of the first film 13D is greater than the surface roughness of the second film 13E. This makes it possible to increase the creepage distance from each of the plurality of first electrodes 13A to one of the plurality of second electrodes 13B that is located closest to that first electrode 13A, which contributes to improving the withstand voltage of insulating element 13.

[0024] In the semiconductor device A1, the conductive support member 2 constitutes a conductive path between the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 and the wiring substrate of the inverter device. The conductive support member 2 is made of, for example, an alloy containing Cu. The conductive support member 2 is formed from a lead frame 81, which will be described later. The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are mounted on the conductive support member 2. As shown in FIG. 1, the conductive support member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, and a plurality of second terminals 52. As shown in FIG. 2, the first die pad 3 is disposed on one side in the x direction. The second die pad 4 is disposed on the other side in the x direction relative to the first die pad 3 and is spaced apart from the first die pad 3 in the x direction. Therefore, a pad gap 21 is provided between the first die pad 3 and the second die pad 4 in the x direction. In a plan view, the pad gap 21 extends along the y direction.

[0025] As shown in FIGS. 2 and 10 , the first die pad 3 has a first semiconductor element 11 and an insulating element 13 mounted thereon. The first die pad 3 is electrically connected to the first semiconductor element 11 and is one element of the first circuit described above. The first die pad 3 has a substantially rectangular shape in a plan view. The thickness (dimension in the z direction) of the first die pad 3 is, for example, 100 μm or more and 300 μm or less. The first die pad 3 has a first main surface 31, a first back surface 32, a first opposing surface 33, a first end surface 34, and a pair of first side surfaces 35.

[0026] As shown in FIGS. 10 and 11 , the first main surface 31 and the first back surface 32 are spaced apart from each other in the z direction. The first main surface 31 and the first back surface 32 face opposite each other in the z direction. The first main surface 31 and the first back surface 32 are each substantially flat. The distance in the z direction between the first main surface 31 and the first back surface 32 is, for example, not less than 100 μm and not more than 300 μm. The first semiconductor element 11 and the insulating element 13 are joined to the first main surface 31 by a conductive bonding material (solder, metal paste, sintered metal, etc.) not shown.

[0027] The first opposing surface 33, the first end surface 34, and the pair of first side surfaces 35 are connected to the first main surface 31 and the first back surface 32, respectively, and are sandwiched between the first main surface 31 and the first back surface 32 in the z direction. As shown in FIGS. 2 , 10 , and 11 , the first opposing surface 33 faces the second die pad 4 in the x direction. The first opposing surface 33 includes a first main surface-side recess 331, a first back surface-side recess 332, a first main surface-side protrusion 333, a first back surface-side protrusion 334, and a first intermediate protrusion 335.

[0028] 11, the first main surface side recess 331 is a portion that connects the first main surface 31 and the first back surface side recess 332. When viewed along the y direction, the first main surface side recess 331 is recessed inward of the first die pad 3 and is curved.

[0029] As shown in FIG. 11, the first rear surface side recess 332 is a portion that connects to the first rear surface 32 and the first main surface side recess 331. When viewed along the y direction, the first rear surface side recess 332 is recessed inward of the first die pad 3 and curved. This results in the first opposing surface 33 including two recesses (the first main surface side recess 331 and the first rear surface side recess 332) that are aligned in the z direction. As shown in FIG. 11, the dimension t332 of the first rear surface side recess 332 in the z direction is larger than the dimension t331 of the first main surface side recess 331 in the z direction. The ratio (t332 / t331) of the dimension t332 to the dimension t331 is 1 or greater and 2 or less.

[0030] As shown in FIG. 11 , the first main surface protrusion 333 is a portion formed by the first main surface 31 and the first main surface recess 331. When viewed along the y direction, the angle α1 of the first main surface protrusion 333 is, for example, not less than 70° and not more than 80°. As shown in FIG. 11 , the angle α1 is determined by the vertex P11, which is the tip of the first main surface protrusion 333 when viewed along the y direction, and two half rays extending from the vertex P11. When viewed along the y direction, one of the two half rays passes through a point located on the first main surface 31 and that is 20 μm to 40 μm (typically 30 μm) away from the vertex P11 in terms of linear distance. When viewed along the y direction, the other of the two half lines passes through a point located in the first main surface side recess 331 and that is 20 μm to 40 μm (typically 30 μm) away from the vertex P11 in a linear distance. For ease of understanding, in FIG. 11, the vertex P11 is indicated by a black circle, and each point through which the two half lines pass is indicated by an x.

[0031] As shown in FIG. 11 , the first rear surface side protrusion 334 is a portion formed by the first rear surface 32 and the first rear surface side recess 332. When viewed along the y direction, the angle β1 of the first rear surface side protrusion 334 is smaller than the angle α1 described above. The angle β1 is, for example, not less than 60° and not more than 80°. As shown in FIG. 11 , the angle β1 is determined by the vertex P12, which is the tip of the first rear surface side protrusion 334 when viewed along the y direction, and two half rays extending from the vertex P12. When viewed along the y direction, one of the two half rays passes through a point located on the first rear surface 32 and that is 20 μm to 40 μm (typically 30 μm) away from the vertex P12 in terms of a linear distance. When viewed along the y direction, the other of the two half lines passes through a point located in the first rear-surface-side recess 332 and a point that is 20 μm to 40 μm (typically 30 μm) away from the vertex P12 in a linear distance. For ease of understanding, in FIG. 11, the vertex P12 is indicated by a black circle, and each point through which the two half lines pass is indicated by an x.

[0032] As shown in FIG. 11 , the first intermediate protrusion 335 is a portion formed by the first main surface recess 331 and the first back surface recess 332. When viewed along the y direction, the angle γ1 of the first intermediate protrusion 335 is equal to or greater than the sum (α1 + β1) of the aforementioned angles α1 and β1, and is, for example, equal to or greater than 160° and equal to or less than 180°. As shown in FIG. 11 , the angle γ1 is determined by the vertex P13, which is the tip of the first intermediate protrusion 335 when viewed along the y direction, and two half lines extending from the vertex P13. When viewed along the y direction, one of the two half lines passes through a point located on the first main surface recess 331 and a point that is 20 μm to 40 μm (typically 30 μm) away from the vertex P13 in terms of linear distance. When viewed along the y direction, the other of the two half lines passes through a point located in the first rear-surface-side recess 332 and a point that is 20 μm to 40 μm (typically 30 μm) away from the vertex P13 in a linear distance. For ease of understanding, in FIG. 11, the vertex P13 is indicated by a black circle, and each point through which the two half lines pass is indicated by an x.

[0033] 11 , of the first main surface side protrusion 333, the first back surface side protrusion 334, and the first intermediate protrusion 335, the first main surface side protrusion 333 is closest to the second die pad 4 in the x direction. Therefore, the first main surface side protrusion 333 is located closer to the second die pad 4 in the x direction than the first back surface side protrusion 334 and the first intermediate protrusion 335. Furthermore, the first intermediate protrusion 335 is located farther from the second die pad 4 in the x direction than the first main surface side protrusion 333 and the first back surface side protrusion 334. Unlike the example shown in FIG. 11 , the first intermediate protrusion 335 is located farther from the second die pad 4 in the x direction than the first main surface side protrusion 333 and the first back surface side protrusion 334, and is located closer to the second die pad 4 in the x direction than the first back surface side protrusion 334.

[0034] 2, the first end face 34 is located away from the first opposing surface 33 in the x direction. The first end face 34 faces the opposite side of the first opposing surface 33 in the x direction. The first end face 34 is, for example, substantially flat. Note that the first end face 34 may include two recesses aligned in the z direction, similar to the first opposing surface 33.

[0035] As shown in FIG. 2, the pair of first side surfaces 35 are spaced apart from each other in the y direction. The pair of first side surfaces 35 face opposite each other in the y direction. Each of the pair of first side surfaces 35 is, for example, substantially flat. Note that each of the pair of first side surfaces 35 may include two recesses aligned in the z direction, similar to the first opposing surface 33. Each of the pair of first side surfaces 35 extends along the x direction in a plan view.

[0036] The periphery 36 of the first main surface 31 includes a pair of first far corners 361, a pair of first near corners 362, and a first near edge 363, as shown in FIGS.

[0037] As shown in FIG. 2 , the pair of first far corners 361 correspond to the two corners of the first die pad 3 that are located farthest from the second die pad 4 in the x-direction among the four corners in a plan view. In a plan view, each of the pair of first far corners 361 is formed by the first end face 34 and one of the pair of first side faces 35. In a plan view, each of the pair of first far corners 361 is curved, for example, a simple curve. A simple curve is a circular arc with a constant radius of curvature. In a plan view, the curvature radius r11 of each of the pair of first far corners 361 is, for example, 20 μm or more and 80 μm or less. In a plan view, each of the pair of first far corners 361 may be formed at a substantially right angle rather than a curve. Furthermore, the curvature radius r11 can be appropriately changed depending on the size of the first die pad 3 in a plan view.

[0038] As shown in FIG. 2 , the pair of first near corners 362 correspond to the two corners of the first die pad 3 that are closest to the second die pad 4 in the x-direction among the four corners in a plan view. Each of the pair of first near corners 362 includes a pair of first end portions 362A. In a plan view, each of the pair of first near corners 362 is farther from the second die pad 4 in the x-direction as it approaches the first end portion 362A in the y-direction. Therefore, in each of the pair of first near corners 362, the first end portion 362A is located farthest from the second die pad 4 in the x-direction. As shown in FIG. 3 , each of the pair of first near corners 362 is curved, for example, configured as a simple curve. In a plan view, the radius of curvature r12 of each of the pair of first near corners 362 is greater than the radius of curvature r11 of each of the pair of first far corners 361. In plan view, the radius of curvature r12 of each of the pair of first near corners 362 is, for example, not less than 60 μm and not more than 240 μm (preferably 120 μm). The radius of curvature r12 can be changed as appropriate depending on the size of the first die pad 3 in plan view. In the semiconductor device A1, the pair of first near corners 362 are intentionally formed.

[0039] 2 and 3, in plan view, the line segment connecting the pair of first ends 362A is located closer to the second die pad 4 in the x direction than the insulating element 13. Alternatively, in plan view, the line segment may overlap the insulating element 13.

[0040] 2, the first near edge 363 is located closest to the second die pad 4 among the periphery 36 of the first main surface 31. The first near edge 363 extends along the y direction. The first near edge 363 is connected to the pair of first near corners 362 at both ends of the first near edge 363 in the y direction. The first near edge 363 is an element included in the first main surface protrusion 333 described above. The first near edge 363 may have a section recessed inward of the first die pad 3 in the x direction.

[0041] 2 and 3, in plan view, the first die pad 3 includes a portion that protrudes from the insulating element 13 toward the second die pad 4. The dimension of this portion in the x direction is 0.3 to 3 times (preferably 1 time) the dimension of the insulating element 13 in the z direction.

[0042] In the semiconductor device A1, the pair of first far corners 361 and the pair of first near corners 362 are each configured by a simple curve in plan view, but this is not limiting. For example, unlike the examples shown in these figures, they may include a portion configured by a simple curve and a portion configured by a transition curve. A transition curve is a curve whose curvature gradually decreases and smoothly connects a simple curve and a straight line. Alternatively, they may be configured by a compound curve. A compound curve is a curve configured by two or more arcs that curve in the same direction but have different radii, and the arcs are connected by a common tangent or transition curve as appropriate.

[0043] As shown in FIGS. 2 and 10 , the second die pad 4 has a second semiconductor element 12 mounted thereon. The second die pad 4 is electrically connected to the second semiconductor element 12 and is one element of the second circuit described above. The second die pad 4 has a substantially rectangular shape in a plan view. The first die pad 3 and the second die pad 4 are spaced apart and aligned in the x-direction. In the example shown in FIG. 2 , the second die pad 4 is disposed, for example, on the x-direction side of the first die pad 3. The first die pad 3 and the second die pad 4 are galvanically insulated from each other. The thickness (dimension in the z-direction) of the second die pad 4 is, for example, 100 μm or more and 300 μm or less. The second die pad 4 has a second main surface 41, a second back surface 42, a second opposing surface 43, a second end surface 44, and a pair of second side surfaces 45.

[0044] As shown in FIGS. 10 and 11 , the second main surface 41 and the second back surface 42 are spaced apart from each other in the z direction. The second main surface 41 and the second back surface 42 face opposite each other in the z direction. Each of the second main surface 41 and the second back surface 42 is substantially flat. The distance in the z direction between the second main surface 41 and the second back surface 42 is, for example, not less than 100 μm and not more than 300 μm. Furthermore, the thickness of the first die pad 3 and the thickness of the second die pad 4 are each not less than 0.2 times and not more than 1.2 times the length of the pad gap 21. The second semiconductor element 12 is bonded to the second main surface 41 by a conductive bonding material (e.g., solder, metal paste, or sintered metal) not shown.

[0045] The second opposing surface 43, the second end surface 44, and the pair of second side surfaces 45 are connected to the second main surface 41 and the second back surface 42, respectively, and are sandwiched between the second main surface 41 and the second back surface 42 in the z direction. As shown in FIGS. 2 , 10 , and 11 , the second opposing surface 43 faces the first opposing surface 33 of the first die pad 3. The second opposing surface 43 includes a second main surface-side recess 431, a second back surface-side recess 432, a second main surface-side protrusion 433, a second back surface-side protrusion 434, and a second intermediate protrusion 435.

[0046] 11, the second main surface side recess 431 is a portion that connects to the second main surface 41 and the second back surface side recess 432. When viewed along the y direction, the second main surface side recess 431 is recessed inward of the second die pad 4 and is curved.

[0047] 11, the second rear surface-side recess 432 is a portion connecting the second rear surface 42 and the second main surface-side recess 431. When viewed along the y direction, the second rear surface-side recess 432 is recessed inward of the second die pad 4 and curved. This results in the second opposing surface 43 including two recesses (the second main surface-side recess 431 and the second rear surface-side recess 432) aligned in the z direction. As shown in FIG. 11, the dimension t432 of the second rear surface-side recess 432 in the z direction is larger than the dimension t431 of the second main surface-side recess 431 in the z direction. The ratio (t432 / t431) of the dimension t432 to the dimension t431 is 1 or greater and 2 or less.

[0048] As shown in FIG. 11 , the second main surface protrusion 433 is a portion formed by the second main surface 41 and the second main surface recess 431. When viewed along the y direction, the angle α2 of the second main surface protrusion 433 is, for example, not less than 70° and not more than 80°. As shown in FIG. 11 , the angle α2 is determined by the vertex P21, which is the tip of the second main surface protrusion 433 when viewed along the y direction, and two half rays extending from the vertex P21. When viewed along the y direction, one of the two half rays passes through a point located on the second main surface 41 and that is 20 μm to 40 μm (typically 30 μm) away from the vertex P21 in linear distance. When viewed along the y direction, the other of the two half lines passes through a point located in the second principal surface side recess 431 and that is 20 μm to 40 μm (typically 30 μm) away from the vertex P21 in a linear distance. For ease of understanding, in FIG. 11, the vertex P21 is indicated by a black circle, and each point through which the two half lines pass is indicated by an x.

[0049] As shown in FIG. 11 , the second rear surface side protrusion 434 is a portion formed by the second rear surface 42 and the second rear surface side recess 432. When viewed along the y direction, the angle β2 of the second rear surface side protrusion 434 is smaller than the angle α2 described above. The angle β2 is, for example, not less than 60° and not more than 80°. As shown in FIG. 11 , the angle β1 is determined by the vertex P22, which is the tip of the second rear surface side protrusion 434 when viewed along the y direction, and two half lines extending from the vertex P22. When viewed along the y direction, one of the two half lines passes through a point located on the second rear surface 42 and that is 20 μm to 40 μm (typically 30 μm) away from the vertex P22 in terms of a linear distance. When viewed along the y direction, the other of the two half lines passes through a point located in the second rear-surface-side recess 432 and a point that is 20 μm to 40 μm (typically 30 μm) away from the vertex P22 in a linear distance. For ease of understanding, in FIG. 11, the vertex P22 is indicated by a black circle, and each point through which the two half lines pass is indicated by an x.

[0050] As shown in FIG. 11 , the second intermediate protrusion 435 is a portion formed by the second main surface recess 431 and the second back surface recess 432. When viewed along the y direction, the angle γ2 of the second intermediate protrusion 435 is equal to or greater than the sum (α2 + β2) of the aforementioned angles α2 and β2, and is, for example, equal to or greater than 160° and equal to or less than 180°. As shown in FIG. 11 , the angle γ2 is determined by the vertex P23, which is the tip of the second intermediate protrusion 435 when viewed along the y direction, and two half lines extending from the vertex P23. When viewed along the y direction, one of the two half lines passes through a point located on the second main surface recess 431 and a linear distance of 20 μm to 40 μm (typically 30 μm) from the vertex P23. When viewed along the y direction, the other of the two half lines passes through a point located in the second rear-surface-side recess 432 and a point that is 20 μm to 40 μm (typically 30 μm) away from the vertex P23 in a linear distance. For ease of understanding, in FIG. 11, the vertex P23 is indicated by a black circle, and each point through which the two half lines pass is indicated by an x.

[0051] 11 , of the second main surface side protrusion 433, the second back surface side protrusion 434, and the second intermediate protrusion 435, the second main surface side protrusion 433 is located closest to the first die pad 3 in the x direction. Therefore, the second main surface side protrusion 433 is located closer to the first die pad 3 in the x direction than the second back surface side protrusion 434 and the second intermediate protrusion 435. Furthermore, the second intermediate protrusion 435 is located farther from the first die pad 3 in the x direction than the second main surface side protrusion 433 and closer to the first die pad 3 in the x direction than the second back surface side protrusion 434. Unlike the example shown in FIG. 11 , the second intermediate protrusion 435 is located farther from the first die pad 3 in the x direction than both the second main surface side protrusion 433 and the second back surface side protrusion 434.

[0052] As shown in FIG. 11 , when viewed along the y direction, the separation distance d2 between the first back surface 32 and the second back surface 42 is greater than the separation distance d1 between the first main surface 31 and the second main surface 41. Here, the separation distance d1 corresponds to the distance in the x direction between the first main surface-side protrusion 333 of the first opposing surface 33 and the second main surface-side protrusion 433 of the second opposing surface 43. The separation distance d2 corresponds to the distance in the x direction between the first back surface-side protrusion 334 of the first opposing surface 33 and the second back surface-side protrusion 434 of the second opposing surface 43. Therefore, the distance in the x direction between the first main surface-side protrusion 333 and the second main surface-side protrusion 433 is smaller than the distance in the x direction between the first back surface-side protrusion 334 and the second back surface-side protrusion 434. The separation distance d1 is 250 μm or more and 500 μm or less. The separation distance d2 is equal to or greater than 250 μm and equal to or less than 500 μm, and is greater than the separation distance d1.

[0053] 2, the second end surface 44 is spaced apart from the second opposing surface 43 in the x direction. The second end surface 44 faces the side opposite the first die pad 3 in the x direction, and faces the x direction in the semiconductor device A1. The second end surface 44 is, for example, substantially flat. Note that, like the second opposing surface 43, the second end surface 44 may include two recesses aligned in the z direction.

[0054] As shown in FIG. 2, the pair of second side surfaces 45 are spaced apart from each other in the y direction. One of the pair of second side surfaces 45 faces the y direction, and the other of the pair of second side surfaces 45 faces the y direction. Each of the pair of second side surfaces 45 is, for example, substantially flat. Note that each of the pair of second side surfaces 45 may include two recesses aligned in the z direction, similar to the second opposing surface 43. Each of the pair of second side surfaces 45 extends along the x direction in a plan view.

[0055] As shown in FIGS. 2, 3 and 5, the periphery 46 of the second main surface 41 includes a pair of second far corners 461, a pair of second near corners 462, and a second near edge 463.

[0056] As shown in FIG. 2 , the pair of second far corners 461 correspond to the two corners located farthest from the first die pad 3 in the x-direction among the four corners of the second die pad 4 in a plan view. In a plan view, each of the pair of second far corners 461 is formed by the second end face 44 and one of the pair of second side faces 45. In a plan view, each of the pair of second far corners 461 is curved, for example, a simple curve. A simple curve is a circular arc with a constant radius of curvature. The curvature radius r21 of each of the pair of second far corners 461 is, for example, 20 μm or more and 80 μm or less. In a plan view, each of the pair of second far corners 461 may be formed at a substantially right angle rather than a curve. Furthermore, the curvature radius r21 can be appropriately changed depending on the size of the second die pad 4 in a plan view.

[0057] As shown in FIG. 2, the pair of second near corners 462 correspond to the two corners located closest to the first die pad 3 in the x-direction among the four corners of the second die pad 4 in a plan view. Each of the pair of second near corners 462 includes a pair of second end portions 462A. In a plan view, each of the pair of second near corners 462 is farther from the first die pad 3 in the x-direction as it approaches the second end portion 462A in the y-direction. Therefore, in each of the pair of second near corners 462, the second end portion 462A is located farthest from the first die pad 3 in the x-direction. As shown in FIG. 3, each of the pair of second near corners 462 is curved, for example, configured as a simple curve. In a plan view, the radius of curvature r22 of each of the pair of second near corners 462 is greater than the radius of curvature r21 of each of the pair of second far corners 461. The radius of curvature r22 of each of the pair of second near corners 462 is, for example, not less than 60 μm and not more than 240 μm (preferably 120 μm). The radius of curvature r22 can be changed as appropriate depending on the size of the second die pad 4 in a plan view. In the semiconductor device A1, the pair of second near corners 462 are intentionally formed.

[0058] 2 and 3, in plan view, the line segment connecting the pair of second end portions 462A overlaps with the second semiconductor element 12 in the x direction. Alternatively, in plan view, the line segment may be located closer to the first die pad 3 than the second semiconductor element 12.

[0059] As shown in FIG. 2 , the second near edge 463 is located closest to the first die pad 3 among the periphery 46 of the second main surface 41. The second near edge 463 extends along the y direction. In a plan view, the second near edge 463 is substantially parallel to the first near edge 363. The second near edge 463 is connected to a pair of second near corners 462 at both ends of the second near edge 463 in the y direction. The second near edge 463 is an element included in the second main surface side protrusion 433 described above. The second near edge 463 may have a section recessed inward of the second die pad 4 in the x direction.

[0060] 2, 3, and 5, the pair of second far corners 461 and the pair of second near corners 462 are each configured with a simple curve, but are not limited to this. For example, unlike the examples shown in these figures, they may include a portion configured with a simple curve and a portion configured with a transition curve. Alternatively, they may be configured with a compound curve.

[0061] The first terminals 51 are components that are bonded to a wiring board such as an inverter device to form a conductive path between the semiconductor device A1 and the wiring board. At least one of the first terminals 51 is electrically connected to the first semiconductor element 11. The first terminals are elements of the first circuit described above. As shown in FIGS. 1, 2, and 8, the first terminals 51 are spaced apart from one another and arranged along the y direction. The first terminals 51 are exposed from the sealing resin 7 (a first side surface 73 described below) so as to extend in the x direction. Each of the first terminals 51 is located closer to the x direction than the second die pad 4. Each of the first terminals 51 is located closer to the x direction than the first near edge 363 in a plan view. The first terminals 51 include a plurality of first intermediate terminals 511, a pair of first side terminals 512, and a pair of first support terminals 513.

[0062] 2 and 8, the multiple first intermediate terminals 511 are arranged between a pair of first side terminals 512. As shown in FIG. 2, each of the multiple first intermediate terminals 511 includes a lead portion 511A and a pad portion 511B.

[0063] The lead portion 511A is a rectangular portion extending along the x direction. The lead portion 511A has a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIGS. 6 and 7 , the portion of the lead portion 511A exposed from the sealing resin 7 is bent into a gull-wing shape. The portion of the lead portion 511A exposed from the sealing resin 7 may be plated. The plating layer formed by the plating process is made of an alloy containing Sn, such as solder, and covers the portion exposed from the sealing resin 7. When the semiconductor device A1 is surface-mounted on a wiring board of an inverter device by soldering, the plating layer improves solder adhesion to the exposed portion and prevents erosion of the exposed portion due to soldering.

[0064] The pad portion 511B is connected to the lead portion 511A and is a rectangular portion that is wider in the y direction than the lead portion 511A. The upper surface (the surface facing the z direction) of the pad portion 511B may be plated. The plating layer formed by the plating process is made of a metal containing Ag, for example, and covers the upper surface of the pad portion 511B. The plating layer increases the bonding strength of the first wire 61 described below, while protecting the lead frame 81 (described below) from impacts during wire bonding of the first wire 61. The entire surface of the pad portion 511B is covered with sealing resin 7. The pad portion 511B is approximately flat.

[0065] The pair of first side terminals 512 are arranged in the y direction on both sides of the plurality of first intermediate terminals 511. Each of the pair of first side terminals 512 includes a lead portion 512A and a pad portion 512B, as shown in FIG.

[0066] The lead portion 512A is a rectangular portion extending along the x-direction. The lead portion 512A has a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIGS. 6 and 7, the portion of the lead portion 512A exposed from the sealing resin 7 is bent into a gull-wing shape. Similarly to the lead portion 511A, the portion of the lead portion 521A exposed from the sealing resin 7 may be covered with a plating layer (for example, an alloy containing Sn, such as solder).

[0067] The pad portion 512B is connected to the lead portion 512A and is wider in the y direction than the lead portion 512A. The upper surface of the pad portion 512B (the surface facing the z direction) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 511B. The entire surface of the pad portion 512B is covered with the sealing resin 7. The pad portion 512B is approximately flat.

[0068] 2 and 8, the pair of first support terminals 513 are spaced apart in the y direction. The pair of first support terminals 513 are connected to both ends of the first die pad 3 in the y direction and support the first die pad 3. As shown in FIGS. 2 and 8, the pair of first support terminals 513 are arranged, for example, on both sides of the pair of first side terminals 512 in the y direction. Each of the pair of first support terminals 513 includes a lead portion 513A and a pad portion 513B as shown in FIG.

[0069] The lead portion 513A is a rectangular portion extending along the x direction. The lead portion 513A has a portion exposed from the sealing resin 7 and a portion covered with the sealing resin 7. As shown in FIGS. 6 and 7, the portion of the lead portion 513A exposed from the sealing resin 7 is bent into a gull-wing shape. Similarly to the lead portion 511A, the portion of the lead portion 513A exposed from the sealing resin 7 may be covered with a plating layer (for example, an alloy containing Sn, such as solder). The length of the portion of the lead portion 513A covered with the sealing resin 7 is longer than the length of the portions of the lead portions 511A and 512A covered with the sealing resin 7.

[0070] The pad portion 513B is a portion that is connected to the lead portion 513A and extends in the y direction. As shown in FIG. 2, an end of the pad portion 513B is connected to the first die pad 3. The upper surface of the pad portion 513B (the surface facing the z direction) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 511B. The entire surface of the pad portion 513B is covered with the sealing resin 7. The pad portion 513B is approximately flat.

[0071] The second terminals 52, like the first terminals 51, are bonded to a wiring board of an inverter device or the like, thereby forming a conductive path between the semiconductor device A1 and the wiring board. At least one of the second terminals 52 is electrically connected to the second semiconductor element 12. The second terminals are elements of the second circuit described above. As shown in FIGS. 1, 2, and 9, the second terminals 52 are spaced apart from one another and arranged along the y direction. The second terminals 52 are exposed from the sealing resin 7 (second side surface 74 described below) so as to extend in the x direction. Each of the second terminals 52 is located closer to the x direction than the first die pad 3 in the x direction. The second terminals 52 include second intermediate terminals 521, a pair of second side terminals 522, and a pair of second support terminals 523.

[0072] 2 and 9, the second intermediate terminals 521 are arranged between a pair of second side terminals 522. As shown in FIG. 2, each of the second intermediate terminals 521 includes a lead portion 521A and a pad portion 521B.

[0073] The lead portion 521A is a rectangular portion extending along the x-direction. The lead portion 521A has a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIGS. 6 and 7, the portion of the lead portion 521A exposed from the sealing resin 7 is bent into a gull-wing shape. Furthermore, a plating layer (for example, an alloy containing Sn, such as solder) may be formed on the portion of the lead portion 521A exposed from the sealing resin 7, similar to the lead portion 511A.

[0074] The pad portion 521B is connected to the lead portion 521A and is wider in the y direction than the lead portion 521A. The upper surface of the pad portion 521B (the surface facing the z direction) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 511B. The entire surface of the pad portion 521B is covered with the sealing resin 7. The pad portion 521B is approximately flat.

[0075] The pair of second side terminals 522 are arranged in the y direction on both sides of the plurality of second intermediate terminals 521. Each of the pair of second side terminals 522 includes a lead portion 522A and a pad portion 522B, as shown in FIG.

[0076] The lead portion 522A is a rectangular portion extending along the x direction. The lead portion 522A has a portion exposed from the sealing resin 7 and a portion covered with the sealing resin 7. As shown in FIGS. 6 and 7, the portion of the lead portion 522A exposed from the sealing resin 7 is bent into a gull-wing shape. Similarly to the lead portion 511A, the portion of the lead portion 522A exposed from the sealing resin 7 may be covered with a plating layer (for example, an alloy containing Sn, such as solder). The length of the portion of the lead portion 522A covered with the sealing resin 7 is longer than the length of the portion of the lead portion 521A covered with the sealing resin 7.

[0077] The pad portion 522B is connected to the lead portion 522A and is wider in the y direction than the lead portion 522A. The upper surface of the pad portion 522B (the surface facing the z direction) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 511B. The entire surface of the pad portion 522B is covered with the sealing resin 7. The pad portion 522B is approximately flat.

[0078] As shown in FIGS. 2 and 9, the pair of second support terminals 523 are spaced apart in the y direction. The second support terminals 523 are connected to both ends of the second die pad 4 in the y direction and support the second die pad 4. As shown in FIGS. 2 and 9, a plurality of second intermediate terminals 521 are arranged inside the pair of second support terminals 523 in the y direction. Furthermore, a pair of second side terminals 522 are arranged outside the pair of second support terminals 523 in the y direction. As shown in FIG. 2, each of the pair of second support terminals 523 includes a lead portion 523A, a pad portion 523B, and a connecting portion 523C.

[0079] The lead portion 523A is a rectangular portion extending along the x-direction. The lead portion 523A has a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIGS. 6 and 7, the portion of the lead portion 523A exposed from the sealing resin 7 is bent into a gull-wing shape. Similarly to the lead portion 511A, the portion of the lead portion 523A exposed from the sealing resin 7 may be covered with a plating layer (for example, an alloy containing Sn, such as solder).

[0080] The pad portion 523B is connected to the lead portion 523A and is wider than the lead portion 523A in the y direction. The pad portion 523B extends in the x direction. The upper surface of the pad portion 523B (the surface facing the z direction) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 511B. The entire surface of the pad portion 523B is covered with the sealing resin 7. The pad portion 523B is approximately flat.

[0081] The connecting portion 523C is a portion that is connected to the pad portion 523B and extends in the y direction. As shown in FIG. 2, an end of the connecting portion 523C is connected to the second die pad 4. The upper surface of the connecting portion 523C (the surface facing the z direction) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 511B. The connecting portion 523C is entirely covered with sealing resin 7.

[0082] 2 , in a plan view, the conductive support member 2 has the first die pad 3 and the second die pad 4 closest to each other between the portion constituting the first circuit and the portion constituting the second circuit. That is, the distance between the closest portions of the first die pad 3 and the second die pad 4 is smaller than the distance between the closest portions of the multiple first terminals 51 and the second die pad 4, and is also smaller than the distance between the closest portions of the multiple second terminals 52 and the first die pad 3. In the semiconductor device A1, the first near edge 363 and the second near edge 463 are located between the two closest portions of the first die pad 3 and the second die pad 4. Therefore, the electric field strength between the first near edge 363 and the second near edge 463 is strongest.

[0083] 2, the plurality of first wires 61, the plurality of second wires 62, the plurality of third wires 63, and the plurality of fourth wires 64, together with the conductive support member 2, form a conductive path that enables the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 to perform predetermined functions. The material of each of the plurality of first wires 61, the plurality of second wires 62, the plurality of third wires 63, and the plurality of fourth wires 64 is a metal containing, for example, any one of Au, Cu, and Al.

[0084] As shown in FIGS. 2 and 10 , the multiple first wires 61 form a conductive path between the first semiconductor element 11 and the multiple first terminals 51. The multiple first wires 61 electrically connect the first semiconductor element 11 to at least one of the multiple first terminals 51. The multiple first wires 61 are elements of the first circuit described above. As shown in FIG. 2 , each of the multiple first wires 61 is bonded to one of the multiple electrodes 11A of the first semiconductor element 11 and one of the pad portions 511B of the multiple first intermediate terminals 511, the pad portions 512B of the pair of first side terminals 512, and the pad portions 513B of the pair of first support terminals 513. Furthermore, the angle formed by at least one of the multiple first wires 61 with respect to the x-direction is larger than the angle formed by the first wire 61 with respect to the y-direction. As shown in FIG. 2 , the multiple first wires 61 include a specific first wire 61A. The specific first wire 61A is located closest to a first gate mark 791, which will be described later. The angle that the specific first wire 61A makes with respect to the x direction is larger than the angle that the specific first wire 61A makes with respect to the y direction. Of the lengths of the multiple first wires 61, the length of the specific first wire 61A is the longest.

[0085] 2, in the semiconductor device A1, two first wires 61 are bonded to a pad portion 511B of one of the plurality of first intermediate terminals 511 and a pad portion 513B of each of the pair of first support terminals 513. The two first wires 61 are bonded to the pad portion 511B and the pad portion 513B, respectively, in an overlapping state. This further strengthens the bond between the two first wires 61 and the pad portion 511B and the pad portion 513B, respectively. This contributes to improving the reliability of the semiconductor device A1.

[0086] As shown in FIGS. 2 and 10 , the multiple second wires 62 form a conductive path between the second semiconductor element 12 and the multiple second terminals 52. The multiple second wires 62 electrically connect the second semiconductor element 12 to at least one of the multiple second terminals 52. The multiple second wires 62 are elements of the second circuit described above. As shown in FIG. 2 , each of the multiple second wires 62 is bonded to one of the multiple electrodes 12A of the second semiconductor element 12 and one of the pad portions 521B of the multiple second intermediate terminals 521, the pad portions 522B of the pair of second side terminals 522, and the pad portions 523B of the pair of second support terminals 523. Furthermore, the angle formed by at least one of the multiple second wires 62 with respect to the x-direction is larger than the angle formed by the second wire 62 with respect to the y-direction. As shown in FIG. 2 , the multiple second wires 62 include a specific second wire 62A. The specific second wire 62A is located closest to a first gate mark 791, which will be described later. The angle that the specific second wire 62A makes with respect to the x direction is larger than the angle that the specific second wire 62A makes with respect to the y direction. Of the lengths of each of the multiple second wires 62, the length of the specific second wire 62A is the longest.

[0087] 2, in the semiconductor device A1, two second wires 62 are bonded to a pad portion 521B of one of the plurality of second intermediate terminals 521, a pad portion 522B of one of the pair of second side terminals 522, and a pad portion 523B of each of the pair of second support terminals 523. The two second wires 62 are bonded to the pad portion 521B, the pad portion 522B, and the pad portion 523B, respectively, in an overlapping state. This further strengthens the bond between the two second wires 62 and the pad portion 521B, the pad portion 522B, and the pad portion 523B, respectively. This contributes to improving the reliability of the semiconductor device A1.

[0088] As shown in FIGS. 2 and 10, the multiple third wires 63 form a conductive path between the first semiconductor element 11 and the insulating element 13. The multiple third wires 63 provide mutual conduction between the first semiconductor element 11 and the insulating element 13. The multiple third wires 63 are one element of the first circuit described above. Each of the multiple third wires 63 is joined to one of the electrodes 11A of the first semiconductor element 11 and one of the first electrodes 13A of the insulating element 13. The multiple third wires 63 are arranged along the y direction.

[0089] As shown in FIGS. 2 and 10 , the multiple fourth wires 64 form a conductive path between the second semiconductor element 12 and the insulating element 13. The multiple fourth wires 64 electrically connect the second semiconductor element 12 and the insulating element 13 to each other. The multiple fourth wires 64 are elements of the second circuit described above. Each of the multiple fourth wires 64 is joined to one of the electrodes 12A of the second semiconductor element 12 and one of the second electrodes 13B of the insulating element 13. The multiple fourth wires 64 are arranged along the y direction. In the semiconductor device A1, the multiple fourth wires 64 straddle the pad gap 21.

[0090] As shown in FIG. 1 , the sealing resin 7 covers the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first die pad 3, the second die pad 4, and portions of the first terminals 51 and the second terminals 52. As shown in FIG. 10 , the sealing resin 7 also covers the first wires 61, the second wires 62, the third wires 63, and the fourth wires 64. The sealing resin 7 has electrical insulation properties. The sealing resin 7 insulates the first die pad 3 and the second die pad 4 from each other. The sealing resin 7 is made of a material containing, for example, black epoxy resin. In a plan view, the sealing resin 7 is rectangular.

[0091] As shown in FIGS. 1, 6, 7, and 10, the sealing resin 7 includes a first resin portion 7A and a second resin portion 7B. The first resin portion 7A penetrates the pad gap 21 in the z direction and has the same dimension in the x direction as the pad gap 21. The first resin portion 7A extends in the y direction. The second resin portions 7B are located on both sides of the first resin portion 7A in the x direction and are connected to the first resin portion 7A. The second resin portions 7B are located apart from each other in the x direction. The average void volume per unit volume of the first resin portion 7A is smaller than the average void volume per unit volume of the second resin portion 7B.

[0092] As shown in FIGS. 6 to 9, the sealing resin 7 has a top surface 71, a bottom surface 72, a first side surface 73, a second side surface 74, a third side surface 75, and a fourth side surface .

[0093] 6 to 9, the top surface 71 and the bottom surface 72 are spaced apart from each other in the z direction. The top surface 71 and the bottom surface 72 face opposite each other in the z direction. Each of the top surface 71 and the bottom surface 72 is substantially flat.

[0094] As shown in Figures 6 to 9, the first side surface 73, the second side surface 74, the third side surface 75, and the fourth side surface 76 are each connected to the top surface 71 and the bottom surface 72 and are sandwiched between the top surface 71 and the bottom surface 72 in the z direction. As shown in Figures 1, 6, and 7, the first side surface 73 is located on one side in the x direction, the second side surface 74 is located on the other side in the x direction, and the third side surface 75 and the fourth side surface 76 are located apart from each other in the y direction and are connected to the first side surface 73 and the second side surface 74. A portion of each of the multiple first terminals 51 protrudes from the first side surface 73. A portion of each of the multiple second terminals 52 protrudes from the second side surface 74.

[0095] As shown in FIGS. 6 to 8 , the first side surface 73 includes a first region 731, a second region 732, and a third region 733. One end of the first region 731 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the third region 733. The first region 731 is inclined with respect to the top surface 71. One end of the second region 732 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the third region 733. The second region 732 is inclined with respect to the bottom surface 72. One end of the third region 733 in the z direction is connected to the first region 731, and the other end in the z direction is connected to the second region 732. The third region 733 extends in both the z direction and the y direction. In a plan view, the third region 733 is located outward from the top surface 71 and the bottom surface 72. A portion of each of the multiple first terminals 51 is exposed from the third region 733.

[0096] As shown in FIGS. 6, 7, and 9, the second side surface 74 includes a fourth region 741, a fifth region 742, and a sixth region 743. One end of the fourth region 741 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the sixth region 743. The fourth region 741 is inclined with respect to the top surface 71. One end of the fifth region 742 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the sixth region 743. The fifth region 742 is inclined with respect to the bottom surface 72. One end of the sixth region 743 in the z direction is connected to the fourth region 741, and the other end in the z direction is connected to the fifth region 742. The sixth region 743 extends in both the z direction and the y direction. In a plan view, the sixth region 743 is located outward from the top surface 71 and the bottom surface 72. From the sixth region 743, a portion of each of the plurality of second terminals 52 is exposed.

[0097] As shown in FIGS. 7 to 9 , the third side surface 75 includes a seventh region 751, an eighth region 752, and a ninth region 753. One end of the seventh region 751 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the ninth region 753. The seventh region 751 is inclined with respect to the top surface 71. One end of the eighth region 752 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the ninth region 753. The eighth region 752 is inclined with respect to the bottom surface 72. One end of the ninth region 753 in the z direction is connected to the seventh region 751, and the other end in the z direction is connected to the eighth region 752. The ninth region 753 extends in both the z direction and the y direction. In a plan view, the ninth region 753 is located outward from the top surface 71 and the bottom surface 72.

[0098] As shown in FIG. 7 , a first gate mark 791 is formed on the third side surface 75. The first gate mark 791 has a rougher surface than other regions of the third side surface 75 excluding the first gate mark 791. The first gate mark 791 appears when the sealing resin 7 is cut at the first gate 891 during the process of forming the sealing resin 7 in the manufacturing process of the semiconductor device A1, which will be described later. When viewed along the y direction, the first gate mark 791 overlaps the pad gap 21. When viewed further along the y direction, the first gate mark 791 includes a region located on the opposite side of the first semiconductor element 11 with respect to the first die pad 3 in the z direction. In the semiconductor device A1, the first gate mark 791 includes a region located in the eighth region 752 and a region located in the ninth region 753. The first gate mark 791 is located at the center of the third side surface 75 in the x direction.

[0099] As shown in FIGS. 6 , 8 , and 9 , the fourth side surface 76 includes a tenth region 761, an eleventh region 762, and a twelfth region 763. The tenth region 761 has one end in the z direction connected to the top surface 71 and the other end in the z direction connected to the twelfth region 763. The tenth region 761 is inclined with respect to the top surface 71. The eleventh region 762 has one end in the z direction connected to the bottom surface 72 and the other end in the z direction connected to the twelfth region 763. The eleventh region 762 is inclined with respect to the bottom surface 72. The twelfth region 763 has one end in the z direction connected to the tenth region 761 and the other end in the z direction connected to the eleventh region 762. The twelfth region 763 extends in both the z direction and the y direction. In a plan view, the twelfth region 763 is located outward from the top surface 71 and the bottom surface 72.

[0100] As shown in FIG. 6 , a second gate mark 792 is formed on the fourth side surface 76. The second gate mark 792 has a rougher surface than the other regions of the fourth side surface 76 excluding the second gate mark 792. The second gate mark 792 appears when the sealing resin 7 is cut at the second gate 892 during the process of forming the sealing resin 7 in the manufacturing process of the semiconductor device A1, which will be described later. When viewed along the y direction, the second gate 892 overlaps the pad gap 21. When viewed further along the y direction, the second gate 892 includes a region located on the opposite side of the first semiconductor element 11 with respect to the first die pad 3 in the z direction. In the semiconductor device A1, the second gate mark 792 includes a region located in the 11th region 762 and a region located in the 12th region 763. The second gate mark 792 is located at the center of the fourth side surface 76 in the x direction.

[0101] Next, the circuit configuration of the semiconductor device A1 will be described with reference to FIGS.

[0102] 15, the circuit configured in first semiconductor element 11 includes a first transmitter 111, a second transmitter 112, a third receiver 113, a fourth receiver 114, a logic unit 115, a first low voltage lockout unit 116, an external error detector 117, and transistors Na and Nb. Each of transistors Na and Nb is an n-channel MOSFET.

[0103] 15, the circuit configured in second semiconductor element 12 includes first receiving unit 121, second receiving unit 122, third transmitting unit 123, fourth transmitting unit 124, logic unit 125, driver unit 126, second undervoltage lockout unit 27, overcurrent detection unit 28, OCP (Over Current Protection) timer 29, transistors P1 and P2, transistors N1, N2, and N3, and SR flip-flop FF. Each of transistors P1 and P2 is a p-channel MOSFET. Each of transistors N1, N2, and N3 is an n-channel MOSFET.

[0104] As shown in FIG. 15, the circuit formed in the isolation element 13 includes a first transformer 131, a second transformer 132, a first transformer 131, and a fourth transformer .

[0105] The first transmitting unit 111 is a means for transmitting the switch control signal S1 input from the logic unit 115 to the first receiving unit 121 via the first transformer 131. The second transmitting unit 112 is a means for transmitting the switch control signal S2 input from the logic unit 115 to the second receiving unit 122 via the second transformer 132. The third receiving unit 113 is a means for receiving the watchdog signal S3 input from the third transmitting unit 123 via the third transformer 133 and transmitting it to the logic unit 115. The fourth receiving unit 114 is a means for receiving the driver abnormality signal S4 input from the fourth transmitting unit 124 via the fourth transformer 134 and transmitting it to the logic unit 115.

[0106] The logic unit 115 is a means for exchanging various signals (IN, RST, FLT, OCPOUT) with the ECU 90, and also for exchanging various signals (S1 to S4) with the second semiconductor element 12 using the first transmitting unit 111, the second transmitting unit 112, the third receiving unit 113 and the fourth receiving unit 114.

[0107] The logic unit 115 generates switch control signals S1 and S2 so as to set the output signal OUT to a high level when the input signal IN is at a high level, and conversely generates switch control signals S1 and S2 so as to set the output signal OUT to a low level when the input signal IN is at a low level. More specifically, the logic unit 115 detects a positive edge (a rising edge from a low level to a high level) of the input signal IN to generate a pulse in the switch control signal S1, and detects a negative edge (a falling edge from a high level to a low level) of the input signal IN to generate a pulse in the switch control signal S2.

[0108] When the reset signal RST is at a low level, the logic unit 115 generates the switch control signals S1 and S2 to disable the generation of the output signal OUT, i.e., to fix the output signal OUT at a low level, and conversely, when the reset signal RST is at a high level, the logic unit 115 generates the switch control signals S1 and S2 to enable the generation of the output signal OUT, i.e., to set the output signal OUT to a logic level corresponding to the input signal IN. Note that when the reset signal RST is maintained at a low level for a predetermined time (for example, 500 ns), the logic unit 115 generates the switch control signals S1 and S2 to resume the protection operation by the overcurrent detection unit 128.

[0109] When the semiconductor device A1 is normal, the logic unit 115 turns off the transistor Na and sets the first status signal FLT to an open state (pull-up state by the resistor R1). When an abnormality occurs in the semiconductor device A1 (when a low-voltage abnormality on the first semiconductor element 11 side, a transformer transmission abnormality of the switch control signals S1 and S2, or an ERRIN signal abnormality is detected), the logic unit 115 turns on the transistor Na and sets the first status signal FLT to a low level. With this configuration, the ECU 90 can grasp the status of the semiconductor device A1 by monitoring the first status signal FLT. The low-voltage abnormality on the first semiconductor element 11 side can be determined based on the detection result of the first low-voltage lockout unit 116. The transformer transmission abnormality of the switch control signals S1 and S2 can be determined based on the comparison result between the input signal IN (switch control signals S1 and S2) and the watchdog signal S3. The ERRIN signal abnormality can be determined based on the output result of the external error detection unit 117.

[0110] When the semiconductor device A1 is normal, the logic unit 115 turns off the transistor Nb and sets the second state signal OCPOUT to an open state (a pulled-up state by the resistor R2). When an abnormality occurs in the semiconductor device A1 (when a low voltage abnormality on the second semiconductor element 12 side or an overcurrent of the motor drive current flowing through the high-side switch SWH is detected), the logic unit 115 turns on the transistor Nb and sets the second state signal OCPOUT to a low level. With this configuration, the ECU 90 can grasp the state of the semiconductor device A1 by monitoring the second state signal OCPOUT. Note that a low voltage abnormality on the second semiconductor element 12 side or an overcurrent of the motor drive current flowing through the high-side switch SWH can be determined based on the driver abnormality signal S4.

[0111] The first low voltage lockout unit 116 is means for monitoring whether the first power supply voltage VCC1 is in a low voltage state and transmitting the monitoring result to the logic unit 115.

[0112] The external error detection unit 117 is a means for comparing the voltage input to the ERRIN terminal from the connection node between the resistors R3 and R4 (a divided voltage obtained by resistively dividing the analog voltage to be monitored) with a predetermined threshold voltage, and transmitting the comparison result to the logic unit 115.

[0113] The first receiving unit 121 is a means for receiving a switch control signal S1 input from the first transmitting unit 111 via the first transformer 131 and transmitting it to the set input terminal (S) of the SR flip-flop FF. The second receiving unit 122 is a means for receiving a switch control signal S2 input from the second transmitting unit 112 via the second transformer 132 and transmitting it to the reset input terminal (R) of the SR flip-flop FF. The third transmitting unit 123 is a means for transmitting a watchdog signal S3 input from the logic unit 125 to the third receiving unit 113 via the third transformer 133. The fourth transmitting unit 124 is a means for transmitting a driver abnormality signal S4 input from the logic unit 25 to the second receiving unit 14 via the fourth transformer 134.

[0114] The SR flip-flop FF sets its output signal to a high level when triggered by a pulse edge of the switch control signal S1 input to its set input terminal (S), and resets its output signal to a low level when triggered by a pulse edge of the switch control signal S2 input to its reset input terminal (R). That is, the output signal is the same as the input signal IN input from the ECU 90 to the logic unit 115. The output signal is sent from the output terminal (Q) of the SR flip-flop FF to the logic unit 125.

[0115] The logic unit 125 generates a drive signal for the driver unit 126 based on the output signal of the SR flip-flop FF (the same signal as the input signal IN).

[0116] When logic unit 125 determines that an undervoltage abnormality or an overcurrent has occurred based on the detection results of second undervoltage lockout unit 127 and overcurrent detection unit 128, it transmits this information to driver unit 126 using an abnormality detection signal, and also transmits this information to logic unit 115 using driver abnormality signal S4. With this configuration, even if an abnormality occurs in second semiconductor element 12, driver unit 126 can quickly perform a protection operation, and logic unit 115 can perform an abnormality notification operation to ECU 90 (transition of second status signal OCPOUT to low level). Note that logic unit 125 has a function of automatically recovering from the overcurrent protection operation when a predetermined time has elapsed after the overcurrent protection operation.

[0117] The logic unit 125 outputs the output signal of the SR flip-flop FF as is as the watchdog signal S3 to the third transmission unit 123. In this manner, if the configuration is such that the watchdog signal S3 is returned from the second semiconductor element 12 to the first semiconductor element 11, the logic unit 115 can determine whether or not there is a transformer transmission abnormality by comparing the input signal IN input to the first semiconductor element 11 with the watchdog signal S3 returned in response from the second semiconductor element 12.

[0118] The driver unit 126 controls the on / off of the transistors P1 and N1 based on a drive signal input from the logic unit 125, and outputs an output signal OUT from the connection node between the transistors P1 and N1. The output signal OUT is input to the high-side switch SWH via a drive circuit consisting of transistors Q1 and Q2. The drive circuit adjusts the rise / fall time (slew rate) of the output signal OUT so that the output signal OUT has the driving capability of the high-side switch SWH. When the output signal OUT is at a high level, the high-side switch SWH is turned on, and conversely, when the output signal OUT is at a low level, the high-side switch SWH is turned off.

[0119] The driver unit 126 has a function (active mirror clamp function) of turning on the transistor N2 so as to absorb charge (mirror current) from the gate of the high-side switch SWH via the CLAMP terminal when the voltage level (GND2 reference) of the output signal OUT becomes low. With this configuration, when turning off the high-side switch SWH, it is possible to quickly drop the gate potential of the high-side switch SWH to low via the transistor N2, regardless of the slew rate set by the above-mentioned drive circuit.

[0120] The driver unit 126 has a function (short-circuit clamp function) of turning on the transistor P2 so as to clamp the gate of the high-side switch SWH to the second power supply voltage VCC2 via the CLAMP terminal when the voltage level of the output signal OUT (based on GND2) becomes high. With this configuration, when the high-side switch SWH is turned on, the gate potential of the high-side switch SWH does not rise to a potential higher than the second power supply voltage VCC2.

[0121] When the driver unit 126 determines that a protective operation is necessary based on the abnormality detection signal input from the logic unit 125, it turns off transistors P1 and P2 and transistors N1 and N2, while turning on transistor N3 (a slow-off function). This switch control allows charge to be drawn from the gate of the high-side switch SWH via resistor R5 more slowly than during normal operation during protective operation. This configuration prevents momentary interruptions in the motor current during protective operation, thereby suppressing surges caused by the back electromotive force of the motor coil. The fall time during protective operation can be adjusted arbitrarily by appropriately selecting the resistance value of resistor R5.

[0122] The second low voltage lockout unit 127 is a means for monitoring whether the second power supply voltage VCC2 is in a low voltage state and transmitting the monitoring result to the logic unit 125.

[0123] The overcurrent detection unit 128 compares the voltage input to the OCP / DESATIN terminal from the connection node between resistors R7 and R8 (a divided voltage obtained by resistively dividing the anode voltage of diode D1) with a predetermined threshold voltage and transmits the comparison result to the logic unit 125. Note that the larger the motor drive current flowing through the high-side switch SWH, the larger the collector-emitter voltage of the insulated gate bipolar transistor used as the high-side switch SWH. Therefore, the larger the motor drive current flowing through the high-side switch SWH, the higher the anode voltage of diode D1, and ultimately the higher the voltage input to the OCP / DESATIN terminal. Therefore, when the voltage input to OCP / DESATIN (based on GND2) reaches a predetermined threshold (e.g., 0.5 V), the overcurrent detection unit 128 determines that the motor drive current flowing through the high-side switch SWH is in an overcurrent state.

[0124] In this configuration example, a configuration has been described that employs a method (voltage detection method) for detecting the motor drive current by detecting the collector-emitter voltage of the insulated gate bipolar transistor used as the high-side switch SWH. However, the method for detecting the motor drive current is not limited to this. For example, a method (current detection method) may be employed in which the motor drive current flowing through the high-side switch SWH (or a mirror current that behaves in the same way) is passed through a sense resistor to generate a voltage signal, which is then input to the OCP / DESATIN terminal.

[0125] The OCP timer 129 is a means for counting the time that has elapsed since the overcurrent protection operation.

[0126] The first transformer 131 is a DC isolation element for transmitting a switch control signal S1 from the first semiconductor element 11 to the second semiconductor element 12. The second transformer 132 is a DC isolation element for transmitting a switch control signal S2 from the first semiconductor element 11 to the second semiconductor element 12. The third transformer 133 is a DC isolation element for transmitting a watchdog signal S3 from the second semiconductor element 12 to the first semiconductor element 11. The fourth transformer 134 is a DC isolation element for transmitting a driver abnormality signal S4 from the second semiconductor element 12 to the first semiconductor element 11.

[0127] In this way, not only the switch control signals S1 and S2 but also the watchdog signal S3 and the driver abnormality signal S4 are exchanged between the first semiconductor element 11 and the second semiconductor element 12. This configuration makes it possible to appropriately realize not only the on / off control of the high-side switch SWH but also various protection functions.

[0128] As shown in FIG. 16, the terminal types of the multiple first terminals 51 are GND1, VCC1, IN, RST, FLT, OCPOUT, ERRIN, and NC. GND1 is a GND terminal. In the semiconductor device A1, each of a pair of first support terminals 513 among the multiple first terminals 51 is GND1. Therefore, GND1 is electrically connected to both the first semiconductor element 11 and the first die pad 3. VCC1 is a power supply terminal (e.g., 5 V). IN is a control input terminal. RST is a reset input terminal. FLT is an output terminal for a first status signal (an abnormal status detection signal in the first semiconductor element 11). OCPOUT is an output terminal for a second status signal (an abnormal status detection signal in the second semiconductor element 12). ERRIN is an error detection terminal. NC is a non-connection terminal, or a so-called dummy terminal. NC is not electrically connected to the first semiconductor element 11.

[0129] As shown in FIG. 16, the multiple second terminals 52 are classified into the following types: GND2, VCC2, VEE2, OUT, PROOUT, CLAMP, OCP / DESATIN, and NC. GND2 is a GND terminal. As shown in FIG. 15, GND2 is connected to the emitter of the insulated gate bipolar transistor Tr1 outside the semiconductor device A1. VCC2 is a positive power supply terminal. In the semiconductor device A1, each of a pair of second support terminals 523 among the multiple second terminals 52 is VCC2. Therefore, VCC2 is electrically connected to both the second semiconductor element 12 and the second die pad 4. VEE2 is a negative power supply terminal. OUT is an output terminal. PROOUT is a slow-off output terminal. CLAMP is a clamp terminal. OCP / DESATIN is an overcurrent detection terminal. NC is a non-connection terminal, or a so-called dummy terminal. NC is not electrically connected to the second semiconductor element 12.

[0130] In the semiconductor device A1, a first power supply is connected to any two or more of the plurality of first terminals 51, and a second power supply is connected to any two or more of the plurality of second terminals 52. The power supply voltage output by the second power supply is higher than the power supply voltage output by the first power supply. Therefore, the power supply voltage supplied to the second circuit (the second semiconductor element 12, the second die pad 4, the plurality of second terminals 52, and the plurality of second wires 62) is higher than the power supply voltage supplied to the first circuit (the first semiconductor element 11, the first die pad 3, the plurality of first terminals 51, and the plurality of first wires 61). For example, as described above, since the power supply voltage required for the first semiconductor element 11 is about 5 V, the power supply voltage supplied from the first power supply to the first circuit is about 5 V. Furthermore, since the power supply voltage required for the second semiconductor element 12 is 600 V or higher, the power supply voltage supplied from the second power supply to the second circuit is 600 V or higher. In this configuration, when a low-potential terminal (e.g., a GND terminal) of the first power supply is connected to a first terminal 51 among the plurality of first terminals 51 that is conductive with the first die pad 3, and a high-potential terminal of the second power supply is connected to a second terminal 52 among the plurality of second terminals 52 that is conductive with the second die pad 4, the potential difference between the first die pad 3 and the second die pad 4 becomes the largest. When a power supply voltage is supplied to the first circuit and a power supply voltage is supplied to the second circuit, for example, the potential of the first die pad 3 becomes 0 V (GND potential), and the potential of the second die pad 4 becomes 600 V or higher. For example, the insulation voltage between the first die pad 3 and the second die pad 4 is preferably 2,500 Vrms or higher.

[0131] Next, an example of a method for manufacturing the semiconductor device A1 will be described with reference to Figures 17 to 24. Here, the cross-sectional positions in Figures 19 to 21 are the same as the cross-sectional position in Figure 18.

[0132] First, as shown in FIGS. 17 and 18, a lead frame 81 having a main surface 81A and a back surface 81B spaced apart in the z direction is prepared, and then a resist 82 is formed on the main surface 81A and the back surface 81B.

[0133] In the step of preparing the lead frame 81, for example, a copper plate having a rectangular shape in a plan view is punched to form the lead frame 81, which includes an outer frame 811, an island portion 812, a plurality of first leads 813, a plurality of second leads 814, a plurality of support leads 815, and a dam bar 816, as shown in FIG. 17 . Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A1. The plurality of first leads 813 are portions that will later become the plurality of first intermediate terminals 511 and a pair of first side terminals 512. The plurality of second leads 814 are portions that will later become the plurality of second intermediate terminals 521 and a pair of second side terminals 522. The plurality of support leads 815 are portions that will later become the pair of first support terminals 513 and a pair of second support terminals 523.

[0134] In the step of forming the resist 82, the resist 82 is formed on a portion of each of the main surface 81A and the back surface 81B of the lead frame 81. For ease of understanding, dots are drawn on the resist 82 in FIG. 17. As shown in FIGS. 17 and 18, the resist 82 includes a first covering portion 82A and a second covering portion 82B. The first covering portion 82A covers a portion of the main surface 81A. As shown in FIGS. 17 and 18, a portion of the main surface 81A is exposed from the first covering portion 82A, and the main surface 81A includes a first exposed region 810A exposed from the first covering portion 82A. The second covering portion 82B covers a portion of the back surface 81B. As shown in FIG. 18, a portion of the back surface 81B is exposed from the second covering portion 82B, and the back surface 81B includes a second exposed region 810B exposed from the second covering portion 82B. 17, the first exposed region 810A and the second exposed region 810B are each disposed in an island portion 812. Furthermore, the first exposed region 810A and the second exposed region 810B overlap in a plan view, as shown in FIG.

[0135] Next, as shown in FIGS. 19 to 21, the lead frame 81 is subjected to an etching process. In the process of etching the lead frame 81, etching is performed from both the main surface 81A side and the back surface 81B side of the lead frame 81. FIGS. 19 to 21 show state transitions in this etching process, and the etching progresses in the order shown in FIGS. 19, 20, and 21. As shown in FIG. 19, etching progresses from the first exposed region 810A, and etching progresses from the second exposed region 810B. Thereafter, as shown in FIGS. 20 and 21, the island portion 812 is separated into two portions (a first die pad 812A and a second die pad 812B) by etching from the first exposed region 810A and etching from the second exposed region 810B. The first die pad 812A corresponds to the first die pad 3. The second die pad 812B corresponds to the second die pad 4.

[0136] In this way, simultaneous etching is performed from both the main surface 81A side and the back surface 81B side of the lead frame 81, thereby forming the first opposing surface 33 of the first die pad 3 and the second opposing surface 43 of the second die pad 4. Furthermore, a first main surface side recess 331, a first back surface side recess 332, a first main surface side protrusion 333, a first back surface side protrusion 334, and a first intermediate protrusion 335 are formed on the first opposing surface 33 (first die pad 3). A second main surface side recess 431, a second back surface side recess 432, a second main surface side protrusion 433, a second back surface side protrusion 434, and a second intermediate protrusion 435 are formed on the second opposing surface 43 (second die pad 4).

[0137] As shown in FIGS. 19 to 21, the rate at which etching proceeds from the second exposed region 810B is faster than the rate at which etching proceeds from the first exposed region 810A. This is because, by performing the etching process with one side in the z direction facing vertically upward and the other side in the z direction facing vertically downward, for example, in the state shown in FIG. 19, the etching solution accumulates on the main surface 81A side, suppressing the progress of etching. However, the etching solution does not accumulate on the back surface 81B side. Therefore, the depth D of etching proceeding from the second exposed region 810B is 81Bis the etching depth D proceeding from the first exposed region 810A. 81A Furthermore, the distance L81b between the two island portions 812 (the first die pad 812A and the second die pad 812B) separated by etching in the x direction is greater than the distance L81a between the two island portions 812 on the back surface 81B side. 81A The etching conditions are set so that the angle α1, α2, β1, β2, γ1, and γ2 are set in the semiconductor device A1 under these etching conditions. Thereafter, the resist 82 is removed to form the lead frame 81 shown in FIG. 22.

[0138] 23, the first semiconductor element 11 and the insulating element 13 are bonded to the first die pad 812A by die bonding. At the same time, the second semiconductor element 12 is bonded to the second die pad 812B by die bonding. After these steps, the plurality of first wires 61, the plurality of second wires 62, the plurality of third wires 63, and the plurality of fourth wires 64 are each formed by wire bonding.

[0139] Next, as shown in FIG. 24, the sealing resin 7 is formed. The sealing resin 7 is formed by transfer molding. In this process, the lead frame 81 is housed in a mold having multiple cavities 88. At this time, the portion of the lead frame 81 that corresponds to the conductive support member 2 of the semiconductor device A1 and that is covered with the sealing resin 7 is housed in one of the multiple cavities 88. Then, fluidized resin flows from the pot 86 through the runners 87 into each of the multiple cavities 88. A plunger (not shown) is connected to the pot 86. When the plunger is actuated, the fluidized resin in the pot 86 flows out toward the runners 87. The lead frame 81 is provided with a first gate 891 and a second gate 892. In each of the multiple cavities 88, the first gate 891 is an inlet for the fluidized resin. In each of the multiple cavities 88, the second gate 892 is an outlet for the fluidized resin. The first gate 891 is located at the center of each of the multiple cavities 88 in the x direction. The second gate 892 is located at the center of each of the multiple cavities 88 in the x direction. As a result, when viewed along the y direction, each of the first gate 891 and the second gate 892 overlaps with the gap between the first die pad 812A and the second die pad 812B in the x direction, i.e., the pad gap 21. After the fluidized sealing resin 7 in the multiple cavities 88 is solidified, resin burrs located outside each of the multiple cavities 88 are removed using high-pressure water or the like. At this time, when the resin burr located at the first gate 891 is removed, a first gate mark 791 is formed in the sealing resin 7. Similarly, when the resin burr located at the second gate 892 is removed, a second gate mark 792 is formed in the sealing resin 7. This completes the formation of the sealing resin 7.

[0140] Then, dicing is performed to separate the island portion 812 (first die pad 812a and second die pad 812b), which were connected to each other by the outer frame 811 and dam bar 816, the multiple first leads 813, the multiple second leads 814, and the multiple support leads 815, as appropriate.

[0141] The semiconductor device A1 is manufactured through the steps described above. In the above manufacturing method, an example has been described in which a lead frame 81 including an island portion 812 is prepared in the preparation step, and the island portion 812 is separated into two portions, a first die pad 812a and a second die pad 812b, in the etching step. However, this is not limiting. For example, the preparation step may prepare a lead frame 81 that is rectangular in plan view, and then the resist formation step and the etching step may simultaneously form an outer frame 811, a first die pad 812a, a second die pad 812b, a plurality of first leads 813, a plurality of second leads 814, a support lead 815, and a dam bar 816 on the lead frame 81.

[0142] Next, the effects of the semiconductor device A1 will be described.

[0143] The semiconductor device A1 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. This makes it possible to improve the withstand voltage between the first circuit and the second circuit when there is a difference between the power supply voltage supplied to the first semiconductor element 11 and the power supply voltage supplied to the second semiconductor element 12. Therefore, the semiconductor device A1 makes it possible to improve the withstand voltage.

[0144] The semiconductor device A1 includes a conductive support member 2 that includes a first die pad 3 and a second die pad 4. In plan view, the periphery 36 of the first die pad 3 has a first near corner 362 that includes a first end 362A in the y direction. The first near corner 362 is spaced further away from the second die pad 4 in the x direction as it approaches the first end 362A in the y direction. This reduces the electric field strength between the first near corner 362 and the second die pad 4 compared to when the first near corner 362 is formed at a right angle in plan view. In other words, the semiconductor device A1 can further improve its dielectric strength. In plan view, the periphery 46 of the second die pad 4 has a second near corner 462 that includes a second end 462A in the y direction. The second near corner 462 is spaced further away from the first die pad 3 in the x direction as it approaches the second end 462a in the y direction. This reduces the electric field strength between the second near corner 462 and the first die pad 3 compared to when the second near corner 462 is formed at a right angle in plan view. Therefore, the semiconductor device A1 can further improve the dielectric strength.

[0145] The semiconductor device A1 includes a conductive support member 2 that includes a first die pad 3 and a second die pad 4. The first die pad 3 has a first main surface 31 that faces the z direction and has a first semiconductor element 11 mounted thereon, and a first back surface 32 that faces the side opposite the first main surface 31 in the z direction. The second die pad 4 has a second main surface 41 that faces the z direction and has a second semiconductor element 12 mounted thereon, and a second back surface 42 that faces the side opposite the second main surface 41 in the z direction. When viewed along the y direction, a separation distance d2 (see FIG. 11) between the first back surface 32 and the second back surface 42 is greater than a separation distance d1 (see FIG. 11) between the first main surface 31 and the second main surface 41. As a result, when viewed along the y direction, the electric field strength at the end of the first die pad 3 and the second die pad 4 on the side where the first main surface 31 and the second main surface 41 are located in the z direction is stronger than the electric field strength at the end of the end of the first back surface 32 and the second back surface 42 in the z direction. Therefore, by adjusting the separation distance between the first main surface 31 and the second main surface 41, the semiconductor device A1 can improve its insulation resistance. Furthermore, in the process of forming the sealing resin 7 (see FIG. 24 ) in the manufacturing process of the semiconductor device A1, depending on the respective positions of the first gate 891 into which the fluidized resin flows and the second gate 892 from which the resin flows out, the resin may not fill the pad gap 21 sufficiently on the first back surface 32 and the second back surface 42 side compared to the first main surface 31 and the second main surface 41 side. In this case, the dielectric strength may decrease on the first back surface 32 and the second back surface 42 side. Therefore, by making the separation distance d2 larger than the separation distance d1, the outflow of the resin is promoted on the first back surface 32 and the second back surface 42 sides, and the resin can be sufficiently filled on the first back surface 32 and the second back surface 42 sides. Therefore, according to the semiconductor device A1, it is possible to further improve the dielectric strength voltage.

[0146] In the semiconductor device A1, the separation distance d1 (see FIG. 11 ) between the first main surface 31 and the second main surface 41 in the x direction is 250 μm or more and 500 μm or less. On the other hand, if the separation distance d1 is greater than 500 μm, the etching process in the aforementioned etching step will be over-etching. When viewed along the y direction, in an over-etched state, the angles of the first main surface side protrusion 333, the first back surface side protrusion 334, the second main surface side protrusion 433, and the second back surface side protrusion 434 become smaller. As a result, the electric field strength between the first main surface side protrusion 333 and the second main surface side protrusion 433 and the electric field strength between the first back surface side protrusion 334 and the second back surface side protrusion 434 become stronger, which causes a decrease in the dielectric strength of the semiconductor device A1. On the other hand, if the separation distance d1 is less than 250 μm, the etching process in the aforementioned etching step will be under-etching. In an under-etched state, the separation distance d1 becomes smaller. As a result, the electric field strength between the first main surface 31 and the second main surface 41 becomes stronger, which causes a decrease in the dielectric strength of the semiconductor device A1. Therefore, in the semiconductor device A1, by setting the separation distance d1 to be 250 μm or more and 500 μm or less, the decrease in the dielectric strength of the semiconductor device A1 can be suppressed.

[0147] In the semiconductor device A1, the distance between the closest portions of the first die pad 3 and the second die pad 4 in a plan view is smaller than the distance between the closest portions of the plurality of first terminals 51 and the first die pad 3 and the distance between the closest portions of the plurality of second terminals 52 and the first die pad 3 in a plan view. With this configuration, the first die pad 3 and the second die pad 4 are closest to each other between the portion constituting the first circuit and the portion constituting the second circuit of the conductive support member 2. Therefore, by improving the dielectric strength between the first die pad 3 and the second die pad 4, the dielectric strength of the semiconductor device A1 can be improved.

[0148] In semiconductor device A1, the power supply voltage supplied to the second circuit including second semiconductor element 12 and second die pad 4 is higher than the power supply voltage supplied to the first circuit including first semiconductor element 11 and first die pad 3. For example, the power supply voltage supplied to the first circuit is about 5 V, while the power supply voltage supplied to the second circuit is 600 V or higher. When there is a significant potential difference in the supplied power supply voltages, it is preferable to further improve the withstand voltage of semiconductor device A1 in addition to incorporating insulating element 13, in order to improve the reliability of semiconductor device A1.

[0149] In the semiconductor device A1, the first terminals 51 are exposed from the first side surface 73. The second terminals 52 are exposed from the second side surface 74. The first die pad 3, the second die pad 4, the first terminals 51, and the second terminals 52 are all components of the conductive support member 2. In this case, the island support and other parts of the conductive support member 2 are not exposed from the third side surface 75 and the fourth side surface 76. With this configuration, no metal part of the conductive support member 2 exposed from the sealing resin 7 exists near the second terminals 52, to which a higher voltage is applied than the first terminals 51. Therefore, the semiconductor device A1 can further improve the dielectric strength.

[0150] In the manufacturing method of the semiconductor device A1, the first die pad 812a and the second die pad 812b are formed by the etching process. That is, the gap between the first die pad 3 and the second die pad 4 is formed by the etching process. This configuration allows the separation distance d1 (see FIG. 11) to be set more accurately than when the gap is formed by punching. Therefore, it is easy to set the separation distance d1 to 250 μm or more and 500 μm or less. In particular, in the manufacturing method of the semiconductor device A1, the outer frame 811, the island portion 812, the plurality of first leads 813, the plurality of second leads 814, the plurality of support leads 815, and the dam bar 816 are formed in the lead frame 81 by punching. The punching process is faster and less expensive than the etching process. Therefore, by performing the etching process only on the gap between the first die pad 3 and the second die pad 4, which requires high processing accuracy, the manufacturing efficiency of the semiconductor device A1 can be improved and the manufacturing cost of the semiconductor device A1 can be reduced.

[0151] In the semiconductor device A1, a first gate mark 791 is formed on the first side surface 73 of the sealing resin 7. The first gate mark 791 is a mark resulting from the first gate 891 through which fluidized resin flows into each of the multiple cavities 88 during the process of forming the sealing resin 7 (see FIG. 24 ) in the manufacturing process of the semiconductor device A1. When viewed along the y direction, the first gate mark 791 overlaps with the pad gap 21 formed between the first die pad 3 and the second die pad 4 in the x direction. As a result, as shown in FIG. 25 , the resin flowing from the first gate 891 into each of the multiple cavities 88 flows toward the pad gap 21 over a shorter distance. This increases the flow rate of the resin flowing through the pad gap 21, thereby increasing the average density of the first resin portion 7A of the sealing resin 7 penetrating the pad gap 21 along the z direction. Therefore, the semiconductor device A1 can achieve a further improvement in dielectric strength.

[0152] In the semiconductor device A1, a second gate mark 792 is formed on the second side surface 74 of the sealing resin 7, the second side surface 74 having a rougher surface than other regions of the second side surface 74. The second gate mark 792 is a mark resulting from the second gate 892, where fluidized resin flows out of each of the cavities 88, during the process of forming the sealing resin 7 (see FIG. 24 ) in the manufacturing process of the semiconductor device A1. When viewed along the y direction, the second gate mark 792 overlaps with the pad gap 21 in the x direction. This causes the main flow of the resin in each of the cavities 88 to follow the arrows shown in FIG. 25 . This further increases the flow rate of the resin flowing through the pad gap 21, further increasing the average density of the first resin portion 7A of the sealing resin 7. Therefore, the semiconductor device A1 can achieve a further improvement in dielectric strength. As a result, in the sealing resin 7, the average void volume per unit volume of the first resin portion 7A is smaller than the average void volume per unit volume of the second resin portion 7B.

[0153] The semiconductor device A1 further includes a plurality of first wires 61 bonded to the first semiconductor element 11 and any of the plurality of first terminals 51. For at least one of the plurality of first wires 61, the angle the first wire 61 forms with respect to the x-direction is greater than the angle the first wire 61 forms with respect to the y-direction. As shown in FIG. 25 , when the resin flowing from the first gate 891 flows into each of the plurality of cavities 88, the resin spreads along the flow F in each of the plurality of cavities 88. Therefore, by adopting this configuration, displacement of the first wire 61 in the x-direction due to the flow of the resin can be suppressed. Therefore, the first wire 61 can be prevented from being extremely close to the second circuit. This effect is particularly beneficial for the specific first wire 61A, which is located closest to the first gate mark 791 and has the longest length among the plurality of first wires 61.

[0154] The semiconductor device A1 further includes a plurality of second wires 62 bonded to the second semiconductor element 12 and any of the plurality of second terminals 52. The angle of at least any of the plurality of second wires 62 relative to the x-direction is greater than the angle of the second wire 62 relative to the y-direction. This, for the same reasons as described above, makes it possible to suppress displacement of the second wire 62 in the x-direction due to the flow of the fluidized resin. Therefore, it is possible to prevent the second wire 62 from being extremely close to the first circuit. This effect is particularly beneficial for the specific second wire 62A, which is located closest to the first gate mark 791 and has the longest length among the plurality of second wires 62.

[0155] Second Embodiment A semiconductor device A2 according to a second embodiment of the present invention will be described with reference to Figs. 26 and 27. In these figures, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Fig. 26 shows the sealing resin 7 through which light is transmitted. In Fig. 26, the transmitted sealing resin 7 is shown by imaginary lines.

[0156] In the semiconductor device A2, the configuration of the first die pad 3 is different from that of the semiconductor device A1 described above.

[0157] As shown in FIGS. 26 and 27, a plurality of holes 39 are formed in the first die pad 3. Each of the plurality of holes 39 is formed in a region of the first die pad 3 located between the first semiconductor element 11 and the insulating element 13 in the x direction. There is no particular limitation on the number of holes 39, but three holes 39 are formed in the semiconductor device A2. Each hole 39 is an elongated hole extending in the y direction. The shape of each hole 39 in a plan view can be freely set. As shown in FIG. 26, in the first die pad 3, the pair of first support terminals 513 and the plurality of holes 39 are arranged on a straight line N (a dashed dotted line) extending in the y direction.

[0158] Next, the effects of the semiconductor device A2 will be described.

[0159] The semiconductor device A2 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A2 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A2 achieves the same effects as the semiconductor device A1.

[0160] In the semiconductor device A2, a hole 39 is formed in the first die pad 3. Because the area of ​​the first die pad 3 in a plan view is larger than the area of ​​the second die pad 4 in a plan view, voids are likely to occur in the portion of the sealing resin 7 located near the first die pad 3 when the sealing resin 7 is formed. Therefore, by forming the hole 39 in the first die pad 3, the molten resin injected into the mold when forming the sealing resin 7 can be sufficiently filled. In other words, the semiconductor device A2 can suppress the occurrence of voids in the sealing resin 7 compared to when the hole 39 is not formed in the first die pad 3.

[0161] Third Embodiment A semiconductor device A3 according to a third embodiment of the present invention will be described with reference to Fig. 28. In this figure, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Fig. 28 shows the sealing resin 7 through which light is transmitted. In Fig. 28, the transmitted sealing resin 7 is shown by imaginary lines.

[0162] In the semiconductor device A3, the configurations of the first die pad 3 and the second die pad 4 differ from those of the semiconductor device A1 described above.

[0163] As shown in FIG. 28 , the pair of first near corners 362 and the pair of second near corners 462 are each formed linearly in a plan view. The pair of first near corners 362 are each inclined with respect to the y direction. In the semiconductor device A3, each first near corner 362 is inclined so as to move away from the second die pad 4 in the x direction toward the first end 362A in the y direction. The pair of second near corners 462 are each inclined with respect to the y direction. In the semiconductor device A3, each second near corner 462 is inclined so as to move away from the first die pad 3 in the x direction toward the second end 462a in the y direction. With this configuration, the gap in the x direction between the pair of first near corners 362 and the pair of second near corners 462 is tapered.

[0164] In the semiconductor device A3, the line segment connecting the pair of first ends 362A in plan view may be located closer to the second die pad 4 than the insulating element 13 in the x direction, or may overlap the insulating element 13 in the x direction. However, if the line segment is located closer to the second die pad 4 than the insulating element 13 in the x direction, it becomes easier to increase the angle between each first near corner 362 and the first near edge 363 in plan view. Furthermore, the line segment connecting the pair of second ends 462a in plan view may overlap the second semiconductor element 12 in the x direction, or may be located closer to the first die pad 3 than the second semiconductor element 12. However, if the line segment is located closer to the first die pad 3 than the second semiconductor element 12, it becomes easier to increase the angle between each second near corner 462 and the second near edge 463 in plan view.

[0165] Next, the effects of the semiconductor device A3 will be described.

[0166] The semiconductor device A3 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A3 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A3 achieves the same effects as the semiconductor device A1.

[0167] [Fourth embodiment] A semiconductor device A4 according to a fourth embodiment of the present invention will be described with reference to Figures 29 and 30. In these figures, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated descriptions will be omitted.

[0168] In the semiconductor device A4, the configuration of the sealing resin 7 is different from that of the semiconductor device A1 described above.

[0169] 29, the plurality of first terminals 51 include a first edge terminal 51A. The first edge terminal 51A is exposed from a first side surface 73 of the sealing resin 7 and is located closest to a third side surface 75 of the sealing resin 7. In the semiconductor device A4, the first edge terminal 51A corresponds to one of a pair of first support terminals 513. The plurality of second terminals 52 include a second edge terminal 52A. The second edge terminal 52A is exposed from a second side surface 74 of the sealing resin 7 and is located closest to the third side surface 75. In the semiconductor device A4, the second edge terminal 52A corresponds to one of a pair of second side terminals 522.

[0170] 29 and 30 show a first creepage distance CD1, a second creepage distance CD2, and a third creepage distance CD3. The first creepage distance CD1 is the shortest distance from the first edge terminal 51A to the second edge terminal 52A along the first side surface 73, the third side surface 75, and the second side surface 74 of the sealing resin 7. The second creepage distance CD2 is the shortest distance from the first edge terminal 51A to the second edge terminal 52A along the first side surface 73, the bottom surface 72, and the second side surface 74 of the sealing resin 7. The third creepage distance CD3 is the shortest distance from the first edge terminal 51A to the second edge terminal 52A along the first side surface 73, the top surface 71, and the second side surface 74 of the sealing resin 7. The first creepage distance CD1 is shorter than the second creepage distance CD2. The third creepage distance CD3 is longer than the second creepage distance CD2. Therefore, the length relationship among the first creepage distance CD1, the second creepage distance CD2 and the third creepage distance CD3 is first creepage distance CD1<second creepage distance CD2<third creepage distance CD3.

[0171] 29, in a plan view, the dimension of a periphery L of the sealing resin 7 along the x direction is larger than the dimension of a periphery B of the sealing resin 7 along the y direction. The dimension of the periphery L is preferably 0.75 to 3 times the dimension of the periphery B.

[0172] 30, in the z direction, the shortest distance H1 from the first die pad 3 to the top surface 71 of the sealing resin 7 is longer than the shortest distance H2 from the first die pad 3 to the bottom surface 72 of the sealing resin 7. This is the main reason why the third creepage distance CD is longer than the second creepage distance CD2.

[0173] Next, the effects of the semiconductor device A4 will be described.

[0174] The semiconductor device A4 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A4 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A4 achieves the same effects as the semiconductor device A1.

[0175] In the semiconductor device A4, the first creepage distance CD1 is shorter than the second creepage distance CD2. In this case, by increasing the dimension of the periphery L shown in Fig. 29, the first creepage distance CD1 becomes longer. This allows the withstand voltage of the semiconductor device A4 to be further improved.

[0176] In the semiconductor device A4, the shortest distance H1 in the z direction from the first die pad 3 to the top surface 71 of the sealing resin 7 is longer than the shortest distance H2 from the first die pad 3 to the bottom surface 72 of the sealing resin 7. This makes it possible to increase the thickness of the sealing resin 7 covering each of the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first die pad 3, the second die pad 4, the plurality of first wires 61, the plurality of second wires 62, the plurality of third wires 63, and the plurality of fourth wires 64. This makes it possible to further improve the withstand voltage of the semiconductor device A4.

[0177] Fifth Embodiment A semiconductor device A5 according to a fifth embodiment of the present invention will be described with reference to Figures 31 to 34. In these figures, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted.

[0178] In the semiconductor device A5, the configuration of the sealing resin 7 is different from that of the semiconductor device A1 described above.

[0179] As shown in FIGS. 32 and 33 , the surfaces of the top surface 71, bottom surface 72, first side surface 73, and second side surface 74 of the sealing resin 7 are rougher than those of the semiconductor device A1. Therefore, the surface area of ​​the sealing resin 7 is larger than that of the sealing resin 7 of the semiconductor device A1. The surface roughness of the top surface 71, bottom surface 72, first region 731 of the first side surface 73, and second region 732 of the first side surface 73 is larger than the surface roughness of the third region 733 of the first side surface 73. Furthermore, the surface roughness of the top surface 71, bottom surface 72, fourth region 741 of the second side surface 74, and fifth region 742 of the second side surface 74 is larger than the surface roughness of the sixth region 743 of the second side surface 74. The surface roughness of each of the top surface 71 and bottom surface 72 is preferably 5 μmRz or more and 20 μmRz or less.

[0180] 31 and 34, the sealing resin 7 has a recess 711 recessed in the z direction from the top surface 71. As a result, the sealing resin 7 has a penetration surface 711A that faces the same side as the top surface 71 in the z direction and defines the recess 711. The surface roughness of the penetration surface 711A is smaller than the surface roughness of the top surface 71. When the semiconductor device A5 is mounted on a wiring board, the recess 711 serves as a marker for distinguishing between the multiple first terminals 51 and the multiple second terminals 52.

[0181] Next, the effects of the semiconductor device A5 will be described.

[0182] The semiconductor device A5 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A5 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A5 achieves the same effects as the semiconductor device A1.

[0183] In semiconductor device A5, the surface roughness of each of top surface 71, bottom surface 72, first region 731 of first side surface 73, and second region 732 of first side surface 73 is greater than the surface roughness of third region 733 of first side surface 73. Furthermore, the surface roughness of each of top surface 71, bottom surface 72, fourth region 741 of second side surface 74, and fifth region 742 of second side surface 74 is greater than the surface roughness of sixth region 743 of second side surface 74. This makes it possible to ensure longer lengths of second creepage distance CD2 and third creepage distance CD3 shown in FIGS. 29 and 30. This therefore enables the dielectric strength of semiconductor device A5 to be further improved.

[0184] Sixth Embodiment A semiconductor device A6 according to a sixth embodiment of the present invention will be described with reference to Fig. 35. In this figure, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Fig. 35 shows the sealing resin 7 through which light is transmitted. In Fig. 35, the transmitted sealing resin 7 is shown by imaginary lines.

[0185] In the semiconductor device A6, the arrangement of the plurality of first wires 61 and the plurality of second wires 62 differs from that of the semiconductor device A1 described above.

[0186] 35, two first wires 61 are joined to the pad portion 511B of any one of the multiple first intermediate terminals 511 and the pad portion 513B of each of the pair of first support terminals 513. In the semiconductor device A6, the two first wires 61 are joined to the pad portion 511B and the pad portion 513B, respectively, in a state spaced apart from each other.

[0187] 35, two second wires 62 are joined to the pad portion 521B of any one of the plurality of second intermediate terminals 521, the pad portion 522B of any one of the pair of second side terminals 522, and the pad portion 523B of each of the pair of second support terminals 523. In the semiconductor device A6, the two second wires 62 are joined to the pad portion 521B, the pad portion 522B, and the pad portion 523B, respectively, in a state spaced apart from each other.

[0188] Next, the effects of the semiconductor device A6 will be described.

[0189] The semiconductor device A6 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A6 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A6 achieves the same effects as the semiconductor device A1.

[0190] Seventh Embodiment A semiconductor device A6 according to a seventh embodiment of the present invention will be described with reference to Fig. 36. In this figure, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Fig. 36 shows the sealing resin 7 through which light is transmitted. In Fig. 36, the transmitted sealing resin 7 is shown by imaginary lines.

[0191] In the semiconductor device A7, the arrangement of the insulating elements 13 is different from that of the semiconductor device A1 described above.

[0192] 36, the insulating element 13 is mounted on the second main surface 41 of the second die pad 4. In the semiconductor device A7, a plurality of third wires 63 span the pad gaps 21.

[0193] Next, the effects of the semiconductor device A7 will be described.

[0194] The semiconductor device A7 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A7 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A7 achieves the same effects as the semiconductor device A1.

[0195] Eighth Embodiment A semiconductor device A8 according to an eighth embodiment of the present invention will be described with reference to Fig. 37. In this figure, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Fig. 37 shows the sealing resin 7 through which light is transmitted. In Fig. 37, the transmitted sealing resin 7 is shown by imaginary lines.

[0196] In the semiconductor device A8, the configurations of the first semiconductor element 11 and the insulating element 13 are different from those of the semiconductor device A1 described above.

[0197] 37, the first semiconductor element 11 and the insulating element 13 are integrated into a single element. Conduction between the first semiconductor element 11 and the insulating element 13 is achieved in a circuit formed in the single element. This eliminates the need for multiple third wires 63.

[0198] Next, the effects of the semiconductor device A8 will be described.

[0199] The semiconductor device A8 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A8 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A8 achieves the same effects as the semiconductor device A1.

[0200] Ninth Embodiment A semiconductor device A9 according to a ninth embodiment of the present invention will be described with reference to Fig. 38. In this figure, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Fig. 38 shows the sealing resin 7 through which light is transmitted. In Fig. 37, the transmitted sealing resin 7 is shown by imaginary lines.

[0201] In the semiconductor device A9, the configuration of the insulating element 13 is different from that of the semiconductor device A1 described above.

[0202] 38, the insulating element 13 is composed of a pair of elements. One of the pair of elements is mounted on the first main surface 31 of the first die pad 3. The other of the pair of elements is mounted on the second main surface 41 of the second die pad 4. The pair of elements are mutually electrically connected by a plurality of fifth wires 65.

[0203] Next, the effects of the semiconductor device A9 will be described.

[0204] The semiconductor device A9 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A9 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A9 achieves the same effects as the semiconductor device A1.

[0205] Tenth Embodiment A semiconductor device A10 according to a tenth embodiment of the present invention will be described with reference to Fig. 39. In this figure, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Fig. 39 shows the sealing resin 7 through which light is transmitted. In Fig. 39, the transmitted sealing resin 7 is shown by imaginary lines.

[0206] In the semiconductor device A10, the configurations of the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are different from those of the semiconductor device A1 described above.

[0207] 39, the insulating element 13 is composed of a pair of elements. One of the pair of elements is a single element integrated with a first semiconductor element 11. The other of the pair of elements is a single element integrated with a second semiconductor element 12. Mutual conduction between these single elements is achieved by a plurality of fifth wires 65. This eliminates the need for a plurality of third wires 63 and a plurality of fourth wires 64, as compared to the semiconductor device A9.

[0208] Next, the effects of the semiconductor device A10 will be described.

[0209] The semiconductor device A10 includes an insulating element 13 that isolates the first circuit from the second circuit. The first circuit includes a first semiconductor element 11. The second circuit includes a second semiconductor element 12. Therefore, the semiconductor device A10 also makes it possible to improve the dielectric strength. Furthermore, by sharing a configuration with the semiconductor device A1, the semiconductor device A10 achieves the same effects as the semiconductor device A1.

[0210] The present invention is not limited to the above-described embodiment, and the specific configuration of each part of the present invention can be freely designed and modified in various ways.

[0211] The technical configuration of the semiconductor device provided by the present invention will be further described below.

[0212] [Appendix 1A] a conductive support member including a first die pad and a second die pad spaced apart in a first direction perpendicular to the thickness direction and having relatively different potentials; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an insulating element that is electrically connected to the first semiconductor element and the second semiconductor element and that insulates the first circuit from the second circuit; a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, and the insulating element and insulates the first die pad and the second die pad from each other, the first die pad and the second die pad overlap each other when viewed along the first direction, When viewed along the thickness direction, a periphery of the first die pad has a first near corner portion including a first end portion in a second direction orthogonal to both the thickness direction and the first direction, The semiconductor device, wherein the first near corner portion becomes farther from the second die pad in the first direction as it moves toward the first end portion in the second direction. [Appendix 2A] When viewed along the thickness direction, the periphery of the second die pad has a second near corner portion including a second end portion in the second direction, The semiconductor device according to Appendix 1A, wherein the second near corner portion becomes farther from the first die pad in the first direction as it moves toward the second end portion in the second direction. [Appendix 3A] The semiconductor device according to Appendix 2A, wherein the first near corner portion has an arc shape when viewed along the thickness direction. [Appendix 4A] the peripheral edge of the first die pad has a first far corner located on the opposite side of the first end portion from the second die pad in the first direction; the first far corner portion has an arc shape when viewed in the thickness direction, The semiconductor device according to Appendix 3A, wherein, when viewed along the thickness direction, the radius of curvature of the first near corner portion is larger than the radius of curvature of the first far corner portion. [Appendix 5A] The semiconductor device according to Appendix 3A or 4A, wherein the radius of curvature of the first near corner portion is not less than 60 μm and not more than 240 μm when viewed along the thickness direction. [Appendix 6A] The semiconductor device according to any one of appendixes 2A to 5A, wherein the second near corner portion has an arc shape when viewed along the thickness direction. [Appendix 7A] the peripheral edge of the second die pad has a second far corner located on the opposite side of the second die pad from the second end in the first direction; the second far corner portion has an arc shape when viewed along the thickness direction, The semiconductor device according to Appendix 6A, wherein the radius of curvature of the second near corner portion is larger than the radius of curvature of the second far corner portion when viewed in the thickness direction. [Appendix 8A] The semiconductor device according to Appendix 6A or 7A, wherein the radius of curvature of the second near corner portion is 60 μm or more and 240 μm or less when viewed along the thickness direction. [Appendix 9A] When viewed along the thickness direction, the peripheral edge of the first die pad has a first near edge that extends along the second direction from an end of the first near corner portion that is opposite to the first end portion and faces the second die pad in the first direction, A semiconductor device as described in any one of Appendices 2A to 8A, wherein, when viewed along the thickness direction, the peripheral edge of the second die pad extends along the second direction from an end of the second near corner portion opposite the second end and has a second near end edge that faces the first die pad in the first direction. [Appendix 10A] The semiconductor device according to Appendix 9A, wherein the distance between the first near edge and the second near edge in the first direction is not less than 250 μm and not more than 500 μm. [Appendix 11A] The semiconductor device according to any one of appendices 1A to 10A, wherein the insulating element is mounted on the first die pad and is arranged between the first semiconductor element and the second semiconductor element in the first direction. [Appendix 12A] The semiconductor device according to any one of appendices 1A to 11A, wherein the insulating element is an inductive type. [Appendix 13A] The semiconductor device according to any one of appendices 1A to 12A, wherein the first semiconductor element, the second semiconductor element, and the insulating element are each composed of an individual element. [Appendix 14A] The semiconductor device according to any one of appendices 1A to 13A, wherein when a power supply voltage is supplied to the first circuit and a power supply voltage is supplied to the second circuit, the power supply voltage supplied to the second circuit is greater than the power supply voltage supplied to the first circuit. [Appendix 15A] the conductive support member includes a plurality of first terminals arranged along the second direction, at least one of which is electrically connected to the first circuit, and a plurality of second terminals arranged along the second direction, at least one of which is electrically connected to the second circuit; a portion of each of the plurality of first terminals is exposed from a first side surface of the sealing resin facing one side in the first direction; The semiconductor device according to any one of appendices 1A to 14A, wherein a portion of each of the plurality of second terminals is exposed from a second side surface of the sealing resin facing the other side in the second direction. [Appendix 16A] The semiconductor device described in Appendix 15A, wherein, when viewed along the thickness direction, the minimum distance between the first die pad and the second die pad is smaller than the minimum distance between each of the plurality of first terminals and the second die pad and the minimum distance between each of the plurality of second terminals and the first die pad.

[0213] [Appendix 1B] a conductive support member including a first die pad and a second die pad spaced apart in a first direction perpendicular to the thickness direction and having relatively different potentials; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an insulating element that is electrically connected to the first semiconductor element and the second semiconductor element and that insulates the first circuit from the second circuit; a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, and the insulating element and insulates the first die pad and the second die pad from each other, the first die pad and the second die pad overlap each other when viewed along the first direction, the first die pad has a first main surface facing the thickness direction and on which the first semiconductor element is mounted, and a first back surface facing the opposite side to the first main surface in the thickness direction; the second die pad has a second main surface facing the thickness direction and on which the second semiconductor element is mounted, and a second back surface facing the opposite side to the second main surface in the thickness direction, When viewed along a second direction perpendicular to both the thickness direction and the first direction, a distance in the first direction between the first back surface and the second back surface is larger than a distance in the first direction between the first main surface and the second main surface. [Appendix 2B] the first die pad has a first opposing surface that is connected to the first main surface and the first back surface and that faces the second die pad; the first opposing surface includes a first main surface-side recess connected to the first main surface and a first back surface-side recess connected to the first back surface, The semiconductor device according to Appendix 1B, wherein, when viewed along the second direction, the first main surface side recess and the first back surface side recess are recessed inward of the first die pad. [Appendix 3B] The semiconductor device described in Appendix 2B, wherein the first opposing surface includes a first main surface side protrusion formed by the first main surface and the first main surface side recess, a first back surface side protrusion formed by the first back surface and the first back surface side recess, and a first intermediate protrusion formed by the first main surface side recess and the first back surface side recess. [Appendix 4B] The semiconductor device according to Appendix 3B, wherein an angle of the first rear surface side protrusion is smaller than an angle of the first main surface side protrusion when viewed along the second direction. [Appendix 5B] The semiconductor device described in Appendix 3B or 4B, wherein, when viewed along the second direction, the angle of the first intermediate protrusion is greater than the sum of the angle of the first main surface side protrusion and the angle of the first back surface side protrusion. [Appendix 6B] A semiconductor device described in any one of Appendixes 3B to 5B, wherein, when viewed along the second direction, the first intermediate protrusion is located more inward of the first die pad than the first main surface side protrusion and the first back surface side protrusion. [Appendix 7B] The semiconductor device according to any one of Appendixes 2B to 6B, wherein the dimension of the first rear surface recess in the thickness direction is larger than the dimension of the first main surface recess in the thickness direction. [Appendix 8B] the second die pad has a second opposing surface that is connected to the second main surface and the second back surface and faces the first die pad; the second opposing surface includes a second main surface side recess connected to the second main surface and a second back surface side recess connected to the second back surface, The semiconductor device according to any one of appendices 2B to 7B, wherein, when viewed along the second direction, the second main surface side recess and the second back surface side recess are recessed inward of the second die pad. [Appendix 9B] The semiconductor device described in Appendix 8B, wherein the second opposing surface includes a second main surface side protrusion formed by the second main surface and the second main surface side recess, a second back surface side protrusion formed by the second back surface and the second back surface side recess, and a second intermediate protrusion formed by the second main surface side recess and the second back surface side recess. [Appendix 10B] The semiconductor device according to Appendix 9B, wherein an angle of the second rear surface side protrusion is smaller than an angle of the second main surface side protrusion when viewed along the second direction. [Appendix 11B] The semiconductor device of Appendix 9B or 10B, wherein, when viewed in the second direction, the angle of the second intermediate protrusion is greater than the sum of the angle of the second main surface side protrusion and the angle of the second back surface side protrusion. [Appendix 12B] A semiconductor device described in any one of Appendices 9B to 11B, wherein, when viewed along the second direction, the second intermediate protrusion is located more inward of the second die pad than the second main surface side protrusion and the second back surface side protrusion. [Appendix 13B] The semiconductor device according to any one of appendices 8B to 12B, wherein the dimension of the second rear surface recess in the thickness direction is larger than the dimension of the second main surface recess in the thickness direction. [Appendix 14B] A semiconductor device according to any one of Appendix 1B to Appendix 13B, wherein the thickness direction dimension of the first die pad and the thickness direction dimension of the second die pad are each 0.2 to 1.2 times the distance in the first direction between the first main surface and the second main surface. [Appendix 15B] The semiconductor device according to any one of appendices 1B to 14B, wherein the distance between the first main surface and the second main surface in the first direction is not less than 250 μm and not more than 500 μm. [Appendix 16B] A semiconductor device according to any one of appendices 1B to 15B, wherein the insulating element is mounted on the first die pad and is arranged between the first semiconductor element and the second semiconductor element in the first direction. [Appendix 17B] The semiconductor device according to any one of appendices 1B to 16B, wherein the insulating element is an inductive type. [Appendix 18B] The semiconductor device according to any one of appendices 1B to 17B, wherein when a power supply voltage is supplied to the first circuit and a power supply voltage is supplied to the second circuit, the power supply voltage supplied to the second circuit is greater than the power supply voltage supplied to the first circuit. [Appendix 19B] the conductive support member includes a plurality of first terminals arranged along the second direction, at least one of which is electrically connected to the first circuit, and a plurality of second terminals arranged along the second direction, at least one of which is electrically connected to the second circuit; a portion of each of the plurality of first terminals is exposed from a first side surface of the sealing resin facing one side in the first direction; The semiconductor device according to any one of appendixes 1B to 18B, wherein a portion of each of the plurality of second terminals is exposed from a second side surface of the sealing resin facing the other side in the second direction. [Appendix 20B] The semiconductor device described in Appendix 19B, wherein, when viewed along the thickness direction, the minimum distance between the first die pad and the second die pad is smaller than the minimum distance between each of the plurality of first terminals and the second die pad and the minimum distance between each of the plurality of second terminals and the first die pad.

[0214] [Appendix 1C] a first die pad disposed on one side in a first direction perpendicular to the thickness direction; a second die pad that is disposed on the other side of the first die pad in the first direction, that is spaced apart from the first die pad in the first direction, and that has a potential that is relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an isolation element mounted on either the first die pad or the second die pad, relaying transmission and reception of signals between the first circuit and the second circuit, and insulating the first circuit and the second circuit from each other; a plurality of first terminals including a portion located on the one side in the first direction with respect to the first die pad, arranged along a second direction perpendicular to both the thickness direction and the first direction, at least one of which is electrically connected to the first circuit; a plurality of second terminals including a portion located on the other side in the first direction with respect to the second die pad, arranged along the second direction, and at least one of which is electrically connected to the second circuit; a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the insulating element, the plurality of first terminals, and a portion of each of the plurality of second terminals, and that insulates the first die pad and the second die pad from each other; the sealing resin has a first side surface located on the one side in the first direction, a second side surface located on the other side in the first direction, and a third side surface and a fourth side surface located apart from each other in the second direction and connected to the first side surface and the second side surface, a first gate mark having a surface rougher than other regions of the third side surface is formed on the third side surface; A semiconductor device, characterized in that, when viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction. [Appendix 2C] a second gate mark having a surface rougher than other regions of the fourth side surface is formed on the fourth side surface; The semiconductor device according to Appendix 1C, wherein the second gate mark overlaps the pad gap when viewed along the second direction. [Appendix 3C] the sealing resin includes a first resin portion that penetrates the pad gap along the thickness direction and has the same dimension as the pad gap in the first direction, and second resin portions that are located at both ends of the first resin portion in the first direction, The semiconductor device according to Appendix 2C, wherein an average void volume per unit volume of the first resin portion is smaller than an average void volume per unit volume of the second resin portion. [Appendix 4C] The semiconductor device according to Appendix 3C, wherein the pad gap extends along the second direction when viewed along the thickness direction. [Appendix 5C] The semiconductor device according to Appendix 4C, wherein the first gate trace is located at the center of the third side surface in the first direction. [Appendix 6C] further comprising a plurality of first wires joined to the first semiconductor element and any of the plurality of first terminals; A semiconductor device described in any of Appendices 2C to 5C, wherein the angle that at least one of the multiple first wires makes with respect to the first direction is greater than the angle that the first wire makes with respect to the second direction. [Appendix 7C] the plurality of first wires include a specific first wire located closest to the first gate mark, an angle formed by the specific first wire with respect to the first direction is larger than an angle formed by the specific first wire with respect to the second direction; The semiconductor device according to Appendix 6C, wherein the length of the specific first wire is the longest among the lengths of the plurality of first wires. [Appendix 8C] further comprising a plurality of second wires joined to the second semiconductor element and any of the plurality of second terminals; A semiconductor device as described in Appendix 6C or 7C, wherein the angle that at least one of the multiple second wires makes with respect to the first direction is greater than the angle that the second wire makes with respect to the second direction. [Appendix 9C] the plurality of second wires include a specific second wire located closest to the first gate mark, an angle formed by the specific second wire with respect to the first direction is larger than an angle formed by the first wire with respect to the second direction; The semiconductor device according to Appendix 8C, wherein the length of the particular second wire is the longest among the lengths of the second wires. [Appendix 10C] The semiconductor device according to any one of appendices 2C to 9C, wherein, when a power supply voltage is supplied to the first circuit and a power supply voltage is supplied to the second circuit, the power supply voltage supplied to the second circuit is greater than the power supply voltage supplied to the first circuit. [Appendix 11C] A semiconductor device described in any one of Appendices 2C to 10C, wherein, when viewed along the second direction, the first gate mark includes an area located on the opposite side of the first die pad from the first semiconductor element in the thickness direction. [Appendix 12C] The semiconductor device described in Appendix 11C, wherein, when viewed along the second direction, the second gate mark includes a region located on the opposite side of the first die pad from the first semiconductor element in the thickness direction. [Appendix 13C] The semiconductor device according to any one of Appendixes 2C to 12C, wherein the second die pad overlaps the first die pad when viewed along the first direction. [Appendix 14C] A semiconductor device described in any one of Appendixes 2C to 13C, wherein the first die pad, the second die pad, the plurality of first terminals, and the plurality of second terminals are located away from both the third side surface and the fourth side surface. [Appendix 15C] When viewed along the thickness direction, each of the plurality of first terminals has a first lead portion that protrudes from the first side surface along the first direction, The semiconductor device according to Appendix 14C, wherein, when viewed along the thickness direction, each of the plurality of second terminals has a second lead portion that protrudes from the second side surface along the first direction. [Appendix 16C] the plurality of first terminals include a pair of first support terminals spaced apart from each other in the second direction, The semiconductor device according to Appendix 15C, wherein the pair of first support terminals are connected to both ends of the first die pad in the second direction. [Appendix 17C] the plurality of second terminals include a pair of second support terminals spaced apart from each other in the second direction; The semiconductor device according to Appendix 16C, wherein the pair of second support terminals are connected to both ends of the second die pad in the second direction. [Appendix 18C] a hole penetrating in the thickness direction is provided in a specific die pad of the first die pad and the second die pad on which the insulating element is mounted; A semiconductor device described in any one of Appendices 1C to 17C, wherein, when viewed along the thickness direction, the hole is located between the insulating element and a specific semiconductor element, one of the first semiconductor element and the second semiconductor element, that is mounted on the specific die pad. [Appendix 19C] The semiconductor device according to any one of appendices 1C to 18C, wherein the insulating element is an inductive type.

[0215] [Appendix 1D] a first die pad disposed on one side in a first direction perpendicular to the thickness direction; a second die pad that is disposed on the other side of the first die pad in the first direction, that is spaced apart from the first die pad in the first direction, and that has a potential that is relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an isolation element mounted on either the first die pad or the second die pad, relaying transmission and reception of signals between the first circuit and the second circuit, and insulating the first circuit and the second circuit from each other; a plurality of first terminals including a portion located on the one side in the first direction with respect to the first die pad, arranged along a second direction perpendicular to both the thickness direction and the first direction, at least one of which is electrically connected to the first circuit; a plurality of second terminals including a portion located on the other side in the first direction with respect to the second die pad, arranged along the second direction, and at least one of which is electrically connected to the second circuit; a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the insulating element, the plurality of first terminals, and a portion of each of the plurality of second terminals, and that insulates the first die pad and the second die pad from each other; the sealing resin has a top surface facing a side where the first semiconductor element is located with respect to the first die pad in the thickness direction, a bottom surface facing the opposite side from the top surface in the thickness direction, a first side surface located on one side in the first direction and connected to the top surface and the bottom surface, a second side surface located on the other side in the first direction and connected to the top surface and the bottom surface, and a third side surface located on either side in the second direction and connected to the first side surface and the second side surface, the plurality of first terminals include a first edge terminal exposed from the first side surface and located closest to the third side surface; the plurality of second terminals include a second edge terminal exposed from the second side surface and located closest to the third side surface; A semiconductor device characterized in that a first creepage distance from the first edge terminal to the second edge terminal along the first side surface, the third side surface, and the second side surface at the shortest distance is shorter than a second creepage distance from the first edge terminal to the second edge terminal along the first side surface, the bottom surface, and the second side surface at the shortest distance. [Appendix 2D] A semiconductor device as described in Appendix 1D, wherein a third creepage distance from the first edge terminal along the first side surface, the top surface, and the second side surface to the second edge terminal at the shortest distance is longer than the second creepage distance. [Appendix 3D] The semiconductor device described in Appendix 1D or 2D, wherein, when viewed along the thickness direction, the peripheral dimension of the sealing resin along the first direction is 0.75 to 3 times the peripheral dimension of the sealing resin along the second direction. [Appendix 4D] The semiconductor device according to any one of appendices 1D to 3D, wherein when a power supply voltage is supplied to the first circuit and a power supply voltage is supplied to the second circuit, the power supply voltage supplied to the second circuit is greater than the power supply voltage supplied to the first circuit. [Appendix 5D] Each of the plurality of first terminals has a first pad portion covered with the sealing resin and a first lead portion connected to the first pad portion and partially exposed from the first side surface, When viewed along the second direction, the first lead portion of each of the plurality of first terminals is bent toward the bottom surface, The semiconductor device according to any one of appendices 1D to 4D, wherein, when viewed along the thickness direction, the first lead portion of each of the plurality of first terminals extends along the first direction. [Appendix 6D] The semiconductor device according to Appendix 5D, wherein, when viewed along the first direction, the first pad portion of each of the plurality of first terminals overlaps the first die pad. [Appendix 7D] Each of the plurality of second terminals has a second pad portion covered with the sealing resin and a second lead portion connected to the second pad portion and partially exposed from the second side surface, When viewed along the second direction, the second lead portion of each of the plurality of second terminals is bent toward the bottom surface, The semiconductor device according to Appendix 5D or 6D, wherein, when viewed along the thickness direction, the second lead portion of each of the plurality of second terminals extends along the first direction. [Appendix 8D] The semiconductor device according to Appendix 7D, wherein, when viewed along the first direction, the second pad portion of each of the plurality of second terminals overlaps the second die pad. [Appendix 9D] The semiconductor device according to any one of appendixes 5D to 8D, wherein the second die pad overlaps the first die pad when viewed along the first direction. [Appendix 10D] The semiconductor device according to Appendix 9D, wherein the shortest distance from the first die pad to the top surface in the thickness direction is longer than the shortest distance from the first die pad to the bottom surface. [Appendix 11D] The semiconductor device according to any one of appendices 5D to 10D, wherein the first die pad, the second die pad, the plurality of first terminals, and the plurality of second terminals are located away from the third side surface. [Appendix 12D] the plurality of first terminals include a pair of first support terminals spaced apart from each other in the second direction, The semiconductor device according to Appendix 11D, wherein the pair of first support terminals are connected to both ends of the first die pad in the second direction. [Appendix 13D] the plurality of second terminals include a pair of second support terminals spaced apart from each other in the second direction; The semiconductor device according to Appendix 12D, wherein the pair of second support terminals are connected to both ends of the second die pad in the second direction. [Appendix 14D] a hole penetrating in the thickness direction is provided in a specific die pad of the first die pad and the second die pad on which the insulating element is mounted; A semiconductor device described in any one of Appendixes 1D to 13D, wherein, when viewed along the thickness direction, the hole is located between the insulating element and a specific semiconductor element, of the first semiconductor element and the second semiconductor element, that is mounted on the specific die pad. [Appendix 15D] A semiconductor device according to any one of appendices 1D to 14D, wherein at least one of the plurality of first terminals and the plurality of second terminals includes a dummy terminal that is not conductive to either the first semiconductor element or the second semiconductor element. [Appendix 16D] The semiconductor device according to any one of appendices 1D to 15D, wherein the insulating element is an inductive type.

[0216] [Appendix 1E] a first die pad disposed on one side in a first direction perpendicular to the thickness direction; a second die pad that is disposed on the other side of the first die pad in the first direction, that is spaced apart from the first die pad in the first direction, and that has a potential that is relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an isolation element mounted on either the first die pad or the second die pad, relaying transmission and reception of signals between the first circuit and the second circuit, and insulating the first circuit and the second circuit from each other; a plurality of first terminals including a portion located on the one side in the first direction with respect to the first die pad, arranged along a second direction perpendicular to both the thickness direction and the first direction, at least one of which is electrically connected to the first circuit; a plurality of second terminals including a portion located on the other side in the first direction with respect to the second die pad, arranged along the second direction, and at least one of which is electrically connected to the second circuit; a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the insulating element, the plurality of first terminals, and a portion of each of the plurality of second terminals, and that insulates the first die pad and the second die pad from each other; the sealing resin has a top surface facing a side where the first semiconductor element is located with respect to the first die pad in the thickness direction, and a bottom surface facing an opposite side to the top surface in the thickness direction; a first side surface located on the one side in the first direction and connected to the top surface and the bottom surface; the first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region and from which the plurality of first terminals are exposed; 10. A semiconductor device, wherein the surface roughness of each of the top surface, the bottom surface, the first region, and the second region is greater than the surface roughness of the third region. [Appendix 2E] the first region is inclined with respect to the top surface, the second region is inclined with respect to the bottom surface, The semiconductor device according to Appendix 1E, wherein the third region is located outward from the top surface and the bottom surface when viewed along the thickness direction. [Appendix 3E] the sealing resin has a second side surface located on the other side in the first direction and connected to the top surface and the bottom surface; the second side surface includes a fourth region connected to the top surface, a fifth region connected to the bottom surface, and a sixth region connected to the fourth region and the fifth region and from which the plurality of second terminals are exposed; The semiconductor device according to Appendix 1E or 2E, wherein the surface roughness of each of the top surface, the bottom surface, the fourth region, and the fifth region is greater than the surface roughness of the sixth region. [Appendix 4E] the fourth region is inclined with respect to the top surface, the fifth region is inclined with respect to the bottom surface, The semiconductor device according to Appendix 3E, wherein the sixth region is located outward from the top surface and the bottom surface when viewed along the thickness direction. [Appendix 5E] a recess recessed from the top surface is formed in the sealing resin; the sealing resin has a penetration surface that faces the same side as the top surface in the thickness direction and defines the recess, The semiconductor device of Appendix 3E or 4E, wherein the surface roughness of the penetration surface is less than the surface roughness of the top surface. [Appendix 6E] The semiconductor device according to any one of Appendixes 3E to 5E, wherein the surface roughness of each of the top surface and the bottom surface is not less than 5 μmRz and not more than 20 μmRz. [Appendix 7E] The semiconductor device according to any one of appendices 3E to 6E, wherein, when a power supply voltage is supplied to the first circuit and a power supply voltage is supplied to the second circuit, the power supply voltage supplied to the second circuit is greater than the power supply voltage supplied to the first circuit. [Appendix 8E] Each of the plurality of first terminals has a first pad portion covered with the sealing resin and a first lead portion connected to the first pad portion and partially exposed from the first side surface, When viewed along the second direction, the first lead portion of each of the plurality of first terminals is bent toward the bottom surface, The semiconductor device according to any one of appendices 3E to 7E, wherein, when viewed along the thickness direction, the first lead portion of each of the plurality of first terminals extends along the first direction. [Appendix 9E] Each of the plurality of second terminals has a second pad portion covered with the sealing resin and a second lead portion connected to the second pad portion and partially exposed from the second side surface, When viewed along the second direction, the second lead portion of each of the plurality of second terminals is bent toward the bottom surface, The semiconductor device according to Appendix 8E, wherein, when viewed along the thickness direction, the second lead portion of each of the plurality of second terminals extends along the first direction. [Appendix 10E] The semiconductor device according to Appendix 8E or 9E, wherein the second die pad overlaps the first die pad when viewed along the first direction. [Appendix 11E] the sealing resin has a third side surface and a fourth side surface that are spaced apart from each other in the second direction and are connected to the top surface and the bottom surface, The semiconductor device according to any one of appendices 8E to 10E, wherein the surface roughness of at least a portion of each of the third side surface and the fourth side surface is greater than the surface roughness of each of the third region and the sixth region. [Appendix 12E] The semiconductor device described in Appendix 11E, wherein the first die pad, the second die pad, the plurality of first terminals, and the plurality of second terminals are positioned away from both the third side surface and the fourth side surface. [Appendix 13E] the plurality of first terminals include a pair of first support terminals spaced apart from each other in the second direction, The semiconductor device according to Appendix 12E, wherein the pair of first support terminals are connected to both ends of the first die pad in the second direction. [Appendix 14E] the plurality of second terminals include a pair of second support terminals spaced apart from each other in the second direction; The semiconductor device according to Appendix 13E, wherein the pair of second support terminals are connected to both ends of the second die pad in the second direction. [Appendix 15E] a hole penetrating in the thickness direction is provided in a specific die pad of the first die pad and the second die pad on which the insulating element is mounted; A semiconductor device described in any one of Appendixes 1E to 14E, wherein, when viewed along the thickness direction, the hole is located between the insulating element and a specific semiconductor element, one of the first semiconductor element and the second semiconductor element, that is mounted on the specific die pad. [Appendix 16E] A semiconductor device described in any one of appendixes 1E to 15E, wherein at least one of the plurality of first terminals and the plurality of second terminals includes a dummy terminal that is not conductive to either the first semiconductor element or the second semiconductor element. [Appendix 17E] The semiconductor device according to any one of appendices 1E to 16E, wherein the insulating element is an inductive type. [Explanation of symbols]

[0217] A1,A2,A3,A4,A5,A6,A7,A8,A9,A10: Semiconductor device 11: First semiconductor element (control element) 11A: Electrode 111: First transmitter 112: Second transmission unit 113: Third receiving unit 114: 4th receiving unit 115: Logic section 116: First low voltage lockout unit 117: External error detection unit 12: Second semiconductor element (drive element) 12A: Electrode 121: First receiving unit 122: Second receiving unit 123: Third transmitter 124: 4th transmitter 125: Logic section 126: Driver section 127: Second low voltage lockout section 128: Overcurrent detection unit 129: OCP timer 13: Isolation element 13A: 1st electrode 13B: 2nd electrode 13C: Passivation film 13D: First membrane 13E:Second membrane 131: First transformer 132: 2nd transformer 133: Third Transformer 134: 4th Trans 2: Conductive support member 21: Pad gap 3: First die pad 31: First main surface 32: First back side 33: First opposing surface 331: First main surface side recess 332: First rear recess 333: First main surface side protrusion 334: 1st back side protrusion 335: 1st intermediate protrusion 34: First end surface 35:1st side 36: Periphery 361: 1st far corner 362: First near corner 362A: 1st end 363: First proximal edge 39: Hole 4: Second die pad 41: Second main surface 42: Second back side 43: Second opposing surface 431: Second main surface recess 432: Second rear recess 433: second main surface side protrusion 434: 2nd back side protrusion 435:Second intermediate protrusion 44:Second end surface 45:Second side 46: Periphery 461:Second far corner 462: Second near corner 462A: 2nd end 463: Second proximal edge 51: 1st terminal 51A: First edge terminal 511: First intermediate terminal 511A: Lead section 511B: Pad section 512: First side terminal 512A: Lead section 512B: Pad section 513: 1st support terminal 513A: Lead part 513B: Pad section 52: 2nd terminal 52A: Second edge terminal 521: Second intermediate terminal 521A: Lead section 521B: Pad section 522: Second side terminal 522A: Lead section 522B: Pad section 523:Second support terminal 523A: Lead section 523B: Pad section 523C: Connection part 61: First wire 61A: Specific first wire 62: Second wire 62A: Specific second wire 63: Third wire 64: 4th wire 7: Sealing resin 71:Top surface 711: Recess 711A: Penetrating surface 72: Bottom 73:1st side 731:First area 732:Second area 733: Third area 74:Second side 741: 4th area 742: 5th area 743:6th area 75:Third side 751:7th area 752:8th area 753:9th area 76:Fourth side 761: 10th area 762: 11th area 763: 12th area 791: First Gate Remains 792: Second Gate Remains 81: Lead frame 81A: Main surface 810A: 1st exposure area 81B: Back 810B: 2nd exposed area 811: Outer frame 812: Island 812A: 1st die pad 812B: Second die pad 813: 1st lead 814: Second Lead 815: Supporting Lead 816:Dambar 82: Resist 82A: First coating part 82B: Second coating part 86: Pot 87: Runner 88: Cavity 891: Gate 1 892: Second Gate 90:ECU

Claims

1. a first die pad disposed on one side in a first direction perpendicular to the thickness direction; a second die pad that is disposed on the other side of the first die pad in the first direction, that is spaced apart from the first die pad in the first direction, and that has a potential relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad; a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad; an isolation element mounted on either the first die pad or the second die pad, relaying transmission and reception of signals between the first circuit and the second circuit, and insulating the first circuit and the second circuit from each other; a plurality of first terminals including a portion located on the one side in the first direction with respect to the first die pad, arranged along a second direction perpendicular to both the thickness direction and the first direction, at least one of which is electrically connected to the first circuit; a plurality of second terminals including a portion located on the other side in the first direction with respect to the second die pad, arranged along the second direction, and at least one of which is electrically connected to the second circuit; a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the insulating element, the plurality of first terminals, and a portion of each of the plurality of second terminals, and that insulates the first die pad and the second die pad from each other; the first die pad is provided with a pair of first near corners located on a side facing the second die pad in the first direction, the pair of first near corner portions are provided on both sides of the first die pad in the second direction, When viewed in the thickness direction, each of the pair of first near corners is inclined with respect to the second direction.

2. the second die pad is provided with a pair of second near corner portions that individually face the pair of first near corner portions in the first direction, The semiconductor device according to claim 1 , wherein each of the pair of second near corners is inclined with respect to the second direction when viewed in the thickness direction.

3. When viewed in the thickness direction, each of the pair of first near corners is inclined toward a side away from the second die pad in the first direction as it extends outward in the second direction of the first die pad, 3. The semiconductor device according to claim 2, wherein, when viewed in the thickness direction, each of the pair of second near corners is inclined in the first direction toward a side away from the first die pad as it extends outward in the second direction of the second die pad.

4. When viewed in the thickness direction, each of the pair of first near corner portions is linear, The semiconductor device according to claim 3 , wherein each of the pair of second near corners is linear when viewed in the thickness direction.

5. a gap is formed between the first die pad and the second die pad as viewed in the thickness direction, the gap being sandwiched between the pair of first near corner portions and the pair of second near corner portions; The semiconductor device according to claim 4 , wherein the dimension of said gap in said first direction gradually decreases from the outside to the inside in said second direction.

6. the plurality of first terminals include a pair of first support terminals spaced apart from each other in the second direction, 6. The semiconductor device according to claim 1, wherein the pair of first support terminals are connected to both sides of the first die pad in the second direction.

7. the plurality of second terminals include a pair of second support terminals spaced apart from each other in the second direction, The semiconductor device according to claim 6 , wherein the pair of second support terminals are connected to both sides of the second die pad in the second direction.

8. When either the first die pad or the second die pad is referred to as a specific die pad, and either the first semiconductor element or the second semiconductor element mounted on the specific die pad is referred to as a specific semiconductor element, the insulating element is mounted on the specific die pad; the specific die pad is provided with a hole penetrating in the thickness direction, 8. The semiconductor device according to claim 1, wherein the hole is located between the insulating element and the specific semiconductor element when viewed in the thickness direction.

9. 9. The semiconductor device according to claim 1, wherein at least one of the plurality of first terminals and the plurality of second terminals includes a dummy terminal that is not electrically connected to either the first semiconductor element or the second semiconductor element.

10. 10. The semiconductor device according to claim 1, wherein said insulating element is an inductive type.

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