Plasma processing apparatus

Abstract

To provide a technique for properly performing plasma processing using a pulsed DC signal.SOLUTION: A plasma processing apparatus includes a plasma processing chamber, a substrate support disposed in the plasma processing chamber, the substrate support including a conductive base, an electrostatic chuck disposed on the conductive base, a chuck electrode disposed in the electrostatic chuck, a bias electrode disposed below the chuck electrode in the electrostatic chuck, an upper electrode disposed above the substrate support, a radio frequency (RF) generator electrically connected to the conductive base, the bias electrode, or the upper electrode and configured to generate an RF signal, a pulsed direct current (DC) generator electrically connected to the bias electrode and configured to generate a pulsed DC signal, and an RF filter connected between the bias electrode and the pulsed DC generator. And a ringing suppression circuit configured to suppress ringing superimposed on the pulsed DC signal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION An exemplary embodiment of the present disclosure relates to a plasma processing apparatus. [Background technology]

[0002] 2. Description of the Related Art Patent Document 1 describes a technique for performing plasma processing using a pulse voltage in a plasma processing apparatus. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0037119 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides techniques for properly performing plasma processing using pulsed DC signals. [Means for solving the problem]

[0005] In one exemplary embodiment of the present disclosure, a plasma processing apparatus includes: a plasma processing chamber; a substrate support disposed in the plasma processing chamber, the substrate support including a conductive base, an electrostatic chuck disposed on the conductive base, a chucking electrode disposed in the electrostatic chuck, and a bias electrode disposed in the electrostatic chuck below the chucking electrode; an upper electrode disposed above the substrate support; an RF generator electrically connected to the conductive base, the bias electrode, or the upper electrode and configured to generate an RF signal; a pulsed DC generator electrically connected to the bias electrode and configured to generate a pulsed DC signal; an RF filter connected between the bias electrode and the pulsed DC generator; and a ringing suppression circuit connected between the bias electrode and the pulsed DC generator and configured to suppress ringing superimposed on the pulsed DC signal. [Effects of the Invention]

[0006] According to one exemplary embodiment of the present disclosure, a technique for properly performing plasma processing using a pulsed DC signal can be provided. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a plasma processing system. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of a capacitively coupled plasma processing apparatus. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a substrate support and a power supply in the first exemplary embodiment. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of a first ringing suppression circuit. [Figure 5] FIG. 4 is a diagram showing an example of a sequence of first voltage pulses. [Figure 6] FIG. 10 is a diagram showing the results of measuring the substrate potential on the electrostatic chuck to which a pulsed DC signal is applied, in the cases where a ferrite core is disposed as a ringing suppression circuit between the pulsed DC generator and the substrate bias electrode, and where a ferrite core is not disposed. [Figure 7] FIG. 10 is a diagram showing an ion energy distribution function on a substrate during plasma processing in the absence of a ferrite core. [Figure 8] FIG. 10 is a diagram showing an ion energy distribution function on a substrate during plasma processing in the presence of a ferrite core. [Figure 9] FIG. 10 is a diagram showing the results of measuring the etching rate of a substrate in an etching process with and without a ferrite core. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a first ringing suppression circuit having a plurality of conductors. [Figure 11] 10A and 10B are diagrams illustrating an example of the configuration of a substrate support and a power supply in a second exemplary embodiment. [Figure 12]FIG. 10 is a diagram illustrating a configuration example of a second ringing suppression circuit. [Figure 13] FIG. 10 is a diagram showing an example of a sequence of second voltage pulses. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment of the present disclosure will be described.

[0009] In one exemplary embodiment, a plasma processing apparatus is provided, including: a plasma processing chamber; a substrate support disposed within the plasma processing chamber, the substrate support including a conductive base, an electrostatic chuck disposed on the conductive base, a chucking electrode disposed within the electrostatic chuck, and a bias electrode disposed within the electrostatic chuck below the chucking electrode; an upper electrode disposed above the substrate support; an RF generator electrically connected to the conductive base, the bias electrode, or the upper electrode and configured to generate an RF signal; a pulsed DC generator electrically connected to the bias electrode and configured to generate a pulsed DC signal; an RF filter connected between the bias electrode and the pulsed DC generator; and a ringing suppression circuit connected between the bias electrode and the pulsed DC generator and configured to suppress ringing superimposed on the pulsed DC signal.

[0010] In one exemplary embodiment, the ringing suppression circuit includes at least one ferrite core.

[0011] In one exemplary embodiment, the ringing suppression circuit includes a plurality of conductors connected in parallel and a plurality of ferrite cores, at least one of which is disposed on each of the plurality of conductors.

[0012] In one exemplary embodiment, the pulsed DC signal comprises a sequence of voltage pulses.

[0013] In one exemplary embodiment, the sequence of voltage pulses has negative polarity voltage levels.

[0014] In one exemplary embodiment, the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 1 MHz.

[0015] In one exemplary embodiment, the pulsed DC signal comprises a sequence of voltage pulses having a first voltage level for a first period within each cycle and a second voltage level for a second period within each cycle, the absolute value of the first voltage level being greater than the absolute value of the second voltage level.

[0016] In one exemplary embodiment, the first voltage level has a negative polarity.

[0017] In one exemplary embodiment, the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 1 MHz.

[0018] In one exemplary embodiment, the second voltage level comprises a zero voltage level.

[0019] In one exemplary embodiment, a plasma processing apparatus includes a plasma processing chamber; a substrate support disposed within the plasma processing chamber, the substrate support including: a base; an electrostatic chuck disposed on the base and having a substrate support surface and an edge ring support surface; an edge ring disposed on the edge ring support surface to surround a substrate on the substrate support surface; a substrate bias electrode disposed within the electrostatic chuck below the substrate support surface; and an edge ring bias electrode disposed within the electrostatic chuck below the edge ring support surface; an RF generator configured to generate an RF signal to generate a plasma in the plasma processing chamber; and a first pulsed DC generator electrically connected to the substrate bias electrode and configured to generate a first pulsed DC signal. a first RF filter connected between the substrate bias electrode and the first pulsed DC generation unit; a first ringing suppression circuit connected between the substrate bias electrode and the first pulsed DC generation unit and configured to suppress ringing superimposed on the first pulsed DC signal; a second pulsed DC generation unit electrically connected to the edge ring bias electrode and configured to generate a second pulsed DC signal; a second RF filter connected between the edge ring bias electrode and the second pulsed DC generation unit; and a second ringing suppression circuit connected between the edge ring bias electrode and the second pulsed DC generation unit and configured to suppress ringing superimposed on the second pulsed DC signal.

[0020] In one exemplary embodiment, the first ringing suppression circuit includes at least one first ferrite core.

[0021] In one exemplary embodiment, the second ringing suppression circuit includes at least one second ferrite core.

[0022] In one exemplary embodiment, the second ringing suppression circuit includes a plurality of second conductors connected in parallel and a plurality of second ferrite cores, at least one of which is disposed in each of the plurality of second conductors.

[0023] In one exemplary embodiment, the first ringing suppression circuit includes a plurality of first conductors connected in parallel and a plurality of first ferrite cores, at least one of which is disposed in each of the plurality of first conductors.

[0024] In one exemplary embodiment, the second ringing suppression circuit includes at least one second ferrite core.

[0025] In one exemplary embodiment, the second ringing suppression circuit includes a plurality of second conductors connected in parallel and a plurality of second ferrite cores, at least one of which is disposed in each of the plurality of second conductors.

[0026] In one exemplary embodiment, a plasma processing apparatus is provided, including: a plasma processing chamber; a substrate support disposed within the plasma processing chamber, the substrate support including a base, an electrostatic chuck disposed on the base, and a bias electrode disposed within the electrostatic chuck; an RF generator configured to generate an RF signal to generate a plasma in the plasma processing chamber; a pulsed DC generator electrically connected to the bias electrode and configured to generate a pulsed DC signal; and a ringing suppression circuit connected between the bias electrode and the pulsed DC generator, the ringing suppression circuit configured to suppress ringing generated between a first parasitic capacitor and a second parasitic capacitor from being superimposed on the pulsed DC signal, wherein the first parasitic capacitor is generated between the bias electrode and ground potential, and the second parasitic capacitor is generated between the ground potential and a node on a path from the pulsed DC generator to the bias electrode.

[0027] In one exemplary embodiment, the ringing suppression circuit includes at least one ferrite core.

[0028] In one exemplary embodiment, the ringing suppression circuit includes a plurality of conductors connected in parallel and a plurality of ferrite cores, at least one of which is disposed on each of the plurality of conductors.

[0029] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are designated by the same reference numerals, and redundant explanations will be omitted. Unless otherwise specified, the positional relationships, such as up, down, left, and right, will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and the actual ratios are not limited to the ratios shown in the drawings.

[0030] <An example of a plasma processing device> FIG. 1 is a diagram illustrating an exemplary configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing device 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing device 1 is an example of a substrate processing device. The plasma processing device 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0031] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), or surface wave plasma (SWP). Various types of plasma generating units may be used, including alternating current (AC) plasma generating units and direct current (DC) plasma generating units. In one embodiment, the AC signal (AC power) used in the AC plasma generating unit has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes a radio frequency (RF) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0032] The controller 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The controller 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the controller 2 may be included in the plasma processing apparatus 1. The controller 2 may include, for example, a computer 2a. The computer 2a may include, for example, a processing unit (CPU: Central Processing Unit) 2a1, a storage unit 2a2, and a communication interface 2a3. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. The program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The storage unit 2a2 may include a random access memory (RAM), a read only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0033] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0034] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0035] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called an edge ring support surface for supporting the ring assembly 112.

[0036] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 may include a conductive member and function as a conductive base. The conductive member of the base 1110 may function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode (chuck electrode) 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Alternatively, an RF or DC electrode may be disposed within the ceramic member 1111a, in which case the RF or DC electrode functions as the lower electrode. When a bias RF signal or DC signal, which will be described later, is connected to the RF or DC electrode, the RF or DC electrode is also called a bias electrode. Note that both the conductive member of the base 1110 and the RF or DC electrode may function as two lower electrodes.

[0037] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0038] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas between the backside of the substrate W and the central region 111a.

[0039] The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes an upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0040] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0041] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power), such as a source RF signal and a bias RF signal, to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0042] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0043] The second RF generating unit 31b is coupled to at least one lower electrode via at least one impedance matching circuit and configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generating unit 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0044] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0045] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of DC-based voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof. In one embodiment, a waveform generator for generating a sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0046] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0047] First Exemplary Embodiment FIG. 3 shows a configuration example of the substrate support 11 and the power supply 30 in the first exemplary embodiment. In one embodiment, the substrate support 11 has a chuck electrode 1111b and a substrate bias electrode 1111c inside an electrostatic chuck 1111. The substrate bias electrode 1111c may be disposed below the chuck electrode 1111b. A first pulsed DC generator 200 that generates a first pulsed DC signal is electrically connected to the substrate bias electrode 1111c. The first pulsed DC generator 200 may be an example of the first DC generator 32a described above. An RF generator 201 that generates an RF signal is electrically connected to the base 1110. The RF generator 201 may be an example of the first RF generator 31a and / or the second RF generator 31b described above. Note that in one embodiment, the RF generator 201 may be connected to the substrate bias electrode 1111c.

[0048] In one embodiment, a first RF filter 210 and a first ringing suppression circuit 211 are connected between the substrate bias electrode 1111c and the first pulsed DC generator 200. The substrate bias electrode 1111c is grounded, and a first parasitic capacitor C1 may be generated between the substrate bias electrode 1111c and the ground potential. A path 230 from the first pulsed DC generator 200 to the substrate bias electrode 1111c is grounded, and a second parasitic capacitor C2 may be generated between a node 231 on the path 230 and the ground potential. Furthermore, the base 1110 is grounded, and a third parasitic capacitor C3 may be generated between the base 1110 and the ground potential.

[0049] In one embodiment, the first RF filter 210 is configured to suppress the RF signal supplied from the RF generating unit 201 to the base 1110 from entering the first pulsed DC generating unit 200 via the path 230. The first RF filter 210 may remove signals of a specific frequency depending on the frequency of the RF signal. The first RF filter 210 may be a coil. The first RF filter 210 may be disposed outside the chamber 10.

[0050] Due to the coil inductance of the first RF filter 210, resonance occurs between the first parasitic capacitor C1 and the second parasitic capacitor C2, which may cause ringing (high-frequency components) in the first pulsed DC signal supplied from the first pulsed DC generating unit 200. In one embodiment, the first ringing suppression circuit 211 is configured to suppress ringing superimposed on the first pulsed DC signal. The first ringing suppression circuit 211 may be provided outside the chamber 10. The first ringing suppression circuit 211 may be connected between the first RF filter 210 and the first pulsed DC generating unit 200. The first ringing suppression circuit 211 may be connected between the first RF filter 210 and the substrate bias electrode 1111c.

[0051] 4, the first ringing suppression circuit 211 includes a first conductor 250 connected to the path 230 and a first ferrite core 251 disposed on the first conductor 250. The first ferrite core 251 can remove ringing superimposed on the first pulse DC signal.

[0052] In one embodiment, the first pulsed DC signal of the first pulsed DC generator 200 has a sequence of voltage pulses. FIG. 5 shows an example of the first voltage pulse sequence DC1 generated by the first pulsed DC generator 200. The first voltage pulse sequence DC1 has a pulse frequency in the range of 100 kV to 1 MHz. The first voltage pulse sequence DC1 has a repetition cycle T. The first voltage pulse sequence DC1 may have a first voltage level V1 during a first period T1 within each cycle T, and a second voltage level V2 serving as a reference voltage level during a second period T2 within each cycle T. The absolute value of the first voltage level V1 is greater than the absolute value of the second voltage level V2. In one embodiment, the first voltage level V1 has negative polarity. In one embodiment, the second voltage level V2 has a zero voltage level. In one embodiment, the first voltage level V1 is between 0 V and −15 kV.

[0053] <An example of a plasma processing method> The plasma processing performed using the plasma processing apparatus 1 includes an etching process in which a film on the substrate W is etched using plasma. In one embodiment, the plasma processing is executed by the control unit 2.

[0054] First, the substrate W is carried into the chamber 10 by the transport arm, placed on the substrate support portion 11 by the lifter, and held by suction on the substrate support portion 11 as shown in FIG.

[0055] Next, the processing gas is supplied to the shower head 13 by the gas supply unit 20, and is then supplied to the plasma processing space 10s from the shower head 13. The processing gas supplied at this time includes a gas that generates active species necessary for etching the substrate W.

[0056] In one embodiment, a source RF signal for plasma generation is supplied to the lower electrode and / or the upper electrode. A bias signal for ion attraction may be supplied to the lower electrode. At this time, the atmosphere in the plasma processing space 10s may be exhausted through the gas exhaust port 10e, and the pressure in the plasma processing space 10s may be reduced to a predetermined pressure. As a result, plasma is generated in the plasma processing space 10s, and the substrate W is etched.

[0057] 3, an RF signal is supplied to the base 1110 by the RF generating unit 201. A first pulsed DC signal is applied as a bias signal to the substrate bias electrode 1111c by the first pulsed DC generating unit 200. At this time, the first RF filter 210 prevents the RF signal supplied from the RF generating unit 201 to the base 1110 from entering the first pulsed DC generating unit 200 via the path 230. In addition, the first ringing suppression circuit 211 prevents ringing occurring between the first parasitic capacitor C1 and the second parasitic capacitor C2 from being superimposed on the first pulsed DC signal.

[0058] According to this exemplary embodiment, the plasma processing apparatus 1 includes a base 1110, an RF generating unit 201, a first pulsed DC generating unit 200, a first RF filter 210, and a first ringing suppression circuit 211. This makes it possible to suppress ringing from being superimposed on the pulsed DC signal applied from the first pulsed DC generating unit 200 to the substrate bias electrode 1111c. Therefore, plasma processing using the pulsed DC signal can be performed appropriately.

[0059] (Example) The substrate potential on the electrostatic chuck to which a pulsed DC signal was applied was measured for both cases where a ferrite core was placed between the pulsed DC generator and the substrate bias electrode as a ringing suppression circuit (with ferrite core) and where a ferrite core was not placed (without ferrite core). Figure 6 shows the measurement results. The substrate potential with the ferrite core was closer to the rectangular waveform of the pulsed DC signal than without the ferrite core, confirming that the ringing (high-frequency components) superimposed on the pulsed DC signal was reduced. It was also confirmed that the absolute value of the substrate potential with the ferrite core was higher (ΔV in Figure 6) than without the ferrite core. This confirms that the electrical energy of the pulsed DC signal was efficiently transmitted to the substrate when the ferrite core was present.

[0060] Figure 7 shows the ion energy distribution function (IEDF) on a substrate during plasma processing when there is no ferrite core. Figure 8 shows the ion energy distribution function on a substrate during plasma processing when there is a ferrite core. It can be seen that when there is no ferrite core, there are multiple peaks in the ion energy distribution function in the high ion energy (IE) region, whereas when there is a ferrite core, there is only one peak in the high ion energy (IE) region. This shows that when there is a ferrite core, the ion energy on the substrate is high and stable.

[0061] Figure 9 shows the results of measuring the etching rate (ER) of a substrate during etching processing with and without a ferrite core. The horizontal axis of Figure 9 represents the DC voltage of the pulsed DC signal. It can be seen that the etching rate with a ferrite core is higher than that without a ferrite core.

[0062] 10, the first ringing suppression circuit 211 may have a plurality of first conductors 250 connected in parallel and a plurality of first ferrite cores 251 arranged in each of the plurality of first conductors 250. In one embodiment, a plurality of first ferrite cores 251 may be arranged in each first conductor 250, or a single first ferrite core 251 may be arranged in each first conductor 250. In such a case, the pulsed DC signal reduces the current flowing in each first conductor 250, and as a result, heat generation in the first ferrite core 251 caused by eliminating ringing can be suppressed.

[0063] (Second Exemplary Embodiment) 11 shows an example of the configuration of the substrate support 11 and the power supply 30 in the second exemplary embodiment. In one embodiment, the substrate support 11 may have an edge ring bias electrode 1111d inside the electrostatic chuck 1111 in addition to a chuck electrode 1111b and a substrate bias electrode 1111c. The edge ring bias electrode 1111d may be disposed below the edge ring support surface. A second pulsed DC generator 300 that generates a second pulsed DC signal is electrically connected to the edge ring bias electrode 1111d.

[0064] In one embodiment, a second RF filter 310 and a second ringing suppression circuit 311 are connected between the edge ring bias electrode 1111d and the second pulsed DC generator 300. The edge ring bias electrode 1111d is grounded, and a fourth parasitic capacitor C4 may be generated between the edge ring bias electrode 1111d and ground potential. A path 330 from the second pulsed DC generator 300 to the edge ring bias electrode 1111d is grounded, and a fifth parasitic capacitor C5 may be generated between a node 331 on the path 330 and ground potential.

[0065] In one embodiment, the second RF filter 310 is configured to suppress the RF signal supplied from the RF generating unit 201 to the base 1110 from entering the second pulsed DC generating unit 300 via the path 330. The second RF filter 310 can remove signals of a specific frequency depending on the frequency of the RF signal. The second RF filter 310 can be a coil. The second RF filter 310 can be provided outside the chamber 10.

[0066] Due to the coil inductance of the second RF filter 310, resonance may occur between the fourth parasitic capacitor C4 and the fifth parasitic capacitor C5, causing ringing (high-frequency components) in the second pulsed DC signal. In one embodiment, the second ringing suppression circuit 311 is configured to suppress ringing superimposed on the second pulsed DC signal. The second ringing suppression circuit 311 may be provided outside the chamber 10. The second ringing suppression circuit 311 may be connected between the second RF filter 310 and the second pulsed DC generation unit 300. The second ringing suppression circuit 311 may be connected between the second RF filter 310 and the edge ring bias electrode 1111d.

[0067] 12 , the second ringing suppression circuit 311 includes a second conductor 350 connected to the path 330 and a second ferrite core 351 disposed on the second conductor 350. A plurality of second ferrite cores 351 may be disposed on each second conductor 350, or a single second ferrite core 351 may be disposed on each second conductor 350. The second ferrite core 351 can remove ringing superimposed on the second pulse DC signal.

[0068] The second pulsed DC signal of the second pulsed DC generator 300 has a sequence of voltage pulses. FIG. 13 shows an example of the second voltage pulse sequence DC2 generated by the second pulsed DC generator 300. The second voltage pulse sequence DC2 has a pulse frequency in the range of 100 kHz to 1 MHz. In one embodiment, the second voltage pulse sequence DC2 has the same repetition cycle T as the first voltage pulse sequence DC1. The second voltage pulse sequence DC2 may have a third voltage level V3 during a first period T1 within each cycle T and a fourth voltage level V4, which serves as a reference voltage level, during a second period T2 within each cycle T. The absolute value of the third voltage level V3 is greater than the absolute value of the fourth voltage level V4. In one embodiment, the third voltage level V3 has negative polarity. In one embodiment, the fourth voltage level V4 has a zero voltage level. In one embodiment, the third voltage level V3 is between 0V and -15kV.

[0069] Other configurations of the substrate support 11 and the power supply 30 in the second exemplary embodiment may be similar to those in the first exemplary embodiment.

[0070] According to this exemplary embodiment, it is possible to suppress ringing from being superimposed on the pulsed DC signal applied to the edge ring bias electrode 1111d from the second pulsed DC generating unit 300. Therefore, it is possible to properly perform plasma processing using the pulsed DC signal.

[0071] In the above embodiments, the ringing suppression circuit may have a damping resistor instead of or in addition to the ferrite core.

[0072] For example, although the above embodiment has been described using a capacitively coupled plasma device as an example, the present invention is not limited thereto and may be applied to other plasma devices. For example, an inductively coupled plasma device may be used instead of the capacitively coupled plasma device. In this case, the inductively coupled plasma device includes an antenna and a lower electrode. The lower electrode is disposed within the substrate support, and the antenna is disposed above or at the top of the chamber. In one embodiment, the RF power supply 31 may be electrically connected to the antenna and may supply an RF signal to the antenna.

[0073] Embodiments of the present disclosure further include the following aspects.

[0074] (Appendix 1) a plasma processing chamber; a substrate support disposed within the plasma processing chamber, the substrate support including: a conductive base; an electrostatic chuck disposed on the conductive base; a chucking electrode disposed within the electrostatic chuck; and a bias electrode disposed within the electrostatic chuck below the chucking electrode; an upper electrode disposed above the substrate support; an RF generator electrically connected to the conductive base, the bias electrode, or the upper electrode and configured to generate an RF signal; a pulsed DC generator electrically connected to the bias electrode and configured to generate a pulsed DC signal; an RF filter connected between the bias electrode and the pulsed DC generator; a ringing suppression circuit connected between the bias electrode and the pulsed DC generator and configured to suppress ringing superimposed on the pulsed DC signal; A plasma processing apparatus comprising:

[0075] (Appendix 2) 2. The plasma processing apparatus of claim 1, wherein the ringing suppression circuit includes at least one ferrite core.

[0076] (Appendix 3) The ringing suppression circuit includes: a plurality of conductors connected in parallel; 3. The plasma processing apparatus according to claim 1, further comprising: a plurality of ferrite cores, at least one of which is disposed on each of the plurality of conductors.

[0077] (Appendix 4) 4. The plasma processing apparatus of claim 1, wherein the pulsed DC signal comprises a sequence of voltage pulses.

[0078] (Appendix 5) 5. The plasma processing apparatus of claim 4, wherein the sequence of voltage pulses has negative voltage levels.

[0079] (Appendix 6) 6. The plasma processing apparatus of claim 4, wherein the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 1 MHz.

[0080] (Appendix 7) the pulsed DC signal comprises a sequence of voltage pulses having a first voltage level for a first period within each cycle and a second voltage level for a second period within each cycle; 4. The plasma processing apparatus according to claim 1, wherein an absolute value of the first voltage level is greater than an absolute value of the second voltage level.

[0081] (Appendix 8) 8. The plasma processing apparatus of claim 7, wherein the first voltage level has a negative polarity.

[0082] (Appendix 9) 9. The plasma processing apparatus of claim 7 or 8, wherein the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 1 MHz.

[0083] (Appendix 10) 10. The plasma processing apparatus of claim 7, wherein the second voltage level has a zero voltage level.

[0084] (Appendix 11) a plasma processing chamber; a substrate support disposed within the plasma processing chamber, the substrate support comprising: The base and an electrostatic chuck disposed on the base and having a substrate support surface and an edge ring support surface; an edge ring disposed on the edge ring support surface to surround the substrate on the substrate support surface; a substrate bias electrode disposed within the electrostatic chuck below the substrate support surface; the substrate support including an edge ring bias electrode disposed within the electrostatic chuck below the edge ring support surface; an RF generator configured to generate an RF signal to generate a plasma in the plasma processing chamber; a first pulsed DC generator electrically connected to the substrate bias electrode and configured to generate a first pulsed DC signal; a first RF filter connected between the substrate bias electrode and the first pulsed DC generator; a first ringing suppression circuit connected between the substrate bias electrode and the first pulsed DC generation unit and configured to suppress ringing superimposed on the first pulsed DC signal; a second pulsed DC generator electrically connected to the edge ring bias electrode and configured to generate a second pulsed DC signal; a second RF filter connected between the edge ring bias electrode and the second pulsed DC generator; a second ringing suppression circuit connected between the edge ring bias electrode and the second pulsed DC generation unit and configured to suppress ringing superimposed on the second pulsed DC signal; A plasma processing apparatus comprising:

[0085] (Appendix 12) 12. The plasma processing apparatus of claim 11, wherein the first ringing suppression circuit includes at least one first ferrite core.

[0086] (Appendix 13) 13. The plasma processing apparatus according to claim 11, wherein the second ringing suppression circuit includes at least one second ferrite core.

[0087] (Appendix 14) The second ringing suppression circuit includes: a plurality of second conductors connected in parallel; and a plurality of second ferrite cores, at least one of which is disposed in each of the plurality of second conductors.

[0088] (Appendix 15) The first ringing suppression circuit includes: a plurality of first conductors connected in parallel; and a plurality of first ferrite cores, at least one of which is disposed in each of the plurality of first conductors.

[0089] (Appendix 16) 16. The plasma processing apparatus of claim 15, wherein the second ringing suppression circuit includes at least one second ferrite core.

[0090] (Appendix 17) The second ringing suppression circuit includes: a plurality of second conductors connected in parallel; 17. The plasma processing apparatus according to claim 15, further comprising: a plurality of second ferrite cores, at least one of which is disposed in each of the plurality of second conductors.

[0091] (Appendix 18) a plasma processing chamber; a substrate support disposed within the plasma processing chamber, the substrate support including a base, an electrostatic chuck disposed on the base, and a bias electrode disposed within the electrostatic chuck; an RF generator configured to generate an RF signal to generate a plasma in the plasma processing chamber; a pulsed DC generator electrically connected to the bias electrode and configured to generate a pulsed DC signal; a ringing suppression circuit connected between the bias electrode and the pulsed DC generation unit, configured to suppress ringing occurring between a first parasitic capacitor and a second parasitic capacitor from being superimposed on the pulsed DC signal, wherein the first parasitic capacitor occurs between the bias electrode and a ground potential, and the second parasitic capacitor occurs between a node on a path from the pulsed DC generation unit to the bias electrode and a ground potential; A plasma processing apparatus comprising:

[0092] (Appendix 19) 19. The plasma processing apparatus of claim 18, wherein the ringing suppression circuit includes at least one ferrite core.

[0093] (Appendix 20) The ringing suppression circuit includes: a plurality of conductors connected in parallel; 20. The plasma processing apparatus according to claim 18 or 19, further comprising: a plurality of ferrite cores, at least one of which is disposed on each of the plurality of conductors.

[0094] The above embodiments are described for the purpose of explanation and are not intended to limit the scope of the present disclosure. Various modifications can be made to the above embodiments without departing from the scope and spirit of the present disclosure. For example, some components in one embodiment can be added to other embodiments. Also, some components in one embodiment can be replaced with corresponding components in other embodiments. [Explanation of symbols]

[0095] 1: Plasma processing apparatus, 10: Chamber, 11: Substrate support, 30: Power supply, 1110: Base, 1111: Electrostatic chuck, 1111c: Substrate bias electrode, 200: First pulsed DC generator, 201: RF generator, 210: First RF filter, 211: First ringing suppression circuit, W: Substrate

Claims

1. Plasma processing chamber and A substrate support portion is disposed within the plasma processing chamber, A bias electrode disposed within the substrate support portion, A voltage pulse generation unit is electrically connected to the bias electrode and configured to generate a voltage pulse signal, A ringing suppression circuit is connected between the bias electrode and the voltage pulse generation unit and configured to suppress ringing superimposed on the voltage pulse signal, A plasma processing device, including a plasma treatment device.

2. The plasma processing apparatus according to claim 1, wherein the ringing suppression circuit includes at least one ferrite core.

3. The ringing suppression circuit described above is Multiple conductors connected in parallel, The plasma apparatus according to claim 1, further comprising a plurality of ferrite cores, each of the plurality of conductors, having at least one ferrite core disposed on each of the plurality of conductors.

4. The plasma processing apparatus according to any one of claims 1 to 3, wherein the voltage pulse signal has a sequence of voltage pulses.

5. The plasma processing apparatus according to claim 4, wherein the sequence of voltage pulses has a negative polarity voltage level.

6. The plasma processing apparatus according to claim 5, wherein the sequence of voltage pulses has a pulse frequency in the range of 100 kHz to 1 MHz.

7. The voltage pulse signal has a sequence of voltage pulses having a first voltage level during a first period within each cycle and a second voltage level during a second period within each cycle. The plasma processing apparatus according to any one of claims 1 to 3, wherein the absolute value of the first voltage level is greater than the absolute value of the second voltage level.

8. The plasma processing apparatus according to claim 7, wherein the first voltage level has negative polarity.

9. The plasma processing apparatus according to claim 8, wherein the sequence of voltage pulses has pulse frequencies in the range of 100 kHz to 1 MHz.

10. The plasma apparatus according to claim 9, wherein the second voltage level has a zero voltage level.

11. Plasma processing chamber and A substrate support portion is disposed within the plasma processing chamber and has a substrate support surface and an edge ring support surface, Within the substrate support portion, a substrate bias electrode is positioned below the substrate support surface, Within the substrate support portion, an edge ring bias electrode is positioned below the edge ring support surface, A first voltage pulse generation unit is electrically connected to the substrate bias electrode and configured to generate a first voltage pulse signal, A first ringing suppression circuit is connected between the substrate bias electrode and the first voltage pulse generation unit and configured to suppress ringing superimposed on the first voltage pulse signal, A second voltage pulse generation unit is electrically connected to the edge ring bias electrode and configured to generate a second voltage pulse signal, A second ringing suppression circuit is connected between the edge ring bias electrode and the second voltage pulse generation unit and configured to suppress ringing superimposed on the second voltage pulse signal, A plasma processing device, including a plasma treatment device.

12. The plasma processing apparatus according to claim 11, wherein the first ringing suppression circuit includes at least one first ferrite core.

13. The plasma processing apparatus according to claim 12, wherein the second ringing suppression circuit includes at least one second ferrite core.

14. The second ringing suppression circuit described above is: Multiple second conductors connected in parallel, The plasma apparatus according to claim 11, further comprising a plurality of second ferrite cores, each of the plurality of second conductors, at least one of which is disposed on each of the plurality of second conductors.

15. The first ringing suppression circuit described above is: Multiple first conductors connected in parallel, The plasma apparatus according to claim 11, comprising a plurality of first ferrite cores, each of the plurality of first conductors, at least one of which is disposed on each of the plurality of first conductors.

16. The plasma processing apparatus according to claim 15, wherein the second ringing suppression circuit includes at least one second ferrite core.

17. The second ringing suppression circuit is, Multiple second conductors connected in parallel, The plasma apparatus according to claim 15, comprising a plurality of second ferrite cores, each of the plurality of second conductors, at least one of which is disposed on each of the plurality of second conductors.

18. A plasma processing chamber, A substrate support portion is disposed within the plasma processing chamber and has a substrate support surface and an edge ring support surface, Within the substrate support portion, an edge ring bias electrode is positioned below the edge ring support surface, A voltage pulse generation unit is electrically connected to the edge ring bias electrode and configured to generate a voltage pulse signal, A ringing suppression circuit is connected between the edge ring bias electrode and the voltage pulse generation unit and configured to suppress ringing superimposed on the voltage pulse signal, A plasma processing device, including a plasma treatment device.

19. The plasma processing apparatus according to claim 18, wherein the ringing suppression circuit includes at least one first ferrite core.

20. The ringing suppression circuit described above is Multiple second conductors connected in parallel, The plasma apparatus according to claim 18, further comprising a plurality of second ferrite cores, each of the plurality of second conductors, at least one of which is disposed on each of the plurality of second conductors.

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