Modular multilevel cascaded converter and method of controlling the same

Abstract

To prevent such a problem that a predetermined volts alternating current required for system interconnection cannot be output from an SST when operation is continued in the case where a part of cells fails.SOLUTION: A plurality of cells each including an AC-DC converter ACDC, a primary-side DC capacitor C1, an insulated DC-DC converter DCDC, and a secondary-side DC capacitor C2 are provided per phase. A plurality of DC systems to which a plurality of secondary side DC capacitors C2 are connected in parallel are provided, and voltages of the plurality of DC systems are supplied to a load or a power source. When a cell fails, the control unit of the AC / DC converter ACDC increases the output voltage on the AC system side of the cell connected to the same DC system as the failed cell, and decreases the output voltage on the AC system side of the cell connected to the other DC system. The third harmonic is superimposed on the AC output voltage of the cell connected to the same DC system as the failed cell, and the third harmonic in the opposite direction is superimposed on the AC output voltage of the cell connected to the DC system different from the failed cell.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a modular multilevel cascade converter (MMCC) of single star bridge cells (SSBC) connected to a three-phase AC system, in which a bidirectional isolated DC / DC converter (isolated DC / DC converter) or the like is connected to the DC side of the full bridge cells (AC / DC converter) that make up the converter, enabling multiple DC systems to be output. [Background technology]

[0002] A prime example of this configuration is the solid-state transformer (SST). Figure 1 shows an SST consisting of m = 4 cells per phase, which combines an MMCC-SSBC configured by cascading AC-DC converters ACDC and an isolated DC-DC converter DCDC using the dual active bridge (DAB) method. A cell consists of an AC-DC converter ACDC, an isolated DC-DC converter DCDC, and capacitors C1 and C2.

[0003] High-voltage AC power is converted into DC power using series-connected cells, and the DC power is converted into high-frequency AC power, which is then insulated and rectified using a transformer to convert back into DC power. Reverse power interchange is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

[0004] Isolated DC / DC converter DCDC: By connecting the output terminals of 3m / x = 6 units in parallel, it is possible to output x = 2 isolated DC systems with the same capacity. By connecting multiple DC systems in series, it is also possible to obtain a high DC voltage.

[0005] In cases where high reliability is required, such as when important loads are connected to the DC grid, it is necessary to realize a fault tolerance function that allows operation to continue even if some of the cells that make up the SST fail.

[0006] If a fault occurs inside a cell, such as an open or short circuit caused by a broken conductor, or an open or short circuit in one of the switching devices, the output terminal on the three-phase AC system side can be short-circuited using the remaining healthy switching devices or a separately provided mechanical switch, and the output terminal on the DC system side can be opened, thereby preventing the effects of the fault from spreading to other cells.

[0007] However, the next problem is balancing the voltage of the DC capacitor (primary DC voltage) connected to the AC grid side of the remaining cells' high-frequency transformers, and the voltage of each stage connected in series at the output. Also, as the ratio of faulty cells to the total number of cells increases, the MMCC-SSBC is more likely to be unable to output the AC voltage required for grid connection.

[0008] Patent Document 6 discloses a control method for uniformly maintaining the primary DC voltage inside the cell and the voltage of the output DC system in the SST shown in Figure 1. The control method in Patent Document 6 is configured by the following feedback control.

[0009] (1) Primary side DC voltage average value control If the average value of the primary side DC voltage is lower than the command value, active power is input from the AC grid; if it is higher, the AC output current of the MMCC-SSBC is adjusted so that active power is output to the AC grid.

[0010] (2) Primary side DC voltage phase balance control The primary DC voltage of a cell connected to a phase of the AC system is compared with the average primary DC voltage of all cells connected to the same phase, and the AC output voltage of the AC / DC converter for that cell is adjusted. If the primary DC voltage of a cell is high and power is flowing in from the AC system, the AC voltage is reduced to suppress charging. If the power is flowing in the opposite direction to the AC system, the AC voltage is increased to encourage discharge.

[0011] (3) Individual balance control of primary side DC voltage The current of the isolated DC / DC converter is controlled so that the primary DC voltage of all cells connected to a DC system is equal. Cells with a high primary DC voltage increase the power transferred from the AC system to the DC system via the isolated DC / DC converter, while cells with a low primary DC voltage reduce the power transferred from the AC system to the DC system via the isolated DC / DC converter.

[0012] (4) Secondary DC voltage individual control The power transfer from the isolated DC / DC converters (DCDC) of all cells connected to the corresponding DC system is adjusted so that the voltage of the DC capacitor inside the cell that is closer to the DC system than the high-frequency transformer, i.e., the voltage of the DC system (secondary DC voltage), is equal to the command value.

[0013] Patent documents 1, 2, and 3 disclose a method in which, when a cell constituting a converter fails, a switch connected to one of the input / output terminals of the cell is turned on to short-circuit the terminals, thereby preventing the effects of the failure from spreading to other cells and allowing operation to continue.

[0014] Furthermore, Patent Document 1 assumes that either AC or DC power is input and DC power is output, and is configured with the cells on the output side connected in series (the input side can be either parallel or series).If some of the cells fail, the DC capacitor voltage on the output side of the series-connected cells can be increased to obtain an output voltage from the converter with the same amplitude as before the failure.

[0015] Patent Document 2 describes a technology that assumes mutual conversion of two types of AC power and applies it to a configuration in which both the input and output terminals of the cells are connected in series. If one of the cells fails, the switch on the failed side of the input and output terminals of the relevant cell is short-circuited, and the other terminal is controlled to maintain a constant DC capacitor voltage inside the cell, thereby enabling the converter to obtain an output voltage with the same amplitude as before the failure.

[0016] Furthermore, in Patent Document 2, the waveform before the failure is shown in Figure 5, and the waveform after the failure is shown in Figure 6. The pulse width of the AC output voltages (Vo2 to Vo4) of the non-failed cells increases. In other words, the AC output voltage of the converter is made equal before and after the failure by operating with the highest priority on increasing amplitude even if the distortion of the AC output voltage of the non-failed cells worsens, and by removing the distortion of the failed cell.

[0017] Patent Document 3 describes a technology that assumes the mutual conversion of two DC power sources, and applies it to a configuration in which one cell is connected in parallel and the other in series within the unit that makes up the converter. If one of the cells fails, the voltage of the DC capacitor on the parallel-connected side of the cells is not changed, but the voltage of the DC capacitor on the series-connected side is increased. With Patent Document 3, the voltage of the DC system on the series-connected side does not change before and after the failure. Furthermore, the input and output power are equal, allowing for continued stable operation.

[0018] Non-Patent Document 1 and Patent Documents 4 and 5 disclose a technique for lowering the peak of the voltage command value by superimposing a third harmonic on the output phase voltage command value, thereby enabling an AC voltage of larger amplitude to be output, and preventing the superimposed third harmonic from affecting the line voltage.

[0019] Patent Documents 7 and 8 disclose techniques for superimposing a zero-phase sequence voltage of the fundamental wave so that the amplitude of the AC voltage output by the SST can be maintained even when some cells fail. [Prior art documents] [Patent documents]

[0020] [Patent Document 1] Patent No. 6476318 [Patent Document 2] Patent No. 6725758 [Patent Document 3] Patent No. 6976426 [Patent Document 4] Japanese Patent Application Publication No. 3-107373 [Patent Document 5] Japanese Patent Publication No. 2022-107230 [Patent Document 6] Patent application No. 2023-191251 [Patent Document 7] Patent application No. 2023-215645 [Patent Document 8] Patent application No. 2023-215646 [Non-patent literature]

[0021] [Non-Patent Document 1] "Sensorless Vector Control of AC Drive Systems," Institute of Electrical Engineers of Japan, Committee on Sensorless Vector Control, Ohmsha, pp. 54 (2016) Summary of the Invention [Problem to be solved by the invention]

[0022] In order to operate an SST stably, it is necessary to improve the stability of the primary side DC voltage inside the cell and the voltage balance of the output DC system even when a power imbalance in each DC system, a sudden load change, or a cell failure occurs.One possible method for achieving this is the method described in Patent Document 6 (2) in which feedforward adjustment is made to the AC output voltage of the AC / DC converter ACDC of the cell for the primary side DC voltage intra-phase balance control.

[0023] In addition, the following method can be considered to maintain the DC voltage of each DC system uniform. Other cells connected to the DC grid with the faulty cell will output a larger AC voltage than the remaining cells. The amplitude ratio of the output voltage on the AC side is other cells in the DC system where the faulty cell is located: remaining cells = 3m:3m-x (=6:5).

[0024] As a result, the power transferred from the AC system to each DC system can be made equal, and the primary voltage inside the cell and the DC voltage of each secondary DC system are both balanced.

[0025] However, the above methods require increasing the AC output voltage of the cell's AC-DC converter (ACDC). However, the maximum amplitude of the cell's AC output voltage is limited by the primary-side DC voltage. Therefore, there is a limit to how much the cell's AC output voltage can be increased. Lowering the AC output voltage of cells connected to a DC grid without a faulty cell can also maintain an equal DC voltage in each DC grid, and is not limited by the primary-side DC voltage. However, since the AC output voltage of the entire MMCC-SSBC drops due to a cell failure, the AC output voltage of even more cells must be lowered, increasing the risk that the MMCC-SSBC will not be able to output the AC voltage required for grid connection.

[0026] One possible solution is to lower the AC system voltage by injecting reactive power into the AC system, thereby lowering the AC voltage required for grid interconnection. However, changing the AC system voltage will affect other devices connected to the same system. If a reactive power compensator is connected nearby, not only will it not be possible to lower the AC voltage, but unnecessary reactive power will be exchanged between the reactive power compensator and the system, resulting in losses.

[0027] If the primary-side DC voltage is increased in advance, the AC output voltage of the AC / DC converter (ACDC) can be freely increased. However, this requires a corresponding cell voltage resistance design, and components with high voltage resistance must be selected, which increases cost and size. Furthermore, switching losses also increase steadily. Methods such as those described in Patent Documents 1 and 3 can be considered, in which the cell primary-side DC voltage is increased only when some cells fail. However, this still requires a cell voltage resistance design, and switching losses in the event of a failure are unavoidable.

[0028] To apply the technology of Patent Document 2, it is necessary to keep the primary side DC voltage constant using the full-bridge inverter of the failed cell. Therefore, if a failure occurs in the full-bridge inverter, the technology of Patent Document 2 cannot be applied.

[0029] Furthermore, in Patent Document 2, the AC output voltage of all cells that are not failing is increased (the pulse width is increased). Considering the case of Figure 1, in order to maintain equal power in DC system 21 and DC system 22, the AC output voltage of cells V11 to W12 should be increased, but the AC output voltage of cells U21 to W22 must not be increased. In this respect, too, the technology of Patent Document 2 cannot be applied as is.

[0030] Non-Patent Document 1, Patent Document 4, and Patent Document 5 can also be applied to MMCC-SSBCs. However, a problem exists in that third-order harmonics are superimposed on the neutral point of the MMCC-SSBC. Fluctuations in the neutral point potential cause common-mode current to flow through stray capacitance, potentially resulting in false detection of ground faults and adversely affecting other devices connected to the same AC system. Since SSTs are designed to be directly connected to high-voltage AC systems (6.6 kV or higher) without a transformer, large common-mode currents flow even with small stray capacitance. The method described in Patent Document 4 also superimposes many ninth-order and higher harmonics, further increasing the common-mode current and increasing the risk of problems.

[0031] The zero-phase voltage superimposed in Patent Documents 7 and 8 is a fundamental wave. Therefore, the common-mode current flowing out from the stray capacitance is one-third that of Non-Patent Document 1 and Patent Documents 4 and 5, thereby reducing the impact. However, Patent Documents 7 and 8 assume that all cells are connected in parallel on the DC grid side. They do not mention maintaining voltage balance when connected in series.

[0032] As shown above, when continuing operation in the event of a failure in one of the cells, the challenge is to prevent problems such as the SST not being able to output the specified AC voltage required for grid connection, not being able to transfer power according to the command value, outputting distorted current to the AC side, or having to apply a gate block due to an overcurrent, which causes the device to stop. [Means for solving the problem]

[0033] The present invention has been devised in view of the above-mentioned problems of the prior art, and one aspect thereof is a power supply system including m (m is an integer of 2 or more) cells per phase, each cell including an AC / DC converter connected to an AC system, a primary-side DC capacitor connected to the DC side of the AC / DC converter, an isolated DC / DC converter having one DC side connected to the primary-side DC capacitor, and a secondary-side DC capacitor connected to the other DC side of the isolated DC / DC converter, and x (x is an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel, and a power supply system for supplying voltages of the plurality of DC systems to a load or a power source. a control unit of the AC-DC converter, when a cell fails, increases an output voltage on the AC system side of the cell connected to the same DC system as the failed cell, decreases an output voltage on the AC system side of the cell connected to the other DC system, superimposes a third harmonic on the AC output voltage of the cell connected to the same DC system as the failed cell, and superimposes an opposite third harmonic on the AC output voltage of the cell connected to the DC system different from the failed cell.

[0034] In one aspect, the control unit of the AC-DC converter includes a second multiplier that multiplies each phase voltage command value of the AC-DC converter by 3m / (3m-x+1) when one of the cells fails, by (3m-x) / (3m-x+1) when one of the cells fails, by 1 when one of the cells fails, by 3m / (3m+1-x) when one of the cells fails, by (3m-x) / (3m-x+1) when one of the cells fails, and by 1 when there is no failed cell; the primary side DC voltage intra-phase balance control unit outputs a primary side DC voltage intra-phase balance control value based on the primary side DC voltage intra-phase average value of each phase and the primary side DC voltage of each cell; and a first subtractor outputs each cell voltage command value by subtracting the primary side DC voltage intra-phase balance control value from the output of the first adder, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0035] In one aspect, the control unit of the AC-DC converter comprises: a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-x+1) / (3m-x-2) as a coefficient for the phase to which the faulty cell is connected and 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary side DC voltage of all cells and outputs the result as the voltage command value for each phase.

[0036] In one aspect, when two of the cells connected to the same DC system in the same phase fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-2x+2) / (3m-2x-4) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the coefficient a third adder that adds the zero-phase voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltage of all cells and outputs the result as the voltage command value for each phase; a first multiplier that multiplies 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and (3m-2x) / (3m+2-2x) for the cell connected to a DC system different from the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-2x) for the cells connected to the same DC system as the failed cell, by -3(m-2x) / ((x-1)(3m+2-2x)) for the cells connected to the same phase as the failed cell or to a different DC system, and by -3m / (x-1)(3m+2-2x) for the cells connected to a different phase than the failed cell or to a different DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0037] In one aspect, when two of the cells connected to different phases but the same DC system fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-2x+2) / (3m-2x-1) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the a computing unit that outputs a zero-phase voltage based on a coefficient; a third adder that adds the zero-phase voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltage of all cells and outputs the result as the voltage command value for each phase; a first multiplier that multiplies 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and (3m-2x) / (3m+2-2x) for the cell connected to the DC system different from the failed cell, and a third multiplier that multiplies the third harmonic by 3m / (3m+2-2x) for the cells connected to the same DC system as the failed cell, by -3(mx) / ((x-1)(3m+2-2x)) for the cells connected to the same phase as the failed cell or to a different DC system, and by -3m / (x-1)(3m+2-2x) for the cells connected to a different phase than the failed cell or to a different DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0038] In one aspect, when two cells connected to the same phase but different DC systems fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-x+2) / (3m-x-4) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the coefficient a third adder that adds the zero-phase voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all cells and outputs the result as the voltage command value for each phase; a first multiplier that multiplies 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for the cells connected to the same DC system as the failed cell, by -6(mx) / ((x-2)(3m+2-x)) for the cells connected to the same phase as the failed cell or to a different DC system, and by -6m / (x-2)(3m+2-x) for the cells connected to a different phase than the failed cell or to a different DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder and outputs each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0039] In one aspect, when two of the cells connected to different phases and different DC systems fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-x+2) / (3m-x-1) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the a computing unit that outputs a zero-phase voltage based on a coefficient; a third adder that adds the zero-phase voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all cells and outputs the result as the voltage command value for each phase; a first multiplier that multiplies 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, by -3(2m-x) / ((x-2)(3m+2-x)) for the cell connected to the same phase as the failed cell or to a different DC system, and by -6m / (x-2)(3m+2-x) for the cell connected to a different phase than the failed cell or to a different DC system; and a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder and outputs each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value. [Effects of the Invention]

[0040] According to the present invention, when continuing operation in the event of a failure in one of the cells, it is possible to prevent problems such as the SST being unable to output the specified AC voltage required for grid connection, being unable to transfer power according to the command value, outputting distorted current to the AC side, and the need to apply a gate block due to an overcurrent, which causes the device to stop. [Brief explanation of the drawings]

[0041] [Figure 1] FIG. 2 is a diagram showing an example of a main circuit configuration of the modular multilevel cascade converter of the first embodiment. [Figure 2] A diagram showing the main circuit configuration when a failure occurs in cell U11, causing the AC side to be short-circuited and the DC side to be open. [Figure 3] FIG. 2 is a block diagram showing a control unit of the AC-DC converter according to the first embodiment. [Figure 4] FIG. 10 is a block diagram showing a voltage command value calculation unit according to a second embodiment. [Figure 5] FIG. 10 is a diagram showing an output voltage waveform of the AC-DC converter when the second embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0042] Hereinafter, first to third embodiments of the modular multilevel cascade converter of the present invention will be described in detail with reference to FIGS.

[0043] [Embodiment 1] Here, m (m: an integer of 2 or more) is the number of cells per phase, and x (x: an integer of 2 or more) is the number of DC systems to output. In Figure 1, m=4 and x=2.

[0044] Figure 1 shows the main circuit configuration of a modular multilevel cascade converter (SST) that generates multiple DC systems. As shown in Figure 1, the SST includes an AC-DC converter (ACDC) connected to a high-voltage AC system via reactors Lu, Lv, and Lw; a primary-side DC capacitor C1 connected to the DC side of the AC-DC converter (ACDC); an isolated DC-DC converter (DCDC) with one DC side connected to the primary-side DC capacitor C1; and a secondary-side DC capacitor C2 connected to the other DC side of the isolated DC-DC converter (DCDC). The AC-DC converter (ACDC) and the isolated DC-DC converter (DCDC) can be appropriately selected from conventionally known converters. Because the AC-DC converter (ACDC) and the isolated DC-DC converter (DCDC) are well known, detailed description thereof will be omitted here.

[0045] Here, the AC-DC converter ACDC, primary side DC capacitor C1, isolated DC-DC converter DCDC, and secondary side DC capacitor C2 constitute one cell. In FIG. 1, there are U-phase cells U11 to U22, V-phase cells V11 to V22, and W-phase cells W11 to W22. The AC sides of the cells of each phase are connected in series. The cells U11 to W12 are connected in parallel to form a DC system 21, and the DC sides of the cells U21 to W22 are connected in parallel to form a DC system 22. The DC systems 21 and 22 are connected in series. V ACU11 ~V ACW22 indicates the AC output voltage of each cell, and V DC21 , V DC22 indicates the DC system voltage detection value, and I DC21 , I DC22 indicates the detected DC system current value.

[0046] In the first embodiment, the secondary side DC capacitors C2 are connected in parallel to form one DC system V dc21 or DC system V dc22 In addition, the DC system V dc21 , or V dc22 , or V dc21 +V dc22 The power supply supplies the load or power source. Each cell (AC-DC converter ACDC, isolated DC-DC converter DCDC) is equipped with a switching element. The voltage and current of each cell can be controlled by turning the switching element on and off.

[0047] In this embodiment 1, the above-mentioned (3) individual balance control of primary-side DC voltage and (4) individual control of secondary-side DC voltage are applied as they are. However, modifications are made to (1) average value control of primary-side DC voltage and (2) intra-phase balance control of primary-side DC voltage.

[0048] Here, (1) to (4) will be explained.

[0049] (1) Primary DC voltage average value control calculates the total primary DC voltage of all cells as the total primary DC voltage of all cells, and calculates the primary DC voltage average of all cells from the product of the total primary DC voltage of all cells and the reciprocal of the total number of cells. The deviation between the primary DC voltage average command value and the primary DC voltage average of all cells is amplified, and the d-axis current command value i d_ref Output as

[0050] In addition, the AC system voltage V u ,V v ,V w The phase ωt is output based on the three-phase system current value i u , i v , i w and phase ωt, a d-q transformation is performed to obtain the d-axis current detection value id and the q-axis current detection value i on the rotating coordinate system synchronized with the grid. q Output.

[0051] The grid current control section calculates the d-axis current command value I d_ref to d-axis current detection value I d is subtracted and amplified to obtain the d-axis voltage command value V d_ref Also, the q-axis current command value I q_ref The q-axis current detection value Iq is subtracted from the q-axis voltage command value V q_ref Output as

[0052] (2) The primary DC voltage intra-phase balance control unit calculates the total value of the primary DC voltages within a phase as the primary DC voltage intra-phase total value, and calculates the primary DC voltage intra-phase average value for each phase from the product of the primary DC voltage intra-phase total value and the reciprocal of the number of cells in the phase.The deviation between the primary DC voltage intra-phase average value for each phase and the primary DC voltage of each cell in the phase is amplified, multiplied by the sign of the system current value for each phase, and output as the primary DC voltage intra-phase balance control value.This value is used to calculate each cell voltage command value, as described below.

[0053] (3) The primary DC voltage individual balance control unit calculates the total value of the primary DC voltages of the cells connected to each DC system, multiplies this by the reciprocal of the number of cells connected to each DC system, and calculates the DC system primary DC voltage average value for the cells connected to each DC system. It calculates the deviation between the DC system primary DC voltage average value and the primary DC voltage of each cell in the phase, removes the system frequency double component superimposed on the deviation as necessary, amplifies it with an amplifier, multiplies it by the turns ratio of the transformer of the AC-DC converter and the transformer of the isolated DC-DC converter, and outputs it as the primary DC voltage individual balance control value.

[0054] (4) The secondary DC voltage individual control unit amplifies the difference between the secondary DC voltage command value and the secondary DC voltage of each DC system, calculates the product by the reciprocal of the number of cells connected to the DC system, and outputs the result as the secondary DC voltage individual control value.The isolated DC / DC converter DCDC of each cell adds the corresponding primary DC voltage individual balance control value and secondary DC voltage individual control value to obtain a current command value, and performs power interchange based on this command.

[0055] 3 shows a block diagram of the control unit of the AC-DC converter ACDC of this embodiment 1. In this embodiment 1, when a cell fails, the output voltage on the AC system side of the cell connected to the same DC system as the failed cell is increased, and the output voltage on the AC system side of the cell connected to another DC system is decreased. Then, a third harmonic is superimposed on the AC output voltage of the cell connected to the same DC system as the failed cell, and a third harmonic in the opposite direction is superimposed on the AC output voltage of the cell connected to a DC system different from the failed cell.

[0056] Specifically, the dq inverse converter 1 converts the d-axis voltage command value V d_ref , q-axis voltage command value V q_ref and phase ωt are input, and the voltage command value on the rotating coordinate system synchronized with the grid is converted to a voltage command value on the fixed coordinate system. The d-axis voltage command value V d_ref , q-axis voltage command value V q_ref The phase ωt is the value calculated in (1). The first multiplier 2 multiplies the output of the dq inverter 1 by the reciprocal 1 / V of the average value of the primary side DC voltage of all cells. dc1_ave The output of the first multiplier 2 is multiplied by the voltage command value V u_ref , V v_ref , V w_ref Let's say.

[0057] A fixed value of 3m / (3m+1-x) is input as a coefficient for increasing the output voltage on the AC grid side of the cell. In Figure 1, m = 4 and x = 2, so 3m / (3m+1-x) = 12 / 11. A fixed value of (3m-x) / (3m+1-x) is input as a coefficient for decreasing the output voltage on the AC grid side of the cell. When this same value is applied to Figure 1, (3m-x) / (3m+1-x) = 10 / 11.

[0058] The switch SW1 outputs 3m / (3m+1-x) if a cell connected to the DC system 21 fails, and outputs (3m-x) / (3m+1-x) if not. The switch SW2 outputs (3m-x) / (3m+1-x) if a cell connected to the DC system 21 fails, and outputs 3m / (3m+1-x) if not.

[0059] If a faulty cell exists, switch SW3 outputs the output of switch SW1, and if not, it outputs 1. If there is no faulty cell, switch SW3 outputs 1, if a cell connected to DC system 21 has failed, it outputs 3m / (3m+1-x), and if a cell connected to DC system 22 has failed, it outputs (3m-x) / (3m+1-x).

[0060] If a faulty cell exists, switch SW4 outputs the output of switch SW2, and if not, it outputs 1. Switch SW4 outputs 1 if there is no faulty cell, (3m-x) / (3m+1-x) if a cell connected to DC system 21 fails, and 3m / (3m+1-x) if a cell connected to DC system 22 fails.

[0061] The second multiplier 3 calculates the voltage command value V u_ref , V v_ref , V w_ref is multiplied by the outputs of the switches SW3 and SW4. The number of second multipliers 3 is 3x, and six when applied to Fig. 1. For example, if the DC system has three stages connected in series, the voltage command value for each phase V is 1 if there is no faulty cell, 3m / (3m+1-x) if there is a faulty cell in the DC system 23, and (3m-x) / (3m+1-x) if there is a faulty cell in another stage. u_ref , V v_ref , V w_ref Three second multipliers 3 are added to calculate the product of

[0062] 3rd harmonic V 03 is a value found in Non-Patent Document 1, Patent Documents 4 and 5, etc. The switch SW5 sets 0 if there is no faulty cell, and sets the third harmonic V 03 Output.

[0063] The third harmonic V superimposed on the AC output voltage of a cell connected to the same phase as the faulty cell but a different DC system 03 The fixed value -3(mx) / ((x-1)(3m+1-x)) is input as a coefficient to determine the amplitude of the third harmonic V. In the example shown in Figure 1, it is -6 / 11. 03 A fixed value of -3m / ((x-1)(3m+1-x)) is input as a coefficient that determines the amplitude of the signal. In the example shown in Figure 1, this is -12 / 11.

[0064] Switch SW6 outputs -3(mx) / ((x-1)(3m+1-x)) if the faulty cell is in the U phase, and -3m / ((x-1)(3m+1-x)) otherwise. Switch SW7 outputs -3(mx) / ((x-1)(3m+1-x)) if the faulty cell is in the V phase, and -3m / ((x-1)(3m+1-x)) otherwise. Switch SW8 outputs -3(mx) / ((x-1)(3m+1-x)) if the faulty cell is in the W phase, and -3m / ((x-1)(3m+1-x)) otherwise.

[0065] The third harmonic V superimposed on the AC output voltage of a cell connected to the same DC grid as the faulty cell 03 A fixed value of 3m / (3m+1-x) is input as a coefficient that determines the amplitude of the signal. In the example of Figure 1, where m=4 and x=2, the value is 12 / 11.

[0066] The switch SW9 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 21, and outputs the output of the switch SW6 otherwise. The switch SW10 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 22, and outputs the output of the switch SW6 otherwise. The switch SW11 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 21, and outputs the output of the switch SW7 otherwise. The switch SW12 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 22, and outputs the output of the switch SW7 otherwise. The switch SW13 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 21, and outputs the output of the switch SW8 otherwise. The switch SW14 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 22, and outputs the output of the switch SW8 otherwise.

[0067] The third multiplier 5 calculates the product of the output of the switch SW5 and the outputs of the switches SW9 to SW14. That is, the third multiplier 5 multiplies the third harmonic by 3m / (3m+1-x) for cells connected to the same DC system as the faulty cell, by -3(mx) / ((x-1)(3m+1-x)) for cells connected to the same phase as the faulty cell or a different DC system, by -3m / (x-1)(3m+1-x) for cells connected to a different phase or a different DC system from the faulty cell, and by 0 if there is no faulty cell.

[0068] The first adder 6 adds the output of the third multiplier 5 to the voltage command value V u_ref , V v_ref , V w_ref and the product of the switches SW3 and SW4 (the output of the second multiplier 3) are added together. Then, the first subtractor 4 subtracts the primary side DC voltage intra-phase balance control value calculated in (2) from the output of the first adder 6 to calculate each cell voltage command value. Based on each cell voltage command value, a gate signal for the AC / DC converter ACDC is generated by PWM modulation.

[0069] In Patent Document 6's (2) primary-side DC voltage intra-phase balance control, feedforward adjustment is performed on the AC output voltage of the cell's AC / DC converter (ACDC). The problem with this method is that if some of the cells constituting the SST fail, it is unable to output a voltage sufficient for connection to the AC grid. The reason why the amplitude of the AC voltage output by the cell cannot be increased is that it is limited by the primary-side DC voltage within the cell, and in order to maintain voltage balance at each stage of the DC grid, the amplitude of the AC voltage of a cell connected to the DC grid without a failed cell must be smaller than the AC voltage of a cell connected to the DC grid with a failed cell.

[0070] In this first embodiment, the third-order harmonic superposition described in Non-Patent Document 1, Patent Documents 5, and 6 is applied to the AC output voltage of the AC-DC converter ACDC of a cell connected to a DC system with a faulty cell, thereby enabling the AC output voltage of the AC-DC converter ACDC to be increased without increasing the primary-side DC voltage average value control. Furthermore, because the AC voltage amplitude must be reduced for cells connected to a DC system without a faulty cell, there is a margin in the limit of the AC voltage amplitude. Therefore, by superimposing a third-order harmonic in the opposite direction to that of the cell connected to the DC system with the faulty cell, the third-order harmonics cancel each other out, preventing the third-order harmonic from being superimposed on the neutral point of the MMCC-SSBC.

[0071] The amplitude of the superimposed third harmonic will be explained. Consider the case where one cell connected to both the U phase and the DC grid 21 fails. Non-Patent Document 1 states that in order to minimize the voltage peak after superimposition, it is sufficient to superimpose a third harmonic whose amplitude is 1 / 6 of the voltage amplitude before superimposition. The third harmonic V in Figure 3 03 is assumed to be a third harmonic of the corresponding amplitude. Alternatively, each phase voltage command value V u_ref , V v_ref , V w_ref Patent documents 4 and 5 are applied to the third harmonic V 03 You may ask for:

[0072] When a fault occurs, the remaining cells connected to the DC grid 21 must increase the AC output voltage of the AC-DC converter ACDC by 3m / (3m+1-x) times. Third-order harmonic superposition is applied to these cells. The amplitude of the third-order harmonic must be multiplied by 3m / (3m+1-x) in accordance with the increase in the AC output voltage of the AC-DC converter ACDC.

[0073] In the remaining cells, the superimposed third harmonic must be cancelled out. Focusing on the U phase, there are m / x-1 cells on which a third harmonic multiplied by 3m / (3m+1-x) has been superimposed, one faulty cell, and the remaining cells are in the mm / x range. To cancel out the third harmonic in these remaining cells, the amplitude of the third harmonic to be superimposed on the remaining cells is -3(mx) / ((x-1)(3m+1-x)) times.

[0074] In the V and W phases, the cells onto which the third harmonic multiplied by 3m / (3m+1-x) is superimposed are in the m / x range, while the remaining cells are in the mm / x range. The amplitude of the third harmonic to be superimposed on the remaining cells is -3m / ((x-1)(3m+1-x)) times.

[0075] For example, in Figure 1, m=4 and x=2, the remaining cells connected to the DC grid 21 have the third harmonic V 03 This applies to one U-phase cell, and the remaining two U-phase cells are superimposed with the third harmonic V 03 If you multiply it by -6 / 11 and superimpose it, the third harmonic will be zero for the U phase. 03 The remaining two cells are multiplied by 12 / 11 and the third harmonic V 03 By multiplying and superimposing the third harmonic V 03 can be cancelled out.

[0076] By applying third-order harmonic superposition, the fundamental component of the output voltage amplitude can be increased by 2 / √3 ≒ 1.15 times. On the other hand, to restore the output voltage of a phase of a failed cell to the same level as before the failure, the AC output voltage of the AC-DC converter ACDC must be increased by (3m-x+1) / (3m-x-2) times.

[0077] In this first embodiment, if m>7.8 when x=2, the AC output voltage of the AC-DC converter ACDC is increased within 1.15 times. In the example of m=4 in FIG. 1, the AC output voltage of the AC-DC converter ACDC needs to be increased to 1 1 / 8 = 1.375, which exceeds 1.15 times. In such a case, it is necessary to design the primary-side DC voltage average value control to be high in advance. However, even in the example of m=4 in FIG. 1, if this first embodiment is applied, the increase in the intra-cell primary-side DC voltage can be reduced to 1.2 times instead of 1.375 times.

[0078] According to the first embodiment, in a modular multilevel cascade converter (SST) that can output a higher DC voltage by connecting output terminals in series, the problem of a drop in the AC voltage output by the SST when some of the cells fail can be solved. This makes it possible to suppress phenomena such as an inability to transfer a predetermined amount of power, outputting a distorted current on the AC side, and generating an overcurrent.

[0079] Furthermore, according to the first embodiment, if one cell fails, the cells connected in parallel to the same DC system as the failed cell can increase their AC voltage output by up to 1.15 times. This makes it possible to maintain both the balance of the DC voltage output and the AC system interconnection without increasing the DC capacitor voltage inside the cell. This is advantageous in terms of cost and size, as there is no need to strengthen the voltage resistance design of the cells or change to components that can handle high voltages. It also avoids an increase in switching loss.

[0080] [Embodiment 2] FIG. 4 shows the phase voltage command value V u_ref , V v_ref , V w_ref A block diagram of the calculation unit is shown.

[0081] AC system voltage detection value V u , V v , V w Enter the fixed value (3m-x+1) / (3m-x-2). Assuming application to Figure 1, the number of cells per phase is m=4, and the number of DC systems is x=2, so (3m-x+1) / (3m-x-2)=11 / 8.

[0082] Switch SW15 sets (3m-x+1) / (3m-x-2) if a cell connected to the U phase fails, and sets 1 otherwise to the coefficient N / n u The switch SW16 outputs (3m-x+1) / (3m-x-2) if a cell connected to the V phase fails, and outputs 1 otherwise as a coefficient N / n vThe switch SW17 outputs (3m-x+1) / (3m-x-2) if a cell connected to the W phase fails, and outputs 1 otherwise as a coefficient N / n w Output as

[0083] The numerator of the coefficient, N, is the number of cells in each phase, N=m. The notation of N conforms to Patent Documents 7 and 8. The denominator of the coefficient, n u , n v , n w is the number of cells in each phase that are operating without failure.

[0084] The fourth multiplier 7 multiplies the AC system voltage detection value V u and coefficient N / n u , AC system voltage detection value V v and coefficient N / n v , AC system voltage detection value V w and coefficient N / n w Find the product of

[0085] The computing unit 8 multiplies the output V of the fourth multiplier 7 by u N / n u , V v N / n v , V w N / n w , coefficient N / n u , N / n v , N / n w Based on Patent Document 7, the zero-phase voltage V 0q sinωt, V 0d Outputs cosωt.

[0086] Here, the method of calculating the zero-phase voltage of Patent Document 7, which is implemented inside the computing unit 8, will be described.

[0087] The correction voltage command value generator outputs a phase ωt synchronized with the AC voltage of the grid. The first dq converter converts the phase voltage detection signal or voltage command value, or the phase voltage detection signal or voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system synchronized with the grid frequency. The second dq converter converts the phase voltage detection signal or voltage command value, or the phase voltage detection signal or voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system that rotates in the direction opposite to the grid frequency. The calculator extracts a DC component from the output of the first dq converter and converts it into a positive-phase d-axis component V 1d , positive-phase q-axis component V 1q and the negative-phase d-axis component V extracted from the output of the second dq converter. 2d , the out-of-phase q-axis component V 2q Based on this, the zero-phase-sequence voltage d-axis component and the zero-phase-sequence voltage q-axis component that make the AC side output voltage of each cell uniform are calculated using one of the following equations (1) to (3). 0d is multiplied by cosωt. The zero-phase voltage q-axis component V 0q Multiply by sinωt.

[0088]

number

[0089]

number

[0090]

number

[0091] Next, a method for calculating the zero-phase voltage when the method disclosed in Patent Document 8 is implemented in the computing unit 8 will be described.

[0092] The correction voltage command value generator calculates the amplitude of the correction voltage command value for each phase. The amplitude may be, for example, the effective value of the voltage command value, the value obtained by extracting the amplitude of the fundamental wave component of the voltage command value, or the peak value per cycle of the voltage command value. The calculated amplitude is multiplied by a coefficient based on the number of failed cells. The deviation between the three-phase average value of the amplitude of the multiplied correction voltage command value and the amplitude of the multiplied correction voltage command value is amplified and multiplied by a sine wave in phase with the voltage command value. The multiplied values ​​for the three phases are added together and output as the zero-phase sequence voltage.

[0093] The zero-phase voltage V output from the calculator 8 0q sinωt, V 0d cosωt is added by the second adder 9. The third adder 10 adds the zero-phase voltage V 0q sinωt+V 0d cosωt is added to the output of the dq inverse converter 1, and a corrected voltage command value for each phase is output.

[0094] The correction voltage command value of each phase is input to the first multiplier 2 and is also input again to the calculator 12, where it is again subjected to feedback control based on Patent Document 8 to calculate the zero-phase voltage V 0q sinωt, V 0d cosωt is calculated (when the calculation is performed based on Patent Document 7, the correction voltage command value for each phase does not need to be input to the calculator 8).

[0095] The first multiplier 2 adds the reciprocal 1 / V of the average DC voltage on the primary side of all cells to the output of the third adder 10. dc1_ave and each phase voltage command value V u_ref , V v_ref , V w_ref Let's say.

[0096] The second embodiment is a combination of the first embodiment and Patent Documents 7 and 8.

[0097] In Patent Documents 7 and 8, the AC voltage of the phase including the failed cell is multiplied by a coefficient N / n u , N / n v , N / n wBy multiplying this, the voltage amplitude appears larger according to the number of faulty cells, and a zero-phase sequence voltage is calculated and superimposed to equalize the voltage amplitude. However, this can only be applied if the amplitude of the AC output voltage of the AC / DC converter ACDC of each cell is equal.

[0098] In the first embodiment, the AC output voltage of the AC-DC converter ACDC is multiplied by the fixed values ​​3m / (3m+1-x) and (3m-x) / (3m+1-x), so the amplitudes of the AC output voltages of the AC-DC converter ACDC are not equal. Therefore, in order to apply Patent Documents 7 and 8, the coefficient N / n u , N / n v , N / n w adjustments need to be made.

[0099] Here, the output voltage of the AC-DC converter ACDC of all cells before a cell failure is set to 1, and a case where a cell connected to both the U phase and the DC system 21 fails will be considered. The remaining 3m / x-1 cells connected to the DC system 21 have an AC output voltage of 3m / (3m+1-x) based on embodiment 1. The cells connected to the other DC systems 22 to 2x have an AC output voltage of (3m-x) / (3m+1-x).

[0100] Looking at the U phase, there are m / x-1 cells whose AC output voltage of the AC-DC converter ACDC has become 3m / (3m+1-x), mm / x cells whose AC output voltage has become (3m-x) / (3m+1-x), and 1 cell that has failed and become 0. The total U phase of the AC output voltage of the AC-DC converter ACDC is m(3m-x-2) / (3m-x+1). Before the failure, there were m cells that output 1, so the total U phase of the AC output voltage of the AC-DC converter ACDC changes by a factor of (3m-x-2) / (3m-x+1).

[0101] For the V and W phases, the cells where the AC output voltage of the AC / DC converter ACDC has become 3m / (3m+1-x) due to the failure are in the m / x range, and the cells where it has become (3m-x) / (3m+1-x) are in the mm / x range, just like the U phase. The total AC output voltage of the AC / DC converter ACDC for the V and W phases is m, and does not change before or after the failure. Therefore, the coefficient N / nu may be set to (3m-x+1) / (3m-x-2), which is the reciprocal of the total amount of change in the U-phase AC output voltage of the AC-DC converter ACDC.

[0102] The following describes again the case where a cell connected to both the U phase and the DC system 21 fails in the configuration of m=4 and x=2 in FIG. 1 . According to the first embodiment, the output voltage of the AC / DC converter ACDC with five cells connected to the DC system 21 is 12 / 11 times. The output voltage of the AC / DC converter ACDC with six cells connected to the DC system 22 is 10 / 11 times. In the U phase, there is one cell that has been multiplied by 12 / 11 and two cells that have been multiplied by 10 / 11. The total output voltage changes from 4 to 32 / 11, decreasing to 8 / 11 times. The decrease in the total output voltage is not simply 3 / 4 times because the number of cells is reduced from four to three, but because there are more cells whose output voltage of the AC / DC converter ACDC has decreased, the decrease in the total output voltage is greater. In the V phase and W phase, there are two cells that have been multiplied by 12 / 11 and two cells that have been multiplied by 10 / 11, so the total output voltage remains 4. From the above, u This can be made to appear larger by multiplying it by a factor of 11 / 8.

[0103] FIG. 5 shows the AC output voltage waveform of the U-phase AC-DC converter ACDC when the second embodiment is applied. Initially, all cells normally output the AC voltage of the AC-DC converter ACDC. For example, the amplitude of the AC voltage is dc1u11 ~V dc1u22 ) is set to 0.9 times.

[0104] After two cycles, cell U11 fails and shorts the AC output terminal, so V ACU11 becomes zero. V ACU12 is the amplitude multiplied by 12 / 11, V ACU21 , V ACU22 is multiplied by 10 / 11.

[0105] Furthermore, by applying Patent Documents 7 and 8, a zero-phase voltage is superimposed, and the AC voltage is three-phase balanced. At this time, the AC voltage of the AC / DC converters ACDC of all cells is multiplied by approximately 1.09. As a result, V ACU12In this case, the amplitude exceeds the primary side DC voltage, resulting in overmodulation. In reality, it is not possible to output such a voltage, which can cause distortion and overcurrent.

[0106] Four cycles later, this is the case where the second embodiment is applied. The fundamental wave component of the AC voltage of each AC-DC converter ACDC is not changed. ACU12 The third harmonic is added to V, reducing the peak, and the amplitude is contained within the primary side DC voltage, preventing overmodulation. The superimposed third harmonic is divided into two equal parts in the opposite direction to V ACU21 , V ACU22 V ACU21 , V ACU22 Although the distortion peak increases in a triangular wave shape, the amplitude is reduced before application, allowing for some margin, so overmodulation can be avoided. ACU12 , V ACU21 , V ACU22 The distortions cancel each other out, preventing the superposition of third harmonics on the neutral point.

[0107] However, for the V phase, V ACV11 , V ACV12 The amplitude of both is multiplied by 12 / 11 x 1.09, and the third harmonic must be superimposed on both. This is shared and canceled by the two cells V21 and V22, so the V ACV21 , V ACV22 A double third harmonic is superimposed on the W phase, increasing the risk of overmodulation. The same applies to the W phase. Here, we have used an example where m=4, but in configurations where m is larger, the number of cells that can share the load by canceling out the third harmonic increases, making it possible to prevent overmodulation.

[0108] According to the second embodiment, even if one cell fails, the AC output voltages of the AC-DC converters ACDC of cells connected to the same DC system can be made equal. This prevents a chain reaction of failures caused by excessive DC voltage being applied to other cells in the phase where the failed cell is located, or the AC output voltage of the phase where the failed cell is located being insufficient, causing grid connection to become unmaintainable and resulting in overcurrent and voltage / current distortion. Furthermore, as in Patent Documents 7 and 8, the effect of equalizing the AC output voltages of the cells can also be achieved even when an imbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output.

[0109] [Embodiment 3] Table 1 shows the formulas for calculating the fixed values ​​used in this embodiment 3. The fixed values ​​used in the embodiments 1 and 2 are changed to the values ​​found in Table 1 depending on the number and positions of the faulty cells.

[0110] [Table 1]

[0111] In this third embodiment, a case where two cells fail will be described. The voltage command value fault stage in Table 1 is the value input to the upper side of switch SW1 and the lower side of switch SW2. The voltage command value healthy stage is the value input to the lower side of switch SW1 and the upper side of switch SW2. The coefficient N / n·faulty phase is the value input to the upper side of switch SW15, the middle of switch SW16, and the lower side of switch SW17. The third harmonic fault stage is the value input to the upper side of switches SW9, SW11, and SW13, and the lower side of switches SW10, SW12, and SW14. The third harmonic healthy stage fault phase is the value input to the upper side of switch SW6, the middle of switch SW7, and the lower side of switch SW8. The third harmonic healthy stage healthy phase is the value input to the middle and lower side of switch SW6, the upper and lower sides of switch SW7, and the upper and middle side of switch SW8.

[0112] (1) When two faulty cells are connected to the same phase and the same DC system (stage) Consider the case where two faulty cells are connected to the U-phase DC system 21. The number of cells in the DC system 21 is 3m / x-2 excluding the faulty cell, and the AC output voltage is increased by 3m / (3m+2-2x) times. The number of cells in the DC systems 22 to 2x is 3m-3m / x in total, and the AC output voltage is reduced by (3m-2x) / (3m+2-2x) times.

[0113] Excluding the faulty cell, there are m / x-2 cells connected to the DC grid 21 in the U phase, and mm / x cells connected to other DC grids. There are m / x cells connected to the DC grid 21 in the V and W phases, and mm / x cells connected to other DC grids.

[0114] Due to the fault, the AC output voltage of U phase will decrease by {(3m / (3m+2-2x))·(m / x-2)+((3m-2x) / (3m+2-2x))·(mm / x)} / m=(3m-2x-4) / (3m-2x+2) times. The AC output voltage of V and W phases will decrease by {(3m / (3m+2-2x))·m / x+((3m-2x) / (3m+2-2x))(mm / x)} / m=1 time, and will remain unchanged before and after the fault.

[0115] Therefore, the coefficient N / n u is set to (3m-2x+2) / (3m-2x-4). Since the third harmonic superposition is performed to reduce the peak value of the cell that has increased the AC output voltage, the amplitude of the third harmonic superposed on the cell of the DC system 21 is set to 3m / (3m+2-2x) times.

[0116] The cell in which this third harmonic is superimposed on the U phase is in the m / x-2 range. The remaining cells in the mm / x range cancel this out, so the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x-2) / (mm / x)=-3(m-2x) / ((x-1)(3m+2-2x)). The cell in which this third harmonic is superimposed on the V and W phases is in the m / x range. The remaining cells in the mm / x range cancel this out, so the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x) / (mm / x)=-3m / ((x-1)(3m+2-2x)).

[0117] (2) When two faulty cells are connected to different phases and the same DC system (stage), Consider the case where there is one faulty cell each in the U and V phases, and both are connected to the DC system 21. The cells in the DC system 21, excluding the faulty cell, are 3m / x-2, and the AC output voltage increases by 3m / (3m+2-2x) times. The cells in the DC systems 22 to 2x total 3m-3m / x, and the AC output voltage decreases by (3m-2x) / (3m+2-2x) times.

[0118] The number of cells connected to the DC grid 21 in the U and V phases is m / x-1, excluding the faulty cell, and the number of cells connected to other DC grids is mm / x. The number of cells connected to the DC grid 21 in the W phase is m / x, and the number of cells connected to other DC grids is mm / x.

[0119] Due to the fault, the AC output voltage of the U and V phases will decrease by {(3m / (3m+2-2x))·(m / x-1)+((3m-2x) / (3m+2-2x))·(mm / x)} / m=(3m-2x-1) / (3m-2x+2) times. The AC output voltage of the W phase will decrease by {(3m / (3m+2-2x))·m / x+((3m-2x) / (3m+2-2x))(mm / x)} / m=1 time, and will remain unchanged before and after the fault.

[0120] Therefore, the coefficient N / n u , N / n v is set to (3m-2x+2) / (3m-2x-1). The third harmonic is superimposed to reduce the peak value of the cell that has increased the AC output voltage, so the amplitude of the superimposed third harmonic is set to 3m / (3m+2-2x).

[0121] The cells in which this third harmonic is superimposed on the U and V phases are in the m / x-1 range. The remaining cells in the mm / x range cancel this out, so the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x-1) / (mm / x)=-3(mx) / ((x-1)(3m+2-2x)). The cells in which this third harmonic is superimposed on the W phase are in the m / x range. The remaining cells in the mm / x range cancel this out, so the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x) / (mm / x)=-3m / ((x-1)(3m+2-2x)).

[0122] (3) When two faulty cells are connected to the same phase but different DC systems (stages) Consider a case where two faulty cells are connected to the U phase, one each to DC system 21 and DC system 22. Excluding the faulty cell, the number of cells in DC system 21 and DC system 22 is 3m / x-1 each, increasing the AC output voltage by 3m / (3m+2-x) times. The number of cells in DC systems 23 to 2x is a total of 3m-6m / x, decreasing the AC output voltage by (3m-x) / (3m+2-x) times.

[0123] In the U phase, the number of cells connected to DC system 21 and DC system 22 is a total of 2m / x-2, excluding the faulty cell, and the number of cells connected to other DC systems is m-2m / x. In the V and W phases, the number of cells connected to DC system 21 and DC system 22 is a total of 2m / x, and the number of cells connected to other DC systems is m-2m / x.

[0124] Due to the fault, the AC output voltage of U phase will decrease by {(3m / (3m+2-x))·(2m / x-2)+((3m-x) / (3m+2-x))·(m-2m / x)} / m=(3m-x-4) / (3m-x+2). The AC output voltage of V and W phases will decrease by {(3m / (3m+2-x))·2m / x+((3m-x) / (3m+2-x))(m-2m / x)} / m=1, and will remain unchanged before and after the fault.

[0125] Therefore, the coefficient N / n uis set to (3m-x+2) / (3m-x-4). The third harmonic is superimposed to reduce the peak value of the cell that has increased the AC output voltage, so the amplitude of the superimposed third harmonic is set to 3m / (3m+2-x).

[0126] The cell in which this third harmonic is superimposed on the U phase is 2m / x-2 units. Since the remaining cells m-2m / x units cancel this out, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x)·(2m / x-2) / (m-2m / x)=-6(mx) / ((x-2)(3m+2-x)). The cell in which this third harmonic is superimposed on the V and W phases is 2m / x units. Since the remaining cells m-2m / x units cancel this out, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x)·(2m / x) / (m-2m / x)=-6m / ((x-2)(3m+2-x)).

[0127] (4) When two faulty cells are connected to different phases or different DC systems (stages) Consider the case where there is one faulty cell each in U phase and V phase, connected to DC system 21 and DC system 22, respectively. Excluding the faulty cell, the number of cells in DC system 21 and DC system 22 is 3m / x-1 each, and the AC output voltage increases by 3m / (3m+2-x) times. The number of cells in DC systems 23 to 2x is a total of 3m-6m / x, and the AC output voltage decreases by (3m-x) / (3m+2-x) times.

[0128] The total number of cells connected to DC system 21 and DC system 22 in U and V phases is 2m / x-1 for each phase, excluding the faulty cell, and the total number of cells connected to other DC systems is m-2m / x. The total number of cells connected to DC system 21 and DC system 22 in W phase is 2m / x, and the total number of cells connected to other DC systems is m-2m / x.

[0129] Due to the fault, the AC output voltage of the U and V phases will decrease by {(3m / (3m+2-x))·(2m / x-1)+((3m-x) / (3m+2-x))·(m-2m / x)} / m=(3m-x-1) / (3m-x+2) times. The AC output voltage of the W phase will decrease by {(3m / (3m+2-x))·2m / x+((3m-x) / (3m+2-x))(m-2m / x)} / m=1 time, and will remain unchanged before and after the fault.

[0130] Therefore, the coefficient N / n u , N / n v is set to (3m-x+2) / (3m-x-1). The third harmonic is superimposed to reduce the peak value of the cell that has increased the AC output voltage, so the amplitude of the superimposed third harmonic is set to 3m / (3m+2-x).

[0131] The cells in which this third harmonic is superimposed on the U and V phases are in the 2m / x-1 order. This is canceled out by the remaining cells in the m-2m / x order, so the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x)·(2m / x-1) / (m-2m / x)=-3(2m-x) / ((x-2)(3m+2-x)). The cells in which this third harmonic is superimposed on the W phase are in the 2m / x order. This is canceled out by the remaining cells in the m-2m / x order, so the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x)·(2m / x) / (m-2m / x)=-6m / ((x-2)(3m+2-x)).

[0132] Table 1 summarizes the above. From Table 1, the voltage command value V for each phase according to the number and location of the faulty cells is calculated. u_ref , V v_ref , V w_ref Fixed value to be multiplied by, coefficient N / n u , N / n v , N / n w By referencing and applying the values ​​to be set and the amplitude of the third harmonic to be superimposed, operation can continue even if up to two units fail.

[0133] If m is sufficiently large and the modular multilevel cascade converter (SST) can output the AC voltage required for grid connection even when only one cell is faulty, it may be possible not to superimpose the third harmonic. In this case, the third embodiment will be applied when the number of faulty cells reaches two. Alternatively, if only one cell is faulty, the third harmonic V 03 The amplitude of the superimposed third harmonic may be reduced, for example, by multiplying by a coefficient of 2 / 3 to superimpose a third harmonic having 1 / 9 of the voltage amplitude before superimposition.

[0134] By expanding the above, it is possible to deal with cases where three or more cells fail. However, as the number of failed cells increases, the case distinction becomes more complicated, and there is a high possibility that the AC output voltage of the cells connected to the same DC system as the failed cell will need to be increased by more than 1.15 times. In this case, it becomes necessary to increase the cell primary DC voltage in advance. However, even when increasing the cell primary DC voltage, by applying this embodiment 3, the increase can be limited to √3 / 2≒0.866 times.

[0135] According to the third embodiment, the effects of the first and second embodiments can be obtained even when two cells fail.

[0136] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims. [Explanation of symbols]

[0137] 1...dq inverse converter, 2...first multiplier, 3...second multiplier, 4...first subtractor, 5...third multiplier, 6...first adder, 7...fourth multiplier, 8...arithmetic unit, 9...second adder, 10...third adder, SW1 to SW17...switches, ACDC...AC-DC converter, C1...primary side DC capacitor, DCDC...isolated DC-DC converter, C2...secondary side DC capacitor

Claims

1. A modular multilevel cascade converter having m (m: an integer of 2 or more) cells per phase, each cell including an AC / DC converter connected to an AC system, a primary-side DC capacitor connected to the DC side of the AC / DC converter, an isolated DC / DC converter having one DC side connected to the primary-side DC capacitor, and a secondary-side DC capacitor connected to the other DC side of the isolated DC / DC converter, and having x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel, and supplying voltages of a plurality of the DC systems to a load or a power source, The control unit of the AC-DC converter When the cell fails, Increasing the output voltage of the AC system side of the cell connected to the same DC system as the failed cell, and decreasing the output voltage of the AC system side of the cell connected to the other DC system; A modular multilevel cascade converter, characterized in that a third harmonic is superimposed on the AC output voltage of the cell connected to the same DC system as the failed cell, and a third harmonic in the opposite direction is superimposed on the AC output voltage of the cell connected to a DC system different from that of the failed cell.

2. The control unit of the AC-DC converter a second multiplier that multiplies each phase voltage command value of the AC-DC converter by 3m / (3m-x+1) when one of the cells fails, by (3m-x) / (3m-x+1) when one of the cells fails, by 1 when one of the cells fails, and by 1 when there is no failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+1-x) for the cells connected to the same DC system as the failed cell, by -3(m-x) / ((x-1)(3m+1-x)) for the cells connected to the same phase as the failed cell or to a different DC system, by -3m / (x-1)(3m+1-x) for the cells connected to a different phase than the failed cell or to a different DC system, and by 0 if there is no failed cell; a first adder that adds the output of the second multiplier to the output of the third multiplier; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; a first subtractor that subtracts the primary-side DC voltage intra-phase balance control value from the output of the first adder and outputs each cell voltage command value; 2. The modular multilevel cascade converter according to claim 1, further comprising: a gate signal for the AC-DC converter based on the voltage command value of each cell.

3. The control unit of the AC-DC converter a dq inverse transformer for transforming a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; A switch for each phase outputs (3m-x+1) / (3m-x-2) as a coefficient for the phase to which the faulty cell is connected, and outputs 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch of each phase; a computing unit that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the respective phase voltage command values; 3. The modular multilevel cascade converter according to claim 2, comprising:

4. When two of the cells connected to the same phase and the same DC system fail, The control unit of the AC-DC converter a dq inverse transformer for transforming a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; A switch for each phase outputs (3m-2x+2) / (3m-2x-4) as a coefficient for the phase to which the faulty cell is connected, and outputs 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch of each phase; a computing unit that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the respective phase voltage command values; a second multiplier that multiplies each phase voltage command value of the AC-DC converter by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and by (3m-2x) / (3m+2-2x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-2x) for the cells connected to the same DC system as the failed cell, by -3(m-2x) / ((x-1)(3m+2-2x)) for the cells connected to the same phase as the failed cell but a different DC system, and by -3m / (x-1)(3m+2-2x) for the cells connected to a different phase than the failed cell or a different DC system; a first adder that adds the output of the second multiplier to the output of the third multiplier; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; a first subtractor that subtracts the primary-side DC voltage intra-phase balance control value from the output of the first adder and outputs each cell voltage command value; 2. The modular multilevel cascade converter according to claim 1, further comprising: a gate signal for the AC-DC converter based on the voltage command value of each cell.

5. When two cells connected to the same DC grid in different phases fail, The control unit of the AC-DC converter a dq inverse transformer for transforming a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; A switch for each phase outputs (3m-2x+2) / (3m-2x-1) as a coefficient for the phase to which the faulty cell is connected, and outputs 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch of each phase; a computing unit that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the respective phase voltage command values; a second multiplier that multiplies each phase voltage command value of the AC-DC converter by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and by (3m-2x) / (3m+2-2x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-2x) for the cells connected to the same DC system as the failed cell, by -3(m-x) / ((x-1)(3m+2-2x)) for the cells connected to the same phase as the failed cell but a different DC system, and by -3m / (x-1)(3m+2-2x) for the cells connected to a different phase than the failed cell or a different DC system; a first adder that adds the output of the second multiplier to the output of the third multiplier; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; a first subtractor that subtracts the primary-side DC voltage intra-phase balance control value from the output of the first adder and outputs the cell voltage command value; 2. The modular multilevel cascade converter according to claim 1, further comprising: a gate signal for the AC-DC converter based on the voltage command value of each cell.

6. If two cells connected to the same phase but different DC grids fail, The control unit of the AC-DC converter a dq inverse transformer for transforming a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; A switch for each phase outputs (3m-x+2) / (3m-x-4) as a coefficient for the phase to which the faulty cell is connected, and outputs 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch of each phase; a computing unit that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the respective phase voltage command values; a second multiplier that multiplies each phase voltage command value of the AC-DC converter by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and by (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for the cells connected to the same DC system as the failed cell, by -6(m-x) / ((x-2)(3m+2-x)) for the cells connected to the same phase as the failed cell but a different DC system, and by -6m / (x-2)(3m+2-x) for the cells connected to a different phase than the failed cell or a different DC system; a first adder that adds the output of the second multiplier to the output of the third multiplier; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; a first subtractor that subtracts the primary-side DC voltage intra-phase balance control value from the output of the first adder and outputs the cell voltage command value; 2. The modular multilevel cascade converter according to claim 1, further comprising: a gate signal for the AC-DC converter based on the voltage command value of each cell.

7. When two cells connected to different phases and different DC systems fail, The control unit of the AC-DC converter a dq inverse transformer for transforming a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; A switch for each phase outputs (3m-x+2) / (3m-x-1) as a coefficient for the phase to which the faulty cell is connected, and outputs 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch of each phase; a computing unit that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the respective phase voltage command values; a second multiplier that multiplies each phase voltage command value of the AC-DC converter by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and by (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for the cells connected to the same DC system as the failed cell, by -3(2m-x) / ((x-2)(3m+2-x)) for the cells connected to the same phase as the failed cell but a different DC system, and by -6m / (x-2)(3m+2-x) for the cells connected to a different phase than the failed cell or a different DC system; a first adder that adds the output of the second multiplier to the output of the third multiplier; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; a first subtractor that subtracts the primary-side DC voltage intra-phase balance control value from the output of the first adder and outputs the cell voltage command value; 2. The modular multilevel cascade converter according to claim 1, further comprising: a gate signal for the AC-DC converter based on the voltage command value of each cell.

8. A control method for a modular multilevel cascade converter, the converter comprising: m (m: an integer of 2 or more) cells per phase, each cell including an AC-DC converter connected to an AC system; a primary-side DC capacitor connected to a DC side of the AC-DC converter; an isolated DC-DC converter having one DC side connected to the primary-side DC capacitor; and a secondary-side DC capacitor connected to the other DC side of the isolated DC-DC converter; x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel; and the converter supplies voltages of a plurality of the DC systems to a load or a power source, When the cell fails, The control unit of the AC-DC converter Increasing the output voltage of the AC system side of the cell connected to the same DC system as the failed cell, and decreasing the output voltage of the AC system side of the cell connected to the other DC system; A method for controlling a modular multilevel cascade converter, comprising: superimposing a third harmonic on the AC output voltage of a cell connected to the same DC system as the failed cell; and superimposing an opposite third harmonic on the AC output voltage of a cell connected to a DC system different from the failed cell.

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