Semiconductor memory device

Abstract

To suppress deterioration in current characteristics of a semiconductor memory device.SOLUTION: A semiconductor memory device according to an embodiment includes a first chip and a second chip that is in contact with the first chip and is electrically connected to the first chip via a first connection pad. The second chip includes a memory cell array provided in the first region and including a source line, a plurality of word lines, and a memory pillar, and a first wiring 39 provided in the second region and including a first contact 207 extending in the Z direction and electrically connected to the first connection pad, a first connection portion V2 electrically connected to an upper end of the first contact, and a first extending portion continuing from an upper end of the first connection portion and extending in the Y direction at a position above an upper surface of the source line in the Z direction, the first connection portion V2 has a shape in which a groove above the first contact in the Z direction is embedded to a position of a lower surface of the first extension portion in the Z direction, and a lower surface of the first connection portion V2 is located below an upper surface of the source line in the Z direction.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is a well-known semiconductor memory device capable of storing data nonvolatilely. NAND flash memory employs a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-141616 [Patent Document 2] Japanese Patent Application Publication No. 2024-319 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention suppresses the deterioration of the current characteristics of a semiconductor memory device. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a first chip including a substrate having a first region and a second region, and a second chip that contacts the first chip in a first direction intersecting a surface of the substrate and is electrically connected to the first chip via a first connection pad provided in a boundary region with the first chip, the second chip including a memory cell array provided in the first region and having a source line, a plurality of word lines provided below the source line and spaced apart from each other in the first direction, and memory pillars that extend in the first direction so as to intersect with the plurality of word lines and have upper ends connected to the source line, and a memory cell array provided in the second region. and a first wiring having a first contact extending in the first direction and electrically connected to the first connection pad, a first connection portion electrically connected to an upper end of the first contact, and a first extension portion continuing from the upper end of the first connection portion and extending in a second direction intersecting the first direction from a position above an upper surface of the source line in the first direction, wherein the first connection portion has a shape in which a groove above the first contact in the first direction is filled up to the position of a lower surface of the first extension portion in the first direction, and the lower surface of the first connection portion is located lower than the upper surface of the source line in the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 3] FIG. 1 is a plan view showing an example of a planar layout of a semiconductor memory device according to an embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 6]6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of the cross-sectional structure of a memory pillar of the semiconductor memory device according to the embodiment. [Figure 8] FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of the semiconductor memory device according to the embodiment. [Figure 9] 1 is a cross-sectional view showing an example of a connection portion between a wiring layer and a source line and a contact in a semiconductor memory device according to an embodiment. [Figure 10] 9 is a cross-sectional view taken along line XX in FIG. 8, showing an example of a connection portion between a wiring layer and a contact in the semiconductor memory device according to the embodiment. [Figure 11] FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure of a connection pad of the semiconductor memory device according to the embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 18] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a first modification. [Figure 20] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a first modification. [Figure 21]10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a first modification. [Figure 22] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a first modification. [Figure 23] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a first modification. [Figure 24] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a first modification. [Figure 25] FIG. 10 is a cross-sectional view showing an example of a connection portion between a wiring layer and a contact in a semiconductor memory device according to a second modification. [Figure 26] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region of a semiconductor memory device according to a third modification. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Note that the dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. Furthermore, when particularly distinguishing between elements having similar configurations, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. Embodiment The semiconductor memory device according to the embodiment will be described below.

[0009] 1.1 Configuration The configuration of the semiconductor memory device according to the embodiment will be described.

[0010] 1.1.1 Memory System First, an example of the configuration of a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment.

[0011] The memory system 3 is, for example, an SSD (solid state drive) or SD TMThe memory system 3 is a card. The memory system 3 is connected to, for example, an external host device (not shown). The memory system 3 stores data from the host device. The memory system 3 also reads data to the host device.

[0012] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0013] The semiconductor memory device 1 is, for example, a NAND flash memory. The semiconductor memory device 1 stores data in a non-volatile manner. In the following, an example will be described in which the semiconductor memory device 1 is a NAND flash memory.

[0014] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 writes data to the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also reads data from the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also transmits the data read from the semiconductor memory device 1 to the host device.

[0015] The communication between the semiconductor memory device 1 and the memory controller 2 complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0016] 1.1.2 Semiconductor memory devices Continuing with the description of the internal configuration of the semiconductor memory device 1, the semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0017] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(m-1) (m is an integer equal to or greater than 2). A block BLK is a set of a plurality of memory cells capable of storing data in a non-volatile manner. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. For example, one memory cell is associated with one bit line and one word line.

[0018] The command register 11 holds the command CMD that the semiconductor memory device 1 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, and the like.

[0019] The address register 12 holds address information ADD that the semiconductor memory device 1 receives from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. The page address PA, the block address BA, and the column address CA are used to select, for example, a word line, a block BLK, and a bit line, respectively.

[0020] The sequencer 13 controls the overall operation of the semiconductor memory device 1. Based on the command CMD stored in the command register 11, the sequencer 13 executes a read operation, a write operation, and an erase operation.

[0021] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PA held in the address register 12.

[0022] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0023] In a write operation, the sense amplifier module 16 transfers write data DAT received from the memory controller 2 to the memory cell array 10. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line. The sense amplifier module 16 transfers the result of this determination to the memory controller 2 as read data DAT.

[0024] 1.1.3 Memory cell array circuit configuration An example of the circuit configuration of the memory cell array 10 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory device according to the embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. In the example shown in Fig. 2, the block BLK includes four string units SU0, SU1, SU2, and SU3.

[0025] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BL(n-1) (n is an integer equal to or greater than 2). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage film. Each of the memory cell transistors MT0 to MT7 stores data in a non-volatile manner. The select transistors ST1 and ST2 are used to select the string unit SU during various operations. In the following description, when the bit lines BL0 to BL(n-1) are not distinguished from one another, each of the bit lines BL0 to BL(n-1) will simply be referred to as a bit line BL. When the memory cell transistors MT0 to MT7 are not distinguished from one another, each of the memory cell transistors MT0 to MT7 will simply be referred to as a memory cell transistor MT.

[0026] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. One end of the select transistor ST1 is connected to the bit line BL associated with the select transistor ST1. The other end of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. One end of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The other end of the select transistor ST2 is connected to a source line SL.

[0027] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistor ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In contrast, the gates of multiple select transistors ST2 in the same block BLK are commonly connected to a select gate line SGS. However, this is not limited to this, and the gates of multiple select transistors ST2 may be connected to multiple select gate lines SGS that are different for each string unit SU. In the following description, when the word lines WL0 to WL7 are not distinguished, each of the word lines WL0 to WL7 will simply be referred to as a word line WL. Furthermore, when the select gate lines SGD0 to SGD3 are not distinguished, each of the select gate lines SGD0 to SGD3 will simply be referred to as a select gate line SGD.

[0028] A different column address is assigned to each of the bit lines BL0 to BL(n-1). Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Word lines WL0 to WL7 are provided for each block BLK. A source line SL is shared, for example, among multiple blocks BLK.

[0029] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called a cell unit CU. For example, the storage capacity of a cell unit CU including multiple memory cell transistors MT, each storing one bit of data, is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0030] The circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, each block BLK may include any number of string units SU. Each NAND string NS may include any number of memory cell transistors MT and select transistors ST1 and ST2.

[0031] 1.1.4 Structure of semiconductor memory device An example of the structure of the semiconductor memory device 1 according to the embodiment will be described.

[0032] In the following description, the X direction is approximately parallel to the semiconductor substrate of the semiconductor memory device 1. The X direction corresponds to the extension direction of the word lines WL. The Y direction is approximately parallel to the semiconductor substrate and perpendicular to the X direction. The Y direction corresponds to the extension direction of the bit lines BL. The Z1 and Z2 directions are approximately perpendicular to the semiconductor substrate. The Z1 direction corresponds to the direction from the semiconductor substrate of the semiconductor memory device 1 toward the electrode pads. The Z2 direction corresponds to the direction from the electrode pads toward the semiconductor substrate. When the Z1 and Z2 directions are not distinguished, each of the Z1 and Z2 directions will be simply referred to as the Z direction. Hereinafter, the Z1 direction side of a certain component will be referred to as one side in the Z direction (or simply one side), and the Z2 direction side of a certain component will be referred to as the other side in the Z direction (or simply the other side). Furthermore, the surface of a certain component facing the electrode pads will be referred to as the first surface, and the surface of a certain component facing the semiconductor substrate will be referred to as the second surface. The first surface and the second surface can also be called the surface on one side in the Z direction and the surface on the other side in the Z direction, respectively.

[0033] 1.1.4.1 Planar structure of semiconductor memory device An example of the planar configuration of the semiconductor memory device 1 will be described with reference to Fig. 3. Fig. 3 is a plan view showing an example of the planar layout of the semiconductor memory device according to the embodiment.

[0034] 3, the semiconductor memory device 1 is divided into a circuit region CR, a wall region WR, and a kerf region KR. The circuit region CR is further divided into an array region AR and a peripheral region PR.

[0035] The circuit region CR is a region in which elements constituting the semiconductor memory device 1, such as a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16, are provided. The memory cell array 10 is provided in an array region AR within the circuit region CR. Electrode pads PD are further provided in the peripheral region PR. The electrode pads PD are exposed, for example, on the surface of the semiconductor memory device 1 and function as connection pads for connecting to devices external to the semiconductor memory device 1. The circuit region CR is, for example, a rectangular region.

[0036] The wall region WR is, for example, a region provided so as to surround the outer periphery of the circuit region CR. A sealing portion (not shown) is provided in the wall region WR so as to surround the outer periphery of the circuit region CR when viewed from above. The sealing portion functions, for example, as a crack stopper or an edge seal.

[0037] The kerf region KR is a region provided to surround the outer periphery of the wall region WR. The kerf region KR is located at the outermost periphery of the semiconductor memory device 1. For example, alignment marks used during manufacturing of the semiconductor memory device 1 and circuits for performance testing of the semiconductor memory device 1 are provided in the kerf region KR.

[0038] 1.1.4.2 Memory Cell Array Structure First, an example of the structure of the memory cell array 10 provided in the array region AR in the circuit region CR will be described.

[0039] 1.1.4.2.1 Overall Configuration of Memory Cell Array The overall configuration of the memory cell array 10 will be described with reference to Fig. 4. Fig. 4 is a plan view showing an example of a planar layout of the memory cell array included in the semiconductor memory device according to the embodiment. Fig. 4 shows areas corresponding to four blocks BLK0 to BLK3.

[0040] The memory cell array 10 includes a stacked wiring structure and a plurality of components SLT and SHE. The stacked wiring structure includes select gate lines SGD and SGS and a plurality of word lines WL. The stacked wiring structure is a structure in which the select gate lines SGD and SGS and the plurality of word lines WL are stacked along the Z direction according to the number of layers. In the following description, the select gate lines SGD and SGS and the plurality of word lines WL are also collectively referred to as stacked wiring.

[0041] The stacked wiring structure is provided, for example, in the X direction across the memory region MR and the lead-out region HR.

[0042] The memory region MR is essentially a region where data is stored.

[0043] The lead-out region HR is a region used for connecting the stacked wiring to the peripheral circuits PERI such as the row decoder module 15.

[0044] Each member SLT extends in the X direction. Each member SLT crosses the stacked wiring structure in the X direction across the memory region MR and the lead region HR. Each member SLT has a structure in which, for example, an insulator or a plate-shaped conductor is embedded inside. Each member SLT separates adjacent stacked wirings via that member SLT. Each area separated by multiple members SLT corresponds to one block BLK. In the following description, the end of the blocks BLK0 to BLK3 on the block BLK0 side along the Y direction is referred to as one end in the Y direction. Furthermore, the end of the blocks BLK0 to BLK3 on the block BLK3 side along the Y direction is referred to as the other end in the Y direction.

[0045] Each member SHE extends in the X direction. In the embodiment, a case where three members SHE are provided between adjacent members SLT will be described. Each member SHE crosses the stacked wiring structure in the X direction across the memory region MR. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates adjacent select gate lines SGD via the member SHE, for example. Each area partitioned by multiple members SLT and SHE corresponds to one string unit SU.

[0046] In the memory cell array 10, for example, the planar layout shown in FIG. 4 is repeatedly arranged in the Y direction.

[0047] Note that the planar layout of the memory cell array 10 is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be any number depending on the number of string units SU.

[0048] 1.1.4.2.2 Memory Cell Array Structure in the Memory Area The structure of the memory cell array 10 in the memory region MR will be described.

[0049] 1.1.4.2.2.1 Planar structure The planar structure of the memory cell array 10 in the memory region MR will be described with reference to Fig. 5. Fig. 5 is a plan view showing an example of a planar layout of the memory cell array included in the semiconductor memory device according to the embodiment.

[0050] In the memory region MR, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Also, each member SLT includes a core portion LI and a spacer SP.

[0051] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent members SLT. Then, for example, counting from one end in the Y direction, one member SHE overlaps with the fifth memory pillar MP, the tenth memory pillar MP, and the fifteenth memory pillar MP.

[0052] Each of the multiple bit lines BL extends in the Y direction. The multiple bit lines BL are also aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example of FIG. 5, each bit line BL is arranged so as to overlap two memory pillars MP for each string unit SU. One of the multiple bit lines BL overlapping with a memory pillar MP is electrically connected to the memory pillar MP via a contact CV. For example, no contact is provided between the memory pillar MP overlapping with the member SHE and the bit line BL. In other words, the memory pillar MP overlapping with the member SHE is not electrically connected to the bit line BL.

[0053] The core portion LI is a conductor extending in the X direction. The spacers SP are insulators provided on the side surfaces of the core portion LI. The core portion LI is sandwiched between the spacers SP. The core portion LI and the stacked wiring adjacent to the core portion LI in the Y direction are electrically separated by the spacers SP. As a result, the core portion LI and the stacked wiring adjacent to the core portion LI in the Y direction are electrically insulated from each other.

[0054] 1.1.4.2.2.2 Cross-sectional structure The cross-sectional structure of the memory region MR of the memory cell array 10 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the embodiment.

[0055] The memory cell array 10 further includes conductor layers 30, 31, 32, 33, and 35, multiple conductor layers 34, 36, 37, and 38, insulator layers 40, 41, 43, 44, and 45, and multiple insulator layers 42. FIG. 6 shows five memory pillars MP out of the multiple memory pillars MP. FIG. 6 also shows a case where the multiple conductor layers 34 and multiple insulator layers 42 include eight conductor layers 34 and eight insulator layers 42. The memory cell array 10 is provided between the electrode pads PD of the semiconductor memory device 1 and a semiconductor substrate in the Z direction.

[0056] The conductor layer 30 is provided, for example, in the shape of a plate extending along the XY plane. The conductor layer 30 is made of a conductive material. The conductive material is, for example, an N-type semiconductor doped with impurities.

[0057] A conductor layer 31 is provided on the first surface of the conductor layer 30. The conductor layer 31 is made of a conductive material. For example, the conductive material is doped polysilicon to which N-type impurities are added. As will be described later, the conductor layer 31 is formed on the conductor layer 30 and the first surfaces of the multiple memory pillars MP. As a result, the first surface of the conductor layer 31 has irregularities corresponding to, for example, the multiple memory pillars MP. In other words, the first surface of the conductor layer 31 does not need to be flat.

[0058] The conductor layer 32 is provided on the first surface of the conductor layer 31. The conductor layer 32 is made of a conductive material. The conductive material includes, for example, at least one of tungsten, aluminum, titanium, and titanium nitride. The conductor layer 32 is formed on the first surface of the conductor layer 31, as described below. As a result, the first surface of the conductor layer 32 has irregularities corresponding to the multiple memory pillars MP, similar to the first surface of the conductor layer 31. In other words, the first surface of the conductor layer 32 does not have to be flat, similar to the first surface of the conductor layer 31.

[0059] The conductive layers 30, 31, and 32 thus formed function as source lines SL.

[0060] An insulator layer 40 is stacked on the second surface of the conductor layer 30. A conductor layer 33 is stacked on the second surface of the insulator layer 40. The conductor layer 33 is provided, for example, in the shape of a plate extending along the XY plane. The conductor layer 33 is used as a select gate line SGS. The conductor layer 33 includes, for example, tungsten.

[0061] An insulator layer 41 is stacked on the second surface of the conductor layer 33. Eight conductor layers 34 and eight insulator layers 42 are stacked on the second surface of the insulator layer 41 in the Z2 direction in the order conductor layer 34, insulator layer 42, ..., conductor layer 34, insulator layer 42. The conductor layer 34 is provided, for example, in the shape of a plate extending along the XY plane. The eight conductor layers 34 are used as word lines WL0 to WL7 in order along the Z2 direction. The conductor layers 34 include, for example, tungsten.

[0062] A conductor layer 35 is stacked on the second surface of the othermost insulator layer 42 in the Z direction among the eight insulator layers 42. The conductor layer 35 is provided, for example, in the shape of a plate extending along the XY plane. The conductor layer 35 is used as a select gate line SGD. The conductor layer 35 includes, for example, tungsten. The conductor layer 35 is electrically insulated for each string unit SU by, for example, a plurality of members SHE.

[0063] An insulating layer 43 is stacked on the second surface of the conductive layer 35. A plurality of conductive layers 36 are stacked on the second surface of the insulating layer 43. Each conductive layer 36 is provided to extend along the Y direction. FIG. 6 illustrates one of the plurality of conductive layers 36. Each conductive layer 36 functions as a bit line BL. The plurality of conductive layers 36 are electrically connected to a plurality of memory pillars MP via a plurality of conductive layers 37 and 38.

[0064] The laminated structure including the conductive layers 30-33 and 35, the plurality of conductive layers 34 and 36-38, the insulator layers 40, 41, and 43, and the plurality of insulator layers 42 is provided so as to be surrounded by insulators. FIG. 6 shows the insulator layer 44 in contact with the first surface of the conductive layer 32 and the insulator layer 45 in contact with the second surface of the conductive layer 36. Although not shown in FIG. 6, the conductive layer 32 is electrically connected to the peripheral circuit PERI via a conductive layer on one side of the conductive layer 32, as will be described later. Although not shown in FIG. 6, each of the plurality of conductive layers 36 is electrically connected to the peripheral circuit PERI via, for example, a conductive layer on the other side of the plurality of conductive layers 36, as will be described later.

[0065] A plurality of memory pillars MP are provided extending along the Z direction on one side of the plurality of conductive layers 36. The plurality of memory pillars MP penetrate the conductive layers 30, 33, and 35 and the plurality of conductive layers 34.

[0066] Each of the multiple memory pillars MP includes, for example, a core member 50, a semiconductor film 51, and a stacked film 52. The core member 50 is provided extending along the Z direction. The semiconductor film 51 covers the periphery of the core member 50. The semiconductor film 51 contacts the conductor layer 31. The stacked film 52 covers the side surface of the semiconductor film 51 except for the portion where the semiconductor film 51 contacts the conductor layer 31. The core member 50 includes an insulator such as silicon oxide. The semiconductor film 51 includes, for example, silicon. The configuration of the stacked film 52 will be described later.

[0067] A conductor layer 37 is provided on the second surface of the semiconductor film 51. The conductor layer 37 functions, for example, as a columnar contact. A conductor layer 38 is provided on the second surface of the conductor layer 37. The conductor layer 38 functions, for example, as a contact CV. With the above configuration, the conductor layers 37 and 38 connect the semiconductor film 51 and the conductor layer 36. One conductor layer 37 and one conductor layer 38 are connected to one conductor layer 36 in each of the spaces partitioned by the members SLT and SHE.

[0068] The member SLT divides, for example, the conductive layers 30, 33, and 35 and the plurality of conductive layers 34. A core portion LI within the member SLT is provided along the member SLT. The second surface of the core portion LI is located between the conductive layer 35 and the conductive layer 36. The first surface of the core portion LI is located, for example, between the conductive layer 30 and the insulating layer 44. A spacer SP is provided between the core portion LI and the conductive layers 30, 31, 33, and 35 and the plurality of conductive layers 34. The core portion LI is separated and electrically insulated from the conductive layers 33 and 35 and the plurality of conductive layers 34 by the spacer SP. Although not shown in FIG. 6 , the core portion LI may include a barrier metal. That is, the core portion LI may have a structure in which a barrier metal covers the first surface and side surfaces of a conductive member containing a metal such as tungsten. Moreover, the core portion LI may be formed of a semiconductor member, or may have a structure in which the entire member SLT is embedded in the insulating material of the spacer SP.

[0069] The intersections of the memory pillars MP and the conductive layer 33 function as select transistors ST2. The intersections of the memory pillars MP and the conductive layers 34 function as memory cell transistors MT. The intersections of the memory pillars MP and the conductive layer 35 function as select transistors ST1.

[0070] 1.1.4.2.2.3 Cross-sectional structure of memory pillar The structure of the memory pillar MP will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of the cross-sectional structure of the memory pillar of the semiconductor memory device according to the embodiment.

[0071] The stacked film 52 includes a tunnel insulating film 53, a charge storage film 54, and a block insulating film 55. The tunnel insulating film 53 covers the side surface of the semiconductor film 51 except for the portion where the semiconductor film 51 and the conductor layer 31 contact each other. The charge storage film 54 covers the side surface of the tunnel insulating film 53. The block insulating film 55 covers the side surface of the charge storage film 54.

[0072] The tunnel insulating film 53 and the block insulating film 55 include, for example, silicon oxide. The charge storage film 54 includes, for example, silicon nitride. The charge storage film 54 is a film that can store electric charges.

[0073] In the above configuration, the semiconductor film 51 functions as the channels of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. The charge storage film 54 has the function of storing an amount of charge corresponding to the data stored in the memory cell transistors MT. By turning on the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2, the semiconductor memory device 1 passes a current between the source line SL and the bit line BL via the memory pillar MP and the conductor layers 37 and 38.

[0074] 1.1.4.3 Overall cross-sectional structure of semiconductor memory device The overall cross-sectional structure of the semiconductor memory device 1 will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region of the semiconductor memory device according to the embodiment. Fig. 8 shows the cross-sectional structure of a portion of the semiconductor memory device 1.

[0075] The semiconductor memory device 1 has a structure in which a circuit chip 1-1 and a memory chip 1-2 are bonded together.

[0076] 1.1.4.3.1 Circuit Chip First, the cross-sectional structure of the circuit chip 1-1 will be described.

[0077] The circuit chip 1-1 includes, for example, a semiconductor substrate 70, a plurality of conductor layers 101, 102, 103, 104, 105, and 106 that form part of the peripheral circuit PERI, and insulator layers 46 and 60. The semiconductor substrate 70 is made of, for example, a P-type semiconductor doped with impurities.

[0078] The plurality of conductive layers 101 to 106 each function as, for example, a columnar contact or wiring. The plurality of conductive layers 103 includes conductive layers 103-1 and 103-2. The plurality of conductive layers 104 includes conductive layers 104-1 and 104-2. The plurality of conductive layers 105 includes conductive layers 105-1 and 105-2. The plurality of conductive layers 106 includes conductive layers 106-1 and 106-2.

[0079] An insulator layer 46 is provided on the first surface of the semiconductor substrate 70. The insulator layer 46 includes, for example, silicon oxide. A plurality of conductor layers 101, 102, 103, 104, and 105 are provided within the insulator layer 46.

[0080] A peripheral circuit PERI is provided in a circuit region CR on the first surface of the semiconductor substrate 70. In FIG. 8, transistors Tr1 and Tr2 are shown as examples of components included in the peripheral circuit PERI. In the following description, when there is no need to distinguish between the transistors Tr1 and Tr2, the transistors Tr1 and Tr2 will simply be referred to as transistors Tr. Each transistor Tr includes a gate insulating film, a gate electrode, and a source and a drain (not shown) provided in the semiconductor substrate 70.

[0081] A plurality of conductive layers 101 are provided on the first surfaces of the gate electrode, source, and drain of transistor Tr1 and the gate electrode, source, and drain of transistor Tr2. A plurality of conductive layers 102 are connected to the first surfaces of the plurality of conductive layers 101, respectively.

[0082] Each of the plurality of conductive layers 103 is connected to a first surface of the conductive layer 102 corresponding to that conductive layer 103 among the plurality of conductive layers 102. Conductive layers 103-1 and 103-2 are electrically connected to transistors Tr1 and Tr2, respectively.

[0083] The conductive layers 104-1 and 104-2 are connected to the first surfaces of the conductive layers 103-1 and 103-2, respectively.

[0084] The conductive layers 105-1 and 105-2 are connected to the first surfaces of the conductive layers 104-1 and 104-2, respectively. The first surfaces of the plurality of conductive layers 105 are provided so as to be flush with the first surface of the insulating layer 46.

[0085] An insulator layer 60 is provided on the insulator layer 46 and the first surfaces of the plurality of conductor layers 105. The insulator layer 60 includes, for example, silicon oxide.

[0086] A plurality of conductor layers 106 are provided on the same layer as the insulator layer 60. The conductor layers 106-1 and 106-2 are connected to first surfaces of the conductor layers 105-1 and 105-2, respectively. The first surfaces of the plurality of conductor layers 106 are provided so as to be flush with the first surface of the insulator layer 60. The plurality of conductor layers 106 include, for example, copper. The plurality of conductor layers 106 function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. The connection pads are also called bonding pads.

[0087] 1.1.4.3.2 Memory Chips Next, the cross-sectional structure of the memory chip 1-2 will be described with reference to FIG.

[0088] The memory chip 1-2 includes, for example, a plurality of conductive layers 201, 202, 203, 204, 205, 206, and 207, a conductive layer 39, insulating layers 44, 45, 47, 48a, 48b, 48c, 61, and 62, semiconductor layers 301 and 302, and a memory cell array 10.

[0089] The plurality of conductor layers 201 to 207 each function as, for example, a columnar contact or wiring. The plurality of conductor layers 201 includes conductor layers 201-1 and 201-2. The plurality of conductor layers 202 includes conductor layers 202-1 and 202-2. The plurality of conductor layers 203 includes conductor layers 203-1 and 203-2. The plurality of conductor layers 204 includes conductor layers 204-1 and 204-2. The plurality of conductor layers 205 includes conductor layers 36 (205) and 205-1. The plurality of conductor layers 206 includes conductor layers 206-1, 206-2, and 206-3. The plurality of conductor layers 207 includes conductor layers 207-1, 207-2, and 207-3.

[0090] In the memory chip 1-2, an insulating layer 61 is provided on the first surface of the circuit chip 1-1. The insulating layer 61 includes, for example, silicon oxide.

[0091] A plurality of conductor layers 201 are provided on the same layer as the insulator layer 61. The conductor layers 201-1 and 201-2 are connected to first surfaces of the conductor layers 106-1 and 106-2, respectively. The second surfaces of the plurality of conductor layers 201 are provided so as to be flush with the second surface of the insulator layer 61. The plurality of conductor layers 201 include, for example, copper. The plurality of conductor layers 201 function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. With the above-described configuration, the circuit chip 1-1 and the memory chip 1-2 are electrically connected by the plurality of conductor layers 106 and 201.

[0092] An insulating layer 45 is provided on the first surfaces of the insulating layer 61 and the plurality of conductor layers 201. In the insulating layer 45, the plurality of conductor layers 202 to 206, a portion of the plurality of conductor layers 207, and a portion of the memory cell array 10 are provided.

[0093] The memory cell array 10 is provided so that the conductive layer 32 is disposed on one side in the Z direction, and the conductive layer 36 (205) is disposed on the other side in the Z direction.

[0094] Conductor layer 202-1 is provided on a first surface of conductive layer 201-1. Conductor layer 203-1 is connected to the first surface of conductive layer 202-1. Conductor layer 204-1 is connected to the first surface of conductive layer 203-1. The first surface of conductive layer 204-1 is connected to conductive layer 36 (205). With the above configuration, conductive layer 36 and transistor Tr1 are connectable. That is, bit lines BL of memory cell array 10 and peripheral circuit PERI are electrically connected.

[0095] A conductor layer 202-2 is provided on the first surface of the conductor layer 201-2. A conductor layer 203-2 is provided on the first surface of the conductor layer 202-2. A conductor layer 204-2 is provided on the first surface of the conductor layer 203-2. A conductor layer 205-1 is provided on the first surface of the conductor layer 204-2. A conductor layer 206-1, 206-2, and 206-3 are provided on the first surface of the conductor layer 205-1. A conductor layer 207-1 is provided on the first surface of the conductor layer 206-1. The conductor layer 207-1 extends in the Z direction. One side of the conductor layer 207-1 protrudes from the insulator layer 45. The conductor layer 207-1 functions, for example, as a columnar contact.

[0096] Similar to the conductor layer 206-1, conductor layers 207-2 and 207-3 are provided on the first surfaces of the conductor layers 206-2 and 206-3, respectively. Similar to the conductor layer 207-1, the conductor layers 207-2 and 207-3 extend in the Z direction. One side of each of the conductor layers 207-2 and 207-3 protrudes from the insulating layer 45. The conductor layers 207-2 and 207-3 function as, for example, columnar contacts. The conductor layers 207-1, 207-2, and 207-3 are electrically connected to the common conductor layer 201-2 via the conductor layer 205-1 in the insulating layer 45. In addition, each of the conductive layers 207-1, 207-2, and 207-3 may be electrically connected to the conductive layer 201-2 via the common conductive layer 203-2, and also via a plurality of conductive layers 204 and a plurality of conductive layers 205, respectively, provided on the first surface of the conductive layer 203-2.

[0097] In a region excluding the memory cell array 10, for example, a semiconductor layer 301 is provided on a portion of the first surface of the insulator layer 45, sandwiching a region R1 including a portion where the plurality of conductor layers 207 are provided, and adjacent to the region R1. The semiconductor layer 301 and the conductor layer 30 in the memory cell array 10 are provided in the same layer. An insulator layer 62 is provided on the first surface of the semiconductor layer 301. A semiconductor layer 302 is provided on the first surface of the insulator layer 62. The semiconductor layers 301 and 302 are, for example, non-doped polysilicon. The semiconductor layers 301 and 302 are electrically insulated from the source line SL. An insulator layer 47 is provided on the first surface of the semiconductor layer 302. With the above configuration, in FIG. 8 , the region R1 is sandwiched in the Y direction between two wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62.

[0098] The first surface of the insulator layer 45 in the region R1 is located, for example, on the other side of the first surface of the insulator layer 45 in a region adjacent to the region R1 in a region excluding the memory cell array 10. In other words, the first surface of the insulator layer 45 in the region R1 is located, for example, on the other side of the second surface of the semiconductor layer 301.

[0099] Insulator layers 44 are provided on the first surfaces of the insulator layer 45 and 47 in region R1, as well as on the first surfaces of the conductor layer 32. The first surface of the insulator layer 44 has, for example, a step near the boundary between region R1 and the regions sandwiching region R1. More specifically, the first surface of the insulator layer 44 in region R1 is located on the other side of the first surface of the insulator layer 44 on the first surface of the insulator layer 47. Furthermore, the first surface of the insulator layer 44 in region R1 is located at approximately the same height as the first surface of the insulator layer 44 on the first surface of the conductor layer 32. Although not shown in FIG. 8 , the first surface of the insulator layer 44 also has a step near the boundary between the region where the conductor layer 32 is provided and the region adjacent to that region.

[0100] Conductor layers 31A and 32A resulting from the formation of conductor layers 31 and 32 (described later) may be provided on two wall surfaces sandwiching region R1 in the Y direction, the wall surfaces being composed of semiconductor layers 301 and 302 and insulator layers 47 and 62. Note that in regions not shown in FIG. 8 , region R1 may also be sandwiched in the X direction, for example, by a similar configuration. That is, the semiconductor memory device 1 has, for example, two wall surfaces sandwiching region R1 in the X direction, the wall surfaces being composed of semiconductor layers 301 and 302 and insulator layers 47 and 62. Conductor layers 31A and 32A resulting from the formation of conductor layers 31 and 32 (described later) may also be provided on these two wall surfaces. As described above, region R1 is surrounded by four wall surfaces, for example, when viewed from above. With the above configuration, conductor layers 31A and 32A may be provided between the wall surfaces and the insulator layer 44. The conductive layers 31A and 32A may be provided on a portion of each wall surface or on the entire surface.

[0101] The first surface of the conductor layer 32 has a portion where the insulator layer 44 is not provided. Furthermore, portions of one side of the plurality of conductor layers 207 protruding from the insulator layer 45 and portions of the first surface of the insulator layer 45 surrounding each of the plurality of conductor layers 207 are not covered by the insulator layer 44. The conductor layer 39 is provided on the first surface of the insulator layer 44, on portions of the first surface of the conductor layer 32 where the insulator layer 44 is not provided, on portions of one side of the plurality of conductor layers 207 protruding from the insulator layer 45, and on portions of the first surface of the insulator layer 45 surrounding each of the plurality of conductor layers 207. With this configuration, the conductor layer 39 includes a connection portion V1 in contact with the conductor layer 32, a plurality of connection portions V2 in contact with the plurality of conductor layers 207, and an extension portion extending in the Y direction excluding the connection portions V1 and V2. The conductor layer 39 functions as a wiring layer. The conductor layer 39 includes, for example, aluminum. The first and second surfaces of the extending portion of the conductive layer 39 have a step due to, for example, the step on the first surface of the insulating layer 44 described above.

[0102] The connection portion V1 can be considered to be a via in which the space between the extended portion of the conductor layer 39 and the conductor layer 32 is filled. Each of the multiple connection portions V2 can be considered to be a via in which the space between the extended portion of the conductor layer 39, the conductor layer 207 corresponding to the connection portion V2, and a portion of the first surface of the insulator layer 45 surrounding the conductor layer 207 is filled. Each of the multiple connection portions V2 is provided so as to cover one side of the multiple conductor layers 207 protruding from the insulator layer 45. More specific structures of the connection portions V1 and V2 will be described later. The extended portion of the conductor layer 39 is provided on one side of the first surface of the conductor layer 32. That is, the extended portion of the conductor layer 39 is provided on one side of the first surface on the one side of the source line SL. Furthermore, the extended portion of the conductor layer 39 is provided on one side of the first surface of the semiconductor layer 302.

[0103] With the above configuration, for example, the conductive layer 32 and the transistor Tr2 are connectable via the conductive layers 39, 101 to 106, and 201 to 207. That is, the source line SL and the peripheral circuit PERI are electrically connected.

[0104] In a cross section (not shown), the semiconductor memory device 1 may include a configuration similar to the portion of the conductive layer 39 including the electrode pad PD and the plurality of connection portions V2, which is electrically insulated from the portion of the conductive layer 39 including the connection portion V1. This configuration is electrically connected to the peripheral circuit PERI via, for example, the conductive layers 101 to 106 and 201 to 207.

[0105] The extending portion of the conductor layer 39 includes a region exposed on the first surface of the semiconductor memory device 1. This region constitutes, for example, an electrode pad PD that is connected to an external device of the semiconductor memory device 1. The electrode pad PD is provided at a position overlapping with the region R1 in the Z direction. As a result, the semiconductor layers 301 and 302 are not provided in the region overlapping with the electrode pad PD in the Z direction. Furthermore, the electrode pad PD is provided at a position that does not overlap with, for example, the plurality of conductor layers 207 and the plurality of connection portions V2 in the Z direction. With the above configuration, in the region overlapping with the electrode pad PD in the Z direction, the insulator layer 44 is provided in the same layer as the semiconductor layers 301 and 302 and the insulator layer 62.

[0106] Except for the region where the electrode pads PD are provided, insulator layers 48a, 48b, and 48c are stacked in this order on one side in the Z direction on the first surface of the conductor layer 39. The insulator layer 48a is an insulator containing, for example, silicon oxide. The insulator layers 48b and 48c contain, for example, silicon nitride and a resin material. The insulator layers 48b and 48c function, for example, as a passivation film.

[0107] 1.1.4.3.3 Structure around the connection The structure around connection portions V1 and V2 will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view showing an example of connection portions between the wiring layer and the source line and contact in the semiconductor memory device according to the embodiment. Fig. 9 shows a portion including connection portion V1, a portion including connection portion V2, and a portion including insulator layers 47 and 62 adjacent to region R1.

[0108] The second surface of the connection portion V2 is located, for example, on the other side of the first surface of the conductor layer 32. That is, the second surface of the connection portion V2 is located, for example, on the other side of the first surface at the most one side of the source line SL. Also, the second surface of the connection portion V2 is located, for example, on the other side of the first surface of the conductor layer 30 and the first surface of the semiconductor layer 301.

[0109] Furthermore, the second surface of the extending portion of the conductive layer 39 excluding the connection portion V1 in the memory region MR and the second surface of the extending portion of the conductive layer 39 excluding the connection portion V2 in the region R1 are located at approximately the same position in the Z direction. As a result, one end of the connection portion V1 and one end of the connection portion V2 are aligned at that position. Therefore, the height H2 of the connection portion V2 is higher than the height H1 of the connection portion V1. The height H1 is the height from the second surface of the connection portion V1 to the above-mentioned position. The height H2 is the height from the second surface of the connection portion V2 to the above-mentioned position.

[0110] Furthermore, the aspect ratio H2 / W1 of the height H2 to the width W1 of the connection portion V2 along the Y direction is, for example, about 1.5 or less. The aspect ratio H2 / W2 of the height H2 to the width W2 (not shown) of the connection portion V2 along the X direction is also, for example, about 1.5 or less. With this configuration of the connection portion V2, when forming the conductive layer 39 in the manufacturing process of the semiconductor memory device 1 described below, the trench corresponding to the connection portion V2 is not insufficiently filled with a conductor.

[0111] Note that the first surface of the conductor layer 39 may have recesses at portions that overlap with the connection portions V1 and V2 in the Z direction, resulting from the conductor being embedded in the grooves.

[0112] 1.1.4.3.4 Structure around multiple connection parts V2 The structure around the multiple connection portions V2 will be further described with reference to Fig. 10. Fig. 10 is a cross-sectional view taken along line XX in Fig. 8, showing an example of a connection portion between a wiring layer and a contact in the semiconductor memory device according to the embodiment.

[0113] In the XY cross section, the plurality of conductive layers 207 functioning as contacts are arranged, for example, in a lattice pattern. In Fig. 10, nine conductive layers 207 are arranged in a lattice pattern of 3 rows and 3 columns.

[0114] In the XY cross section, the multiple connection portions V2 are arranged in a lattice pattern, for example, corresponding to the multiple conductor layers 207. Each of the multiple connection portions V2 is provided so as to surround, in the XY cross section, the conductor layer 207 that corresponds to the connection portion V2 among the multiple conductor layers 207.

[0115] 1.1.4.3.5 Cross-sectional structure of connection pads The cross-sectional structure of the connection pad will be described with reference to Fig. 11. Fig. 11 is a cross-sectional view showing an example of the cross-sectional structure of the connection pad of the semiconductor memory device according to the embodiment. Note that, although the following describes the portion where the conductor layer 106-1 and the conductor layer 201-1 are connected, the same applies to the portions where each of the other plurality of conductor layers 106 is connected to the conductor layer 201 corresponding to that conductor layer 106.

[0116] On the bonding surface where the circuit chip 1-1 and the memory chip 1-2 are bonded together, the area of ​​the conductor layer 106-1 and the area of ​​the conductor layer 40-1 are, for example, equal. If the conductor layers 106-1 and 201-1 are copper, they may become integrated, making it difficult to identify the boundary between the copper layers. However, for example, the bonding can be confirmed by the distortion of the bonded shape of the conductor layers 106-1 and 201-1 due to misalignment during bonding. Furthermore, the bonding can be confirmed by the misalignment of the copper barrier metal, for example. That is, the bonding can be confirmed by the occurrence of discontinuities on the side surfaces.

[0117] Furthermore, when the conductive layers 106-1 and 201-1 are formed by the damascene method, their respective side surfaces have a tapered shape. As a result, the sidewalls of the conductive layers 106-1 and 201-1 are not linear. As a result, the cross section along the Z direction at the bonded portion of the conductive layers 106-1 and 201-1 is non-rectangular.

[0118] Furthermore, when the conductive layers 106-1 and 201-1 are bonded together, the first, second, and side surfaces of the copper that forms them are covered with a barrier metal. In contrast, in a typical wiring layer using copper, an insulating layer (such as silicon nitride or silicon carbide containing nitrogen) that functions to prevent oxidation of copper is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0119] 1.2 Manufacturing method of semiconductor memory device A method for manufacturing the semiconductor memory device 1 will be described with reference to Figures 12 to 18. Figures 12 to 18 are cross-sectional views for explaining an example of a method for manufacturing the semiconductor memory device according to the embodiment. The cross-sectional views shown in Figures 12 to 18 show the region corresponding to Figure 8.

[0120] 12, the transistors Tr1 and Tr2 included in the peripheral circuit PERI, the plurality of conductor layers 101 to 106, and the insulator layers 46 and 60 are formed on the semiconductor substrate 70. That is, the circuit chip 1-1 is formed.

[0121] 13, on the second surface of semiconductor substrate 71 made of an impurity-doped P-type semiconductor, insulator layer 47, conductor layers 33 and 35, multiple conductor layers 34 and 201-207, semiconductor layers 301 and 302, insulator layers 40, 41, 43, 44, and 62, multiple insulator layers 42, structures corresponding to multiple memory pillars MP, and portions of insulator layer 45 and insulator layer 61 covering these are formed. In other words, a structure corresponding to memory chip 1-2 is formed. Note that semiconductor layers 301 and 302 and insulator layers 47 and 62 are entirely formed on the second surface of semiconductor substrate 71.

[0122] 14, the circuit chip 1-1 and the structure corresponding to the memory chip 1-2 are bonded together by a bonding process. More specifically, a plurality of conductor layers 106 functioning as connection pads in the circuit chip 1-1 and a plurality of conductor layers 201 functioning as connection pads in the memory chip 1-2 are arranged to face each other. The facing connection pads are then bonded together by a heat treatment. Thereafter, the semiconductor substrate 71 is removed by, for example, CMP (Chemical Mechanical Polishing).

[0123] 15, the insulator layer 47 and the semiconductor layer 302 are removed from the portion corresponding to the memory cell array 10 and the portion corresponding to the region R1. The removal of the portion corresponding to the memory cell array 10 and the portion corresponding to the region R1 is performed, for example, all at once.

[0124] Furthermore, in the memory pillar MP, a portion of the stacked film 52 on one side of the insulator layer 62 is removed. As a result, the semiconductor film 51 on one side of the insulator layer 62 is exposed to the surface. Furthermore, the insulator layer 62 is removed in a portion corresponding to the memory cell array 10 and a portion corresponding to the region R1. As a result, the semiconductor layer 301 is exposed to the surface in a portion corresponding to the memory cell array 10 and a portion corresponding to the region R1. Note that in the portion corresponding to the memory cell array 10, for example, portions on one side of the plurality of members SLT are also exposed to the surface. Furthermore, in the portion corresponding to the region R1, for example, portions on one side of the plurality of conductor layers 207 are also exposed to the surface.

[0125] Next, as shown in FIG. 16 , conductor layers 31 and 32 are stacked on the exposed portions of the first surface of the semiconductor layer 301, the exposed portions of the memory pillars MP, the first surface of the insulator layer 47, the portions on one side of the plurality of members SLT, and the portions on one side of the plurality of conductor layers 207. At this time, the portion of the semiconductor layer 301 corresponding to the memory cell array 10 is transformed into the conductor layer 30 by impurity diffusion. More specifically, in the above process, amorphous silicon is first deposited on the exposed portions of the first surface of the semiconductor layer 301, the exposed portions of the memory pillars MP, the first surface of the insulator layer 47, the portions on one side of the plurality of members SLT, and the portions on one side of the plurality of conductor layers 207. Then, by introducing impurities into the deposited amorphous silicon and subsequent heat treatment, the impurities diffuse into the semiconductor layer 301, and the deposited amorphous silicon is transformed into polysilicon. This forms the conductive layers 30 and 31. Then, the conductive layer 32 is formed on the first surface of the conductive layer 31 that has been formed.

[0126] 17, portions of the conductor layers 31 and 32 formed as described above, excluding the memory cell array 10, are removed by etching or the like using a mask. At this time, the semiconductor layer 301 and one side of the insulator layer 45 are also removed in the portion corresponding to region R1. As a result, in the portion corresponding to region R1, the first surface of the insulator layer 45 and one side portions of the plurality of conductor layers 207 protruding from the insulator layer 45 are exposed to the surface. Also, in FIG. 17, conductor layers 31A and 32A are formed as traces of the conductor layers 31 and 32 on the wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62 by the above-mentioned process.

[0127] Then, an insulator layer 44 is formed on the first surface of the conductor layer 32, the first surface of the insulator layer 47, the exposed portion of the first surface of the insulator layer 45 in the region corresponding to region R1, the portions of one side of the plurality of conductor layers 207 protruding from the insulator layer 45, and the conductor layers 31A and 32A. The portion on one side of the insulator layer 44 is then removed by CMP. Note that the CMP process does not need to be performed until the first surface of the structure formed as described above is flat. This may result in a step being formed on the first surface of the insulator layer 44 near the boundary between the portion corresponding to region R1 and the adjacent portion.

[0128] Next, as shown in FIG. 18 , a groove SH1 corresponding to the connection portion V1 and multiple grooves SH2 corresponding to the multiple connection portions V2 are formed. More specifically, anisotropic etching is performed using a mask including openings corresponding to the connection portion V1 and the multiple connection portions V2 to simultaneously remove the regions where the connection portion V1 and the multiple connection portions V2 are to be formed. This results in the formation of the groove SH1 and the multiple grooves SH2. The anisotropic etching is performed, for example, until the insulator layer 45 is exposed in each region overlapping the openings corresponding to the multiple connection portions V2 in the Z direction. At this time, portions of the insulator layer 45 may be removed in these regions. As a result, after the anisotropic etching, the portions of the first surface of the insulator layer 45 that overlap the multiple grooves SH2 in the Z direction are located on the other side of the first surface of the insulator layer 45 other than these portions. The anisotropic etching in this process is, for example, RIE. The mask is then removed. Since the etching selectivity between the insulating layers 44 and 45 and the conductive layer 32 is high, the groove SH1 and the plurality of grooves SH2 can be formed collectively.

[0129] Then, a conductor layer 39 is formed on the first surface of the insulator layer 44, on portions of the first surface of the conductor layer 32 where the insulator layer 44 is not provided, on portions of one side of the plurality of conductor layers 207 protruding from the insulator layer 45, and on portions of the first surface of the insulator layer 45 surrounding each of the plurality of conductor layers 207. At this time, the conductor layer 39 is formed so as to be embedded in the groove SH1 and the plurality of grooves SH2. The portion of the conductor layer 39 embedded in the groove SH1 is the connection portion V1. The portion of the conductor layer 39 embedded in the plurality of grooves SH2 is the connection portion V2. Furthermore, on the first surface of the structure formed as described above, excluding the region of the conductor layer 39 corresponding to the electrode pad PD, insulator layers 48a, 48b, and 48c are formed.

[0130] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0131] It should be noted that the manufacturing process described above is merely an example, and other processes may be inserted between the respective manufacturing processes, or the order of the manufacturing processes may be changed. For example, since the structures corresponding to the circuit chip 1-1 and the memory chip 1-2 are formed using different semiconductor substrates 70 and 71, the process of forming the circuit chip 1-1 shown in Figure 12 and the process of forming the structure corresponding to the memory chip 1-2 shown in Figure 13 can be carried out in parallel.

[0132] 1.3 Effects According to the embodiment, it is possible to suppress the deterioration of the current characteristics of the semiconductor memory device 1. The effects of the embodiment will be described below.

[0133] In this embodiment, the semiconductor memory device 1 includes a circuit chip 1-1 including a semiconductor substrate 70 having an array region AR and a peripheral region PR, and a memory chip 1-2 that contacts the circuit chip 1-1 in the Z direction and is electrically connected to the circuit chip 1-1 via connection pads provided in a boundary region between the circuit chip 1-1 and the memory chip 1-2. The memory chip 1-2 includes a memory cell array 10 provided in the array region AR, a conductive layer 207 provided in the peripheral region PR and functioning as a contact, and a conductive layer 39 functioning as wiring. The conductive layer 207 extends in the Z direction and is electrically connected to the connection pads. The conductive layer 39 has a connection portion V2 electrically connected to one side of the conductive layer 207, and an extension portion that is continuous from the upper end (one end) of the connection portion V2 and extends in the Y direction to a position on one side of the first surface of the source line SL in the Z direction. The connection portion V2 has a shape in which a groove on one side of the conductive layer 207 in the Z direction is filled up to the second surface of the extension portion. Furthermore, the second surface of the connection portion V2 is located on the other side of the first surface of the source line SL in the Z direction. With the above-described configuration, for example, it is possible to suppress a decrease in the amount of current flowing through the conductive layer 39 on which the electrode pad PD is formed and in the EM (Electro Migration) resistance. Therefore, it is possible to suppress a decrease in the current characteristics of the semiconductor memory device 1.

[0134] To add to this, for example, in a comparative example where the wiring layer connected to the contact has a stepped structure in the YZ cross section, the thickness of the portion of the wiring layer extending in the Z direction that forms the step may become thin, which may make it difficult for the wiring layer to satisfy the current requirement of the device or may result in a decrease in EM resistance.

[0135] According to the embodiment, the conductor layer 39 on one side of the insulating layer 44 is connected to the plurality of conductor layers 207 via the plurality of connection portions V2. As a result, unlike the comparative example, the conductor layer 39 according to the embodiment does not include a stepped structure provided on the other side of the extension portion extending in the Y direction. In other words, the thickness of the wiring layer is prevented from becoming thin. Therefore, according to the semiconductor memory device 1 according to the embodiment, it is possible to prevent a deterioration in the current characteristics of the semiconductor memory device 1.

[0136] Furthermore, according to the embodiment, in the region overlapping with the electrode pad PD in the Z direction, an insulator layer 44 is provided in the same layer as the conductor layer 30. As a result, the semiconductor layers 301 and 302 are not included in this region. With this structure, it is possible to ensure a gap in the Z direction between the electrode pad PD and the wiring layer provided on the other side of the electrode pad PD. This suppresses interference between the electrode pad PD and the wiring layer having a different potential from that of the electrode pad PD. Therefore, it is possible to suppress a decrease in interface speed.

[0137] Furthermore, according to the embodiment, manufacturing costs can be reduced compared to the comparative example. Supplementally, in the manufacturing process of the device of the comparative example, for example, after a structure in which source lines are formed is filled with an insulator layer, the filled insulator layer and the polysilicon layer included in the same layer as the source lines are removed in a region including contacts outside the memory cell array when viewed from above. Then, for example, an insulator layer is formed on the surface of the region. Here, the top surface of the formed insulator layer is lower than the top surface of the insulator layer above the source lines. In such a case, if etching to form a portion connecting the source lines and the wiring layer and etching to form a portion connecting the contacts and the wiring layer are performed simultaneously, the contacts will be overexposed. Therefore, in the comparative example, these etchings are performed, for example, in separate processes. According to the embodiment, as shown in FIG. 15 , the insulator layer 47 and the semiconductor layer 302 in the portions corresponding to the memory cell array 10 and region R1 are simultaneously removed. Then, after the source lines SL are formed, an insulator layer 44 is filled in the portion formed by the removal. 18, it is possible to form the groove SH1 corresponding to the connection portion V1 and the plurality of grooves SH2 corresponding to the plurality of connection portions V2 at the same time, thereby reducing the manufacturing cost.

[0138] 2. Variations The above-described embodiment can be modified in various ways, and semiconductor memory devices according to modifications of the embodiment will be described below.

[0139] 2.1 First Modification In the above-described embodiment, the connection portion V2 is directly connected to the plurality of conductive layers 207, but this is not limiting. The connection portion V2 may be connected to the plurality of conductive layers 207 via a conductive layer different from the plurality of conductive layers 207. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the first modification will be described, focusing on differences from the configuration and manufacturing method of the semiconductor memory device according to the embodiment.

[0140] The configuration of the semiconductor memory device 1 according to the first modification will be described with reference to Fig. 19. Fig. 19 is a cross-sectional view showing an example of the cross-sectional structure of the circuit region of the semiconductor memory device according to the first modification.

[0141] As shown in FIG. 19 , in the semiconductor memory device 1 according to the first modification, in region R1, a conductor layer 32B is provided on the first surface of the insulator layer 45 so as to cover one side of the plurality of conductor layers 207. The conductor layer 32B is provided in a plate shape extending along the XY plane. The first surface of the conductor layer 32B may have irregularities corresponding to the plurality of conductor layers 207. That is, the first surface of the conductor layer 32B does not have to be flat, for example. Note that the first surface of the conductor layer 32B may also be flat.

[0142] The second surfaces of the plurality of connection portions V2 contact the first surface of the conductive layer 32B. Fig. 19 shows an example in which two connection portions V2 contact the conductive layer 32B. Note that the plurality of connection portions V2 only need to be connected to the conductive layer 32B, and do not necessarily need to be provided corresponding to the plurality of conductive layers 207. The number of connection portions V2 only needs to be one or more, and may be the same as or different from the number of the plurality of conductive layers 207.

[0143] Next, a method for manufacturing the semiconductor memory device 1 according to the first modification will be described with reference to Figures 20 to 24. Figures 20 to 24 are cross-sectional views for explaining an example of the method for manufacturing the semiconductor memory device according to the first modification. The cross-sectional views shown in Figures 20 to 24 show the region corresponding to Figure 19.

[0144] First, the same steps as those described with reference to FIGS. 12 to 15 in the embodiment are carried out.

[0145] Next, similar to the embodiment, a portion of the stacked film 52 on one side of the insulator layer 62 of the memory pillar MP is removed. Also, similar to the embodiment, the insulator layer 62 is removed from the portion corresponding to the memory cell array 10 and the region R1.

[0146] 20, a conductor layer 31 is stacked on the exposed portions of the first surface of the semiconductor layer 301, the exposed portions of the memory pillars MP, the first surface of the insulator layer 47, and portions on one side of the plurality of conductor layers 207. Furthermore, similar to the process described with reference to FIG. 16 of the embodiment, the portion of the semiconductor layer 301 corresponding to the memory cell array 10 is made into the conductor layer 30 by diffusing impurities.

[0147] 21 , a portion of the conductive layer 31 formed as described above excluding the memory cell array 10 and a portion of the semiconductor layer 301 corresponding to region R1 are removed. As a result, portions of the first surface of the insulator layer 45 in the portion corresponding to region R1 and portions on one side of the plurality of conductive layers 207 are exposed. Note that in the portion corresponding to region R1, for example, in addition to the conductive layer 31 and the semiconductor layer 301, one side of the insulator layer 45 is also removed. Also, in FIG. 21 , a conductive layer 31A is formed as a trace of the conductive layer 31 on the wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62 by the above-described process.

[0148] Then, as shown in FIG. 22, a conductor layer 32 is laminated on the first surface of the conductor layer 31, on the conductor layer 31A, on the first surface of the insulator layer 47, on the exposed portion of the first surface of the insulator layer 45, and on one side portions of the multiple conductor layers 207 protruding from the insulator layer 45.

[0149] 23, the conductive layer 32 formed as described above is removed except for the regions corresponding to the memory cell array 10 and the conductive layer 32B. This forms the conductive layer 32 and the conductive layer 32B of the memory cell array 10. Also, in FIG. 23, a conductive layer 32A is formed as a trace of the conductive layer 32 on the wall surfaces formed by the semiconductor layers 301 and 302 and the insulator layers 47 and 62 by the above-described process. Note that in this process, a portion on one side of the insulator layer 45 can also be removed, similar to the process of removing the conductive layer 31 and the semiconductor layer 301 in the portion corresponding to the region R1 described above.

[0150] Then, as in the embodiment, the insulating layer 44 is formed.

[0151] 24, similarly to the embodiment, a groove SH1 and a plurality of grooves SH2 are formed at once. The etching for forming the groove SH1 and the plurality of grooves SH2 is performed until the conductive layer 32B is exposed in the regions corresponding to the plurality of grooves SH2.

[0152] Also, similar to the embodiment, a conductive layer 39 and insulating layers 48a, 48b, and 48c are formed.

[0153] Through the manufacturing process described above, the semiconductor memory device 1 according to the first modification is formed.

[0154] The first modified example also provides the same effects as the embodiment.

[0155] Furthermore, according to the first modification, a conductor layer 32B is provided that is connected to the plurality of conductor layers 207. As a result, the plurality of connection portions V2 only need to be in contact with the conductor layer 32B, and do not need to be provided corresponding to the plurality of conductor layers 207. In other words, the positions of the plurality of connection portions V2 do not need to be precisely aligned with the positions of the plurality of conductor layers 207. This allows for a reduction in the manufacturing cost of the semiconductor memory device 1.

[0156] 2.2 Second variant In the above-described embodiment, as shown in Fig. 10, the case where the multiple connection portions V2 are arranged in a grid pattern is shown, but this is not limited to this. Below, the configuration of the semiconductor memory device 1 according to the second modification will be described, focusing on differences from the configuration of the semiconductor memory device according to the embodiment. Note that the method for manufacturing the semiconductor memory device 1 according to the second modification is the same as the method for manufacturing the semiconductor memory device according to the embodiment.

[0157] The configuration of the semiconductor memory device 1 according to the second modification will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view showing an example of a connection portion between a wiring layer and a contact in the semiconductor memory device according to the second modification. Fig. 25 corresponds to the cross-sectional view shown in Fig. 10 of the embodiment.

[0158] 25, each of the multiple connection portions V2 is provided to extend in the X direction in the XY cross section. That is, the multiple connection portions V2 are provided so that multiple line-shaped structures are aligned in the Y direction. Each of the multiple connection portions V2 can be connected to multiple conductive layers 207 aligned in the X direction in the XY cross section.

[0159] The second modified example also achieves the same effects as the embodiment.

[0160] 2.3 Third variant In the above-described embodiment, first modification, and second modification, the insulator layer 44 has a step near the boundary between region R1 and a region adjacent to region R1, but this is not limited to this. The insulator layer 44 does not have to have a step near the boundary. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the third modification will be described, focusing on differences from the configuration and manufacturing method of the semiconductor memory device according to the embodiment.

[0161] The configuration of the semiconductor memory device 1 according to the third modification will be described with reference to Fig. 26. Fig. 26 is a cross-sectional view showing an example of the cross-sectional structure of the circuit region of the semiconductor memory device according to the third modification.

[0162] 26, the first surface of the insulator layer 44 does not have a step near the boundary between the region R1 and the portion adjacent to the region R1. Furthermore, although not shown in FIG. 26, the first surface of the insulator layer 44 also does not have a step near the boundary between the region where the conductor layer 32 is provided and the region adjacent to that region.

[0163] The manufacturing method of the semiconductor memory device 1 according to the third variant is the same as the manufacturing method of the semiconductor memory device according to the embodiment, except that the first surface of the insulator layer 44 is flattened when removing the portion of the insulator layer 44 embedded therein by CMP after the process described using Figure 17 of the embodiment.

[0164] The third modified example also achieves the same effects as the embodiment.

[0165] 3. Other Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0166] 1...semiconductor memory device, 2...memory controller, 3...memory system, 10...memory cell array, 11...command register, 12...address register, 13...sequencer, 14...driver module, 15...row decoder module, 16...sense amplifier module, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, ST1, ST2...select transistor, BL...bit line, WL...word line, SGS, SGD...select gate line, SHE...component.

Claims

1. a first chip including a substrate having a first region and a second region; a second chip that contacts the first chip in a first direction intersecting the surface of the substrate and is electrically connected to the first chip via a first connection pad provided in a boundary region with the first chip; Equipped with The second chip is a memory cell array provided in the first region, the memory cell array including a source line, a plurality of word lines provided below the source line and spaced apart from one another in the first direction, and a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the upper end of which is connected to the source line; a first contact provided in the second region, extending in the first direction, and electrically connected to the first connection pad; a first wiring including a first connection portion electrically connected to an upper end of the first contact, and a first extension portion that is continuous with the upper end of the first connection portion and extends in a second direction intersecting with the first direction at a position above an upper surface of the source line in the first direction; Including, the first connection portion has a shape in which a groove above the first contact in the first direction is filled up to a position of a lower surface of the first extension portion in the first direction, a lower surface of the first connection portion is located lower than an upper surface of the source line in the first direction; Semiconductor memory device.

2. The second chip is a pattern portion included in the same layer as the source line in the second region, the portion overlapping with the first contact being removed when viewed from above; a first insulator portion provided between the first connection portion and the pattern portion; further comprising a lower surface of the first connection portion is located lower than an upper surface of the pattern portion in the first direction; 2. The semiconductor memory device according to claim 1.

3. The second chip is a second wiring provided in the first region, the second wiring having a second connection portion in contact with an upper surface of the source line, and a second extension portion electrically connected to the source line via the second connection portion and extending to a position above the source line; further comprising:

2. The semiconductor memory device according to claim 1.

4. a height of the first connection portion in the first direction being greater than a height of the second extension portion in the first direction; 4. The semiconductor memory device according to claim 3.

5. The second chip is a second contact provided in the second region, extending in the first direction, and electrically connected to the first connection pad; further comprising The first wiring is a second connection portion electrically connected to an upper end of the second contact and having an upper end continuous with the first extension portion; and the second connection portion has a shape in which a groove above the second contact in the first direction is filled up to a position of a lower surface of the first extension portion in the first direction, a lower surface of the second connection portion is located lower than an upper surface of the source line in the first direction; 2. The semiconductor memory device according to claim 1.

Images