Semiconductor device

Abstract

To reduce the ratio of an invalid region in a semiconductor device.SOLUTION: The semiconductor device 10 includes a semiconductor layer 12, a plurality of gate trenches 24 located in the semiconductor layer 12, a plurality of gate electrodes, and gate wires 20 electrically connected to the plurality of gate electrodes. The semiconductor layer 12 includes an outer peripheral region 14 and an inner region 16. The outer peripheral surface 12C includes a first side surface 12C1 and a second side surface 12C2 extending in a first direction in a plan view, and a third side surface 12C3 and a fourth side surface 12C4 extending in a second direction intersecting the first direction in a plan view. Gate wire 20 includes one or a plurality of gate fingers 20Y extending in the first direction. Each of the gate fingers 20Y overlaps at least the inner region 16 in a plan view, but does not overlap any of a first outer peripheral portion 12C1 located between the first side surface P1 and the inner region 16 and a second outer peripheral portion 12C2 located between the second side surface P2 and the inner region 16.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a metal insulator semiconductor field effect transistor (MISFET) having a trench gate structure. In the semiconductor device of Patent Document 1, a gate electrode embedded in each of a plurality of gate trenches is electrically connected to a gate terminal electrode including gate fingers extending in strip-like shapes in an outer region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-202313

[0004] [overview] In a semiconductor device including a MISFET having a trench gate structure, it is desired to reduce the proportion of an ineffective region that cannot be driven as a transistor.

[0005] A semiconductor device according to one embodiment of the present disclosure includes: a semiconductor layer having a rectangular outer peripheral surface in a plan view, the semiconductor layer including an outer peripheral region including the outer peripheral surface and an inner region having a rectangular shape in a plan view surrounded by the outer peripheral region; a plurality of gate trenches located in the semiconductor layer; an insulating layer located on the semiconductor layer; a plurality of gate electrodes, each located in a corresponding one of the gate trenches; a gate wiring located on the insulating layer and electrically connected to the gate electrodes; a source wiring located on the insulating layer and spaced from the gate wiring; and a plurality of mesa contact plugs, each of which is located in the inner region but not in the outer peripheral region, between two of the gate trenches in a plan view, penetrating the insulating layer to connect the source wiring to the semiconductor layer. The outer peripheral surface includes first and second side surfaces extending in a first direction in a plan view, and third and fourth side surfaces extending in a second direction intersecting the first direction in a plan view. The outer periphery region includes a first outer periphery portion located between the first side surface and the inner region, a second outer periphery portion located between the second side surface and the inner region, a third outer periphery portion located between the third side surface and the inner region, and a fourth outer periphery portion located between the fourth side surface and the inner region. The gate wiring includes one or more gate finger portions extending in the first direction, and each of the one or more gate finger portions extending in the first direction overlaps at least the inner region in a plan view but does not overlap either the first outer periphery portion or the second outer periphery portion.

[0006] Other features and aspects will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment of the present disclosure. [Figure 2]FIG. 2 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic plan view of a semiconductor device according to a reference example. [Figure 6] FIG. 6 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the semiconductor device taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic plan view of an exemplary semiconductor device according to the second embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a schematic plan view of an exemplary semiconductor device according to a third embodiment of the present disclosure. [Figure 11] FIG. 11 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a schematic plan view of an exemplary semiconductor device according to the fourth embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of an exemplary semiconductor device according to a fifth embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view of an exemplary semiconductor device according to a sixth embodiment of the present disclosure. [Figure 17]FIG. 17 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view of an exemplary semiconductor device according to the seventh embodiment of the present disclosure. [Figure 19] FIG. 19 is a schematic plan view showing the arrangement of components located in the semiconductor layer of the semiconductor device shown in FIG.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0009] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Example embodiments may have different forms and are not limited to the described examples.

[0010] First Embodiment An exemplary semiconductor device 10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 4. FIG. 1 is a schematic plan view of the semiconductor device 10. FIG. 2 is a schematic plan view showing the arrangement of components located in a semiconductor layer 12 of the semiconductor device 10 shown in FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device 10 taken along line F3-F3 in FIG. 2. FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG. 2. As will be understood from the following description, the semiconductor device 10 may be configured as a MISFET having a trench gate structure.

[0011] (Overall structure of semiconductor device) As shown in FIGS. 1 to 4, the semiconductor device 10 includes a semiconductor layer 12. The semiconductor layer 12 may have a rectangular parallelepiped shape. The semiconductor layer 12 may be formed of, for example, silicon (Si). The semiconductor layer 12 has a first surface 12A and a second surface 12B opposite the first surface 12A (see FIGS. 3 and 4). The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 and other drawings intersects (e.g., is perpendicular to) the first surface 12A of the semiconductor layer 12. As used herein, the term "plan view" refers to a view drawn from a perspective looking down on an object from above along the Z-axis direction, unless explicitly stated otherwise.

[0012] 1 and 2, the semiconductor layer 12 has an outer peripheral surface 12C that is rectangular in plan view. The outer peripheral surface 12C may extend between the first surface 12A and the second surface 12B. The outer peripheral surface 12C includes a first side surface 12C1 and a second side surface 12C2 that extend in a first direction (the Y-axis direction in the illustrated example) in plan view, and a third side surface 12C3 and a fourth side surface 12C4 that extend in a second direction (the X-axis direction in the illustrated example) that intersects with the first direction in plan view.

[0013] The semiconductor layer 12 includes a peripheral region 14 including an outer peripheral surface 12C, and an inner region 16 that is rectangular in plan view and surrounded by the peripheral region 14. As will be described in more detail below, the inner region 16 can be defined as a rectangular region in plan view that includes all of the multiple mesa contact plugs 44 (see FIG. 2). The boundary between the peripheral region 14 and the inner region 16 is rectangular in plan view.

[0014] The outer peripheral region 14 includes a first outer peripheral portion P1 located between the first side surface 12C1 and the inner region 16, a second outer peripheral portion P2 located between the second side surface 12C2 and the inner region 16, a third outer peripheral portion P3 located between the third side surface 12C3 and the inner region 16, and a fourth outer peripheral portion P4 located between the fourth side surface 12C4 and the inner region 16.

[0015] The first outer peripheral portion P1 may extend from the first side surface 12C1 to the boundary between the inner region 16 facing the first side surface 12C1 and the outer peripheral region 14. The second outer peripheral portion P2 may extend from the second side surface 12C2 to the boundary between the inner region 16 facing the second side surface 12C2 and the outer peripheral region 14. The third outer peripheral portion P3 may extend from the third side surface 12C3 to the boundary between the inner region 16 facing the third side surface 12C3 and the outer peripheral region 14. The fourth outer peripheral portion P4 may extend from the fourth side surface 12C4 to the boundary between the inner region 16 facing the fourth side surface 12C4 and the outer peripheral region 14.

[0016] The semiconductor device 10 includes an insulating layer 18 located on the semiconductor layer 12. In one example, the insulating layer 18 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and hafnium oxide (HfO).

[0017] (Gate and source wiring placement) The semiconductor device 10 includes a gate wiring 20 located on an insulating layer 18, and a source wiring 22 located on the insulating layer 18 and spaced apart from the gate wiring 20. The gate wiring 20 and the source wiring 22 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0018] In this embodiment, the gate wiring 20 may include one or more gate finger portions 20Y extending in a first direction (Y-axis direction) and one or more gate finger portions 20X extending in a second direction (X-axis direction). The gate wiring 20 may also include a gate pad portion 20P connected to at least one of the one or more gate finger portions 20Y extending in the first direction and the one or more gate finger portions 20X extending in the second direction. The gate pad portion 20P can be used to connect the gate wiring 20 to an external connection terminal (not shown). The gate finger portions 20Y and 20X extending in the first direction or the second direction may be covered with an insulating material (not shown), while the gate pad portion 20P may be exposed for connection to an external connection terminal.

[0019] The gate pad portion 20P has a smaller aspect ratio in plan view than the gate finger portions 20Y, 20X. In the present disclosure, the aspect ratio is defined as the value obtained by dividing the dimension of the long side by the dimension of the short side. In one example, the aspect ratio in plan view of each of the gate finger portions 20Y, 20X extending in the first direction or the second direction may be 3 or more. The aspect ratio in plan view of the gate pad portion 20P may be less than 3.

[0020] In the example shown in FIG. 1 , the gate wiring 20 includes first and second gate finger portions 20Y1 and 20Y2 extending in a first direction, third and fourth gate finger portions 20X1 and 20X2 extending in a second direction, and a gate pad portion 20P. The gate pad portion 20P is located relatively close to a corner of the semiconductor device 10 (a position where the first side surface 12C1 and the fourth side surface 12C4 of the semiconductor layer 12 intersect in a plan view). The gate pad portion 20P is connected to the third gate finger portion 20X1. The third gate finger portion 20X1 connects the gate pad portion 20P and the first gate finger portion 20Y1. The first gate finger portion 20Y1 extends from the third gate finger portion 20X1 toward the fourth side surface 12C4. The second gate finger portion 20Y2 connects between the third gate finger portion 20X1 and the fourth gate finger portion 20X2. Two ends of the fourth gate finger portion 20X2 are located relatively close to the first side surface 12C1 and the second side surface 12C2, respectively. The fourth gate finger portion 20X2 is connected to the second gate finger portion 20Y2 at its middle portion.

[0021] The source wiring 22 may include multiple portions 22A, 22B, 22C, and 22D separated by the gate wiring 20. In the example shown in FIG. 1 , the source wiring 22 includes a first portion 22A, a second portion 22B, a third portion 22C, and a fourth portion 22D separated by the gate wiring 20. The first portion 22A of the source wiring 22 is surrounded by the gate pad portion 20P, the third gate finger portion 20X1, the second gate finger portion 20Y2, the fourth gate finger portion 20X2, and the first side surface 12C1 in a plan view. The second portion 22B of the source wiring 22 is surrounded by the fourth gate finger portion 20X2, the first side surface 12C1, the third side surface 12C3, and the second side surface 12C2 in a plan view. The third portion 22C of the source wiring 22 is surrounded in plan view by the first gate finger portion 20Y1, the third gate finger portion 20X1, the fourth gate finger portion 20X2, the second side surface 12C2, and the fourth side surface 12C4. The fourth portion 22D of the source wiring 22 is surrounded in plan view by the gate pad portion 20P, the third gate finger portion 20X1, the first gate finger portion 20Y1, and the fourth side surface 12C4.

[0022] (Gate trench placement) 2 to 4, the semiconductor device 10 includes a plurality of gate trenches 24 located in the semiconductor layer 12. In FIG. 2, the insulating layer 18, the gate wiring 20, and the source wiring 22 are shown transparently to facilitate understanding of the arrangement of the gate trenches 24. Each gate trench 24 is arranged so as to overlap both the gate wiring 20 and the source wiring 22 in a plan view.

[0023] In this disclosure, the term "gate trench" can refer to at least a trench (or a portion of a trench) in which an electrode to which a gate voltage is applied (e.g., an electrode to which a gate voltage is applied to form a channel in the semiconductor layer 12, such as the gate electrode 36 described below) is disposed. Note that in addition to the electrode to which the gate voltage is applied, other electrodes to which a voltage different from the gate voltage is applied (e.g., the field plate electrode 38 described below) can also be disposed in the gate trench 24.

[0024] In this embodiment, the multiple gate trenches 24 may include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction. Each of the multiple first trenches 24Y may overlap, in a plan view, with at least one of the one or more gate finger portions 20X extending in the second direction. Furthermore, each of the multiple second trenches 24X may overlap, in a plan view, with at least one of the one or more gate finger portions 20Y extending in the first direction.

[0025] 2, each of the multiple first trenches 24Y overlaps with the third gate finger portion 20X1 or the fourth gate finger portion 20X2 in plan view, and each of the multiple second trenches 24X overlaps with the first gate finger portion 20Y1 or the second gate finger portion 20Y2 in plan view.

[0026] (Details of the semiconductor layer) 3 , the semiconductor layer 12 has a first surface 12A and a second surface 12B opposite the first surface 12A. The semiconductor layer 12 may include an n-type drain region 26, an n-type drift region 28 located on the drain region 26, a p-type body region 30 located on the drift region 28, and an n-type source region 32 located on the body region 30. The drain region 26 may include at least a portion of the second surface 12B of the semiconductor layer 12. The source region 32 may include at least a portion of the first surface 12A of the semiconductor layer 12.

[0027] The drain region 26 is a region containing n-type impurities. The n-type impurity concentration of the drain region 26 is 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 26 may have a thickness of 10 μm or more and 450 μm or less.

[0028] The drift region 28 is a region containing n-type impurities at a lower concentration than the drain region 26. The n-type impurity concentration of the drift region 28 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 28 may have a thickness of 1 μm or more and 25 μm or less.

[0029] The body region 30 is a region containing p-type impurities. The p-type impurity concentration of the body region 30 is 1×10 15 cm -3 More than 1×10 18 cm -3 The body region 30 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0030] The source region 32 is a region containing n-type impurities at a higher concentration than the drift region 28. The n-type impurity concentration of the source region 32 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 32 may have a thickness of 0.1 μm or more and 1 μm or less.

[0031] In one example, drift region 28 may be formed from a Si substrate, and drift region 28, body region 30, and source region 32 may be formed from a Si epitaxial layer.

[0032] In this disclosure, n-type may be referred to as the first conductivity type, and p-type may be referred to as the second conductivity type. The n-type impurities may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). The p-type impurities may include, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0033] The semiconductor device 10 may include a drain electrode 34 in contact with the second surface 12B of the semiconductor layer 12. The drain electrode 34 is electrically connected to the drain region 26. The drain electrode 34 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0034] (Explanation of trench gate structure) We will now describe the trench gate structure of semiconductor device 10. As previously mentioned, semiconductor device 10 includes gate trenches 24. While the following description generally focuses on one gate trench 24, it will be understood that such description is equally applicable to other gate trenches 24.

[0035] 3 and 4, the gate trench 24 has a sidewall 24A that extends from the first surface 12A into the semiconductor layer 12. The insulating layer 18 is located on the first surface 12A of the semiconductor layer 12 and covers the sidewall 24A of the gate trench 24.

[0036] The gate trench 24 may extend through the source region 32 and the body region 30 to the drift region 28. In one example, the gate trench 24 may have a depth of not less than 1 μm and not more than 15 μm.

[0037] The semiconductor device 10 includes a plurality of gate electrodes 36 and a plurality of field plate electrodes 38. Each of the plurality of gate electrodes 36 is located in a corresponding one of the plurality of gate trenches 24. Each of the plurality of field plate electrodes 38 is located in a corresponding one of the plurality of gate trenches 24. The plurality of field plate electrodes 38 are separated from the plurality of gate electrodes 36 by an insulating layer 18. Within the gate trench 24, the gate electrode 36 faces the field plate electrode 38 in a depth direction (the Z-axis direction in the illustrated example) that intersects with the first surface 12A of the semiconductor layer 12, with the insulating layer 18 interposed therebetween. The gate electrode 36 is located between the field plate electrode 38 and the first surface 12A in the depth direction.

[0038] Each gate electrode 36 may be disposed so as to face at least the body region 30 across the insulating layer 18 in the width direction of the gate trench 24. Here, the width direction of the gate trench 24 is a direction perpendicular to the longitudinal direction of the gate trench 24. For example, the longitudinal direction of the gate trench 24 shown in FIG. 3 is the Y-axis direction, and the width direction is the X-axis direction.

[0039] Each field plate electrode 38 may be disposed to face the drift region 28 across the insulating layer 18 in the width direction of the gate trench 24. The field plate electrodes 38 may have dimensions smaller than the gate electrode 36 in the width direction of the gate trench 24. As a result, the thickness of the insulating layer 18 between the field plate electrode 38 and the drift region 28 is greater than the thickness of the insulating layer 18 between the gate electrode 36 and the body region 30.

[0040] The gate electrode 36 and the field plate electrode 38 may each comprise conductive polysilicon. Since a gate electrode 36 and a field plate electrode 38 having different potentials are provided in the gate trench 24, each gate trench 24 is arranged so as to overlap both the gate wiring 20 and the source wiring 22 in plan view.

[0041] 2 and 4, the semiconductor device 10 may include a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 may be disposed in a region where the gate wiring 20 and the gate trench 24 overlap in a plan view. Each gate electrode 36 may be electrically connected to the gate wiring 20 via one or more gate electrode contact plugs 40. Each field plate electrode contact plug 42 may be disposed in a region where the source wiring 22 and the gate trench 24 overlap in a plan view. Each field plate electrode 38 may be electrically connected to the source wiring 22 via one or more field plate electrode contact plugs 42.

[0042] In this embodiment, the field plate electrode contact plugs 42 may overlap the peripheral region 14 in a plan view, which allows each field plate electrode 38 to be connected to the source wiring 22 at the end of the gate trench 24.

[0043] 4, each gate electrode 36 and each field plate electrode 38 may extend along the longitudinal direction of the gate trench 24 in which they are disposed. Each field plate electrode 38 may include a portion 38A that is raised toward the opening of the gate trench 24 to connect to the field plate electrode contact plug 42. Therefore, within the gate trench 24, the gate electrode 36 does not need to extend around the field plate electrode contact plug 42. The end of the gate electrode 36 may face the raised portion 38A of the field plate electrode 38 in the longitudinal direction of the gate trench 24, with the insulating layer 18 interposed therebetween.

[0044] 2 and 3, the semiconductor device 10 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 22 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 22 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 20 in a plan view.

[0045] Each of the multiple mesa contact plugs 44 is located between two of the multiple gate trenches 24 in a plan view. Note that a portion of the semiconductor layer 12 defined between two gate trenches 24 can be referred to as a mesa portion 46. Each mesa contact plug 44 is in contact with the mesa portion 46 of the semiconductor layer 12. The mesa contact plug 44 located between two gate trenches 24 extends parallel to the two gate trenches 24, but may have a smaller dimension than the two gate trenches 24 in the extending direction (the longitudinal direction of the gate trenches 24).

[0046] 3, the semiconductor layer 12 may include p-type contact regions 48 in contact with each mesa contact plug 44. The contact regions 48 are regions containing p-type impurities at a higher concentration than the body region 30. In one example, the p-type impurity concentration of the contact regions 48 is 1×10 19 cm -3 More than 1×10 21 cm -3 Each mesa contact plug 44 can electrically connect the source wiring 22 located on the insulating layer 18 to the semiconductor layer 12.

[0047] 2 , each of the multiple mesa contact plugs 44 is located in the inner region 16 and is not located in the outer periphery region 14. The inner region 16 can be defined as a rectangular region that includes all of the multiple mesa contact plugs 44 in a plan view. More specifically, the inner region 16 can be defined by a rectangle that is formed by connecting the edges of the mesa contact plugs 44 that are closest to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4, respectively, among the multiple mesa contact plugs 44.

[0048] (Gate finger placement relative to the outer periphery) Each of the one or more gate finger portions 20Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. In other words, the one or more gate finger portions 20Y extending in the first direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14.

[0049] Note that the fact that one or more gate finger portions 20Y extending in the first direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14 does not necessarily mean that the outer peripheral region 14 and the gate finger portions 20Y do not overlap. At least one of the one or more gate finger portions 20Y extending in the first direction may partially overlap with at least one of the third outer peripheral portion P3 and the fourth outer peripheral portion P4 in a plan view. The third outer peripheral portion P3 including the third side surface 12C3 and the fourth outer peripheral portion P4 including the fourth side surface 12C4 extend in the second direction. The second direction in which the third outer peripheral portion P3 and the fourth outer peripheral portion P4 extend is different from the first direction in which the gate finger portions 20Y extend. The fact that one or more gate finger portions 20Y extending in a first direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14 means that the one or more gate finger portions 20Y do not overlap with the outer peripheral portions extending in the same first direction, i.e., the first outer peripheral portion P1 and the second outer peripheral portion P2.

[0050] In the example of FIG. 2, the first gate finger portion 20Y1 extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. Furthermore, the first gate finger portion 20Y1 partially overlaps the fourth outer peripheral portion P4 in a plan view. The second gate finger portion 20Y2 extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. Furthermore, the second gate finger portion 20Y2 does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4 in a plan view.

[0051] Similarly, each of the one or more gate finger portions 20X extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. In other words, the one or more gate finger portions 20X extending in the second direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14.

[0052] Note that the fact that one or more gate finger portions 20X extending in the second direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14 does not necessarily mean that the outer peripheral region 14 and the gate finger portions 20X do not overlap. At least one of the one or more gate finger portions 20X extending in the second direction may partially overlap with at least one of the first outer peripheral portion P1 and the second outer peripheral portion P2 in a plan view. The first outer peripheral portion P1 including the first side surface 12C1 and the second outer peripheral portion P2 including the second side surface 12C2 extend in the first direction. The first direction in which the first outer peripheral portion P1 and the second outer peripheral portion P2 extend is different from the second direction in which the gate finger portions 20X extend. The fact that one or more gate finger portions 20X extending in the second direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14 means that the one or more gate finger portions 20X do not overlap with the outer peripheral portions extending in the same second direction, i.e., the third outer peripheral portion P3 and the fourth outer peripheral portion P4.

[0053] 2, the third gate finger portion 20X1 extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. Furthermore, the third gate finger portion 20X1 overlaps neither the first outer peripheral portion P1 nor the second outer peripheral portion P2 in a plan view. The fourth gate finger portion 20X2 extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. Furthermore, the fourth gate finger portion 20X2 partially overlaps the first outer peripheral portion P1 and the second outer peripheral portion P2 in a plan view.

[0054] Each of the one or more gate finger portions 20Y extending in the first direction overlaps at least the inner region 16 in a plan view but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2, so that at least one of the multiple gate trenches 24 can be located within the first outer peripheral portion P1 or the second outer peripheral portion P2. More specifically, at least one of the first trenches 24Y may be included within the first outer peripheral portion P1 or the second outer peripheral portion P2. In the example of FIG. 2, two first trenches 24Y are included within the first outer peripheral portion P1 and the second outer peripheral portion P2, respectively.

[0055] Similarly, each of the one or more gate finger portions 20X extending in the second direction overlaps at least the inner region 16 in a plan view but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4, so that at least one of the multiple gate trenches 24 can be located within the third outer peripheral portion P3 or the fourth outer peripheral portion P4. More specifically, at least one of the second trenches 24X may be included within the third outer peripheral portion P3 or the fourth outer peripheral portion P4. In the example of FIG. 2, one second trench 24X is included within the fourth outer peripheral portion P4.

[0056] (Function of Semiconductor Device) The following describes the operation of semiconductor device 10. Semiconductor device 10 includes semiconductor layer 12 having outer peripheral surface 12C that is rectangular in plan view. Semiconductor layer 12 includes outer peripheral region 14 that includes outer peripheral surface 12C, and inner region 16 that is rectangular in plan view and is surrounded by outer peripheral region 14.

[0057] The outer peripheral surface 12C includes a first side surface 12C1 and a second side surface 12C2 extending in a first direction in a plan view, and a third side surface 12C3 and a fourth side surface 12C4 extending in a second direction intersecting the first direction in a plan view. The outer peripheral region 14 includes a first outer peripheral portion P1 located between the first side surface 12C1 and the inner region 16, a second outer peripheral portion P2 located between the second side surface 12C2 and the inner region 16, a third outer peripheral portion P3 located between the third side surface 12C3 and the inner region 16, and a fourth outer peripheral portion P4 located between the fourth side surface 12C4 and the inner region 16.

[0058] The gate wiring 20 includes one or more gate finger portions 20Y extending in the first direction. Each of the one or more gate finger portions 20Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. Therefore, the one or more gate finger portions 20Y extending in the first direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14.

[0059] The gate wiring 20 also includes one or more gate finger portions 20X extending in the second direction. Each of the one or more gate finger portions 20X extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. Therefore, the one or more gate finger portions 20X extending in the second direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14.

[0060] As described above, in this embodiment, in the peripheral region 14, the gate finger portions 20Y, 20X do not extend along the peripheral surface 12C of the semiconductor layer 12. This makes it possible to reduce the proportion of ineffective regions in the semiconductor device 10 that cannot be driven as MISFETs.

[0061] Here, the ineffective region will be described with reference to a semiconductor device 100 of a reference example shown in Figures 5 to 7. Figure 5 is a schematic plan view of the semiconductor device 100. Figure 6 is a schematic plan view showing the arrangement of components located in the semiconductor layer 12 of the semiconductor device 100 shown in Figure 5. Figure 7 is a schematic cross-sectional view of the semiconductor device 100 taken along line F7-F7 in Figure 6. In Figures 5 to 7, components similar to those in the semiconductor device 10 are assigned the same reference numerals. Furthermore, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0062] 5, the semiconductor device 100 includes a gate wiring 102 located on the insulating layer 18, and a source wiring 104 located on the insulating layer 18 and spaced apart from the gate wiring 102. In the semiconductor device 100 of the reference example, the source wiring 104 is surrounded by the gate wiring 102 located in the peripheral region 14.

[0063] The gate wiring 102 includes two gate finger portions 102Y (first and second gate finger portions 102Y1 and 102Y2) extending in a first direction (Y-axis direction), two gate finger portions 102X (third and fourth gate finger portions 102X1 and 102X2) extending in a second direction (X-axis direction), and a gate pad portion 102P. The gate pad portion 102P is connected to the first gate finger portion 102Y1. The first gate finger portion 102Y1 is connected to the third gate finger portion 102X1. The third gate finger portion 102X1 is connected to the second gate finger portion 102Y2. The second gate finger portion 102Y2 is connected to the fourth gate finger portion 102X2. The fourth gate finger portion 102X2 is connected to the gate pad portion 102P.

[0064] The first gate finger portion 102Y1 overlaps with the first outer peripheral portion P1 in a planar view. The second gate finger portion 102Y2 overlaps with the second outer peripheral portion P2 in a planar view. The third gate finger portion 102X1 overlaps with the third outer peripheral portion P3 in a planar view. The fourth gate finger portion 102X2 overlaps with the fourth outer peripheral portion P4 in a planar view. In contrast to the gate wiring 20 of this embodiment, the gate wiring 102 of the reference example extends along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14.

[0065] 6, the semiconductor device 100 includes a plurality of gate trenches 24 located in the semiconductor layer 12. Note that in FIG. 6, the insulating layer 18, the gate wiring 102, and the source wiring 104 are shown transparently to facilitate understanding of the arrangement of the gate trenches 24. Each gate trench 24 is arranged so as to overlap both the gate wiring 102 and the source wiring 104 in a plan view.

[0066] The gate trenches 24 include first trenches 24Y extending in a first direction and second trenches 24X extending in a second direction. Each of the first trenches 24Y overlaps, in plan view, one of the third and fourth gate finger portions 102X1, 102X2 extending in the second direction. Each of the second trenches 24X overlaps, in plan view, one of the first and second gate finger portions 102Y1, 102Y2 extending in the first direction.

[0067] The semiconductor device 100 includes a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 is arranged in a region where the gate wiring 102 and the gate trench 24 overlap in a plan view. In the semiconductor device 100 of the reference example, the gate wiring 102 is located in the peripheral region 14, and therefore the plurality of gate electrode contact plugs 40 are also located in the peripheral region 14. Each field plate electrode contact plug 42 is arranged in a region where the source wiring 104 and the gate trench 24 overlap in a plan view.

[0068] Each gate electrode 36 is electrically connected to a gate wiring 102 via one or more gate electrode contact plugs 40. Each field plate electrode 38 is electrically connected to a source wiring 104 via one or more field plate electrode contact plugs 42.

[0069] 6 and 7, the semiconductor device 100 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 104 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 104 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 102 in a plan view.

[0070] Because the gate electrode 36 and the field plate electrode 38, which have different potentials, are provided in the gate trench 24, the gate trench 24 is arranged to overlap both the gate wiring 102 and the source wiring 104 in a planar view. Therefore, the first trench 24Y is arranged to intersect with the gate finger portions 102X extending in the second direction in a planar view, and the second trench 24X is arranged to intersect with the gate finger portions 102Y extending in the first direction in a planar view. On the other hand, arranging a trench extending in the first direction, such as the first trench 24Y, to overlap with the gate finger portions 102Y extending in the first direction in a planar view prevents such a trench from overlapping with the source wiring 104, making it difficult to establish an appropriate contact plug connection. Similarly, arranging a trench extending in the second direction, such as the second trench 24X, so that it overlaps in a planar view with the gate finger portion 102X extending in the second direction prevents such a trench from overlapping with the source wiring 104, making it difficult to achieve proper contact plug connection.

[0071] When the gate trenches 24 are arranged to enable appropriate contact plug connection, in the semiconductor device 100 of the reference example, multiple invalid regions 106A, 106B, and 106C (corresponding to the hatched regions in FIG. 6 ) where the gate electrode contact plug 40 cannot be provided are generated below the gate wiring 102. As shown in FIGS. 6 and 7 , the invalid region 106A is located below a portion of the first gate finger portion 102Y1 adjacent to the first trench 24Y intersecting with the third gate finger portion 102X1 in a plan view. The invalid region 106B is located below a portion of the second gate finger portion 102Y2 adjacent to the first trench 24Y intersecting with the third gate finger portion 102X1 in a plan view. The invalid region 106C is located below a portion of the fourth gate finger portion 102X2 adjacent to the second trench 24X intersecting with the second gate finger portion 102Y2 in a plan view. Such ineffective regions 106A, 106B, and 106C can occur because the first to fourth gate finger portions 102Y1, 102Y2, 102X1, and 102X2 extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14.

[0072] Since the first to fourth gate finger portions 102Y1, 102Y2, 102X1, and 102X2 of the gate wiring 102 need to be at the same potential, it is difficult to remove a portion of the gate wiring 102, which is formed in a rectangular loop shape in a plan view, in order to prevent the creation of invalid areas 106A, 106B, and 106C.

[0073] The ineffective regions 106A, 106B, and 106C located below the gate wiring 102 cannot accommodate the mesa contact plug 44 and the field plate electrode contact plug 42 to be connected to the source wiring 104. Therefore, it is difficult to place the gate trench 24 in the ineffective regions 106A, 106B, and 106C. Because the ineffective regions 106A, 106B, and 106C do not contribute to the operation of the semiconductor device 100 as a MISFET, the semiconductor device 100 of the reference example may have a relatively high on-resistance.

[0074] In this regard, in the semiconductor device 10 of this embodiment, each of the one or more gate finger portions 20Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. This configuration allows the gate electrode contact plug 40 to be efficiently arranged below the gate finger portion 20Y (ineffective regions as in the reference example are less likely to occur), and at least one of the multiple gate trenches 24 can be arranged in the first outer peripheral portion P1 or the second outer peripheral portion P2. Therefore, the proportion of ineffective regions in the semiconductor device 10 can be reduced, and the proportion of the cell region (also referred to as the active region) that contributes to operation as a MISFET can be increased.

[0075] Similarly, each of the one or more gate finger portions 20X extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 20X (making it less likely that an ineffective region like in the reference example will occur), and allows at least one of the multiple gate trenches 24 to be arranged in the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This reduces the proportion of ineffective regions in the semiconductor device 10, and increases the proportion of the cell region that contributes to operation as a MISFET.

[0076] The semiconductor device 10 according to this embodiment has the following advantages. (1-1) The gate wiring 20 includes one or more gate finger portions 20Y extending in a first direction, and each of the one or more gate finger portions 20Y extending in the first direction overlaps at least the inner region 16 in a planar view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2.

[0077] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 20Y, and allows at least one of the gate trenches 24 to be arranged in the first outer peripheral portion P1 or the second outer peripheral portion P2. This reduces the proportion of ineffective regions in the semiconductor device 10 and increases the proportion of cell regions that contribute to MISFET operation. As a result, the on-resistance of the semiconductor device 10 can be reduced.

[0078] (1-2) The gate wiring 20 includes one or more gate finger portions 20X extending in the second direction, and each of the one or more gate finger portions 20X extending in the second direction overlaps at least the inner region 16 in a planar view, but does not necessarily overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4.

[0079] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 20X, and at least one of the multiple gate trenches 24 to be arranged in the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This reduces the proportion of ineffective regions in the semiconductor device 10 and increases the proportion of cell regions that contribute to MISFET operation. As a result, the on-resistance of the semiconductor device 10 can be reduced.

[0080] (1-3) The multiple gate trenches 24 may include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction, and each of the multiple first trenches 24Y may overlap, in a planar view, with at least one of the one or more gate finger portions 20X extending in the second direction, and each of the multiple second trenches 24X may overlap, in a planar view, with at least one of the one or more gate finger portions 20Y extending in the first direction.

[0081] According to this configuration, the multiple gate trenches 24 include trenches extending in different directions, and therefore warping of the semiconductor layer 12 can be reduced compared to when the multiple gate trenches 24 include only trenches extending in the same direction.

[0082] (1-4) The semiconductor device 10 may further include a plurality of field plate electrodes 38 insulated from the plurality of gate electrodes 36, and each of the plurality of field plate electrodes 38 may be located within a corresponding one of the plurality of gate trenches 24.

[0083] According to this configuration, the depletion layer is expanded in the semiconductor layer 12 by the field plate electrode 38, thereby improving the breakdown voltage of the semiconductor device 10. (1-5) At least one of the one or more gate finger portions 20Y extending in the first direction may partially overlap with at least one of the third outer periphery portion P3 and the fourth outer periphery portion P4 in a plan view.

[0084] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 20Y extending in the first direction, thereby increasing the proportion of the cell region in the semiconductor device 10. As a result, the on-resistance of the semiconductor device 10 can be reduced.

[0085] (1-6) At least one of the one or more gate finger portions 20X extending in the second direction may partially overlap with at least one of the first outer periphery portion P1 and the second outer periphery portion P2 in plan view.

[0086] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 20X extending in the second direction, thereby increasing the proportion of the cell region in the semiconductor device 10. As a result, the on-resistance of the semiconductor device 10 can be reduced.

[0087] (1-7) The semiconductor device 10 may further include a plurality of gate electrode contact plugs 40 that penetrate the insulating layer 18 and connect the gate wiring 20 to the plurality of gate electrodes 36 . According to this configuration, the gate wiring 20 and the plurality of gate electrodes 36 can be set to the same potential.

[0088] (1-8) The semiconductor device 10 may further include a plurality of field plate electrode contact plugs 42 that penetrate the insulating layer 18 and connect the source wiring 22 to the plurality of field plate electrodes 38 .

[0089] According to this configuration, the source wiring 22 and the plurality of field plate electrodes 38 can be set to the same potential. (1-9) At least one of the plurality of gate trenches 24 may be located within the first outer periphery portion P1 or the second outer periphery portion P2.

[0090] According to this configuration, the gate trench 24 can be disposed also in the first outer peripheral portion P1 or the second outer peripheral portion P2, thereby increasing the proportion of the cell region in the semiconductor device 10. As a result, the on-resistance of the semiconductor device 10 can be reduced.

[0091] (1-10) At least one of the plurality of gate trenches 24 may be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. According to this configuration, the gate trench 24 can be disposed also in the third outer peripheral portion P3 or the fourth outer peripheral portion P4, thereby increasing the proportion of the cell region in the semiconductor device 10. As a result, the on-resistance of the semiconductor device 10 can be reduced.

[0092] (1-11) Each of the multiple gate trenches 24 may be arranged so as to overlap both the gate wiring 20 and the source wiring 22 in plan view. This configuration allows for appropriate contact plug connections to provide gate electrodes 36 and field plate electrodes 38 at different potentials within each gate trench 24 .

[0093] Second Embodiment Next, an exemplary semiconductor device 200 according to a second embodiment will be described with reference to Figures 8 and 9. Figure 8 is a schematic plan view of the semiconductor device 200. Figure 9 is a schematic plan view showing the arrangement of components located in the semiconductor layer 12 of the semiconductor device 200 shown in Figure 8. In Figures 8 and 9, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Furthermore, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0094] The semiconductor device 200 includes a gate wiring 202 located on the insulating layer 18, and a source wiring 204 located on the insulating layer 18 and spaced apart from the gate wiring 202. The gate wiring 202 and the source wiring 204 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0095] In this embodiment, the gate wiring 202 may include one or more gate finger portions 202Y extending in a first direction (Y-axis direction) and one or more gate finger portions 202X extending in a second direction (X-axis direction). The gate wiring 202 may also include a gate pad portion 202P connected to at least one of the one or more gate finger portions 202Y extending in the first direction and the one or more gate finger portions 202X extending in the second direction. The gate pad portion 202P can be used to connect the gate wiring 202 to an external connection terminal (not shown). The gate finger portions 202Y and 202X extending in the first direction or the second direction may be covered with an insulating material (not shown), while the gate pad portion 202P may be exposed for connection to an external connection terminal.

[0096] The gate pad portion 202P has a smaller aspect ratio in plan view than the gate finger portions 202Y, 202X. In one example, the aspect ratio in plan view of each of the gate finger portions 202Y, 202X extending in the first direction or the second direction may be 3 or more. Furthermore, the aspect ratio in plan view of the gate pad portion 202P may be less than 3.

[0097] In the example shown in FIG. 8, the gate wiring 202 includes one gate finger portion 202Y extending in the first direction and one gate finger portion 202X extending in the second direction. Furthermore, the gate pad portion 202P is located relatively close to the center of the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. The gate pad portion 202P is connected to the gate finger portion 202Y extending in the first direction. The gate finger portion 202Y extending in the first direction connects the gate pad portion 202P and the gate finger portion 202X extending in the second direction. Two ends of the gate finger portion 202X extending in the second direction are located relatively close to the first side surface 12C1 and the second side surface 12C2, respectively. The gate finger portion 202X extending in the second direction is connected at its middle portion to the gate finger portion 202Y extending in the first direction.

[0098] The source wiring 204 may include multiple portions 204A, 204B, and 204C separated by the gate wiring 202. In the example shown in FIG. 8 , the source wiring 204 includes a first portion 204A, a second portion 204B, and a third portion 204C separated by the gate wiring 202. The first portion 204A of the source wiring 204 is surrounded, in a plan view, by the gate pad portion 202P, the gate finger portions 202Y extending in the first direction, the gate finger portions 202X extending in the second direction, the first side surface 12C1, and the fourth side surface 12C4. The second portion 204B of the source wiring 204 is surrounded, in a plan view, by the gate finger portions 202X extending in the second direction, the first side surface 12C1, the third side surface 12C3, and the second side surface 12C2. In a plan view, the third portion 204C of the source wiring 204 is surrounded by a gate pad portion 202P, a gate finger portion 202Y extending in the first direction, a gate finger portion 202X extending in the second direction, a second side surface 12C2, and a fourth side surface 12C4.

[0099] 9, the semiconductor device 200 includes a plurality of gate trenches 24 located in the semiconductor layer 12. Note that in FIG. 9, the insulating layer 18, the gate wiring 202, and the source wiring 204 are shown transparently to facilitate understanding of the arrangement of the gate trenches 24. Each gate trench 24 is arranged so as to overlap both the gate wiring 202 and the source wiring 204 in a plan view.

[0100] In this embodiment, the multiple gate trenches 24 may include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction. Each of the multiple first trenches 24Y may overlap, in a plan view, at least one of one or more gate finger portions 202X and gate pad portions 202P extending in the second direction. Furthermore, each of the multiple second trenches 24X may overlap, in a plan view, at least one of one or more gate finger portions 202Y and gate pad portions 202P extending in the first direction.

[0101] 9, each of the multiple first trenches 24Y overlaps with a gate finger portion 202X extending in the second direction in plan view. Each of the multiple second trenches 24X overlaps with a gate finger portion 202Y or a gate pad portion 202P extending in the first direction in plan view.

[0102] The trench gate structure of the semiconductor device 200 may be similar to that of the semiconductor device 10. Therefore, in the semiconductor device 200, the gate electrode 36 and the field plate electrode 38 are disposed in the gate trench 24, similar to FIGS.

[0103] The semiconductor device 200 may include a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 may be disposed in a region where the gate wiring 202 and the gate trench 24 overlap in a plan view. Each gate electrode 36 may be electrically connected to the gate wiring 202 via one or more gate electrode contact plugs 40. Each field plate electrode contact plug 42 may be disposed in a region where the source wiring 204 and the gate trench 24 overlap in a plan view. Each field plate electrode 38 may be electrically connected to the source wiring 204 via one or more field plate electrode contact plugs 42.

[0104] The semiconductor device 200 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 204 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 204 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 202 in a plan view.

[0105] 9 , each of the multiple mesa contact plugs 44 is located in the inner region 16 and is not located in the outer periphery region 14. The inner region 16 can be defined as a rectangular region that includes all of the multiple mesa contact plugs 44 in a plan view. More specifically, the inner region 16 can be defined by a rectangle that is formed by connecting the edges of the mesa contact plugs 44 that are closest to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4, respectively, among the multiple mesa contact plugs 44.

[0106] (Gate finger placement relative to the outer periphery) In this embodiment, the gate finger portion 202Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. In other words, the gate finger portion 202Y extending in the first direction does not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14.

[0107] Similarly, the gate finger portions 202X extending in the second direction overlap at least the inner region 16 in a plan view, but do not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. That is, the gate finger portions 202X extending in the second direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, the gate finger portions 202X extending in the second direction partially overlap the first outer peripheral portion P1 and the second outer peripheral portion P2 in a plan view.

[0108] The gate finger portion 202Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2, so that at least one of the multiple gate trenches 24 can be located within the first outer peripheral portion P1 or the second outer peripheral portion P2. More specifically, at least one of the first trenches 24Y may be included within the first outer peripheral portion P1 or the second outer peripheral portion P2. In the example of FIG. 9 , two first trenches 24Y are included within the first outer peripheral portion P1 and the second outer peripheral portion P2, respectively.

[0109] Similarly, the gate finger portion 202X extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer periphery portion P3 or the fourth outer periphery portion P4, so that at least one of the multiple gate trenches 24 can be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. More specifically, at least one of the second trenches 24X may be included within the third outer periphery portion P3 or the fourth outer periphery portion P4. In the example of FIG. 9, two second trenches 24X are included within the fourth outer periphery portion P4.

[0110] (Function of Semiconductor Device) In the semiconductor device 200 of this embodiment, each of the one or more gate finger portions 202Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. This configuration makes it possible to efficiently arrange the gate electrode contact plug 40 below the gate finger portion 202Y, and to arrange at least one of the multiple gate trenches 24 in the first outer peripheral portion P1 or the second outer peripheral portion P2. This reduces the proportion of ineffective regions in the semiconductor device 200 and increases the proportion of the cell region that contributes to operation as a MISFET.

[0111] Similarly, each of the one or more gate finger portions 202X extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. With this configuration, it is possible to efficiently arrange the gate electrode contact plugs 40 below the gate finger portions 202X, and to arrange at least one of the multiple gate trenches 24 in the third outer peripheral portion P3 or the fourth outer peripheral portion P4. Therefore, it is possible to reduce the proportion of ineffective regions in the semiconductor device 200 and increase the proportion of the cell region that contributes to operation as a MISFET.

[0112] The semiconductor device 200 according to this embodiment has the following advantages. (2-1) The gate wiring 202 includes one or more gate finger portions 202Y extending in a first direction, and each of the one or more gate finger portions 202Y extending in the first direction overlaps at least the inner region 16 in a planar view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2.

[0113] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 202Y, and at least one of the gate trenches 24 to be arranged in the first outer peripheral portion P1 or the second outer peripheral portion P2. This reduces the proportion of ineffective regions in the semiconductor device 200 and increases the proportion of cell regions that contribute to MISFET operation. As a result, the on-resistance of the semiconductor device 200 can be reduced.

[0114] (2-2) The gate wiring 202 includes one or more gate finger portions 202X extending in the second direction, and each of the one or more gate finger portions 202X extending in the second direction overlaps at least the inner region 16 in a planar view, but does not necessarily overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4.

[0115] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 202X, and at least one of the multiple gate trenches 24 to be arranged in the third outer periphery portion P3 or the fourth outer periphery portion P4. This reduces the proportion of ineffective regions in the semiconductor device 200 and increases the proportion of cell regions that contribute to MISFET operation. As a result, the on-resistance of the semiconductor device 200 can be reduced.

[0116] (2-3) The multiple gate trenches 24 include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction, and each of the multiple first trenches 24Y may overlap in a planar view with at least one of one or more gate finger portions 202X and gate pad portions 202P extending in the second direction, and each of the multiple second trenches 24X may overlap in a planar view with at least one of one or more gate finger portions 202Y and gate pad portions 202P extending in the first direction.

[0117] According to this configuration, the multiple gate trenches 24 include trenches extending in different directions, which reduces warpage of the semiconductor layer 12 compared to when the multiple gate trenches 24 include only trenches extending in the same direction. Furthermore, the gate trenches 24 can be arranged so as to overlap not only the gate finger portions 202X and 202Y but also the gate pad portion 202P in a plan view, which improves the degree of freedom in arranging the gate trenches 24.

[0118] (2-4) The semiconductor device 200 may further include a plurality of field plate electrodes 38 insulated from the plurality of gate electrodes 36, and each of the plurality of field plate electrodes 38 may be located within a corresponding one of the plurality of gate trenches 24.

[0119] According to this configuration, the depletion layer is expanded in the semiconductor layer 12 by the field plate electrode 38, and thus the breakdown voltage of the semiconductor device 200 can be improved. (2-5) At least one of the one or more gate finger portions 202X extending in the second direction may partially overlap with at least one of the first outer periphery portion P1 and the second outer periphery portion P2 in plan view.

[0120] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 202X extending in the second direction, thereby increasing the proportion of the cell region in the semiconductor device 200. As a result, the on-resistance of the semiconductor device 200 can be reduced.

[0121] (2-6) The semiconductor device 200 may further include a plurality of gate electrode contact plugs 40 that penetrate the insulating layer 18 and connect the gate wiring 202 to the plurality of gate electrodes 36 .

[0122] According to this configuration, the gate wiring 202 and the plurality of gate electrodes 36 can be set to the same potential. (2-7) The semiconductor device 200 may further include a plurality of field plate electrode contact plugs 42 that penetrate the insulating layer 18 and connect the source wiring 204 to the plurality of field plate electrodes 38 .

[0123] According to this configuration, the source wiring 204 and the plurality of field plate electrodes 38 can be set to the same potential. (2-8) At least one of the plurality of gate trenches 24 may be located within the first outer periphery portion P1 or the second outer periphery portion P2.

[0124] According to this configuration, the gate trench 24 can be disposed also in the first outer peripheral portion P1 or the second outer peripheral portion P2, thereby increasing the proportion of the cell region in the semiconductor device 200. As a result, the on-resistance of the semiconductor device 200 can be reduced.

[0125] (2-9) At least one of the plurality of gate trenches 24 may be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. According to this configuration, the gate trench 24 can be disposed also in the third outer peripheral portion P3 or the fourth outer peripheral portion P4, thereby increasing the proportion of the cell region in the semiconductor device 200. As a result, the on-resistance of the semiconductor device 200 can be reduced.

[0126] (2-10) Each of the multiple gate trenches 24 may be arranged so as to overlap both the gate wiring 202 and the source wiring 204 in plan view. This configuration allows for appropriate contact plug connections to provide gate electrodes 36 and field plate electrodes 38 at different potentials within each gate trench 24 .

[0127] <Third embodiment> Next, an exemplary semiconductor device 300 according to a third embodiment will be described with reference to Figures 10 and 11. Figure 10 is a schematic plan view of the semiconductor device 300. Figure 11 is a schematic plan view showing the arrangement of components located in the semiconductor layer 12 of the semiconductor device 300 shown in Figure 10. In Figures 10 and 11, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Furthermore, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0128] The semiconductor device 300 includes a gate wiring 302 located on the insulating layer 18, and a source wiring 304 located on the insulating layer 18 and spaced apart from the gate wiring 302. The gate wiring 302 and the source wiring 304 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0129] In this embodiment, the gate wiring 302 may include one or more gate finger portions 302Y extending in a first direction (Y-axis direction) and a gate pad portion 302P connected to at least one of the one or more gate finger portions 302Y extending in the first direction. The gate pad portion 302P can be used to connect the gate wiring 302 to an external connection terminal (not shown). The gate finger portions 302Y may be covered with an insulating material (not shown), while the gate pad portion 302P may be exposed for connection to an external connection terminal.

[0130] The gate pad portion 302P has a smaller aspect ratio in a plan view than the gate finger portion 302Y. For example, the aspect ratio in a plan view of each gate finger portion 302Y extending in the first direction may be equal to or greater than 3. Furthermore, the aspect ratio in a plan view of the gate pad portion 302P may be less than 3.

[0131] 10, the gate wiring 302 includes one gate finger portion 302Y extending in the first direction. In addition, the gate pad portion 302P is located relatively close to the center of the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. The gate pad portion 302P is connected to the gate finger portion 302Y extending in the first direction. The gate finger portion 302Y extends from the gate pad portion 302P to near the third side surface 12C3.

[0132] The source wiring 304 may include multiple portions 304A and 304B separated by the gate wiring 302. In the example shown in FIG. 10 , the source wiring 304 includes a first portion 304A and a second portion 304B separated by the gate wiring 302. The first portion 304A of the source wiring 304 is surrounded by the gate pad portion 302P, the gate finger portion 302Y extending in the first direction, the third side surface 12C3, the first side surface 12C1, and the fourth side surface 12C4 in a plan view. The second portion 304B of the source wiring 304 is surrounded by the gate pad portion 302P, the gate finger portion 302Y extending in the first direction, the third side surface 12C3, the second side surface 12C2, and the fourth side surface 12C4 in a plan view.

[0133] 11, the semiconductor device 300 includes a plurality of gate trenches 24 located in the semiconductor layer 12. Note that in Fig. 11, the insulating layer 18, the gate wiring 302, and the source wiring 304 are shown transparently to facilitate understanding of the arrangement of the gate trenches 24. Each gate trench 24 is arranged so as to overlap both the gate wiring 302 and the source wiring 304 in a plan view.

[0134] In this embodiment, the plurality of gate trenches 24 may include a plurality of second trenches 24X extending in the second direction. Each of the plurality of second trenches 24X may overlap, in a plan view, at least one of one or more gate finger portions 302Y and gate pad portions 302P extending in the first direction.

[0135] 11, each of the multiple second trenches 24X overlaps with a gate finger portion 302Y or a gate pad portion 302P extending in the first direction in a plan view. Some of the second trenches 24X intersect with the gate finger portion 302Y in a plan view. The two ends of each second trench 24X that intersect with the gate finger portion 302Y are located relatively close to the first side surface 12C1 and the second side surface 12C2, respectively.

[0136] The trench gate structure of the semiconductor device 300 may be similar to that of the semiconductor device 10. Therefore, in the semiconductor device 300, the gate electrode 36 and the field plate electrode 38 are disposed in the gate trench 24, similar to FIGS.

[0137] The semiconductor device 300 may include a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 may be disposed in a region where the gate wiring 302 and the gate trench 24 overlap in a plan view. Each gate electrode 36 may be electrically connected to the gate wiring 302 via one or more gate electrode contact plugs 40. Each field plate electrode contact plug 42 may be disposed in a region where the source wiring 304 and the gate trench 24 overlap in a plan view. Each field plate electrode 38 may be electrically connected to the source wiring 304 via one or more field plate electrode contact plugs 42.

[0138] The semiconductor device 300 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 304 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 304 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 302 in a plan view.

[0139] 11 , each of the multiple mesa contact plugs 44 is located in the inner region 16 and is not located in the outer periphery region 14. The inner region 16 can be defined as a rectangular region that includes all of the multiple mesa contact plugs 44 in a plan view. More specifically, the inner region 16 can be defined by a rectangle that is formed by connecting the edges of the mesa contact plugs 44 that are closest to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4, respectively, among the multiple mesa contact plugs 44.

[0140] (Gate finger placement relative to the outer periphery) In this embodiment, the gate finger portion 302Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. In other words, the gate finger portion 302Y extending in the first direction does not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, the gate finger portion 302Y extending in the first direction partially overlaps the third outer peripheral portion P3 in a plan view.

[0141] Furthermore, in this embodiment, no gate finger portion extending in the second direction overlapping the third outer periphery portion P3 or the fourth outer periphery portion P4 in plan view is provided, and therefore at least one of the multiple gate trenches 24 can be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. More specifically, at least one of the second trenches 24X may be included within the third outer periphery portion P3 or the fourth outer periphery portion P4. In the example of FIG. 11 , one second trench 24X is included within the third outer periphery portion P3, and two second trenches 24X are included within the fourth outer periphery portion P4.

[0142] (Function of Semiconductor Device) In the semiconductor device 300 of this embodiment, each of one or more gate finger portions 302Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. This configuration allows the gate electrode contact plug 40 to be efficiently disposed below the gate finger portion 302Y. Furthermore, because no gate finger portion extending in the second direction overlaps the third outer peripheral portion P3 or the fourth outer peripheral portion P4 in a plan view, at least one of the multiple gate trenches 24 can be located within the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This reduces the proportion of ineffective regions in the semiconductor device 300 and increases the proportion of the cell region that contributes to MISFET operation.

[0143] The semiconductor device 300 according to this embodiment has the following advantages. (3-1) The gate wiring 302 includes one or more gate finger portions 302Y extending in a first direction, and each of the one or more gate finger portions 302Y extending in the first direction overlaps at least the inner region 16 in a planar view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2.

[0144] This configuration allows the gate electrode contact plugs 40 to be efficiently disposed below the gate finger portions 302Y, thereby reducing the proportion of ineffective regions in the semiconductor device 300. As a result, the on-resistance of the semiconductor device 300 can be reduced.

[0145] (3-2) The semiconductor device 300 may further include a plurality of field plate electrodes 38 insulated from the plurality of gate electrodes 36, and each of the plurality of field plate electrodes 38 may be located within a corresponding one of the plurality of gate trenches 24.

[0146] According to this configuration, the depletion layer is expanded in the semiconductor layer 12 by the field plate electrode 38, and thus the breakdown voltage of the semiconductor device 300 can be improved. (3-3) At least one of the one or more gate finger portions 302Y extending in the first direction may partially overlap with at least one of the third outer periphery portion P3 and the fourth outer periphery portion P4 in plan view.

[0147] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 302Y extending in the first direction, thereby increasing the proportion of the cell region in the semiconductor device 300. As a result, the on-resistance of the semiconductor device 300 can be reduced.

[0148] (3-4) The semiconductor device 300 may further include a plurality of gate electrode contact plugs 40 that penetrate the insulating layer 18 and connect the gate wiring 302 to the plurality of gate electrodes 36 .

[0149] According to this configuration, the gate wiring 302 and the plurality of gate electrodes 36 can be set to the same potential. (3-5) The semiconductor device 300 may further include a plurality of field plate electrode contact plugs 42 that penetrate the insulating layer 18 and connect the source wiring 304 to the plurality of field plate electrodes 38 .

[0150] According to this configuration, the source wiring 304 and the plurality of field plate electrodes 38 can be set to the same potential. (3-6) At least one of the plurality of gate trenches 24 may be located within the third outer periphery portion P3 or the fourth outer periphery portion P4.

[0151] According to this configuration, the gate trench 24 can be disposed also in the third outer peripheral portion P3 or the fourth outer peripheral portion P4, thereby increasing the proportion of the cell region in the semiconductor device 300. As a result, the on-resistance of the semiconductor device 300 can be reduced.

[0152] (3-7) The multiple gate trenches 24 may include multiple second trenches 24X extending in the second direction, and each of the multiple second trenches 24X may overlap in a planar view with at least one of one or more gate finger portions 302Y and gate pad portions 302P extending in the first direction.

[0153] According to this configuration, the gate trench 24 can be arranged so as to overlap not only the gate finger portion 302Y but also the gate pad portion 302P in plan view, thereby improving the degree of freedom in arranging the gate trench 24.

[0154] (3-8) Each of the multiple gate trenches 24 may be arranged so as to overlap both the gate wiring 302 and the source wiring 304 in plan view. This configuration allows for appropriate contact plug connections to provide gate electrodes 36 and field plate electrodes 38 at different potentials within each gate trench 24 .

[0155] <Fourth embodiment> Next, an exemplary semiconductor device 400 according to a fourth embodiment will be described with reference to Figures 12 and 13. Figure 12 is a schematic plan view of the semiconductor device 400. Figure 13 is a schematic plan view showing the arrangement of components located in the semiconductor layer 12 of the semiconductor device 400 shown in Figure 12. In Figures 12 and 13, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Furthermore, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0156] The semiconductor device 400 includes a gate wiring 402 located on the insulating layer 18, and a source wiring 404 located on the insulating layer 18 and spaced apart from the gate wiring 402. The gate wiring 402 and the source wiring 404 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0157] In this embodiment, the gate wiring 402 may include one or more gate finger portions 402Y extending in a first direction (Y-axis direction) and a gate pad portion 402P connected to at least one of the one or more gate finger portions 402Y extending in the first direction. The gate pad portion 402P can be used to connect the gate wiring 402 to an external connection terminal (not shown). The gate finger portions 402Y may be covered with an insulating material (not shown), while the gate pad portion 402P may be exposed for connection to the external connection terminal.

[0158] The gate pad portion 402P has a smaller aspect ratio in plan view than the gate finger portion 402Y. In one example, the aspect ratio in plan view of each gate finger portion 402Y extending in the first direction may be equal to or greater than 3. Furthermore, the aspect ratio in plan view of the gate pad portion 402P may be less than 3.

[0159] 12, the gate wiring 402 includes one gate finger portion 402Y extending in the first direction. Furthermore, the gate pad portion 402P is located relatively close to the center of the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. The gate pad portion 402P is connected to the gate finger portion 402Y extending in the first direction. The gate finger portion 402Y extends from the gate pad portion 402P to near the third side surface 12C3.

[0160] The source wiring 404 may include multiple portions 404A and 404B separated by the gate wiring 402. In the example shown in FIG. 12 , the source wiring 404 includes a first portion 404A and a second portion 404B separated by the gate wiring 402. The first portion 404A of the source wiring 404 is surrounded by the gate pad portion 402P, the gate finger portion 402Y extending in the first direction, the third side surface 12C3, the first side surface 12C1, and the fourth side surface 12C4 in a plan view. The second portion 404B of the source wiring 404 is surrounded by the gate pad portion 402P, the gate finger portion 402Y extending in the first direction, the third side surface 12C3, the second side surface 12C2, and the fourth side surface 12C4 in a plan view.

[0161] 13, the semiconductor device 400 includes a plurality of gate trenches 24 located in the semiconductor layer 12. Note that in Fig. 13, the insulating layer 18, the gate wiring 402, and the source wiring 404 are shown transparently to facilitate understanding of the arrangement of the gate trenches 24. Each gate trench 24 is arranged so as to overlap both the gate wiring 402 and the source wiring 404 in a plan view.

[0162] In this embodiment, the plurality of gate trenches 24 may include a plurality of second trenches 24X extending in the second direction. Each of the plurality of second trenches 24X may overlap, in a plan view, at least one of one or more gate finger portions 402Y and gate pad portions 402P extending in the first direction.

[0163] 13, each of the multiple second trenches 24X overlaps with a gate finger portion 402Y or a gate pad portion 402P extending in the first direction in a plan view. The second trenches 24X overlap with the gate finger portion 402Y in a plan view, but do not intersect with the gate finger portion 402Y. Each second trench 24X overlapping with the gate finger portion 402Y has an end portion located below the gate finger portion 402Y. Each second trench 24X overlapping with the gate finger portion 402Y faces another second trench 24X in the second direction below the gate finger portion 402Y.

[0164] The second trench 24X in Fig. 13 has a smaller dimension in the second direction than the second trench 24X in Fig. 11. As a result, the dimensions in the second direction of the gate electrode 36 and the field plate electrode 38 disposed in the second trench 24X are also relatively small, and the resistance of the gate electrode 36 and the field plate electrode 38 can be reduced.

[0165] The trench gate structure of the semiconductor device 400 may be similar to that of the semiconductor device 10. Therefore, in the semiconductor device 400, the gate electrode 36 and the field plate electrode 38 are disposed in the gate trench 24, similar to FIGS.

[0166] The semiconductor device 400 may include a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 may be disposed in a region where the gate wiring 402 and the gate trench 24 overlap in a plan view. Each gate electrode 36 may be electrically connected to the gate wiring 402 via one or more gate electrode contact plugs 40. Each field plate electrode contact plug 42 may be disposed in a region where the source wiring 404 and the gate trench 24 overlap in a plan view. Each field plate electrode 38 may be electrically connected to the source wiring 404 via one or more field plate electrode contact plugs 42.

[0167] The semiconductor device 400 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 404 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 404 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 402 in a plan view.

[0168] 13 , each of the multiple mesa contact plugs 44 is located in the inner region 16 and is not located in the outer periphery region 14. The inner region 16 can be defined as a rectangular region that includes all of the multiple mesa contact plugs 44 in a plan view. More specifically, the inner region 16 can be defined by a rectangle that is formed by connecting the edges of the mesa contact plugs 44 that are closest to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4, respectively, among the multiple mesa contact plugs 44.

[0169] (Gate finger placement relative to the outer periphery) In this embodiment, the gate finger portion 402Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. In other words, the gate finger portion 402Y extending in the first direction does not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, the gate finger portion 402Y extending in the first direction partially overlaps the third outer peripheral portion P3 in a plan view.

[0170] Furthermore, in this embodiment, no gate finger portion extending in the second direction overlapping the third outer periphery portion P3 or the fourth outer periphery portion P4 in plan view is provided, and therefore at least one of the multiple gate trenches 24 can be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. More specifically, at least one of the second trenches 24X may be included within the third outer periphery portion P3 or the fourth outer periphery portion P4. In the example of FIG. 13, two second trenches 24X are included within the third outer periphery portion P3, and two second trenches 24X are included within the fourth outer periphery portion P4.

[0171] (Function of Semiconductor Device) In the semiconductor device 400 of this embodiment, each of one or more gate finger portions 402Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. This configuration allows the gate electrode contact plug 40 to be efficiently disposed below the gate finger portion 402Y. Furthermore, because no gate finger portion extending in the second direction overlaps the third outer peripheral portion P3 or the fourth outer peripheral portion P4 in a plan view, at least one of the multiple gate trenches 24 can be located within the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This reduces the proportion of ineffective regions in the semiconductor device 400 and increases the proportion of cell regions that contribute to MISFET operation.

[0172] The semiconductor device 400 according to this embodiment has the following advantages. (4-1) The gate wiring 402 includes one or more gate finger portions 402Y extending in a first direction, and each of the one or more gate finger portions 402Y extending in the first direction overlaps at least the inner region 16 in a planar view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2.

[0173] This configuration allows the gate electrode contact plug 40 to be efficiently disposed below the gate finger portion 402Y, thereby reducing the proportion of ineffective regions in the semiconductor device 400. As a result, the on-resistance of the semiconductor device 400 can be reduced.

[0174] (4-2) The semiconductor device 400 may further include a plurality of field plate electrodes 38 insulated from the plurality of gate electrodes 36, and each of the plurality of field plate electrodes 38 may be located within a corresponding one of the plurality of gate trenches 24.

[0175] According to this configuration, the depletion layer is expanded in the semiconductor layer 12 by the field plate electrode 38, and thus the breakdown voltage of the semiconductor device 400 can be improved. (4-3) At least one of the one or more gate finger portions 402Y extending in the first direction may partially overlap with at least one of the third outer periphery portion P3 and the fourth outer periphery portion P4 in a plan view.

[0176] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 402Y extending in the first direction, thereby increasing the proportion of the cell region in the semiconductor device 400. As a result, the on-resistance of the semiconductor device 400 can be reduced.

[0177] (4-4) The semiconductor device 400 may further include a plurality of gate electrode contact plugs 40 that penetrate the insulating layer 18 and connect the gate wiring 402 to the plurality of gate electrodes 36 .

[0178] According to this configuration, the gate wiring 402 and the plurality of gate electrodes 36 can be set to the same potential. (4-5) The semiconductor device 400 may further include a plurality of field plate electrode contact plugs 42 that penetrate the insulating layer 18 and connect the source wiring 404 to the plurality of field plate electrodes 38 .

[0179] According to this configuration, the source wiring 404 and the plurality of field plate electrodes 38 can be set to the same potential. (4-6) At least one of the plurality of gate trenches 24 may be located within the third outer periphery portion P3 or the fourth outer periphery portion P4.

[0180] According to this configuration, the gate trench 24 can be disposed also in the third outer peripheral portion P3 or the fourth outer peripheral portion P4, thereby increasing the proportion of the cell region in the semiconductor device 400. As a result, the on-resistance of the semiconductor device 400 can be reduced.

[0181] (4-7) The multiple gate trenches 24 may include multiple second trenches 24X extending in the second direction, and each of the multiple second trenches 24X may overlap in a planar view with at least one of one or more gate finger portions 402Y and gate pad portions 402P extending in the first direction.

[0182] According to this configuration, the gate trench 24 can be arranged so as to overlap not only the gate finger portion 402Y but also the gate pad portion 402P in plan view, thereby improving the degree of freedom in arranging the gate trench 24.

[0183] (4-8) Each of the multiple gate trenches 24 may be arranged so as to overlap both the gate wiring 402 and the source wiring 404 in plan view. This configuration allows for appropriate contact plug connections to provide gate electrodes 36 and field plate electrodes 38 at different potentials within each gate trench 24 .

[0184] Fifth Embodiment Next, an exemplary semiconductor device 500 according to a fifth embodiment will be described with reference to FIGS. 14 and 15. FIG. 14 is a schematic plan view of the semiconductor device 500. FIG. 15 is a schematic plan view showing the arrangement of components located in the semiconductor layer 12 of the semiconductor device 500 shown in FIG. 14. In FIGS. 14 and 15, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Further, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0185] The semiconductor device 500 includes a gate wiring 502 located on the insulating layer 18, and a source wiring 504 located on the insulating layer 18 and spaced apart from the gate wiring 502. The gate wiring 502 and the source wiring 504 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0186] In this embodiment, the gate wiring 502 may include one or more gate finger portions 502Y extending in a first direction (Y-axis direction) and a gate pad portion 502P connected to at least one of the one or more gate finger portions 502Y extending in the first direction. The gate pad portion 502P can be used to connect the gate wiring 502 to an external connection terminal (not shown). The gate finger portions 502Y may be covered with an insulating material (not shown), while the gate pad portion 502P may be exposed for connection to the external connection terminal.

[0187] The gate pad portion 502P has a smaller aspect ratio in plan view than the gate finger portion 502Y. For example, the aspect ratio in plan view of each gate finger portion 502Y extending in the first direction may be equal to or greater than 3. Furthermore, the aspect ratio in plan view of the gate pad portion 502P may be less than 3.

[0188] 14, the gate wiring 502 includes first to third gate finger portions 502Y1, 502Y2, and 502Y3 extending in the first direction. Furthermore, the gate pad portion 502P is located relatively close to the center of the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. The gate pad portion 502P is connected to the first to third gate finger portions 502Y1, 502Y2, and 502Y3. The first gate finger portion 502Y1 extends from the gate pad portion 502P to the vicinity of the third side surface 12C3. The second gate finger portion 502Y2 and the third gate finger portion 502Y3 are located adjacent to the gate pad portion 502P in the second direction and extend toward the fourth side surface 12C4. The gate pad portion 502P is located between the second gate finger portion 502Y2 and the third gate finger portion 502Y3.

[0189] The source wiring 504 may include multiple portions 504A and 504B separated by the gate wiring 502. In the example shown in FIG. 14 , the source wiring 504 includes a first portion 504A and a second portion 504B separated by the gate wiring 502. The first portion 504A of the source wiring 504 is surrounded by the second gate finger portion 502Y2, the gate pad portion 502P, the first gate finger portion 502Y1, the third side surface 12C3, the first side surface 12C1, and the fourth side surface 12C4 in a plan view. The second portion 504B of the source wiring 504 is surrounded by the third gate finger portion 502Y3, the gate pad portion 502P, the first gate finger portion 502Y1, the third side surface 12C3, the second side surface 12C2, and the fourth side surface 12C4 in a plan view.

[0190] 15, the semiconductor device 500 includes a plurality of gate trenches 24 located in the semiconductor layer 12. Note that in FIG. 15, the insulating layer 18, the gate wiring 502, and the source wiring 504 are shown transparently to facilitate understanding of the arrangement of the gate trenches 24. Each gate trench 24 is arranged so as to overlap both the gate wiring 502 and the source wiring 504 in a plan view.

[0191] In this embodiment, the plurality of gate trenches 24 may include a plurality of second trenches 24X extending in the second direction. Each of the plurality of second trenches 24X may overlap, in plan view, with at least one of the one or more gate finger portions 502Y extending in the first direction.

[0192] 15, each of the multiple second trenches 24X overlaps with any of the first to third gate finger portions 502Y1, 502Y2, and 502Y3 in a plan view. Some of the second trenches 24X intersect with the first gate finger portion 502Y1 in a plan view. The two ends of each second trench 24X that intersect with the first gate finger portion 502Y1 are located relatively close to the first side surface 12C1 and the second side surface 12C2, respectively.

[0193] The trench gate structure of the semiconductor device 500 may be similar to that of the semiconductor device 10. Therefore, in the semiconductor device 500, the gate electrode 36 and the field plate electrode 38 are also disposed in the gate trench 24, as in FIGS.

[0194] The semiconductor device 500 may include a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 may be disposed in a region where a gate wiring 502 and a gate trench 24 overlap in a plan view. Each gate electrode 36 may be electrically connected to the gate wiring 502 via one or more gate electrode contact plugs 40. Each field plate electrode contact plug 42 may be disposed in a region where a source wiring 504 and a gate trench 24 overlap in a plan view. Each field plate electrode 38 may be electrically connected to the source wiring 504 via one or more field plate electrode contact plugs 42.

[0195] The semiconductor device 500 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 504 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 504 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 502 in a plan view.

[0196] 15 , each of the multiple mesa contact plugs 44 is located in the inner region 16 and is not located in the outer periphery region 14. The inner region 16 can be defined as a rectangular region that includes all of the multiple mesa contact plugs 44 in a plan view. More specifically, the inner region 16 can be defined by a rectangle that is formed by connecting the edges of the mesa contact plugs 44 that are closest to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4, respectively, among the multiple mesa contact plugs 44.

[0197] (Gate finger placement relative to the outer periphery) In this embodiment, the one or more gate finger portions 502Y extending in the first direction overlap at least the inner region 16 in a plan view, but do not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. In other words, the one or more gate finger portions 502Y extending in the first direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, the one or more gate finger portions 502Y extending in the first direction partially overlap the third outer peripheral portion P3 in a plan view.

[0198] Furthermore, in this embodiment, no gate finger portion extending in the second direction overlapping the third outer periphery portion P3 or the fourth outer periphery portion P4 in plan view is provided, and therefore at least one of the multiple gate trenches 24 can be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. More specifically, at least one of the second trenches 24X may be included within the third outer periphery portion P3 or the fourth outer periphery portion P4. In the example of FIG. 15 , one second trench 24X is included within the third outer periphery portion P3, and two second trenches 24X are included within the fourth outer periphery portion P4.

[0199] (Function of Semiconductor Device) In the semiconductor device 500 of this embodiment, each of one or more gate finger portions 502Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. This configuration allows the gate electrode contact plug 40 to be efficiently disposed below the gate finger portion 502Y. Furthermore, because no gate finger portion extending in the second direction overlaps the third outer peripheral portion P3 or the fourth outer peripheral portion P4 in a plan view, at least one of the multiple gate trenches 24 can be located within the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This reduces the proportion of ineffective regions in the semiconductor device 500 and increases the proportion of cell regions that contribute to MISFET operation.

[0200] The semiconductor device 500 according to this embodiment has the following advantages. (5-1) The gate wiring 502 includes one or more gate finger portions 502Y extending in a first direction, and each of the one or more gate finger portions 502Y extending in the first direction overlaps at least the inner region 16 in a planar view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2.

[0201] This configuration allows the gate electrode contact plug 40 to be efficiently disposed below the gate finger portion 502Y, thereby reducing the proportion of ineffective regions in the semiconductor device 500. As a result, the on-resistance of the semiconductor device 500 can be reduced.

[0202] (5-2) The semiconductor device 500 may further include a plurality of field plate electrodes 38 insulated from the plurality of gate electrodes 36, and each of the plurality of field plate electrodes 38 may be located within a corresponding one of the plurality of gate trenches 24.

[0203] According to this configuration, the depletion layer is expanded in the semiconductor layer 12 by the field plate electrode 38, and thus the breakdown voltage of the semiconductor device 500 can be improved. (5-3) At least one of the one or more gate finger portions 502Y extending in the first direction may partially overlap with at least one of the third outer periphery portion P3 and the fourth outer periphery portion P4 in a plan view.

[0204] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 502Y extending in the first direction, thereby increasing the proportion of the cell region in the semiconductor device 500. As a result, the on-resistance of the semiconductor device 500 can be reduced.

[0205] (5-4) The semiconductor device 500 may further include a plurality of gate electrode contact plugs 40 that penetrate the insulating layer 18 and connect the gate wiring 502 to the plurality of gate electrodes 36 .

[0206] According to this configuration, the gate wiring 502 and the plurality of gate electrodes 36 can be set to the same potential. (5-5) The semiconductor device 500 may further include a plurality of field plate electrode contact plugs 42 that penetrate the insulating layer 18 and connect the source wiring 504 to the plurality of field plate electrodes 38 .

[0207] According to this configuration, the source wiring 504 and the plurality of field plate electrodes 38 can be set to the same potential. (5-6) At least one of the plurality of gate trenches 24 may be located within the third outer periphery portion P3 or the fourth outer periphery portion P4.

[0208] According to this configuration, the gate trench 24 can be disposed also in the third outer peripheral portion P3 or the fourth outer peripheral portion P4, thereby increasing the proportion of the cell region in the semiconductor device 500. As a result, the on-resistance of the semiconductor device 500 can be reduced.

[0209] (5-7) Each of the multiple gate trenches 24 may be arranged so as to overlap both the gate wiring 502 and the source wiring 504 in plan view. This configuration allows for appropriate contact plug connections to provide gate electrodes 36 and field plate electrodes 38 at different potentials within each gate trench 24 .

[0210] Sixth Embodiment Next, an exemplary semiconductor device 600 according to a sixth embodiment will be described with reference to FIGS. 16 and 17. FIG. 16 is a schematic plan view of the semiconductor device 600. FIG. 17 is a schematic plan view showing the arrangement of components located in the semiconductor layer 12 of the semiconductor device 600 shown in FIG. 16. In FIGS. 16 and 17, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Further, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0211] The semiconductor device 600 includes a gate wiring 602 located on the insulating layer 18, and a source wiring 604 located on the insulating layer 18 and spaced apart from the gate wiring 602. The gate wiring 602 and the source wiring 604 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0212] In this embodiment, the gate wiring 602 may include one or more gate finger portions 602Y extending in a first direction (Y-axis direction) and one or more gate finger portions 602X extending in a second direction (X-axis direction). The gate wiring 602 may also include a gate pad portion 602P connected to at least one of the one or more gate finger portions 602Y extending in the first direction and the one or more gate finger portions 602X extending in the second direction. The gate pad portion 602P can be used to connect the gate wiring 602 to an external connection terminal (not shown). The gate finger portions 602Y and 602X extending in the first direction or the second direction may be covered with an insulating material (not shown), while the gate pad portion 602P may be exposed for connection to an external connection terminal.

[0213] The gate pad portion 602P has a smaller aspect ratio in plan view than the gate finger portions 602Y, 602X. In one example, the aspect ratio in plan view of each of the gate finger portions 602Y, 602X extending in the first direction or the second direction may be 3 or greater. Also, the aspect ratio in plan view of the gate pad portion 602P may be less than 3.

[0214] 16, the gate wiring 602 includes first and second gate finger portions 602Y1 and 602Y2 extending in a first direction and third and fourth gate finger portions 602X1 and 602X2 extending in a second direction. Furthermore, the gate pad portion 602P is located relatively close to the center of the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. The gate pad portion 602P is connected to the first gate finger portion 602Y1. The first gate finger portion 602Y1 connects the gate pad portion 602P to the second to fourth gate finger portions 602Y2, 602X1, and 602X2. The first to fourth gate finger portions 602Y1, 602Y2, 602X1, and 602X2 are connected to each other near the center of the semiconductor device 600 in a plan view. The second gate finger portion 602Y2 extends from near the center of the semiconductor device 600 in a plan view toward the third side surface 12C3. The third gate finger portion 602X1 extends from near the center of the semiconductor device 600 in a plan view toward the first side surface 12C1. The fourth gate finger portion 602X2 extends from near the center of the semiconductor device 600 in a plan view toward the second side surface 12C2.

[0215] The source wiring 604 may include multiple portions 604A, 604B, 604C, and 604D separated by the gate wiring 602. In the example shown in FIG. 16 , the source wiring 604 includes a first portion 604A, a second portion 604B, a third portion 604C, and a fourth portion 604D separated by the gate wiring 602. The first portion 604A of the source wiring 604 is surrounded by the gate pad portion 602P, the first gate finger portion 602Y1, the third gate finger portion 602X1, the first side surface 12C1, and the fourth side surface 12C4 in a plan view. The second portion 604B of the source wiring 604 is surrounded by the second gate finger portion 602Y2, the third gate finger portion 602X1, the first side surface 12C1, and the third side surface 12C3 in a plan view. The third portion 604C of the source wiring 604 is surrounded, in plan view, by the second gate finger portion 602Y2, the fourth gate finger portion 602X2, the second side surface 12C2, and the third side surface 12C3. The fourth portion 604D of the source wiring 604 is surrounded, in plan view, by the gate pad portion 602P, the first gate finger portion 602Y1, the fourth gate finger portion 602X2, the second side surface 12C2, and the fourth side surface 12C4.

[0216] 17, the semiconductor device 600 includes a plurality of gate trenches 24 located in the semiconductor layer 12. In order to facilitate understanding of the arrangement of the gate trenches 24, the insulating layer 18, the gate wiring 602, and the source wiring 604 are shown transparently in FIG. 17. Each gate trench 24 is arranged so as to overlap both the gate wiring 602 and the source wiring 604 in a plan view.

[0217] In this embodiment, the multiple gate trenches 24 may include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction. Each of the multiple first trenches 24Y may overlap, in a plan view, at least one of one or more gate finger portions 602X and gate pad portions 602P extending in the second direction. Furthermore, each of the multiple second trenches 24X may overlap, in a plan view, at least one of one or more gate finger portions 602Y and gate pad portions 602P extending in the first direction.

[0218] 17, each of the multiple first trenches 24Y overlaps with the third gate finger portion 602X1 or the fourth gate finger portion 602X2 in plan view, and each of the multiple second trenches 24X overlaps with the second gate finger portion 602Y2 or the gate pad portion 602P in plan view.

[0219] The trench gate structure of the semiconductor device 600 may be similar to that of the semiconductor device 10. Therefore, in the semiconductor device 600, the gate electrode 36 and the field plate electrode 38 are also disposed in the gate trench 24, as in FIGS.

[0220] The semiconductor device 600 may include a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 may be disposed in a region where a gate wiring 602 and a gate trench 24 overlap in a plan view. Each gate electrode 36 may be electrically connected to the gate wiring 602 via one or more gate electrode contact plugs 40. Each field plate electrode contact plug 42 may be disposed in a region where a source wiring 604 and a gate trench 24 overlap in a plan view. Each field plate electrode 38 may be electrically connected to the source wiring 604 via one or more field plate electrode contact plugs 42.

[0221] The semiconductor device 600 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 604 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 604 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 602 in a plan view.

[0222] 17 , each of the multiple mesa contact plugs 44 is located in the inner region 16 and is not located in the outer periphery region 14. The inner region 16 can be defined as a rectangular region that includes all of the multiple mesa contact plugs 44 in a plan view. More specifically, the inner region 16 can be defined by a rectangle that is formed by connecting the edges of the mesa contact plugs 44 that are closest to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4, respectively, among the multiple mesa contact plugs 44.

[0223] (Gate finger placement relative to the outer periphery) In this embodiment, one or more gate finger portions 602Y extending in the first direction overlap at least the inner region 16 in a plan view, but do not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. That is, the one or more gate finger portions 602Y extending in the first direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, at least one of the one or more gate finger portions 602Y extending in the first direction may partially overlap at least one of the third outer peripheral portion P3 and the fourth outer peripheral portion P4 in a plan view. In the example of FIG. 17 , the second gate finger portion 602Y2 partially overlaps the fourth outer peripheral portion P4.

[0224] Similarly, one or more gate finger portions 602X extending in the second direction overlap at least the inner region 16 in a plan view, but do not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. That is, the one or more gate finger portions 602X extending in the second direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, at least one of the one or more gate finger portions 602X extending in the second direction may partially overlap at least one of the first outer peripheral portion P1 and the second outer peripheral portion P2 in a plan view. In the example of FIG. 17 , the third gate finger portion 602X1 partially overlaps the first outer peripheral portion P1, and the fourth gate finger portion 602X2 partially overlaps the second outer peripheral portion P2.

[0225] The one or more gate finger portions 602Y extending in the first direction overlap at least the inner region 16 in a plan view, but do not overlap either the first outer periphery portion P1 or the second outer periphery portion P2, so that at least one of the multiple gate trenches 24 can be located within the first outer periphery portion P1 or the second outer periphery portion P2. More specifically, at least one of the first trenches 24Y may be included within the first outer periphery portion P1 or the second outer periphery portion P2. In the example of FIG. 17 , two first trenches 24Y are included within the first outer periphery portion P1 and the second outer periphery portion P2, respectively.

[0226] Similarly, one or more gate finger portions 602X extending in the second direction overlap at least the inner region 16 in a plan view but do not overlap either the third outer periphery portion P3 or the fourth outer periphery portion P4, so that at least one of the multiple gate trenches 24 can be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. More specifically, at least one of the second trenches 24X may be included within the third outer periphery portion P3 or the fourth outer periphery portion P4. In the example of FIG. 17 , one second trench 24X is included within the third outer periphery portion P3, and two second trenches 24X are included within the fourth outer periphery portion P4.

[0227] (Function of Semiconductor Device) In the semiconductor device 600 of this embodiment, each of the one or more gate finger portions 602Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. This configuration allows the gate electrode contact plug 40 to be efficiently disposed below the gate finger portion 602Y, and at least one of the multiple gate trenches 24 to be disposed in the first outer peripheral portion P1 or the second outer peripheral portion P2. This reduces the proportion of ineffective regions in the semiconductor device 600 and increases the proportion of the cell region that contributes to operation as a MISFET.

[0228] Similarly, each of the one or more gate finger portions 602X extending in the second direction overlaps at least the inner region 16 in a plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. With this configuration, it is possible to efficiently arrange the gate electrode contact plugs 40 below the gate finger portions 602X, and to arrange at least one of the multiple gate trenches 24 in the third outer peripheral portion P3 or the fourth outer peripheral portion P4. Therefore, it is possible to reduce the proportion of ineffective regions in the semiconductor device 600 and increase the proportion of cell regions that contribute to operation as a MISFET.

[0229] The semiconductor device 600 according to this embodiment has the following advantages. (6-1) The gate wiring 602 includes one or more gate finger portions 602Y extending in a first direction, and each of the one or more gate finger portions 602Y extending in the first direction overlaps at least the inner region 16 in a planar view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2.

[0230] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 602Y, and allows at least one of the gate trenches 24 to be arranged in the first outer periphery portion P1 or the second outer periphery portion P2. This reduces the proportion of ineffective regions in the semiconductor device 600 and increases the proportion of cell regions that contribute to MISFET operation. As a result, the on-resistance of the semiconductor device 600 can be reduced.

[0231] (6-2) The gate wiring 602 includes one or more gate finger portions 602X extending in the second direction, and each of the one or more gate finger portions 602X extending in the second direction overlaps at least the inner region 16 in a planar view, but does not necessarily overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4.

[0232] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 602X, and at least one of the multiple gate trenches 24 to be arranged in the third outer periphery portion P3 or the fourth outer periphery portion P4. This reduces the proportion of ineffective regions in the semiconductor device 600 and increases the proportion of cell regions that contribute to MISFET operation. As a result, the on-resistance of the semiconductor device 600 can be reduced.

[0233] (6-3) The multiple gate trenches 24 may include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction, and each of the multiple first trenches 24Y may overlap in a planar view with at least one of one or more gate finger portions 602X and gate pad portions 602P extending in the second direction, and each of the multiple second trenches 24X may overlap in a planar view with at least one of one or more gate finger portions 602Y and gate pad portions 602P extending in the first direction.

[0234] According to this configuration, the multiple gate trenches 24 include trenches extending in different directions, which reduces warpage of the semiconductor layer 12 compared to when the multiple gate trenches 24 include only trenches extending in the same direction. Furthermore, the gate trenches 24 can be arranged so as to overlap not only the gate finger portions 602X and 602Y but also the gate pad portion 602P in plan view, which improves the degree of freedom in arranging the gate trenches 24.

[0235] (6-4) The semiconductor device 600 may further include a plurality of field plate electrodes 38 insulated from the plurality of gate electrodes 36, and each of the plurality of field plate electrodes 38 may be located within a corresponding one of the plurality of gate trenches 24.

[0236] According to this configuration, the depletion layer is expanded in the semiconductor layer 12 by the field plate electrode 38, and thus the breakdown voltage of the semiconductor device 600 can be improved. (6-5) At least one of the one or more gate finger portions 602X extending in the second direction may partially overlap with at least one of the first outer periphery portion P1 and the second outer periphery portion P2 in plan view.

[0237] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 602X extending in the second direction, thereby increasing the proportion of the cell region in the semiconductor device 600. As a result, the on-resistance of the semiconductor device 600 can be reduced.

[0238] (6-6) The semiconductor device 600 may further include a plurality of gate electrode contact plugs 40 that penetrate the insulating layer 18 and connect the gate wiring 602 to the plurality of gate electrodes 36 .

[0239] According to this configuration, the gate wiring 602 and the plurality of gate electrodes 36 can be set to the same potential. (6-7) The semiconductor device 600 may further include a plurality of field plate electrode contact plugs 42 that penetrate the insulating layer 18 and connect the source wiring 604 to the plurality of field plate electrodes 38 .

[0240] According to this configuration, the source wiring 604 and the plurality of field plate electrodes 38 can be set to the same potential. (6-8) At least one of the plurality of gate trenches 24 may be located within the first outer periphery portion P1 or the second outer periphery portion P2.

[0241] According to this configuration, the gate trench 24 can be disposed also in the first outer peripheral portion P1 or the second outer peripheral portion P2, thereby increasing the proportion of the cell region in the semiconductor device 600. As a result, the on-resistance of the semiconductor device 600 can be reduced.

[0242] (6-9) At least one of the plurality of gate trenches 24 may be located within the third outer periphery portion P3 or the fourth outer periphery portion P4. According to this configuration, the gate trench 24 can be disposed also in the third outer peripheral portion P3 or the fourth outer peripheral portion P4, thereby increasing the proportion of the cell region in the semiconductor device 600. As a result, the on-resistance of the semiconductor device 600 can be reduced.

[0243] (6-10) Each of the multiple gate trenches 24 may be arranged so as to overlap both the gate wiring 602 and the source wiring 604 in plan view. This configuration allows for appropriate contact plug connections to provide gate electrodes 36 and field plate electrodes 38 at different potentials within each gate trench 24 .

[0244] Seventh Embodiment Next, an exemplary semiconductor device 700 according to the seventh embodiment will be described with reference to Figures 18 and 19. Figure 18 is a schematic plan view of the semiconductor device 700. Figure 19 is a schematic plan view showing the arrangement of components located in the semiconductor layer 12 of the semiconductor device 700 shown in Figure 18. In Figures 18 and 19, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Furthermore, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0245] The semiconductor device 700 includes a gate wiring 702 located on the insulating layer 18, and a source wiring 704 located on the insulating layer 18 and spaced apart from the gate wiring 702. The gate wiring 702 and the source wiring 704 may include at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0246] In this embodiment, the gate wiring 702 may include one or more gate finger portions 702Y extending in a first direction (Y-axis direction) and one or more gate finger portions 702X extending in a second direction (X-axis direction). The gate wiring 702 may also include a gate pad portion 702P connected to at least one of the one or more gate finger portions 702Y extending in the first direction and the one or more gate finger portions 702X extending in the second direction. The gate pad portion 702P can be used to connect the gate wiring 702 to an external connection terminal (not shown). The gate finger portions 702Y and 702X extending in the first direction or the second direction may be covered with an insulating material (not shown), while the gate pad portion 702P may be exposed for connection to an external connection terminal.

[0247] The gate pad portion 702P has a smaller aspect ratio in plan view than the gate finger portions 702Y, 702X. In one example, the aspect ratio in plan view of each of the gate finger portions 702Y, 702X extending in the first direction or the second direction may be 3 or greater. Furthermore, the aspect ratio in plan view of the gate pad portion 702P may be less than 3.

[0248] 16, the gate wiring 702 includes first and second gate finger portions 702Y1 and 702Y2 extending in a first direction and third and fourth gate finger portions 702X1 and 702X2 extending in a second direction. Furthermore, the gate pad portion 702P is located relatively close to the center of the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. The gate pad portion 702P is connected to the first gate finger portion 702Y1. The first gate finger portion 702Y1 connects the gate pad portion 702P to the second to fourth gate finger portions 702Y2, 702X1, and 702X2. The first to fourth gate finger portions 702Y1, 702Y2, 702X1, and 702X2 are connected to each other near the center of the semiconductor device 700 in a plan view. The second gate finger portion 702Y2 extends from near the center of the semiconductor device 700 in a plan view toward the third side surface 12C3. The third gate finger portion 702X1 extends from near the center of the semiconductor device 700 in a plan view toward the first side surface 12C1. The fourth gate finger portion 702X2 extends from near the center of the semiconductor device 700 in a plan view toward the second side surface 12C2.

[0249] The source wiring 704 includes multiple portions 704A, 704B, 704C, and 704D separated by the gate wiring 702, and one or more connection portions 704E, 704F, and 704G connecting the portions. The one or more connection portions 704E, 704F, and 704G overlap the peripheral region 14 in a plan view. In the example shown in FIG. 18 , the source wiring 704 includes a first portion 704A, a second portion 704B, a third portion 704C, a fourth portion 704D, a connection portion 704E connecting the first portion 704A and the second portion 704B, a connection portion 704F connecting the second portion 704B and the third portion 704C, and a connection portion 704G connecting the third portion 704C and the fourth portion 704D. The first portion 704A of the source wiring 704 is surrounded by the gate pad portion 702P, the first gate finger portion 702Y1, the third gate finger portion 702X1, the first side surface 12C1, and the fourth side surface 12C4 in a plan view. The second portion 704B of the source wiring 704 is surrounded by the second gate finger portion 702Y2, the third gate finger portion 702X1, the first side surface 12C1, and the third side surface 12C3 in a plan view. The third portion 704C of the source wiring 704 is surrounded by the second gate finger portion 702Y2, the fourth gate finger portion 702X2, the second side surface 12C2, and the third side surface 12C3 in a plan view. The fourth portion 704D of the source wiring 704 is surrounded by the gate pad portion 702P, the first gate finger portion 702Y1, the fourth gate finger portion 702X2, the second side surface 12C2, and the fourth side surface 12C4 in plan view.

[0250] 19, the semiconductor device 700 includes a plurality of gate trenches 24 located in the semiconductor layer 12. In order to facilitate understanding of the arrangement of the gate trenches 24, the insulating layer 18, the gate wiring 702, and the source wiring 704 are shown transparently in FIG. 19. Each gate trench 24 is arranged so as to overlap both the gate wiring 702 and the source wiring 704 in a plan view.

[0251] In this embodiment, the multiple gate trenches 24 may include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction. Each of the multiple first trenches 24Y may overlap, in a plan view, at least one of one or more gate finger portions 702X and gate pad portions 702P extending in the second direction. Furthermore, each of the multiple second trenches 24X may overlap, in a plan view, at least one of one or more gate finger portions 702Y and gate pad portions 702P extending in the first direction.

[0252] 19, each of the multiple first trenches 24Y overlaps with the third gate finger portion 702X1 or the fourth gate finger portion 702X2 in plan view, and each of the multiple second trenches 24X overlaps with the second gate finger portion 702Y2 or the gate pad portion 702P in plan view.

[0253] The trench gate structure of the semiconductor device 700 may be similar to that of the semiconductor device 10. Therefore, in the semiconductor device 700, the gate electrode 36 and the field plate electrode 38 are disposed in the gate trench 24, similar to FIGS.

[0254] The semiconductor device 700 may include a plurality of gate electrode contact plugs 40 and a plurality of field plate electrode contact plugs 42. Each gate electrode contact plug 40 may be disposed in a region where the gate wiring 702 and the gate trench 24 overlap in a plan view. Each gate electrode 36 may be electrically connected to the gate wiring 702 via one or more gate electrode contact plugs 40. Each field plate electrode contact plug 42 may be disposed in a region where the source wiring 704 and the gate trench 24 overlap in a plan view. Each field plate electrode 38 may be electrically connected to the source wiring 704 via one or more field plate electrode contact plugs 42.

[0255] The semiconductor device 700 includes a plurality of mesa contact plugs 44 that penetrate the insulating layer 18 and connect the source wiring 704 and the semiconductor layer 12. Each of the plurality of mesa contact plugs 44 is arranged so as to overlap the source wiring 704 in a plan view. The mesa contact plugs 44 are not provided in a region that overlaps with the gate wiring 702 in a plan view.

[0256] 19 , each of the multiple mesa contact plugs 44 is located in the inner region 16 and is not located in the outer periphery region 14. The inner region 16 can be defined as a rectangular region that includes all of the multiple mesa contact plugs 44 in a plan view. More specifically, the inner region 16 can be defined by a rectangle that is formed by connecting the edges of the mesa contact plugs 44 that are closest to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4, respectively, among the multiple mesa contact plugs 44.

[0257] (Gate finger placement relative to the outer periphery) In this embodiment, one or more gate finger portions 702Y extending in the first direction overlap at least the inner region 16 in a plan view, but do not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. That is, the one or more gate finger portions 702Y extending in the first direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, at least one of the one or more gate finger portions 702Y extending in the first direction may partially overlap at least one of the third outer peripheral portion P3 and the fourth outer peripheral portion P4 in a plan view. In the example of FIG. 19 , the second gate finger portion 702Y2 partially overlaps the fourth outer peripheral portion P4.

[0258] Similarly, one or more gate finger portions 702X extending in the second direction overlap at least the inner region 16 in a plan view, but do not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. That is, the one or more gate finger portions 702X extending in the second direction do not extend along the outer peripheral surface 12C of the semiconductor layer 12 in the outer peripheral region 14. Furthermore, at least one of the one or more gate finger portions 702X extending in the second direction may partially overlap at least one of the first outer peripheral portion P1 and the second outer peripheral portion P2 in a plan view. In the example of FIG. 19 , the third gate finger portion 702X1 partially overlaps the first outer peripheral portion P1, and the fourth gate finger portion 702X2 partially overlaps the second outer peripheral portion P2.

[0259] 19, connection portion 704E and connection portion 704G of source wiring 704 are arranged to overlap with first outer periphery portion P1 and second outer periphery portion P2, respectively, in plan view. Connection portion 704F of source wiring 704 is arranged to overlap with third outer periphery portion P3 in plan view. Furthermore, one second trench 24X is included in the third outer periphery portion P3, and two second trenches 24X are included in the fourth outer periphery portion P4.

[0260] (Function of Semiconductor Device) In the semiconductor device 700 of this embodiment, each of the one or more gate finger portions 702Y extending in the first direction overlaps at least the inner region 16 in a plan view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2. This configuration allows the gate electrode contact plug 40 to be efficiently disposed below the gate finger portions 702Y. Therefore, the proportion of ineffective regions in the semiconductor device 700 can be reduced.

[0261] Similarly, each of the one or more gate finger portions 702X extending in the second direction overlaps at least the inner region 16 in plan view, but does not overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This configuration allows the gate electrode contact plugs 40 to be efficiently disposed below the gate finger portions 702X. Therefore, the proportion of ineffective regions in the semiconductor device 700 can be reduced.

[0262] The source wiring 704 also includes multiple portions 704A, 704B, 704C, and 704D separated by the gate wiring 702, and one or more connection portions 704E, 704F, and 704G connecting these portions. The one or more connection portions 704E, 704F, and 704G overlap the peripheral region 14 in a plan view. This configuration makes it possible to easily set the multiple portions 704A, 704B, 704C, and 704D of the source wiring 704 to the same potential.

[0263] The semiconductor device 700 according to this embodiment has the following advantages. (7-1) The gate wiring 702 includes one or more gate finger portions 702Y extending in a first direction, and each of the one or more gate finger portions 702Y extending in the first direction overlaps at least the inner region 16 in a planar view, but does not overlap either the first outer peripheral portion P1 or the second outer peripheral portion P2.

[0264] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 702Y, and allows the connection portions 704E and 704G of the source wiring 704 to be arranged in the first outer peripheral portion P1 or the second outer peripheral portion P2. This reduces the proportion of ineffective regions in the semiconductor device 700, and allows the multiple portions 704A, 704B, 704C, and 704D of the source wiring 704 to be easily set to the same potential.

[0265] (7-2) The gate wiring 702 includes one or more gate finger portions 702X extending in the second direction, and each of the one or more gate finger portions 702X extending in the second direction overlaps at least the inner region 16 in a planar view, but does not necessarily overlap either the third outer peripheral portion P3 or the fourth outer peripheral portion P4.

[0266] This configuration allows the gate electrode contact plugs 40 to be efficiently arranged below the gate finger portions 702X, and allows the connection portions 704F of the source wiring 704 to be arranged in the third outer peripheral portion P3 or the fourth outer peripheral portion P4. This reduces the proportion of ineffective regions in the semiconductor device 700, and allows the multiple portions 704A, 704B, 704C, and 704D of the source wiring 704 to be easily set to the same potential.

[0267] (7-3) The multiple gate trenches 24 may include multiple first trenches 24Y extending in a first direction and multiple second trenches 24X extending in a second direction, and each of the multiple first trenches 24Y may overlap in a planar view with at least one of one or more gate finger portions 702X and gate pad portions 702P extending in the second direction, and each of the multiple second trenches 24X may overlap in a planar view with at least one of one or more gate finger portions 702Y and gate pad portions 702P extending in the first direction.

[0268] According to this configuration, the multiple gate trenches 24 include trenches extending in different directions, which reduces warpage of the semiconductor layer 12 compared to when the multiple gate trenches 24 include only trenches extending in the same direction. Furthermore, the gate trenches 24 can be arranged so as to overlap not only the gate finger portions 702X and 702Y but also the gate pad portion 702P in plan view, which improves the degree of freedom in arranging the gate trenches 24.

[0269] (7-4) The semiconductor device 700 may further include a plurality of field plate electrodes 38 insulated from the plurality of gate electrodes 36, and each of the plurality of field plate electrodes 38 may be located within a corresponding one of the plurality of gate trenches 24.

[0270] According to this configuration, the depletion layer is expanded in the semiconductor layer 12 by the field plate electrode 38, and thus the breakdown voltage of the semiconductor device 700 can be improved. (7-5) At least one of the one or more gate finger portions 702X extending in the second direction may partially overlap with at least one of the first outer periphery portion P1 and the second outer periphery portion P2 in plan view.

[0271] This configuration makes it possible to increase the number of gate trenches 24 that can be arranged to intersect, in plan view, with one or more gate finger portions 702X extending in the second direction, thereby increasing the proportion of the cell region in the semiconductor device 700. As a result, the on-resistance of the semiconductor device 700 can be reduced.

[0272] (6-6) The semiconductor device 700 may further include a plurality of gate electrode contact plugs 40 that penetrate the insulating layer 18 and connect the gate wiring 702 to the plurality of gate electrodes 36 .

[0273] According to this configuration, the gate wiring 702 and the plurality of gate electrodes 36 can be set to the same potential. (7-7) The semiconductor device 700 may further include a plurality of field plate electrode contact plugs 42 that penetrate the insulating layer 18 and connect the source wiring 704 to the plurality of field plate electrodes 38 .

[0274] According to this configuration, the source wiring 704 and the plurality of field plate electrodes 38 can be set to the same potential. (7-8) At least one of the plurality of gate trenches 24 may be located within the third outer periphery portion P3 or the fourth outer periphery portion P4.

[0275] According to this configuration, the gate trench 24 can be disposed also in the third outer peripheral portion P3 or the fourth outer peripheral portion P4, thereby increasing the proportion of the cell region in the semiconductor device 700. As a result, the on-resistance of the semiconductor device 700 can be reduced.

[0276] (7-9) Each of the multiple gate trenches 24 may be arranged so as to overlap both the gate wiring 702 and the source wiring 704 in plan view. This configuration allows for appropriate contact plug connections to provide gate electrodes 36 and field plate electrodes 38 at different potentials within each gate trench 24 .

[0277] <Other change examples> The above embodiment can be modified as follows. Some of the multiple first trenches 24Y extending in the first direction may be connected to each other, for example, in the outer periphery region 14. Similarly, some of the multiple second trenches 24X extending in the second direction may be connected to each other, for example, in the outer periphery region 14.

[0278] The semiconductor layer 12 may further include, in the peripheral region 14, a peripheral trench that surrounds the multiple gate trenches 24 in a plan view. The shapes of the gate electrode 36 and the field plate electrode 38 are not limited to the illustrated examples. For example, the gate electrode 36 or the field plate electrode 38 may include a portion having a relatively large width and a portion having a relatively small width.

[0279] The field plate electrode 38 does not have to include the raised portion 38A as shown in Fig. 4. Instead, the source wiring 22 and the field plate electrode 38 may be connected by increasing the dimension of the field plate electrode contact plug 42 in the depth direction.

[0280] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0281] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0282] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0283] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0284] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0285] (Appendix 1) a semiconductor layer (12) having an outer peripheral surface (12C) that is rectangular in plan view, the semiconductor layer (12) including an outer peripheral region (14) that includes the outer peripheral surface (12C), and an inner region (16) that is rectangular in plan view and is surrounded by the outer peripheral region (14); a plurality of gate trenches (24) located within the semiconductor layer (12); an insulating layer (18) located on the semiconductor layer (12); a plurality of gate electrodes (36), each of which is located within a corresponding one of the plurality of gate trenches (24); a gate wiring (20) located on the insulating layer (18) and electrically connected to the plurality of gate electrodes (36); a source wiring (22) located on the insulating layer (18) and spaced apart from the gate wiring (20); a plurality of mesa contact plugs (44), each of which is located in the inner region (16), not in the outer peripheral region (14), and between two of the plurality of gate trenches (24) in a plan view, and which penetrates the insulating layer (18) to connect the source wiring (22) and the semiconductor layer (12); Equipped with The outer peripheral surface (12C) includes a first side surface (12C1) and a second side surface (12C2) extending in a first direction in a plan view, and a third side surface (12C3) and a fourth side surface (12C4) extending in a second direction intersecting the first direction in a plan view, and the outer peripheral region (14) includes a first outer peripheral portion (P1) located between the first side surface (12C1) and the inner region (16), a second outer peripheral portion (P2) located between the second side surface (12C2) and the inner region (16), a third outer peripheral portion (P3) located between the third side surface (12C3) and the inner region (16), and a fourth outer peripheral portion (P4) located between the fourth side surface (12C4) and the inner region (16), the gate wiring (20) includes one or more gate finger portions (20Y) extending in the first direction, and each of the one or more gate finger portions (20Y) extending in the first direction overlaps at least the inner region (16) in a planar view, but does not overlap either the first outer peripheral portion (P1) or the second outer peripheral portion (P2).

[0286] (Appendix 2) the plurality of gate trenches (24) include a plurality of second trenches (24X) extending in the second direction; 2. The semiconductor device according to claim 1, wherein each of the plurality of second trenches (24X) overlaps, in a plan view, with at least one of one or more gate finger portions (20Y) extending in the first direction.

[0287] (Appendix 3) The semiconductor device described in Appendix 1, wherein the gate wiring (20) includes one or more gate finger portions (20X) extending in the second direction, and each of the one or more gate finger portions (20X) extending in the second direction overlaps at least the inner region (16) in a planar view, but does not overlap either the third outer peripheral portion (P3) or the fourth outer peripheral portion (P4).

[0288] (Appendix 4) the plurality of gate trenches (24) include a plurality of first trenches (24Y) extending in the first direction and a plurality of second trenches (24X) extending in the second direction; each of the plurality of first trenches (24Y) overlaps, in a plan view, with at least one of one or more gate finger portions (20X) extending in the second direction; 4. The semiconductor device according to claim 3, wherein each of the plurality of second trenches (24X) overlaps, in a plan view, with at least one of one or more gate finger portions (20Y) extending in the first direction.

[0289] (Appendix 5) 5. The semiconductor device according to any one of appendixes 1 to 4, further comprising a plurality of field plate electrodes (38) insulated from the plurality of gate electrodes (36), each of the plurality of field plate electrodes (38) being located within a corresponding one of the plurality of gate trenches (24).

[0290] (Appendix 6) A semiconductor device according to any one of appendices 1 to 5, wherein at least one of one or more gate finger portions (20Y) extending in the first direction partially overlaps, in a planar view, with at least one of the third outer peripheral portion (P3) and the fourth outer peripheral portion (P4).

[0291] (Appendix 7) A semiconductor device described in Appendix 3 or 4, wherein at least one of the one or more gate finger portions (20X) extending in the second direction partially overlaps, in a planar view, with at least one of the first outer peripheral portion (P1) and the second outer peripheral portion (P2).

[0292] (Appendix 8) the gate wiring (302) includes a gate pad portion (302P) connected to at least one of one or more gate finger portions (302Y) extending in the first direction; the plurality of gate trenches (24) include a plurality of second trenches (24X) extending in the second direction; The semiconductor device described in Appendix 1, wherein each of the plurality of second trenches (24X) overlaps in a planar view with at least one of one or more gate finger portions (302Y) extending in the first direction and the gate pad portion (302P).

[0293] (Appendix 9) the gate wiring (202) includes a gate pad portion (202P) connected to at least one of one or more gate finger portions (202Y) extending in the first direction and one or more gate finger portions (202X) extending in the second direction; the plurality of gate trenches (24) include a plurality of first trenches (24Y) extending in the first direction and a plurality of second trenches (24X) extending in the second direction; each of the plurality of first trenches (24Y) overlaps, in a plan view, at least one of one or more gate finger portions (202X) extending in the second direction and the gate pad portion (202P); The semiconductor device described in Appendix 3, wherein each of the plurality of second trenches (24X) overlaps in a planar view with at least one of one or more gate finger portions (202Y) extending in the first direction and the gate pad portion (202P).

[0294] (Appendix 10) The semiconductor device according to any one of appendices 1 to 9, further comprising a plurality of gate electrode contact plugs (40) that penetrate the insulating layer (18) and connect the gate wiring (20) and the plurality of gate electrodes (36).

[0295] (Appendix 11) 6. The semiconductor device according to claim 5, further comprising a plurality of field plate electrode contact plugs (42) that penetrate the insulating layer (18) and connect the source wiring (22) and the plurality of field plate electrodes (38).

[0296] (Appendix 12) The semiconductor device according to any one of appendices 1 to 11, wherein at least one of the plurality of gate trenches (24) is located within the first outer periphery portion (P1) or the second outer periphery portion (P2).

[0297] (Appendix 13) 5. The semiconductor device according to claim 3, wherein at least one of the plurality of gate trenches (24) is located within the third outer periphery portion (P3) or the fourth outer periphery portion (P4).

[0298] (Appendix 14) 5. The semiconductor device according to claim 1, wherein the inner region (16) is defined, in a plan view, by a rectangle formed by connecting the edges of the mesa contact plugs (44) that are closest to the first side (12C1), the second side (12C2), the third side (12C3), and the fourth side (12C4), respectively, among the plurality of mesa contact plugs (44).

[0299] (Appendix 15) 15. The semiconductor device according to any one of appendixes 1 to 14, wherein each of the one or more gate finger portions (20Y) extending in the first direction has an aspect ratio of 3 or more in a plan view.

[0300] (Appendix 16) the aspect ratio in a plan view of each of the one or more gate finger portions (20Y) extending in the first direction is 3 or more; 5. The semiconductor device according to claim 3, wherein each of the one or more gate finger portions (20X) extending in the second direction has an aspect ratio of 3 or more in a plan view.

[0301] (Appendix 17) 10. The semiconductor device according to claim 8, wherein the gate pad portion (20P) has an aspect ratio of less than 3 in a plan view.

[0302] (Appendix 18) 18. The semiconductor device according to any one of claims 1 to 17, wherein each of the plurality of gate trenches (24) is arranged so as to overlap both the gate wiring (20) and the source wiring (22) in a plan view.

[0303] (Appendix 19) 19. The semiconductor device according to any one of appendixes 1 to 18, wherein the source wiring (22) includes a plurality of portions (22A, 22B, 22C, 22D) separated by the gate wiring (20).

[0304] (Appendix 20) A semiconductor device described in any one of Appendices 1 to 18, wherein the source wiring (704) includes multiple portions (704A, 704B, 704C, 704D) separated by the gate wiring (702) and one or more connection portions (704E, 704F, 704G) connecting between them.

[0305] Various changes in form and detail may be made to the above-described examples without departing from the scope of the claims and their equivalents. The above-described examples are illustrative and not limiting. The description of a feature in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the sequential events are performed in a different order and / or if components within the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations within the scope of the claims and their equivalents are included herein. [Explanation of symbols]

[0306] 10, 100, 200, 300, 400, 500, 600, 700...Semiconductor device 12...Semiconductor layer 12A…Side 1 12B…Second side 12C…Outer surface 12C1…1st side 12C2…Second side 12C3…Third side 12C4…4th side 14...Outer area P1...first outer circumference part P2…Second outer circumference part P3...Third outer peripheral part P4…4th outer circumference part 16…Inner area 18...Insulating layer 20,102,202,302,402,502,602,702...Gate wiring 20P, 102P, 202P, 302P, 402P, 502P, 602P, 702P...Gate pad section 20X, 20Y, 102X, 102Y, 202X, 202Y, 302Y, 402Y, 502Y, 602X, 602Y, 702X, 702Y...Gate finger part 20Y1, 102Y1, 502Y1, 602Y1, 702Y1...First gate finger part 20Y2, 102Y2, 502Y2, 602Y2, 702Y2...Second gate finger part 20X1, 102X1, 502Y3, 602X1, 702X1...Third gate finger part 20X2, 102X2, 602X2, 702X2...4th gate finger part 22, 104, 204, 304, 404, 504, 604, 704...Source wiring 22A, 204A, 304A, 404A, 504A, 604A, 704A…1st part 22B,204B,304B,404B,504B,604B,704B…Second part 22C,204C,604C,704C…3rd part 22D,604D,704D…4th part 704E, 704F, 704G...Connection 24...Gate trench 24X...Second trench 24Y...1st Trench 24A…Side wall 26...Drain region 28...Drift region 30...Body area 32...Source region 34...Drain electrode 36...Gate electrode 38...Field plate electrode 38A…part 40...Gate electrode contact plug 42...Field plate electrode contact plug 44...Mesa contact plug 46...Mesa section 48...Contact area 106...Invalid area

Claims

1. a semiconductor layer having an outer peripheral surface that is rectangular in plan view, the semiconductor layer including an outer peripheral region that includes the outer peripheral surface, and an inner region that is rectangular in plan view and is surrounded by the outer peripheral region; a plurality of gate trenches located within the semiconductor layer; an insulating layer located on the semiconductor layer; a plurality of gate electrodes, each of which is located within a corresponding one of the plurality of gate trenches; a gate wiring located on the insulating layer and electrically connected to the plurality of gate electrodes; a source wiring located on the insulating layer and spaced apart from the gate wiring; a plurality of mesa contact plugs, each of which is located in the inner region and not in the outer periphery region, is located between two of the plurality of gate trenches in a plan view, and penetrates the insulating layer to connect the source wiring and the semiconductor layer; Equipped with the outer peripheral surface includes a first side surface and a second side surface extending in a first direction in a plan view, and a third side surface and a fourth side surface extending in a second direction intersecting the first direction in a plan view, and the outer peripheral region includes a first outer peripheral portion located between the first side surface and the inner region, a second outer peripheral portion located between the second side surface and the inner region, a third outer peripheral portion located between the third side surface and the inner region, and a fourth outer peripheral portion located between the fourth side surface and the inner region, the gate wiring includes one or more gate finger portions extending in the first direction, and each of the one or more gate finger portions extending in the first direction overlaps at least the inner region in a planar view but does not overlap either the first outer peripheral portion or the second outer peripheral portion.

2. the plurality of gate trenches include a plurality of second trenches extending in the second direction; The semiconductor device according to claim 1 , wherein each of the plurality of second trenches overlaps, in a plan view, at least one of the one or more gate finger portions extending in the first direction.

3. 2. The semiconductor device according to claim 1, wherein the gate wiring includes one or more gate finger portions extending in the second direction, and each of the one or more gate finger portions extending in the second direction overlaps at least the inner region in a planar view but does not overlap either the third outer peripheral portion or the fourth outer peripheral portion.

4. the plurality of gate trenches include a plurality of first trenches extending in the first direction and a plurality of second trenches extending in the second direction; each of the plurality of first trenches overlaps, in a plan view, at least one of the one or more gate finger portions extending in the second direction; The semiconductor device according to claim 3 , wherein each of the plurality of second trenches overlaps, in a plan view, at least one of the one or more gate finger portions extending in the first direction.

5. 5. The semiconductor device according to claim 1, further comprising a plurality of field plate electrodes insulated from the plurality of gate electrodes, each of the plurality of field plate electrodes being located within a corresponding one of the plurality of gate trenches.

6. 5. The semiconductor device according to claim 1, wherein at least one of the one or more gate finger portions extending in the first direction partially overlaps with at least one of the third outer peripheral portion and the fourth outer peripheral portion in a planar view.

7. 5. The semiconductor device according to claim 3, wherein at least one of the one or more gate finger portions extending in the second direction partially overlaps with at least one of the first outer peripheral portion and the second outer peripheral portion in a plan view.

8. the gate wiring includes a gate pad portion connected to at least one of one or more gate finger portions extending in the first direction, the plurality of gate trenches include a plurality of second trenches extending in the second direction; The semiconductor device according to claim 1 , wherein each of the second trenches overlaps, in a plan view, at least one of one or more gate finger portions extending in the first direction and the gate pad portion.

9. the gate wiring includes a gate pad portion connected to at least one of one or more gate finger portions extending in the first direction and one or more gate finger portions extending in the second direction; the plurality of gate trenches include a plurality of first trenches extending in the first direction and a plurality of second trenches extending in the second direction; each of the plurality of first trenches overlaps, in a plan view, at least one of one or more gate finger portions extending in the second direction and the gate pad portion; 4 . The semiconductor device according to claim 3 , wherein each of the second trenches overlaps, in a plan view, at least one of one or more gate finger portions extending in the first direction and the gate pad portion.

10. 5. The semiconductor device according to claim 1, further comprising a plurality of gate electrode contact plugs that penetrate said insulating layer and connect said gate wiring to said plurality of gate electrodes.

11. 6. The semiconductor device according to claim 5, further comprising a plurality of field plate electrode contact plugs that penetrate said insulating layer and connect said source wiring to said plurality of field plate electrodes.

12. 5. The semiconductor device according to claim 1, wherein at least one of said plurality of gate trenches is located within said first outer periphery portion or said second outer periphery portion.

13. 5. The semiconductor device according to claim 3, wherein at least one of the plurality of gate trenches is located within the third outer periphery portion or the fourth outer periphery portion.

14. The semiconductor device according to any one of claims 1 to 4, wherein the inner region is defined, in a planar view, by a rectangle formed by connecting the edges of the mesa contact plugs that are closest to the first side, the second side, the third side, and the fourth side, respectively, among the plurality of mesa contact plugs.

15. 5. The semiconductor device according to claim 1, wherein each of the one or more gate finger portions extending in the first direction has an aspect ratio of 3 or more in a plan view.

16. an aspect ratio in a plan view of each of the one or more gate finger portions extending in the first direction is 3 or more; 5. The semiconductor device according to claim 3, wherein each of the one or more gate finger portions extending in the second direction has an aspect ratio of 3 or more in a plan view.

17. 10. The semiconductor device according to claim 8, wherein the gate pad portion has an aspect ratio of less than 3 in a plan view.

18. 5. The semiconductor device according to claim 1, wherein each of the plurality of gate trenches is arranged so as to overlap both the gate wiring and the source wiring in a plan view.

19. 5. The semiconductor device according to claim 1, wherein the source wiring includes a plurality of portions separated by the gate wiring.

20. 5. The semiconductor device according to claim 1, wherein the source wiring includes a plurality of portions separated by the gate wiring and one or more connection portions connecting the portions.

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