Semiconductor device

Abstract

To achieve both improvement in breakdown voltage and reduction in on-resistance, and relaxation of alignment accuracy between a semiconductor layer and a source contact plug in a semiconductor device.SOLUTION: The semiconductor element 10 includes a first gate trench side 20A, a second gate trench side 20B, a first gate electrode side 60A, a first field plate electrode side 70A, and a source contact plug 42. The first gate trench side 20A and the second gate trench side 20B extend in the first direction and are separated from each other in the second direction. The layer 12 includes a mesa part 90 demarcated between both gate trench side 20A and side 20B. The mesa portion 90 includes a mesa wide portion 92 and a mesa narrow portion 94 having a dimension in the Y direction smaller than that of the mesa wide portion 92. The source contact plug 42 is in contact with the wide mesa portion 92. The mesa narrow portion 94 faces at least a part of the upper side 70A of the first field plate electrodes side 76A in the second direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a metal insulator semiconductor field effect transistor (MISFET) having a trench gate structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-129378

[0004] [overview] In a semiconductor device having a trench gate structure, there is room for improvement in achieving both an improvement in breakdown voltage and a reduction in on-resistance, while relaxing the precision required for aligning a semiconductor layer with a source contact plug.

[0005] A semiconductor device according to one embodiment of the present disclosure includes: a semiconductor layer having a first surface and a second surface opposite the first surface; first and second gate trenches extending from the second surface into the semiconductor layer and having sidewalls and a bottom wall; an insulating layer located on the semiconductor layer; a first gate electrode located in the first gate trench; a first field plate electrode located in the first gate trench, positioned closer to the bottom wall than the first gate electrode in a depth direction perpendicular to the first surface and including a first field plate upper surface facing the first gate electrode via the insulating layer; and a source contact plug penetrating the insulating layer and including a contact lower surface in contact with the semiconductor layer. Each of the first gate trench and the second gate trench extends in a first direction in a plan view and is spaced apart in a second direction perpendicular to the first direction in a plan view. The semiconductor layer includes a mesa portion defined between the first gate trench and the second gate trench. The mesa portion includes a wide mesa portion having a portion of the second surface as an upper surface thereof, and a narrow mesa portion having a width in the second direction smaller than that of the wide mesa portion. The source contact plug is in contact with the wide mesa portion. The narrow mesa portion faces at least a portion of an upper portion of the first field plate electrode in the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is an enlarged view of a portion of FIG. [Figure 4] 4A to 4C are schematic cross-sectional views illustrating an exemplary manufacturing process of the semiconductor device according to one embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 7]FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view of a semiconductor device showing a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying example embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The term "plan view" used in the present disclosure refers to viewing a semiconductor device in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Fig. 1. For ease of explanation, the direction along the Z-axis direction will be referred to as the "Z direction," the direction along the X-axis direction as the "X direction," and the direction along the Y-axis direction as the "Y direction."

[0010] <Embodiment> A semiconductor device 10 according to an exemplary embodiment of the present disclosure will be described with reference to Figures 1 to 3. Figure 1 is a schematic plan view of the semiconductor device 10. Figure 2 is a schematic cross-sectional view taken along line F2-F2 in Figure 2. Figure 3 is an enlarged view of a portion of Figure 2.

[0011] The semiconductor device 10 may be, for example, a MISFET having a split gate structure. As shown in FIGS. 1 to 3, the semiconductor device 10 includes a semiconductor layer 12. The semiconductor layer 12 has a first surface 12F (see FIG. 2) and a second surface 12G opposite to the first surface 12F. The semiconductor layer 12 has a thickness in a direction (Z direction) perpendicular to the first surface 12F and the second surface 12G. In this embodiment, the Z direction can also be referred to as the thickness direction of the semiconductor layer 12. The semiconductor layer 12 may be made of, for example, silicon (Si).

[0012] (Plane layout of semiconductor device) 1, the semiconductor layer 12 may have a rectangular shape in a plan view. In the illustrated example, the semiconductor layer 12 includes two side surfaces 12X1 and 12X2 extending along the X-axis direction in a plan view and two side surfaces 12Y1 and 12Y2 extending along the Y-axis direction in a plan view.

[0013] The semiconductor device 10 includes an insulating layer 14 located on the semiconductor layer 12. In one example, the insulating layer 14 may include at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, and a silicon oxynitride (SiON) layer.

[0014] The semiconductor device 10 may include a gate wiring 16 located on the insulating layer 14. In the example shown in FIG. 1 , the gate wiring 16 includes a gate pad portion 16P, a first gate wiring portion 16Y1 and a second gate wiring portion 16Y2 extending in the Y-axis direction, and a third gate wiring portion 16X extending in the X-axis direction. The gate pad portion 16P is located relatively close to a corner of the semiconductor device 10 (e.g., a position where the side surface 12Y1 and the side surface 12X2 of the semiconductor layer 12 intersect). The first gate wiring portion 16Y1 and the second gate wiring portion 16Y2 are located relatively close to the side surface 12Y1 and the side surface 12Y2 of the semiconductor layer 12, respectively. The third gate wiring portion 16X is located relatively close to the side surface 12X2 of the semiconductor layer 12. The first gate wiring portion 16Y1 is connected to the gate pad portion 16P. The second gate wiring portion 16Y2 is connected to the third gate wiring portion 16X. The third gate wiring portion 16X connects the gate pad portion 16P and the second gate wiring portion 16Y2.

[0015] The semiconductor device 10 may include a source wiring 18 located on the insulating layer 14. The source wiring 18 is spaced apart from the gate wiring 16. In the example shown in FIG. 1 , the source wiring 18 includes an inner source wiring portion 18M and a peripheral source wiring portion 18L. The inner source wiring portion 18M may be at least partially surrounded by the gate wiring 16 in a planar view. The peripheral source wiring portion 18L may surround the gate wiring 16 in a planar view. The inner source wiring portion 18M is electrically connected to the peripheral source wiring portion 18L. The inner source wiring portion 18M and the peripheral source wiring portion 18L are connected in a region between an end of the first gate wiring portion 16Y1 and an end of the second gate wiring portion 16Y2, and thereby are integrally formed.

[0016] The gate wiring 16 and the source wiring 18 may be made of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0017] The layout of the gate wiring 16 and the source wiring 18 is not limited to the illustrated example, and as will be understood by those skilled in the art, different layouts of the gate wiring 16 and the source wiring 18 can be adopted depending on the desired characteristics of the semiconductor device 10.

[0018] (Trench placement) The semiconductor device 10 includes a gate trench 20. In this disclosure, the term "gate trench" can refer to a trench (or a portion of a trench) in which at least an electrode to which a gate voltage is applied (e.g., an electrode to which a gate voltage is applied to form a channel in the semiconductor layer 12, such as the gate electrode 60 described below) is disposed. In this disclosure, the gate trench 20 may also be simply referred to as a trench.

[0019] The semiconductor device 10 includes a plurality of gate trenches 20. The plurality of gate trenches 20 can intersect with the first gate wiring portion 16Y1 or the second gate wiring portion 16Y2 in a plan view. In this case, each of the plurality of gate trenches 20 extends in a first direction in a plan view and is spaced apart in a second direction perpendicular to the first direction in a plan view. The plurality of gate trenches 20 have a constant depth in a direction perpendicular to both the first direction and the second direction. Here, in the present disclosure, the X direction corresponds to the "first direction." The Y direction corresponds to the "second direction." In this case, the direction perpendicular to both the first direction and the second direction corresponds to the Z direction.

[0020] In this disclosure, unless otherwise specified, the "depth direction" refers to the depth direction of the gate trench 20, which corresponds to the Z direction. In other words, the Z direction can also be said to be the depth direction of the gate trench 20. The "width direction" refers to the width direction of the gate trench 20, which corresponds to the Y direction. In other words, the Y direction can also be said to be the width direction of the gate trench 20.

[0021] The plurality of gate trenches 20 are arranged at intervals. In one example, the plurality of gate trenches 20 may be aligned at a constant pitch in the Y direction. Optionally, the semiconductor device 10 may further include one or more peripheral trenches 40 formed in the semiconductor layer 12. Each peripheral trench 40 may be arranged so as to at least partially surround some of the multiple gate trenches 20 in a plan view. In the example shown, each peripheral trench 40 forms a rectangular loop so as to surround some of the gate trenches 20 in a plan view. Furthermore, the gate trenches 20 surrounded by each peripheral trench 40 may be in communication with the peripheral trench 40.

[0022] The layout of the gate trench 20 and the peripheral trench 40 is not limited to the illustrated example. As will be understood by those skilled in the art, different layouts of the gate trench 20 and the peripheral trench 40 can be adopted depending on the desired characteristics of the semiconductor device 10. For example, the semiconductor device 10 may further include a plurality of additional gate trenches (not shown) extending in the Y-axis direction in a plan view. Also, for example, the gate trench 20 may be separated from the peripheral trench 40.

[0023] (Contact plug placement) The semiconductor device 10 may include source contact plugs 42 that connect the source wiring 18 to the semiconductor layer 12. In the example shown in FIG. 1 , the semiconductor device 10 includes a plurality of source contact plugs 42. The plurality of source contact plugs 42 may be arranged to overlap with the inner source wiring portion 18M in a plan view. The plurality of source contact plugs 42 may be arranged such that each gate trench 20 is located between two of the plurality of source contact plugs 42 in a plan view. Each source contact plug 42 may extend parallel to the gate trench 20 (i.e., along the longitudinal direction of the gate trench 20) in a plan view.

[0024] The semiconductor device 10 may include a plurality of gate electrode contact plugs 44 and a plurality of field plate electrode contact plugs 46. Each gate electrode contact plug 44 may be disposed in a region where the gate wiring 16 and the gate trench 20 overlap in a plan view. The gate wiring 16 may be electrically connected to an electrode (e.g., a gate electrode 60, which will be described later with reference to FIG. 2 ) disposed in the gate trench 20 via the plurality of gate electrode contact plugs 44. Each field plate electrode contact plug 46 may be disposed in a region where the source wiring 18 and the peripheral trench 40 overlap in a plan view. The source wiring 18 may be electrically connected to an electrode (e.g., a field plate electrode 70, which will be described later with reference to FIG. 2 ) disposed in the peripheral trench 40 via the plurality of field plate electrode contact plugs 46.

[0025] (Details of the semiconductor layer) A schematic cross-sectional structure of the semiconductor device 10 will be described below with reference to Fig. 2. For ease of understanding, in Fig. 2, the same components as those in Fig. 1 are denoted by the same reference numerals.

[0026] The semiconductor layer 12 includes a drain region 48 of a first conductivity type, a drift region 50 of the first conductivity type located on the drain region 48, a body region 52 of a second conductivity type located on the drift region 50, and a source region 54 of the first conductivity type located on the body region 52.

[0027] In the present disclosure, the first conductivity type region may be an n-type region containing n-type impurities, and the second conductivity type region may be a p-type region containing p-type impurities. The n-type impurities may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb), and the p-type impurities may include, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0028] In this embodiment, the drain region 48 is made of a Si substrate, and the drift region 50, the body region 52, and the source region 54 are made of Si epitaxial layers.

[0029] The drift region 50, the body region 52, and the source region 54 are sequentially stacked on the drain region 48. The drain region 48 includes the first surface 12F of the semiconductor layer 12. That is, the drain region 48 constitutes the lowermost layer of the semiconductor layer 12, and the lower surface of the drain region 48 constitutes the first surface 12F of the semiconductor layer 12.

[0030] The source region 54 includes at least a part of the second surface 12G of the semiconductor layer 12. That is, the source region 54 constitutes the uppermost layer of the semiconductor layer 12, and the upper surface of the source region 54 constitutes at least a part of the second surface 12G of the semiconductor layer 12.

[0031] The drain region 48 is a region of the first conductivity type containing n-type impurities. The n-type impurity concentration of the drain region 48 is 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 48 may have a thickness of 10 μm or more and 450 μm or less.

[0032] The drift region 50 is a region of the first conductivity type that contains n-type impurities at a concentration lower than that of the drain region 48. The n-type impurity concentration of the drift region 50 is 1×10 15 cm -3More than 1×10 18 cm -3 The drift region 50 may have a thickness of 1 μm or more and 25 μm or less.

[0033] The body region 52 is a region of the second conductivity type containing p-type impurities. The p-type impurity concentration of the body region 52 is 1×10 16 cm-3 or more 1×10 18 cm -3 The body region 52 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0034] The source region 54 is a region of the first conductivity type that contains n-type impurities at a higher concentration than the drift region 50. The n-type impurity concentration of the source region 54 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 54 may have a thickness of at least 0.1 μm and at most 1 μm.

[0035] In this embodiment, the thickness of the body region 52 is greater than the thickness of the source region 54. Specifically, the thickness of the body region 52 is more than twice the thickness of the source region 54. The semiconductor device 10 may include a drain electrode 56 in contact with the first surface 12F of the semiconductor layer 12. The drain electrode 56 is electrically connected to the drain region 48. The drain electrode 56 may be made of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy. In this embodiment, the drain electrode 56 is in contact with the entire first surface 12F of the semiconductor layer 12.

[0036] (Gate trench explanation) Next, the gate trenches 20 of the semiconductor device 10 will be described. As described above, the semiconductor device 10 includes a plurality of gate trenches 20 extending from the second surface 12G into the semiconductor layer 12. As shown in FIG. 2 , each of the plurality of gate trenches 20 has an opening 22. The opening 22 may correspond to an entrance portion of the gate trench 20, and more specifically, may be a portion of the gate trench 20 adjacent to the second surface 12G of the semiconductor layer 12.

[0037] Each of the multiple gate trenches 20 has a sidewall 24 and a bottom wall 26. The multiple gate trenches 20 penetrate the source region 54 of the semiconductor layer 12. The multiple gate trenches 20 penetrate the body region 52. The multiple gate trenches 20 reach the drift region 50. In other words, the depth dimension (dimension in the depth direction) of the multiple gate trenches 20 is greater than the combined thickness of the source region 54 and the body region 52. For example, each gate trench 20 can have a depth dimension of, for example, 1 μm or more and 15 μm or less.

[0038] In this embodiment, for convenience of explanation, among the multiple gate trenches 20 and their surrounding components, two gate trenches 20 adjacent to each other in the Y direction and their surrounding components will be described in detail.

[0039] In this embodiment, the multiple gate trenches 20 include a first gate trench 20A and a second gate trench 20B. The first gate trench 20A and the second gate trench 20B each extend in the X direction and are spaced apart from each other in the Y direction. The first gate trench 20A and the second gate trench 20B correspond to two adjacent ones of the multiple gate trenches 20.

[0040] The first gate trench 20A includes a first trench wide portion 28A and a first trench narrow portion 30A. The first trench narrow portion 30A has a smaller dimension in the Y direction than the first trench wide portion 28A. Specifically, the first trench wide portion 28A has a first wide trench width W1a as its dimension in the Y direction. The first trench narrow portion 30A has a first narrow trench width W2a as its dimension in the Y direction. The first narrow trench width W2a is smaller than the first wide trench width W1a. The first trench narrow portion 30A may have a smaller dimension in the Z direction than the first trench wide portion 28A.

[0041] The first trench wide portion 28A is located closer to the first surface 12F in the first gate trench 20A. The first trench wide portion 28A includes the bottom wall 26. The first trench narrow portion 30A includes the opening 22. In other words, the first trench narrow portion 30A is located closer to the second surface 12G than the first trench wide portion 28A.

[0042] In other words, the first gate trench 20A has a smaller Y-direction dimension near the opening 22 due to the first trench narrow portion 30A, and a larger Y-direction dimension near the bottom wall 26 due to the first trench wide portion 28A.

[0043] The first trench wide portion 28A includes a first lower sidewall 32A that is part of the sidewall 24. The first lower sidewall 32A is connected to the bottom wall 26. The first trench narrow portion 30A includes a first upper sidewall 34A that is part of the sidewall 24.

[0044] In this disclosure, the Y-direction dimension of a trench refers to the distance in the Y-direction between the sidewalls 24 of each trench. For example, as shown in FIG. 2, the first wide trench width W1a can also be considered to be the distance in the Y-direction between the first lower sidewalls 32A. Furthermore, the first narrow trench width W2a can also be considered to be the distance in the Y-direction between the first upper sidewalls 34A. The first upper sidewalls 34A may be connected to the second surface 12G of the semiconductor layer 12.

[0045] In this embodiment, the first lower sidewall 32A and the first upper sidewall 34A extend substantially perpendicular to the first surface 12F. However, the first lower sidewall 32A and the first upper sidewall 34A do not have to be substantially perpendicular to the first surface 12F. For example, the first lower sidewalls 32A may have a tapered structure in which the distance between the first lower sidewalls 32A decreases as they approach the first surface 12F. Furthermore, the first lower sidewalls 32A may be partially or entirely curved. The first upper sidewall 34A may also have a similar tapered structure, or may be partially or entirely curved.

[0046] The bottom wall 26 of the first gate trench 20A extends in a direction substantially parallel to the first surface 12F of the semiconductor layer 12. However, the bottom wall 26 does not necessarily have to be flat, and may be, for example, partially or entirely curved.

[0047] The second gate trench 20B includes a second trench wide portion 28B and a second trench narrow portion 30B. The second trench narrow portion 30B has a smaller dimension in the Y direction than the second trench wide portion 28B. Specifically, the second trench wide portion 28B has a second wide trench width W1b as its dimension in the Y direction. The second trench narrow portion 30B has a second narrow trench width W2b as its dimension in the Y direction. The second narrow trench width W2b is smaller than the second wide trench width W1b. The second trench narrow portion 30B may have a smaller dimension in the Z direction than the second trench wide portion 28B.

[0048] The second trench wide portion 28B is located closer to the first surface 12F in the second gate trench 20B. The second trench wide portion 28B includes the bottom wall 26. The second trench narrow portion 30B includes the opening 22. In other words, the second trench narrow portion 30B is located closer to the second surface 12G than the second trench wide portion 28B.

[0049] In other words, the second gate trench 20B has a smaller Y-direction dimension near the opening 22 due to the second trench narrow portion 30B, and a larger Y-direction dimension near the bottom wall 26 due to the second trench wide portion 28B.

[0050] The second trench wide portion 28B includes a second lower sidewall 32B that is part of the sidewall 24. The second lower sidewall 32B is connected to the bottom wall 26. The second trench narrow portion 30B includes a second upper sidewall 34B that is part of the sidewall 24. The second upper sidewall 34B may be connected to the second surface 12G of the semiconductor layer 12.

[0051] 2, the second wide trench width W1b can also be considered to be the distance between the second lower sidewalls 32B in the Y direction, and the second narrow trench width W2b can also be considered to be the distance between the second upper sidewalls 34B in the Y direction.

[0052] In this embodiment, the second lower sidewall 32B and the second upper sidewall 34B extend substantially perpendicular to the first surface 12F. However, the second lower sidewall 32B and the second upper sidewall 34B do not have to be substantially perpendicular to the first surface 12F. For example, the second lower sidewall 32B may have a tapered structure in which the distance between the second lower sidewalls 32B decreases as the second lower sidewall 32B approaches the first surface 12F. Furthermore, the second lower sidewall 32B may be partially or entirely curved. The second upper sidewall 34B may also have a similar tapered structure, or may be partially or entirely curved.

[0053] The bottom wall 26 of the second gate trench 20B extends in a direction substantially parallel to the first surface 12F and the second surface 12G of the semiconductor layer 12. However, the bottom wall 26 does not necessarily have to be flat, and may be, for example, partially or entirely curved.

[0054] 3, the first gate trench 20A and the second gate trench 20B have a stepped structure corresponding to the mesa portion 90 (described later) including a mesa step portion 96. The first gate trench 20A has a stepped structure due to the difference between the first wide trench width W1a and the first narrow trench width W2a. The second gate trench 20B has a stepped structure due to the difference between the second wide trench width W1b and the second narrow trench width W2b.

[0055] The drift region 50 is located between the first lower sidewall 32A and the second lower sidewall 32B. The drift region 50, the body region 52, and the source region 54 are located between the first upper sidewall 34A and the second upper sidewall 34B. In other words, the drift region 50 is provided across the gap between the first lower sidewall 32A and the second lower sidewall 32B and the gap between the first upper sidewall 34A and the second upper sidewall 34B.

[0056] In the illustrated example, the first gate trench 20A and the second gate trench 20B (both see FIG. 2) have the same shape, but they may be different. For example, the second gate trench 20B may not include the second trench wide portion 28B and the second trench narrow portion 30B. The Z-direction depth dimensions of the first gate trench 20A and the second gate trench 20B may be different from each other. Furthermore, the Z-direction dimensions of the first trench wide portion 28A and the second trench wide portion 28B may be different from each other. The Z-direction dimensions of the first trench narrow portion 30A and the second trench narrow portion 30B may be different from each other.

[0057] (Schematic structure inside the gate trench) 2, the semiconductor device 10 includes a plurality of gate electrodes 60, a plurality of field plate electrodes 70, and an insulating layer 14. The plurality of gate electrodes 60 and the plurality of field plate electrodes 70 may be made of conductive polysilicon, for example.

[0058] A plurality of gate electrodes 60 are located in the corresponding gate trenches 20. In this embodiment, the plurality of gate electrodes 60 include a first gate electrode 60A and a second gate electrode 60B. The first gate electrode 60A is located in the first gate trench 20A. The second gate electrode 60B is located in the second gate trench 20B.

[0059] In the illustrated example, the first gate electrode 60A has a rectangular shape with its short side in the Y direction and its long side in the Z direction when viewed from the X direction. The first gate electrode 60A is located near the opening 22 of the first gate trench 20A. In this embodiment, the first gate electrode 60A is located within the first trench narrow portion 30A. When viewed from the X direction, the first gate electrode 60A is surrounded by an insulating layer 14.

[0060] The first gate electrode 60A includes a first gate lower surface 62A as a lower end surface in the Z direction. The first gate electrode 60A includes a first gate side surface 64A as an end surface in the Y direction. The first gate lower surface 62A and the first gate side surface 64A are in contact with the insulating layer 14.

[0061] The shape of the first gate electrode 60A is not limited to the above. For example, the first gate electrode 60A may be rectangular, with the Y direction as the longitudinal direction and the Z direction as the lateral direction, when viewed from the X direction. The first gate electrode 60A does not have to be rectangular. The first gate electrode 60A does not have to be rectangular. For example, the first gate lower surface 62A and / or other surfaces of the first gate electrode 60A may be partially or entirely curved.

[0062] In the illustrated example, the second gate electrode 60B has a rectangular shape with its short side in the Y direction and its long side in the Z direction when viewed from the X direction. The second gate electrode 60B is located closer to the opening 22 of the second gate trench 20B. In this embodiment, the second gate electrode 60B is located within the second trench narrow portion 30B. When viewed from the X direction, the second gate electrode 60B is surrounded by an insulating layer 14.

[0063] The second gate electrode 60B includes a second gate lower surface 62B as its lower end surface in the Z direction. The second gate electrode 60B includes a second gate side surface 64B as its end surface in the Y direction. The second gate lower surface 62B and the second gate side surface 64B are in contact with the insulating layer 14.

[0064] The shape of the second gate electrode 60B is not limited to the above. For example, the second gate electrode 60B may be rectangular, with the Y direction as the longitudinal direction and the Z direction as the lateral direction, as viewed from the X direction. The second gate electrode 60B does not have to be rectangular. For example, the second gate lower surface 62B and / or other surfaces of the second gate electrode 60B may be partially or entirely curved.

[0065] A plurality of field plate electrodes 70 are located in each corresponding gate trench 20. In this embodiment, the plurality of field plate electrodes 70 include a first field plate electrode 70A and a second field plate electrode 70B. The first field plate electrode 70A is located in the first gate trench 20A. The second field plate electrode 70B is located in the second gate trench 20B.

[0066] When viewed from the X direction, the first field plate electrode 70A has a rectangular shape with its short side in the Y direction and its long side in the Z direction. The first field plate electrode 70A is located closer to the bottom wall 26 of the first gate trench 20A in the Z direction. In this embodiment, the first field plate electrode 70A is located within the first trench wide portion 28A. When viewed from the X direction, the first field plate electrode 70A is surrounded by the insulating layer 14.

[0067] The first field plate electrode 70A is spaced apart from the first gate electrode 60A. The first field plate electrode 70A is located closer to the bottom wall 26 than the first gate electrode 60A in the Z direction. In this embodiment, the first field plate electrode 70A is located inside the first trench wide portion 28A.

[0068] The first field plate electrode 70A includes a first field plate upper surface 72A and a first field plate side surface 74A. The first field plate electrode 70A faces the first gate electrode 60A. Specifically, the first field plate upper surface 72A faces the first gate lower surface 62A in the Z direction, with the insulating layer 14 interposed therebetween.

[0069] In this embodiment, the Y-direction dimension of the first gate electrode 60A is equal to the Y-direction dimension of the first field plate electrode 70A. In this disclosure, "equal dimensions" (including thickness, width, length, distance, etc.) means that the difference is within the range of manufacturing variation (for example, 20%). The Y-direction dimension of the first gate electrode 60A does not have to be equal to the Y-direction dimension of the first field plate electrode 70A. The Y-direction dimension of the first gate electrode 60A may be larger or smaller than the Y-direction dimension of the first field plate electrode 70A.

[0070] The Z-direction dimension of the first gate electrode 60A is smaller than the Z-direction dimension of the first field plate electrode 70A. This corresponds to the fact that the Z-direction dimension of the first trench narrow portion 30A is smaller than the Z-direction dimension of the first trench wide portion 28A.

[0071] In the illustrated example, the second field plate electrode 70B has a rectangular shape with its short side in the Y direction and its long side in the Z direction when viewed from the X direction. The second field plate electrode 70B is located closer to the bottom wall 26 of the second gate trench 20B in the Z direction. In this embodiment, the second field plate electrode 70B is located within the second trench wide portion 28B. When viewed from the X direction, the second field plate electrode 70B is surrounded by the insulating layer 14.

[0072] The second field plate electrode 70B is spaced apart from the second gate electrode 60B. The second field plate electrode 70B is located closer to the bottom wall 26 in the Z direction than the second gate electrode 60B. In this embodiment, the second field plate electrode 70B is located within the second trench wide portion 28B.

[0073] The second field plate electrode 70B includes a second field plate upper surface 72B and a second field plate side surface 74B. The second field plate electrode 70B faces the second gate electrode 60B. Specifically, the second field plate upper surface 72B faces the second gate lower surface 62B in the Z direction, with the insulating layer 14 interposed therebetween.

[0074] In this embodiment, the dimension in the Y direction of the second gate electrode 60B is equal to the dimension in the Y direction of the second field plate electrode 70B. The dimension in the Y direction of the second gate electrode 60B does not have to be equal to the dimension in the Y direction of the second field plate electrode 70B. The dimension in the Y direction of the second gate electrode 60B may be larger or smaller than the dimension in the Y direction of the second field plate electrode 70B.

[0075] The Z-direction dimension of the second gate electrode 60B is smaller than the Z-direction dimension of the second field plate electrode 70B, which corresponds to the Z-direction dimension of the second trench narrow portion 30B being smaller than the Z-direction dimension of the second trench wide portion 28B.

[0076] In this embodiment, the first gate side surface 64A and the second gate side surface 64B are substantially perpendicular to the first surface 12F. However, the first gate side surface 64A and the second gate side surface 64B do not have to be substantially perpendicular to the first surface 12F. For example, the first gate electrode 60A may have a tapered structure in which the distance between the first gate side surfaces 64A decreases as the first gate electrode 60A approaches the first surface 12F. Furthermore, the first gate side surfaces 64A may be curved partially or entirely. Similarly, the second gate electrode 60B may have a tapered structure. The second gate side surfaces 64B may be curved partially or entirely.

[0077] Similarly, the first field plate side surface 74A and the second field plate side surface 74B may each have a tapered structure, or may be partially or entirely curved. The insulating layer 14 is located on the semiconductor layer 12. In one example, the insulating layer 14 may be made of SiO2. The insulating layer 14 includes a plurality of trench insulating layers 80 and an interlayer insulating layer 86. The plurality of trench insulating layers 80 are located in the corresponding gate trenches 20. The plurality of trench insulating layers 80 can be said to be portions of the insulating layer 14 that are located between the second surface 12G and the first surface 12F. Each of the plurality of trench insulating layers 80 is formed integrally with the interlayer insulating layer 86. In this embodiment, the plurality of trench insulating layers 80 includes a first trench insulating layer 80A and a second trench insulating layer 80B.

[0078] The first trench insulation layer 80A is located in the first gate trench 20A. The first trench insulation layer 80A covers the sidewall 24 and bottom wall 26 of the first gate trench 20A. The first trench insulation layer 80A also covers the first gate electrode 60A and the first field plate electrode 70A.

[0079] The first trench insulation layer 80A includes a first gate insulation portion 82A and a first field plate insulation portion 84A. The first gate insulation portion 82A is a portion of the first trench insulation layer 80A that is located between the first gate electrode 60A and the sidewall 24. In particular, the first gate insulation portion 82A is located between the first gate side surface 64A and the first upper sidewall 34A.

[0080] In this embodiment, the dimension of the first gate insulating portion 82A in the Y direction is constant. The first field plate insulating portion 84A is a portion of the first trench insulating layer 80A that is located between the first field plate electrode 70A and the sidewall 24. In particular, the first field plate insulating portion 84A is a portion of the first trench insulating layer 80A that is located between the first field plate side surface 74A and the first lower sidewall 32A. In this embodiment, the dimension of the first field plate insulating portion 84A in the Y direction is constant.

[0081] 3, the Y-direction dimension of the first gate insulating portion 82A is smaller than the Y-direction dimension of the first field plate insulating portion 84A. Specifically, the first gate insulating portion 82A has a first gate insulating width W3a as its Y-direction dimension. The first field plate insulating portion 84A has a first field plate insulating width W4a as its Y-direction dimension. The first gate insulating width W3a is smaller than the first field plate insulating width W4a.

[0082] The first gate insulating portion 82A is located in the first trench narrow portion 30A. The sum of twice the first gate insulating width W3a, which is the dimension of the first gate insulating portion 82A in the Y direction, and the dimension of the first gate electrode 60A in the Y direction corresponds to the first narrow trench width W2a, which is the dimension of the first trench narrow portion 30A in the Y direction.

[0083] First field plate insulating portion 84A is located in first trench wide portion 28A. The sum of twice the first field plate insulating width W4a, which is the dimension in the Y direction of first field plate insulating portion 84A, and the dimension in the Y direction of first field plate electrode 70A corresponds to first wide trench width W1a, which is the dimension in the Y direction of first trench wide portion 28A.

[0084] In the illustrated example, the Y-direction dimension of the first gate electrode 60A and the Y-direction dimension of the first field plate electrode 70A are equal. Therefore, the first gate insulation width W3a is smaller than the first field plate insulation width W4a, and therefore the first narrow trench width W2a is smaller than the first wide trench width W1a. In another example, the Y-direction dimension of the first field plate electrode 70A may be smaller than the Y-direction dimension of the first gate electrode 60A. In this case, the first field plate insulation width W4a can be sufficiently larger than the first gate insulation width W3a so that the first wide trench width W1a is larger than the first narrow trench width W2a.

[0085] The Z-direction dimension of the first gate insulating part 82A is smaller than the Z-direction dimension of the first field plate insulating part 84A. This corresponds to the fact that the Z-direction dimension of the first gate electrode 60A is smaller than the Z-direction dimension of the first field plate electrode 70A.

[0086] The second trench insulation layer 80B is located in the second gate trench 20B. The second trench insulation layer 80B covers the sidewall 24 and bottom wall 26 of the second gate trench 20B. The second trench insulation layer 80B also covers the second gate electrode 60B and the second field plate electrode 70B.

[0087] The second trench insulation layer 80B includes a second gate insulation portion 82B and a second field plate insulation portion 84B. The second gate insulation portion 82B is a portion of the second trench insulation layer 80B that is located between the second gate electrode 60B and the sidewall 24. In particular, the second gate insulation portion 82B is located between the second gate side surface 64B and the second upper sidewall 34B.

[0088] In this embodiment, the dimension of the second gate insulating portion 82B in the Y direction is constant. The second field plate insulating portion 84B is a portion of the second trench insulating layer 80B that is located between the second field plate electrode 70B and the sidewall 24. In particular, the second field plate insulating portion 84B is a portion of the second trench insulating layer 80B that is located between the second field plate side surface 74B and the second lower sidewall 32B. In this embodiment, the dimension of the second field plate insulating portion 84B in the Y direction is constant.

[0089] 3, the Y-direction dimension of second gate insulating portion 82B is smaller than the Y-direction dimension of second field plate insulating portion 84B. Specifically, second gate insulating portion 82B has a Y-direction dimension called second gate insulating width W3b. Second field plate insulating portion 84B has a Y-direction dimension called second field plate insulating width W4b. Second gate insulating width W3b is smaller than second field plate insulating width W4b.

[0090] The second gate insulating portion 82B is located in the second trench narrow portion 30B. The sum of twice the second gate insulating width W3b, which is the dimension in the Y direction of the second gate insulating portion 82B, and the dimension in the Y direction of the second gate electrode 60B is the second narrow trench width W2b, which is the dimension in the Y direction of the second trench narrow portion 30B.

[0091] Second field plate insulating portion 84B is located in second trench wide portion 28B. The sum of twice the second field plate insulating width W4b, which is the dimension in the Y direction of second field plate insulating portion 84B, and the dimension in the Y direction of second field plate electrode 70B is second wide trench width W1b, which is the dimension in the Y direction of second trench wide portion 28B.

[0092] In the illustrated example, the Y-direction dimension of the second gate electrode 60B is equal to the Y-direction dimension of the second field plate electrode 70B. Therefore, the second gate insulation width W3b is smaller than the second field plate insulation width W4b, and therefore the second narrow trench width W2b is smaller than the second wide trench width W1b. In another example, the Y-direction dimension of the second field plate electrode 70B may be smaller than the Y-direction dimension of the second gate electrode 60B. In this case, the second field plate insulation width W4b can be sufficiently larger than the second gate insulation width W3b so that the second wide trench width W1b is larger than the second narrow trench width W2b.

[0093] The Z-direction dimension of the second gate insulating part 82B is smaller than the Z-direction dimension of the second field plate insulating part 84B. This corresponds to the fact that the Z-direction dimension of the second gate electrode 60B is smaller than the Z-direction dimension of the second field plate electrode 70B.

[0094] 2, the interlayer insulating layer 86 is located on the second surface 12G of the semiconductor layer 12. The interlayer insulating layer 86 is in contact with a portion of the second surface 12G. In a plan view, the interlayer insulating layer 86 is provided across the first gate trench 20A, the second gate trench 20B, and a mesa portion 90, which will be described later.

[0095] The trench insulation layers 80 and the interlayer insulation layer 86 may be made of the same material. In one example, the trench insulation layers 80 and the interlayer insulation layer 86 may be made of SiO2. The trench insulation layers 80 and the interlayer insulation layer 86 may be made of different materials.

[0096] (Mesa section explanation) 2, the semiconductor layer 12 includes a mesa portion 90. The mesa portion 90 is defined between the first gate trench 20A and the second gate trench 20B. The mesa portion 90 includes a drift region 50, a body region 52, and a source region 54 located between the first gate trench 20A and the second gate trench 20B.

[0097] The mesa portion 90 includes a wide mesa portion 92 and a narrow mesa portion 94. The narrow mesa portion 94 has a smaller width in the Y direction than the wide mesa portion 92. The wide mesa portion 92 includes a part of the second surface 12G as its upper surface. The narrow mesa portion 94 is located closer to the first surface 12F than the wide mesa portion 92.

[0098] In this embodiment, the dimension of the wide mesa portion 92 in the Y direction is constant in the Z direction. The dimension of the narrow mesa portion 94 in the Y direction is also constant in the Z direction. As shown in FIG. 3, the wide mesa portion 92 has a wide mesa width W5 as its dimension in the Y direction. The narrow mesa portion 94 has a narrow mesa width W6 as its dimension in the Y direction. The wide mesa width W5 is larger than the narrow mesa width W6.

[0099] The dimensions of the wide mesa portion 92 and the narrow mesa portion 94 in the Y direction do not have to be constant in the Z direction. For example, the wide mesa portion 92 may have a tapered structure in the Z direction in which the mesa width W5 decreases toward the first surface 12F. The side surfaces of the wide mesa portion 92 may be partially or entirely curved. The narrow mesa portion 94 may also have a similar tapered structure, and the side surfaces of the narrow mesa portion 94 may be partially or entirely curved.

[0100] 2, the wide mesa portion 92 is located between the first narrow trench portion 30A and the second narrow trench portion 30B. The first narrow trench width W2a and the second narrow trench width W2b are smaller than the first wide trench width W1a and the second wide trench width W1b, respectively, and therefore the wide mesa width W5 can be said to be larger than the narrow mesa width W6.

[0101] The sidewall 24 of the first gate trench 20A and the sidewall 24 of the second gate trench 20B can be said to form the side surface of the mesa portion 90. In particular, the first upper sidewall 34A and the second upper sidewall 34B form the side surface of the mesa wide portion 92. Furthermore, the first lower sidewall 32A and the second lower sidewall 32B form the side surface of the mesa narrow portion 94.

[0102] The wide mesa portion 92 is located between the first gate electrode 60A and the second gate electrode 60B. The wide mesa portion 92 contacts the first gate insulating portion 82A and the second gate insulating portion 82B. As shown in FIG. 3, the first gate insulating width W3a and the second gate insulating width W3b are smaller than the first field plate insulating width W4a and the second field plate insulating width W4b, respectively, and therefore the wide mesa width W5 can be said to be larger than the narrow mesa width W6.

[0103] The mesa wide portion 92 includes the source region 54, the body region 52, and the drift region 50. In other words, the interface between the source region 54 and the body region 52 is located in the mesa wide portion 92. The interface between the body region 52 and the drift region 50 is also located in the mesa wide portion 92.

[0104] The first gate electrode 60A faces the mesa wide portion 92 in the Y direction. Specifically, the first gate side surface 64A faces the body region 52 of the mesa wide portion 92 in the Y direction, with the first gate insulating portion 82A interposed therebetween. The second gate electrode 60B faces the mesa wide portion 92 in the Y direction. Specifically, the second gate side surface 64B faces the body region 52 of the mesa wide portion 92 in the Y direction, with the second gate insulating portion 82B interposed therebetween.

[0105] In this embodiment, the dimensions of the first gate electrode 60A and the second gate electrode 60B in the Z direction are equal to the dimension of the body region 52 of the mesa wide portion 92 in the Z direction. The narrow mesa portion 94 is located between the first trench wide portion 28A and the second trench wide portion 28B. The first wide trench width W1a and the second wide trench width W1b are larger than the first narrow trench width W2a and the second narrow trench width W2b, respectively, and therefore, it can be said that the narrow mesa width W6 is smaller than the wide mesa width W5.

[0106] The narrow mesa portion 94 is located between the first field plate electrode 70A and the second field plate electrode 70B. The narrow mesa portion 94 is in contact with the first field plate insulating portion 84A and the second field plate insulating portion 84B. As shown in FIG. 3, the first field plate insulating width W4a and the second field plate insulating width W4b are larger than the first gate insulating width W3a and the second gate insulating width W3b, respectively, and therefore the narrow mesa width W6 can be said to be smaller than the wide mesa width W5.

[0107] 2, the narrow mesa portion 94 includes the drift region 50. The drift region 50 spans both the wide mesa portion 92 and the narrow mesa portion 94. The first field plate electrode 70A faces the drift region 50 of the narrow mesa portion 94 in the Y direction, with a first field plate insulating portion 84A interposed therebetween. The second field plate electrode 70B faces the drift region 50 of the narrow mesa portion 94 in the Y direction, with a second field plate insulating portion 84B interposed therebetween.

[0108] 3, the first field plate electrode 70A includes an upper portion 76A. The mesa narrow portion 94 faces at least a part of the upper portion 76A of the first field plate electrode 70A in the Y direction. In the present disclosure, the upper portion 76A of the first field plate electrode 70A can be a portion that is closer to the first field plate upper surface 72A than the center of the first field plate electrode 70A in the Z direction.

[0109] The semiconductor device 10 has an improved breakdown voltage due to the mesa portion 90 having a portion with a small dimension in the Y direction (a narrow mesa portion 94). To further improve the breakdown voltage of the semiconductor device 10, it is preferable that the dimension of the narrow mesa portion 94 in the Z direction be large. For example, it is preferable that the narrow mesa portion 94 faces, in the Y direction, at least a portion of a quarter of the first field plate electrode 70A in the Z direction from the first field plate top surface 72A. To further improve the breakdown voltage of the semiconductor device 10, it is more preferable that the narrow mesa portion 94 be provided at a position of the first field plate top surface 72A of the mesa portion 90 in the Z direction, as shown in the example shown. In other words, it is more preferable that the narrow mesa portion 94 faces, in the Y direction, the uppermost end of the first field plate electrode 70A. More preferably, the narrow mesa portion 94 faces, in the Y direction, the entire first field plate side surface 74A of the first field plate electrode 70A. In the mesa portion 90, a mesa wide portion 92 may be provided at the position of the first field plate upper surface 72A in the Z direction.

[0110] 3, the second field plate electrode 70B includes an upper portion 76B. The mesa narrow portion 94 faces at least a part of the upper portion 76B of the second field plate electrode 70B in the Y direction. Note that the upper portion 76B of the second field plate electrode 70B is, for example, a portion that is closer to the second field plate upper surface 72B than the center of the second field plate electrode 70B in the Z direction.

[0111] The semiconductor device 10 has an improved breakdown voltage due to the mesa portion 90 having a portion with a small dimension in the Y direction (a narrow mesa portion 94). To further improve the breakdown voltage of the semiconductor device 10, it is preferable that the dimension of the narrow mesa portion 94 in the Z direction be large. For example, it is preferable that the narrow mesa portion 94 faces, in the Y direction, at least a portion of a quarter of the second field plate electrode 70B from the second field plate top surface 72B in the Z direction. To further improve the breakdown voltage of the semiconductor device 10, it is more preferable that the narrow mesa portion 94 be provided at a position of the second field plate top surface 72B of the mesa portion 90 in the Z direction, as shown in the example shown. In other words, it is more preferable that the narrow mesa portion 94 faces, in the Y direction, the uppermost end of the second field plate electrode 70B. More preferably, the narrow mesa portion 94 faces, in the Y direction, the entire second field plate side surface 74B of the second field plate electrode 70B. In the mesa portion 90, a mesa wide portion 92 may be provided at the position of the second field plate upper surface 72B in the Z direction.

[0112] 2, in the mesa portion 90, a mesa narrow portion 94 is provided at the position of the bottom wall 26 of the first gate trench 20A in the Z direction. In this embodiment, the mesa narrow portion 94 extends in the Z direction from at least the first field plate upper surface 72A to the bottom wall 26 of the first gate trench 20A.

[0113] 3, the mesa portion 90 includes a mesa step portion 96 that connects the wide mesa portion 92 and the narrow mesa portion 94. The mesa step portion 96 is located between the wide mesa portion 92 and the narrow mesa portion 94 in the Z direction. At least a portion of the mesa step portion 96 is located between the contact lower surface 106 and the first field plate upper surface 72A in the Z direction. In this embodiment, the entire mesa step portion 96 is located between the contact lower surface 106 and the first field plate upper surface 72A in the Z direction. The mesa step portion 96 is located in the drift region 50.

[0114] In this embodiment, the mesa step portion 96 includes mesa step surfaces 98. The mesa step surfaces 98 are located on both sides of the mesa portion 90 in the Y direction. In this embodiment, the mesa step surfaces 98 are provided substantially parallel to the first surface 12F of the semiconductor layer 12 (see FIG. 2).

[0115] As described above, the first gate trench 20A and the second gate trench 20B have a stepped structure corresponding to the mesa portion 90 having the mesa step portion 96. The mesa step surface 98 can also be considered to be part of the stepped structure of the first gate trench 20A and the second gate trench 20B. Specifically, the mesa step surface 98 can be considered to connect the first lower sidewall 32A, which is the sidewall of the first trench wide portion 28A, to the first upper sidewall 34A, which is the sidewall of the first trench narrow portion 30A. The mesa step surface 98 can also be considered to connect the second lower sidewall 32B, which is the sidewall of the second trench wide portion 28B, to the second upper sidewall 34B, which is the sidewall of the second trench narrow portion 30B.

[0116] In the illustrated example, the mesa step surface 98 extends flat. However, the mesa step surface 98 does not necessarily have to be flat. The mesa step surface 98 may be partially or entirely curved. The mesa step surface 98 may be curved so that the mesa portion 90 side is convex, or so that the mesa portion 90 side is concave.

[0117] Both ends of the mesa step surface 98 in the X direction are connected approximately perpendicularly to the sidewalls 24 of each gate trench 20. However, both ends of the mesa step surface 98 in the X direction do not have to be connected approximately perpendicularly to the sidewalls 24 of each gate trench 20. Both ends of the mesa step surface 98 in the X direction may be connected to the sidewalls 24 of each gate trench 20 with a constant radius of curvature.

[0118] (Contact Description) 2, the semiconductor device 10 includes a contact trench 100, a source contact plug 42, and a source wiring 18. The contact trench 100 penetrates the insulating layer 14 and reaches the mesa portion 90. The source contact plug 42 is buried in the contact trench 100. The source wiring 18 is located on the insulating layer 14. The source contact plug 42 electrically connects the source wiring 18 and the semiconductor layer 12. The source contact plug 42 and the source wiring 18 may be provided integrally.

[0119] The contact trench 100 penetrates the interlayer insulating layer 86. The contact trench 100 penetrates the source region 54 of the mesa portion 90. The contact trench 100 reaches the body region 52 of the mesa portion 90. That is, the contact trench 100 is located in the interlayer insulating layer 86 and the mesa portion 90. In this embodiment, the contact trench 100 is located in the mesa wide portion 92 of the mesa portion 90. More specifically, the contact trench 100 includes a contact trench bottom wall 102 located in the mesa wide portion 92. The contact trench bottom wall 102 is located in the body region 52.

[0120] In this embodiment, the mesa portion 90 includes a contact region 104 that contacts the contact trench bottom wall 102. The contact region 104 is located in the mesa wide portion 92 of the mesa portion 90. The contact region 104 is located inside the body region 52.

[0121] The contact region 104 is a region of the second conductivity type that contains p-type impurities. The p-type impurity concentration of the contact region 104 is higher than the p-type impurity concentration of the body region 52. The p-type impurity concentration of the contact region 104 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 It may be the following:

[0122] The source contact plug 42 is located in the mesa portion 90. The source contact plug 42 is buried in the contact trench 100. It can also be said that the source contact plug 42 penetrates the insulating layer 14 and the source region 54 and reaches the body region 52. The source contact plug 42 is located in the mesa wide portion 92, corresponding to the contact trench 100 being located in the mesa wide portion 92. The source contact plug 42 is in contact with the mesa wide portion 92.

[0123] The source contact plug 42 includes a lower contact surface 106 that forms a lower end surface in the Z direction. The lower contact surface 106 is in contact with the semiconductor layer 12. In this embodiment, the source contact plug 42 is in contact with the contact region 104. Specifically, the lower contact surface 106 is in contact with the contact trench bottom wall 102 and also with the contact region 104. The contact region 104 may be in contact with a side surface of the source contact plug 42.

[0124] As shown in FIG. 3, the mesa portion 90 has a first width Wf as a dimension in the Y direction at the position of the contact lower surface 106 in the Z direction. The mesa portion 90 also has a second width Ws as a dimension in the Y direction at the position of the first field plate upper surface 72A in the Z direction. The second width Ws is smaller than the first width Wf. In the illustrated example, the first width Wf is equal to the wide mesa width W5. The second width Ws is equal to the narrow mesa width W6. The first width Wf may be different from the wide mesa width W5. The second width Ws may be different from the narrow mesa width W6.

[0125] Mesa step surface 98 is located between contact lower surface 106 and first field plate upper surface 72A in the Z direction. Because mesa step surface 98 is located between contact lower surface 106 and first field plate upper surface 72A, it can be said that contact lower surface 106 is located at mesa wide portion 92, and that mesa narrow portion 94 is located at the position of first field plate upper surface 72A of mesa portion 90 in the Z direction.

[0126] The source contact plug 42 has a contact width Wc as a dimension in the Y direction. The contact width Wc can also be said to be the dimension of the contact trench 100 in the Y direction. The contact width Wc is smaller than the wide mesa width W5. In this embodiment, the contact width Wc is smaller than the narrow mesa width W6.

[0127] When aligning the source contact plug 42 with the semiconductor layer 12 (mesa portion 90), manufacturing variations (misalignment) may occur in the Y-direction position of the source contact plug 42. In this case, the difference in the Y-direction dimensions between the mesa wide portion 92 and the source contact plug 42 is the margin width Wm for misalignment of the source contact plug 42 in the Y direction.

[0128] Specifically, the margin width Wm is the difference between the contact width Wc and the wide mesa width W5. More specifically, the margin width Wm is the sum of the distance Wm1 in the Y direction between the source contact plug 42 and the first upper sidewall 34A and the distance Wm2 in the Y direction between the source contact plug 42 and the second upper sidewall 34B. The larger the margin width Wm, the wider the tolerance for misalignment in the Y direction when aligning the source contact plug 42 and the semiconductor layer 12.

[0129] 2, the source wiring 18 is provided on the semiconductor layer 12. The source wiring 18 is provided on the interlayer insulating layer 86 in contact with the interlayer insulating layer 86. The source wiring 18 straddles the source region 54 and the first and second gate trenches 20A and 20B.

[0130] The source wiring 18 and the source contact plug 42 may be made of different materials. The source wiring 18 may be made of, for example, a metal with a relatively low resistance. In one example, the source wiring 18 may be made of a material containing Al. The materials that make up the source contact plug 42 and the source wiring 18 are not limited to those mentioned above.

[0131] The source contact plug 42 may be made of a material containing a metal that is relatively easy to fill in the contact trench 100. For example, the source contact plug 42 may be made of a material containing tungsten (W). The source contact plug 42 and the source wiring 18 may be made of the same material.

[0132] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 10 will be described. Figures 4 to 19 are schematic cross-sectional views showing exemplary manufacturing steps for the semiconductor device 10. For ease of understanding, in Figures 4 to 19, components similar to those in Figure 2 are denoted by the same reference numerals.

[0133] As shown in FIG. 4 , the method for manufacturing the semiconductor device 10 includes forming a semiconductor layer 12 having a first surface 12F and a second surface 12G opposite the first surface 12F. Forming the semiconductor layer 12 may include forming an epitaxial layer 302 on a semiconductor substrate 300. In one example, the semiconductor substrate 300 may be a Si substrate containing n-type impurities. The epitaxial layer 302 may be an n-type Si layer epitaxially grown on the semiconductor substrate 300 while doping it with n-type impurities. The semiconductor layer 12 includes the first surface 12F and a second surface 12G opposite the first surface 12F. The semiconductor substrate 300 may include the second surface 12G of the semiconductor layer 12, and the epitaxial layer 302 may include the first surface 12F of the semiconductor layer 12.

[0134] 5 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 5. As shown in FIG. 5, the manufacturing method of the semiconductor device 10 includes forming a plurality of gate trenches 20 extending from the second surface 12G into the semiconductor layer 12 and having sidewalls 24. The plurality of gate trenches 20 can be formed by selectively removing (e.g., etching) a portion of the epitaxial layer 302. Each gate trench 20 includes a bottom wall 26. A mesa portion 90 is defined between the plurality of gate trenches 20. Forming the plurality of gate trenches 20 includes forming the mesa portion 90 defined between the gate trenches 20.

[0135] 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 6. As shown in FIG. 6, the manufacturing method of the semiconductor device 10 includes forming a first insulating layer 304 in the gate trench 20. The formation of the first insulating layer 304 may include a step of removing excess portions of the insulating layer on the second surface 12G of the semiconductor layer 12 and in the gate trench 20. In one example, the first insulating layer 304 may include SiO formed by thermal oxidation. In another example, the first insulating layer 304 may be formed by chemical vapor deposition (CVD).

[0136] 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 7 , the manufacturing method of the semiconductor device 10 includes forming a protective insulating layer 306 that covers a portion of the sidewall 24 of the gate trench 20. The protective insulating layer 306 is formed on the first insulating layer 304. Forming the protective insulating layer 306 may include forming an insulating layer (not shown) that fills the gate trench 20 on the first insulating layer 304, and removing a portion of the insulating layer. In the step of removing the portion of the insulating layer that fills the gate trench 20, a portion of the first insulating layer 304 may also be removed.

[0137] The protective insulating layer 306 may be made of a material that can be selectively etched from the first insulating layer 304. For example, the protective insulating layer 306 may be made of a material including silicon nitride (SiN). For example, the protective insulating layer 306 may be formed by a CVD method.

[0138] 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 8. As shown in FIG. 8, the manufacturing method for the semiconductor device 10 includes removing the first insulating layer 304 (see FIG. 7). By selectively etching the first insulating layer 304, the protective insulating layer 306 remains covering a portion of the sidewall 24 of the gate trench 20. This exposes the bottom wall 26 of the gate trench 20 and the portion of the sidewall 24 that was covered by the first insulating layer 304.

[0139] 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 9. As shown in FIG. 9, the manufacturing method of the semiconductor device 10 includes forming a second insulating layer 308 on the bottom wall 26 and the portion of the sidewall 24 exposed from the protective insulating layer 306. The second insulating layer 308 is an oxide film made of an oxide of the semiconductor layer 12. The second insulating layer 308 is formed by a thermal oxidation method. By the thermal oxidation, a portion of the semiconductor layer 12 is oxidized from the sidewall 24 of the gate trench 20 and transformed into an insulator, thereby forming the second insulating layer 308. In conjunction with the formation of the second insulating layer 308, a third insulating layer 310 may be formed on the second surface 12G.

[0140] It can be said that the formation of the second insulating layer 308 increases the dimension in the Y direction and the depth dimension in the Z direction of the gate trench 20. It can also be said that forming the second insulating layer 308 includes forming the mesa wide portion 92 and the mesa narrow portion 94, which has a dimension smaller than that of the mesa wide portion 92, in the mesa portion 90.

[0141] 9. As shown in FIG. 10, the method for manufacturing the semiconductor device 10 includes forming a first conductor 312 in the gate trench 20. The first conductor 312 is formed in the gate trench 20 so as to be in contact with the second insulating layer 308 and the protective insulating layer 306. The first conductor 312 may be made of a conductive material. In one example, the first conductor 312 is made of a material including polysilicon.

[0142] 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10. As shown in FIG. 11, the manufacturing method for the semiconductor device 10 includes removing a portion of the first conductor 312 and the protective insulating layer 306 (see FIG. 10). The portion of the first conductor 312 and the protective insulating layer 306 are removed by selective etching. This exposes the portion of the sidewall 24 of the gate trench 20 that was covered with the protective insulating layer 306. In the illustrated example, the first conductor 312 is etched so that its upper portion protrudes from the surface of the second insulating layer 308.

[0143] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11 . As shown in FIG. 12 , the manufacturing method of the semiconductor device 10 includes forming a field plate electrode 70 in the gate trench 20. The field plate electrode 70 is formed by forming a fourth insulating layer 314 that covers the exposed portion of the first conductor 312 (see FIG. 11 ). The fourth insulating layer 314 is formed by thermal oxidation. The thermal oxidation oxidizes a portion of the first conductor 312 and the exposed portion of the sidewall 24 of the gate trench 20, thereby transforming the first conductor 312 and the semiconductor layer 12 to form the fourth insulating layer 314. A portion of the fourth insulating layer 314 is integrated with the second insulating layer 308. The Y-direction dimension of the portion of the fourth insulating layer 314 that covers the sidewall 24 is formed smaller than the Y-direction dimension of the portion of the third insulating layer 310 that covers the sidewall 24. The fourth insulating layer 314 may also be formed on the second surface 12G. The fourth insulating layer 314 may be integral with the third insulating layer 310 (see FIG. 11).

[0144] 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 13. As shown in FIG. 13, the manufacturing method of the semiconductor device 10 includes forming a gate electrode 60 separated from the field plate electrode 70 in the gate trench 20. Forming the gate electrode 60 may include forming a second conductor (not shown) on the semiconductor layer 12 and in the gate trench 20 and removing an excess portion. The gate electrode 60 may be made of a conductive material. In one example, the gate electrode 60 may be made of a material including polysilicon.

[0145] 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 13. As shown in FIG. 14, the manufacturing method of semiconductor device 10 includes forming a drift region 50 in semiconductor layer 12. A p-type region 316 and drift region 50 are formed in epitaxial layer 302 (see FIG. 13) of semiconductor layer 12. In detail, p-type impurities are implanted from the surface (second surface 12G of semiconductor layer 12) of epitaxial layer 302, which is an n-type Si layer, by ion implantation using an ion implantation mask (not shown), thereby forming p-type region 316 in a surface portion of epitaxial layer 302. The remaining portion of epitaxial layer 302 becomes n-type drift region 50. The ion implantation for forming p-type region 316 may be performed in multiple stages with different acceleration energies.

[0146] 14. As shown in FIG. 15, the manufacturing method of the semiconductor device 10 includes forming a body region 52 on the drift region 50. A source region 54 and a body region 52 are formed in the p-type region 316 (see FIG. 14) of the semiconductor layer 12. Specifically, n-type impurities are implanted from the surface of the p-type region 316 (the second surface 12G of the semiconductor layer 12) by ion implantation using an ion implantation mask (not shown), thereby forming an n-type source region 54 in a surface portion of the p-type region 316. The remaining portion of the p-type region 316 becomes the p-type body region 52. The semiconductor substrate 300 corresponds to the drain region 48 in FIG. 2.

[0147] 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 16, the manufacturing method of the semiconductor device 10 includes forming an interlayer insulating layer 86 on the semiconductor layer 12. A portion of the interlayer insulating layer 86 is integrated with the fourth insulating layer 314. In one example, the interlayer insulating layer 86 may include SiO formed by thermal oxidation. In another example, the interlayer insulating layer 86 may be formed by CVD.

[0148] Fig. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 16. As shown in Fig. 17, the manufacturing method of the semiconductor device 10 includes forming a contact trench 100 that penetrates the interlayer insulating layer 86. The contact trench 100 penetrates the interlayer insulating layer 86 and reaches the body region 52. The contact trench 100 is formed in the mesa wide portion 92.

[0149] The contact region 104 may be formed in conjunction with the formation of the contact trench 100. The contact region 104 is formed by implanting p-type impurities into the body region 52 from the contact trench 100.

[0150] 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 17. As shown in FIG. 18, the manufacturing method of the semiconductor device 10 includes forming a source contact plug 42 to fill the contact trench 100. Forming the source contact plug 42 may include forming a third conductor (not shown) in the contact trench 100 and on the interlayer insulating layer 86 and removing an excess portion. The source contact plug 42 may be made of a conductive material. The source contact plug 42 may be made of a material suitable for filling the contact trench 100. In one example, the source contact plug 42 may be made of a material including tungsten (W).

[0151] FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 18. As shown in FIG. 19, the manufacturing method of the semiconductor device 10 includes forming a source wiring 18 on the semiconductor layer 12. The source wiring 18 is formed on and in contact with the interlayer insulating layer 86. The source wiring 18 is formed in contact with the source contact plug 42. The source wiring 18 is made of a conductive material. The source wiring 18 may be made of a material with low resistance. In one example, the source wiring 18 may be made of a material containing Al. The source wiring 18 may be made of the same material as the source contact plug 42. The source wiring 18 may be formed integrally with the source contact plug 42. Through the above steps, the semiconductor device 10 is manufactured.

[0152] (Function of Semiconductor Device) The operation of the semiconductor device 10 will now be described. The semiconductor device 10 includes a semiconductor layer 12 having a first surface 12F and a second surface 12G opposite the first surface 12F, a first gate trench 20A and a second gate trench 20B extending from the second surface 12G into the semiconductor layer 12 and having sidewalls 24 and a bottom wall 26, an insulating layer 14 located on the semiconductor layer 12, a first gate electrode 60A located in the first gate trench 20A, a first field plate electrode 70A located in the first gate trench 20A and closer to the bottom wall 26 than the first gate electrode 60A in a depth direction perpendicular to the first surface 12F and including a first field plate upper surface 72A facing the first gate electrode 60A via the insulating layer 14, and a source contact plug 42 penetrating the insulating layer 14 and including a contact lower surface 106 in contact with the semiconductor layer 12. The semiconductor layer 12 includes a mesa portion 90 defined between the first gate trench 20A and the second gate trench 20B.

[0153] In the semiconductor device 10, when a predetermined voltage (for example, the same voltage as that of the source wiring 18) is applied to the field plate electrode 70, a depletion layer spreads in the semiconductor layer 12. This depletion layer can improve the breakdown voltage of the semiconductor device 10.

[0154] The depletion layer extends from the first gate trench 20A and the second gate trench 20B to the mesa portion 90. Therefore, the smaller the dimension of the mesa portion 90 in the Y direction, the more easily the depletion layer is formed to connect both gate trenches 20A and 20B. The depletion layer extends continuously between both gate trenches 20A and 20B, improving the breakdown voltage. Furthermore, since the depletion layer is more easily connected, it is possible to increase the impurity concentration in the semiconductor layer 12 (e.g., the drift region 50) and reduce the on-resistance, while maintaining the breakdown voltage of the semiconductor device 10.

[0155] On the other hand, when the dimension of the mesa portion 90 in the Y direction is small, the precision of alignment between the semiconductor layer 12 and the source contact plug 42, which is required to provide the source contact plug 42 in the mesa portion 90, becomes high. In particular, when the dimension of the mesa portion 90 in the Y direction is small, the margin width Wm, which is the difference between the dimension of the mesa portion 90 in the Y direction and the contact width Wc, which is the dimension of the source contact plug 42 in the Y direction, becomes small. This increases the precision of alignment required to provide the source contact plug 42.

[0156] In this embodiment, the mesa portion 90 includes a wide mesa portion 92 that includes a portion of the second surface 12G as its upper surface, and a narrow mesa portion 94 that has a smaller dimension in the second direction than the wide mesa portion 92. The narrow mesa portion 94 faces at least a portion of the upper portion 76A of the first field plate electrode 70A in the second direction. This facilitates connection between the depletion layer extending from the first gate trench 20A and the depletion layer extending from the second gate trench 20B in the narrow mesa portion 94. This improves the breakdown voltage of the semiconductor device 10.

[0157] Furthermore, the source contact plug 42 is in contact with the mesa wide portion 92. As a result, the mesa portion 90 has a larger dimension in the Y direction at the portion in contact with the source contact plug 42, even though it has a narrow mesa portion 94. The larger dimension in the Y direction at the portion in contact with the source contact plug 42 increases the margin width Wm. Therefore, compared to when the entire dimension of the mesa portion 90 in the Y direction is narrow, the accuracy of alignment between the semiconductor layer 12 and the source contact plug 42 can be relaxed while maintaining improved breakdown voltage and reduced on-resistance.

[0158] (Effects of the embodiment) The semiconductor device 10 of this embodiment has the following advantages. (1) The semiconductor layer 12 includes a mesa portion 90 defined between the first gate trench 20A and the second gate trench 20B. The mesa portion 90 includes a wide mesa portion 92 that includes a portion of the second surface 12G as its upper surface, and a narrow mesa portion 94 that has a smaller dimension in the Y direction than the wide mesa portion 92. The source contact plug 42 is in contact with the wide mesa portion 92. The wide mesa portion 92 faces at least a portion of the upper portion 76A of the first field plate electrode 70A in the Y direction.

[0159] According to this configuration, the depletion layer extending from the first gate trench 20A and the depletion layer extending from the second gate trench 20B are more likely to connect in the narrow mesa portion 94. This improves the breakdown voltage of the semiconductor device 10. The increased connection of the depletion layers makes it possible to increase the impurity concentration of the semiconductor layer 12, thereby reducing the on-resistance, while maintaining the breakdown voltage of the semiconductor device 10. Additionally, the wide mesa portion 92 increases the width of the portion of the mesa portion 90 that contacts the source contact plug 42. This reduces the precision required for aligning the semiconductor layer 12 and the source contact plug 42. This improves the breakdown voltage and reduces the on-resistance of the semiconductor device 10, while also reducing the precision required for aligning the semiconductor layer 12 and the source contact plug 42.

[0160] (2) Mesa portion 90 has a first width Wf at the position of contact lower surface 106 in the depth direction. Mesa portion 90 has a second width Ws that is smaller than first width Wf at the position of first field plate upper surface 72A in the depth direction.

[0161] With this configuration, the Y-direction dimension of mesa portion 90 at contact lower surface 106 is greater than the Y-direction dimension of mesa portion 90 at first field plate upper surface 72A. This allows the Z-direction depth dimension of mesa narrow portion 94 to be increased while ensuring margin width Wm. Therefore, depletion layers are more likely to connect over a wider range of semiconductor layer 12 (e.g., drift region 50) in the Z direction, further improving the breakdown voltage of semiconductor device 10.

[0162] (3) The mesa narrow portion 94 extends in the depth direction at least from the first field plate upper surface 72A to the bottom wall 26 of the first gate trench 20A. According to this configuration, mesa narrow portion 94 is provided long in the depth direction from first field plate upper surface 72A to bottom wall 26. This further improves the breakdown voltage of semiconductor device 10.

[0163] (4) The mesa portion 90 includes a mesa step portion 96 that connects the wide mesa portion 92 and the narrow mesa portion 94 . With this configuration, it is easier to increase the depth dimension of the narrow mesa portion 94 in the Z direction compared to when the wide mesa portion 92 and the narrow mesa portion 94 are smoothly formed without any boundary between them, thereby further improving the breakdown voltage of the semiconductor device 10.

[0164] (5) At least a portion of mesa step portion 96 is located between contact lower surface 106 and first field plate upper surface 72A in the depth direction. This configuration allows the depth dimension of the mesa narrow portion 94 in the Z direction to be increased while ensuring a margin width Wm for providing the source contact plug 42. Therefore, the breakdown voltage of the semiconductor device 10 is further improved.

[0165] (6) The first gate electrode 60A faces the mesa wide portion 92 in the Y direction. The first field plate electrode 70A faces the mesa narrow portion 94 in the Y direction. With this configuration, the first gate electrode 60A can form a channel in the mesa wide portion 92. Furthermore, the first field plate electrode 70A facilitates the expansion of the depletion layer that spreads in the mesa narrow portion 94. This further improves the breakdown voltage of the semiconductor device 10.

[0166] (7) The semiconductor device 10 includes a second gate electrode 60B and a second field plate electrode 70B. The second gate electrode 60B is located in the second gate trench 20B. The second field plate electrode 70B is located in the second gate trench 20B, is located closer to the bottom wall 26 than the second gate electrode 60B in the depth direction, and faces the second gate electrode 60B with the insulating layer 14 interposed therebetween.

[0167] According to this configuration, when a voltage is applied to the second gate electrode 60B, a channel is also formed in the portion of the mesa portion 90 closer to the second gate trench 20B. This reduces the on-resistance compared to a configuration in which trenches with gate electrodes provided therein are not provided on both sides of the mesa portion 90.

[0168] (8) The wide mesa portion 92 is located between the first gate electrode 60A and the second gate electrode 60B. The narrow mesa portion 94 is located between the first field plate electrode 70A and the second field plate electrode 70B.

[0169] With this configuration, when a predetermined voltage is applied to the first gate electrode 60A and the second gate electrode 60B, channels are formed in both the portion of the mesa wide portion 92 adjacent to the first gate trench 20A and the portion adjacent to the second gate trench 20B. This reduces the on-resistance compared to a configuration in which trenches with gate electrodes provided therein are not provided on both sides of the mesa portion 90. Furthermore, the depletion layer spreads to the mesa narrow portion 94 due to both the first field plate electrode 70A and the second field plate electrode 70B. This makes it easier for the depletion layers to connect. This further improves the breakdown voltage of the semiconductor device 10.

[0170] (9) The dimension of the first gate electrode 60A in the Y direction is equal to the dimension of the first field plate electrode 70A in the Y direction. With this configuration, it is easier to reduce the Y-direction dimension of the portion of the first gate trench 20A where the first gate electrode 60A is located, compared to when the Y-direction dimension of the first gate electrode 60A is larger than the Y-direction dimension of the first field plate electrode 70A. Furthermore, since the Y-direction dimension of the first gate electrode 60A is relatively small, it is possible to prevent the first gate electrode 60A from becoming highly resistant.

[0171] (10) The mesa portion 90 includes a mesa step portion 96 that connects the wide mesa portion 92 and the narrow mesa portion 94. The mesa step portion 96 is located in the drift region 50. According to this configuration, the body region 52 located on the drift region 50 is entirely located in the mesa wide portion 92. This allows the body region 52 to form a channel without being affected by the mesa step portion 96. Furthermore, since the mesa portion 90 includes the mesa step portion 96, it is easier to increase the depth dimension of the mesa narrow portion 94 in the Z direction. This further improves the breakdown voltage of the semiconductor device 10.

[0172] (11) The mesa portion 90 further includes a second conductivity type contact region 104 in the mesa wide portion 92. The contact region 104 is in contact with the source contact plug 42. According to this configuration, when an excessive current occurs in the source contact plug 42, the excessive current can be released through the contact region 104. Furthermore, since the contact region 104, which contacts the source contact plug 42, is provided in the mesa wide portion 92, a sufficient margin width Wm can be ensured.

[0173] (12) The first gate trench 20A includes a first trench wide portion 28A that includes the bottom wall 26 and a portion of the sidewall 24, and a first trench narrow portion 30A that has a smaller width in the Y direction than the first trench wide portion 28A. The first gate electrode 60A is located in the first trench narrow portion 30A, and the first field plate electrode 70A is located in the first trench wide portion 28A.

[0174] According to this configuration, the first trench wide portion 28A is provided at a position corresponding in depth to the position of the first field plate electrode 70A. The first trench narrow portion 30A is provided at a position corresponding in depth to the position of the first gate electrode 60A. This relatively increases the distance between the first field plate electrode 70A and the sidewall 24, improving the breakdown voltage of the semiconductor device.

[0175] (13) The second gate trench 20B includes a second trench wide portion 28B that includes the bottom wall 26 and a portion of the sidewall 24, and a second trench narrow portion 30B that has a smaller dimension in the Y direction than the second trench wide portion 28B. The mesa wide portion 92 is located between the first trench narrow portion 30A and the second trench narrow portion 30B. The mesa narrow portion 94 is located between the first trench wide portion 28A and the second trench wide portion 28B.

[0176] According to this configuration, the mesa wide portion 92 has a larger dimension in the Y direction than when the second gate trench 20B does not have the second trench narrow portion 30B. This further relaxes the precision required for aligning the semiconductor layer 12 with the source contact plug 42. Furthermore, the mesa narrow portion 94 has a relatively smaller dimension in the Y direction than when the second gate trench 20B does not have the second trench wide portion 28B. This further improves the breakdown voltage of the semiconductor device.

[0177] (14) The first field plate electrode 70A includes a first field plate side surface 74A. The first gate electrode 60A includes a first gate side surface 64A. The first field plate insulating portion 84A is located between the first field plate side surface 74A and the sidewall 24. The first gate insulating portion 82A is located between the first gate side surface 64A and the sidewall 24. The dimension in the Y direction of the first gate insulating portion 82A is smaller than the dimension in the Y direction of the first field plate insulating portion 84A.

[0178] With this configuration, the first field plate electrode 70A is in contact with the first field plate insulating portion 84A, which has a relatively large width. This increases the effect of widening the depletion layer, thereby further improving the breakdown voltage of the semiconductor device 10.

[0179] (15) The dimension of the first gate insulating portion 82A in the Y direction is constant, and the dimension of the first field plate insulating portion 84A in the Y direction is constant. According to this configuration, the entire first field plate electrode 70A is in contact with the first field plate insulating portion 84A, which has a relatively large width, which makes it easier for the depletion layer to expand and further improves the breakdown voltage.

[0180] (16) The first gate trench 20A includes a first trench wide portion 28A that includes the bottom wall 26 and a portion of the sidewall 24, and a first trench narrow portion 30A that has a smaller dimension in the Y direction than the first trench wide portion 28A. The first field plate insulating portion 84A is located in the first trench wide portion 28A, and the first gate insulating portion 82A is located in the first trench narrow portion 30A.

[0181] With this configuration, the dimension of the first field plate insulating portion 84A in the Y direction tends to be relatively large, thereby improving the breakdown voltage of the semiconductor device. [Example of gate trench and mesa modification] An exemplary semiconductor device 200 according to a modified example will be described with reference to Fig. 20. Fig. 20 is a schematic cross-sectional view of the semiconductor device 200. For ease of understanding, the same components in Fig. 20 as those in Fig. 2 are denoted by the same reference numerals.

[0182] 2, the semiconductor device 200 in Fig. 20 differs from the semiconductor device 10 in Fig. 2 in the shapes of the first gate trench 20A and the second gate trench 20B and the shape of the mesa portion 90. Further, detailed description of components similar to those of the semiconductor device 10 will be omitted.

[0183] 20 , the semiconductor device 200 differs from the semiconductor device 10 in that the mesa step surface 98 is inclined with respect to the first surface 12F. Accordingly, the first gate trench 20A includes a first trench intermediate portion 202A. The second gate trench 20B includes a second trench intermediate portion 202B. The mesa portion 90 also includes a mesa intermediate portion 204. Specifically, the mesa step portion 96 of the mesa portion 90 includes the mesa intermediate portion 204.

[0184] The first trench intermediate portion 202A is located between the first trench wide portion 28A and the first trench narrow portion 30A in the Z direction. The first trench intermediate portion 202A connects the first trench wide portion 28A and the first trench narrow portion 30A. The first trench intermediate portion 202A has a tapered structure in which the cross-sectional area in the Z direction decreases from the first trench wide portion 28A toward the first trench narrow portion 30A.

[0185] The second trench intermediate portion 202B is located between the second trench wide portion 28B and the second trench narrow portion 30B in the Z direction. The second trench intermediate portion 202B connects the second trench wide portion 28B and the second trench narrow portion 30B. The second trench intermediate portion 202B has a tapered structure in which the cross-sectional area in the Z direction decreases from the second trench wide portion 28B toward the second trench narrow portion 30B.

[0186] The mesa step portion 96 of the mesa portion 90 includes a mesa step surface 98 and a mesa intermediate portion 204. The mesa step surface 98 is inclined at an angle θ from a state parallel to the first surface 12F. Because the mesa step surface 98 is inclined, it can be said that the semiconductor device 200 includes a first trench intermediate portion 202A, a second trench intermediate portion 202B, and a mesa intermediate portion 204.

[0187] In the illustrated example, the mesa step surface 98 extends linearly. However, the mesa step surface 98 does not necessarily have to be linear. The mesa step surface 98 may be partially or entirely curved. The mesa step surface 98 may be curved so that the mesa side is convex, or so that the mesa side is concave.

[0188] The mesa intermediate portion 204 is located between the mesa wide portion 92 and the mesa narrow portion 94 in the Z direction. The mesa intermediate portion 204 connects the mesa wide portion 92 and the mesa narrow portion 94. The mesa intermediate portion 204 is located between the mesa step faces 98. The mesa intermediate portion 204 is located between the first trench intermediate portion 202A and the second trench intermediate portion 202B. The mesa intermediate portion 204 may also be formed by the drift region 50.

[0189] In the semiconductor device 200, the mesa step surface 98 is inclined, so that the electric field concentration in the vicinity of the mesa step portion 96 can be alleviated. [Example of change] This embodiment can be modified as follows: This embodiment and the following modifications can be combined and implemented within the scope of technical compatibility.

[0190] The relationship between the first width Wf of the mesa portion 90 at the position of the contact lower surface 106 in the depth direction and the second width Ws at the position of the first field plate upper surface 72A in the depth direction can be changed as desired. The first width Wf and the second width Ws may be equal. Alternatively, the second width Ws may be greater than the first width Wf.

[0191] The length of the narrow mesa portion 94 in the depth direction can be changed as desired. The narrow mesa portion 94 does not have to extend in the depth direction from the upper surface 72A of the first field plate to the bottom wall 26 of the first gate trench 20A. At a position closer to the first surface 12F of the mesa portion 90, the dimension in the Y direction may be larger than the wide mesa width W5.

[0192] The position of the mesa step 96 in the depth direction can be changed as desired. The mesa step 96 does not have to be located between the contact lower surface 106 and the first field plate upper surface 72A in the depth direction. The mesa step 96 may be flush with the first field plate upper surface 72A. The mesa step 96 may be located closer to the first surface 12F than the first field plate upper surface 72A.

[0193] The configuration inside the second gate trench 20B can be changed as desired. The semiconductor device 10 does not have to include the second gate electrode 60B. The semiconductor device 10 does not have to include the second field plate electrode 70B. The second gate trench 20B may include only one of the second gate electrode 60B and the second field plate electrode 70B.

[0194] The dimensions in the second direction of the first gate electrode 60A and the first field plate electrode 70A can be changed as desired. The dimension in the second direction of the first gate electrode 60A does not have to be equal to the dimension in the second direction of the first field plate electrode 70A. The dimension in the second direction of the first gate electrode 60A may be larger or smaller than the dimension in the second direction of the first field plate electrode 70A.

[0195] The mesa portion 90 does not necessarily have to include the second conductivity type contact region 104. The dimension of the first gate insulating portion 82A in the second direction does not have to be constant. The dimension of the first field plate insulating portion 84A in the second direction does not have to be constant.

[0196] The first field plate insulating portion 84A does not have to be located in the first trench wide portion 28A. A part of the first field plate insulating portion 84A may be located in the first trench narrow portion 30A.

[0197] In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the opposite may be true. In other words, the drain region 48, drift region 50, and source region 54 of the first conductivity type may contain p-type impurities, and the body region 52 and contact region 104 of the second conductivity type may contain n-type impurities.

[0198] As used in this disclosure, the term "on" includes the meanings "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0199] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 2) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0200] [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0201] (Appendix 1) a semiconductor layer (12) having a first surface (12F) and a second surface (12G) opposite to the first surface (12F); a first gate trench (20A) and a second gate trench (20B) extending from the second surface (12G) into the semiconductor layer (12) and having sidewalls (24) and a bottom wall (26); an insulating layer (14) located on the semiconductor layer (12); a first gate electrode (60A) located in the first gate trench (20A); a first field plate electrode (70A) located in the first gate trench (20A), positioned closer to the bottom wall (26) than the first gate electrode (60A) in a depth direction (Z) perpendicular to the first surface (12F), and including a first field plate upper surface (72A) facing the first gate electrode (60A) via the insulating layer (14); a source contact plug (42) that penetrates the insulating layer (14) and includes a contact lower surface (106) that contacts the semiconductor layer (12); Equipped with each of the first gate trench (20A) and the second gate trench (20B) extends in a first direction (X) in a plan view and is spaced apart from each other in a second direction (Y) perpendicular to the first direction (X) in a plan view; the semiconductor layer (12) includes a mesa portion (90) defined between the first gate trench (20A) and the second gate trench (20B); The mesa portion (90) is a mesa wide portion (92) including a part of the second surface (12G) as an upper surface; a mesa narrow portion (94) having a dimension in the second direction (Y) smaller than that of the mesa wide portion (92), The source contact plug (42) is in contact with the mesa wide portion (92), the mesa narrow portion (94) faces at least a part of an upper portion (76A) of the first field plate electrode (70A) in the second direction (Y); A semiconductor device (10).

[0202] (Appendix 2) the upper portion (76A) of the first field plate electrode (70A) is a portion closer to the first field plate upper surface (72A) than to the center of the first field plate electrode (70A) in the depth direction (Z). The semiconductor device (10) according to appendix 1.

[0203] (Appendix 3) the mesa portion (90) has a first width (Wf) at the position of the contact lower surface (106) in the depth direction (Z), and has a second width (Ws) smaller than the first width (Wf) at the position of the first field plate upper surface (72A) in the depth direction (Z). The semiconductor device (10) according to appendix 1 or 2.

[0204] (Appendix 4) the mesa narrow portion (94) extends in the depth direction (Z) at least from the upper surface (72A) of the first field plate to the bottom wall (26) of the first gate trench (20A); A semiconductor device (10) according to any one of appendices 1 to 3.

[0205] (Appendix 5) The mesa portion (90) includes a mesa step portion (96) connecting the mesa wide portion (92) and the mesa narrow portion (94). A semiconductor device (10) according to any one of appendices 1 to 4.

[0206] (Appendix 6) At least a portion of the mesa step portion (96) is located between the contact lower surface (106) and the first field plate upper surface (72A) in the depth direction (Z). The semiconductor device (10) according to appendix 5.

[0207] (Appendix 7) the first gate electrode (60A) faces the mesa wide portion (92) in the second direction (Y); the first field plate electrode (70A) faces the mesa narrow portion (94) in the second direction (Y); A semiconductor device (10) according to any one of appendices 1 to 6.

[0208] (Appendix 8) The semiconductor device (10) includes a second gate electrode (60B) located in the second gate trench (20B); a second field plate electrode (70B) located in the second gate trench (20B), positioned closer to the bottom wall (26) than the second gate electrode (60B) in the depth direction (Z), and facing the second gate electrode (60B) via the insulating layer (14), A semiconductor device (10) according to any one of appendices 1 to 7.

[0209] (Appendix 9) the mesa wide portion (92) is located between the first gate electrode (60A) and the second gate electrode (60B), The mesa narrow portion (94) is located between the first field plate electrode (70A) and the second field plate electrode (70B). The semiconductor device (10) according to appendix 8.

[0210] (Appendix 10) the dimension of the first gate electrode (60A) in the second direction (Y) is equal to the dimension of the first field plate electrode (70A) in the second direction (Y); A semiconductor device (10) according to any one of appendices 1 to 9.

[0211] (Appendix 11) The mesa portion (90) includes a drift region (50) of a first conductivity type, a body region (52) of a second conductivity type located on the drift region (50), and a source region (54) of the first conductivity type located on the body region (52). A semiconductor device (10) according to any one of appendices 1 to 10.

[0212] (Appendix 12) the mesa wide portion (92) includes the source region (54), the body region (52), and the drift region (50); 12. The semiconductor device (10) according to claim 11.

[0213] (Appendix 13) The mesa portion (90) includes a mesa step portion (96) connecting the mesa wide portion (92) and the mesa narrow portion (94), The mesa step portion (96) is located in the drift region (50). 12. The semiconductor device (10) according to claim 11.

[0214] (Appendix 14) The mesa portion (90) further includes a second conductivity type contact region (104) in the mesa wide portion (92), The contact region (104) is in contact with the source contact plug (42). 12. The semiconductor device (10) according to claim 11.

[0215] (Appendix 15) The first gate trench (20A) is a first trench wide portion (28A) including the bottom wall (26) and a portion of the side wall (24); a first trench narrow portion (30A) having a dimension in the second direction (Y) smaller than that of the first trench wide portion (28A), the first gate electrode (60A) is located in the first trench narrow portion (30A), the first field plate electrode (70A) is located in the first trench wide portion (28A); A semiconductor device (10) according to any one of appendices 1 to 14.

[0216] (Appendix 16) The second gate trench (20B) is a second trench wide portion (28B) including the bottom wall (26) and a portion of the side wall (24); a second trench narrow portion (30B) having a dimension in the second direction (Y) smaller than that of the second trench wide portion (28B), the mesa wide portion (92) is located between the first trench narrow portion (30A) and the second trench narrow portion (30B), The mesa narrow portion (94) is located between the first trench wide portion (28A) and the second trench wide portion (28B). The semiconductor device (10) according to appendix 15.

[0217] (Appendix 17) the first field plate electrode (70A) includes a first field plate side surface (74A), the first gate electrode (60A) includes a first gate side surface (64A), The insulating layer (14) includes a first field plate insulating portion (84A) located between the first field plate side surface (74A) and the sidewall (24); a first gate insulating portion (82A) located between the first gate side surface (64A) and the sidewall (24); a dimension of the first gate insulating portion (82A) in the second direction (Y) is smaller than a dimension of the first field plate insulating portion (84A) in the second direction (Y); A semiconductor device (10) according to any one of appendices 1 to 16.

[0218] (Appendix 18) The dimension of the first gate insulating portion (82A) in the second direction (Y) is constant, The dimension of the first field plate insulating portion (84A) in the second direction (Y) is constant. 18. The semiconductor device (10) according to claim 17.

[0219] (Appendix 19) The first gate trench (20A) is a first trench wide portion (28A) including the bottom wall (26) and a portion of the side wall (24); a first trench narrow portion (30A) having a dimension in the second direction (Y) smaller than that of the first trench wide portion (28A), the first field plate insulating portion (84A) is located in the first trench wide portion (28A); the first gate insulating portion (82A) is located in the first trench narrow portion (30A); 18. The semiconductor device (10) according to claim 17.

[0220] (Appendix 20) forming a semiconductor layer (12) having a first surface (12F) and a second surface (12G) opposite to the first surface (12F); forming a plurality of gate trenches (20) extending from the second surface (12G) into the semiconductor layer (12) and having sidewalls (24); forming a first insulating layer (304) within the gate trench (20); forming a protective insulating layer (306) covering a portion of the sidewall; forming a second insulating layer (308) on the bottom wall and on the sidewalls exposed from the protective insulating layer (306); forming a field plate electrode (70) in the gate trench (20); forming a gate electrode (60) spaced apart from the field plate electrode (70) within the gate trench (20); forming a third insulating layer (310) on the semiconductor layer (12) and the gate electrode (60); forming a contact through the second insulating layer (308) and in contact with the semiconductor layer (12); Including, Forming the semiconductor layer (12) forming a drift region (50); forming a body region (52) on the drift region (50); Including, forming the plurality of gate trenches (20) includes forming mesas (90) defined between the gate trenches (20); forming the second insulating layer (308) includes forming a mesa wide portion (92) and a mesa narrow portion (94) having a dimension smaller than that of the mesa wide portion (92) in the mesa portion (90); A method for manufacturing a semiconductor device (10).

[0221] (Appendix 21) The second insulating layer (308) is formed by thermal oxidation. A method for manufacturing the semiconductor device (10) according to appendix 20. [Explanation of symbols]

[0222] 10,200...Semiconductor equipment 12...Semiconductor layer 12F…First page 12G…Second side 12X1,12X2,12Y1,12Y2…Side 14...Insulating layer 16...Gate wiring 16P...Gate pad section 16Y1...First gate wiring section 16Y2...Second gate wiring section 16X...Third gate wiring section 18...Source wiring 18M...Inner source wiring section 18L...Outer peripheral source wiring section 20...Gate trench 20A...First gate trench 20B...Second gate trench 22...Opening 24…Side wall 26...Bottom wall 28A…First trench wide section 28B: Wide part of second trench 30A...Narrow section of first trench 30B: Narrow section of second trench 32A…First lower side wall 32B…Second lower side wall 34A…First upper side wall 34B…Second upper side wall 40...Peripheral trench 42...Source contact plug 44...Gate electrode contact plug 46...Field plate electrode contact plug 48...Drain region 50...Drift region 52...Body area 54...Source region 56...Drain electrode 60...Gate electrode 60A...First gate electrode 60B...Second gate electrode 62A...Underside of the first gate 62B...Underside of the second gate 64A...Side of Gate 1 64B...Side of Gate 2 70...Field plate electrode 70A...First field plate electrode 70B...Second field plate electrode 72A...Top surface of first field plate 72B...Top surface of second field plate 74A...First field plate side 74B...Side of second field plate 76A,76B…Top 80...Trench insulating layer 80A...First trench insulation layer 80B...Second trench insulating layer 82A...First gate insulation part 82B...Second gate insulating part 84A...First field plate insulating part 84B...Second field plate insulating section 86...Interlayer insulating layer 90...Mesa section 92…Wide part of the mesa 94...Narrow part of the mesa 96...Mesa step section 98...Mesa step surface 100...Contact trench 102...Contact trench bottom wall 104...Contact area 106...Contact bottom 202A: Middle part of the first trench 202B: Middle part of second trench 204...Middle of the mesa 300...Semiconductor substrate 302...epitaxial layer 304...First insulating layer 306...Protective insulating layer 308...Second insulating layer 310...Third insulating layer 312...First conductor 314...Fourth insulating layer 316...p-type region W1a…First wide trench width W1b: Second wide trench width W2a: First narrow trench width W2b: Second narrow trench width W3a: First gate insulation width W3b: Second gate insulation width W4a: First field plate insulation width W4b: Second field plate insulation width W5…Wide mesa width W6...narrow mesa width Wf: First width Ws...Second width Wc: Contact width Wm...Margin width Wm1: First margin width Wm2: Second margin width θ…Angle

Claims

1. a semiconductor layer having a first surface and a second surface opposite the first surface; a first gate trench and a second gate trench extending from the second surface into the semiconductor layer and having sidewalls and a bottom wall; an insulating layer located on the semiconductor layer; a first gate electrode located in the first gate trench; a first field plate electrode located in the first gate trench, positioned closer to the bottom wall than the first gate electrode in a depth direction orthogonal to the first surface, and including a first field plate upper surface facing the first gate electrode with the insulating layer interposed therebetween; a source contact plug that penetrates the insulating layer and includes a contact lower surface that contacts the semiconductor layer; Equipped with each of the first gate trench and the second gate trench extends in a first direction in a plan view and is spaced apart from each other in a second direction perpendicular to the first direction in a plan view; the semiconductor layer includes a mesa portion defined between the first gate trench and the second gate trench; The mesa portion is a mesa wide portion including a part of the second surface as an upper surface; a mesa narrow portion having a dimension smaller in the second direction than the mesa wide portion, the source contact plug is in contact with the mesa wide portion, the mesa narrow portion faces at least a part of an upper portion of the first field plate electrode in the second direction. Semiconductor device.

2. the upper portion of the first field plate electrode is a portion closer to an upper surface of the first field plate than a center of the first field plate electrode in the depth direction. The semiconductor device according to claim 1 .

3. the mesa portion has a first width at a position of a lower surface of the contact in the depth direction, and a second width at a position of an upper surface of the first field plate in the depth direction, the second width being smaller than the first width. The semiconductor device according to claim 1 .

4. The mesa narrow portion extends in the depth direction at least from the upper surface of the first field plate to the bottom wall of the first gate trench. The semiconductor device according to claim 1 .

5. the mesa portion includes a mesa step portion connecting the wide mesa portion and the narrow mesa portion; The semiconductor device according to claim 1 .

6. at least a portion of the mesa step portion is located between the lower surface of the contact and the upper surface of the first field plate in the depth direction; 6. The semiconductor device according to claim 5.

7. the first gate electrode faces the mesa wide portion in the second direction, the first field plate electrode faces the mesa narrow portion in the second direction. The semiconductor device according to claim 1 .

8. The semiconductor device includes: a second gate electrode located in the second gate trench; a second field plate electrode located in the second gate trench, positioned closer to the bottom wall than the second gate electrode in the depth direction, and facing the second gate electrode with the insulating layer interposed therebetween; The semiconductor device according to any one of claims 1 to 7.

9. the mesa wide portion is located between the first gate electrode and the second gate electrode, the mesa narrow portion is located between the first field plate electrode and the second field plate electrode. The semiconductor device according to claim 8 .

10. a dimension of the first gate electrode in the second direction is equal to a dimension of the first field plate electrode in the second direction; The semiconductor device according to claim 1 .

11. the mesa portion includes a drift region of a first conductivity type, a body region of a second conductivity type located on the drift region, and a source region of the first conductivity type located on the body region; The semiconductor device according to claim 1 .

12. the mesa wide portion includes the source region, the body region, and the drift region; The semiconductor device according to claim 11.

13. the mesa portion includes a mesa step portion connecting the wide mesa portion and the narrow mesa portion, the mesa step portion is located in the drift region; The semiconductor device according to claim 11.

14. the mesa portion further includes a second conductivity type contact region in the mesa wide portion; the contact region is in contact with the source contact plug. The semiconductor device according to claim 11.

15. The first gate trench is a first trench wide portion including the bottom wall and a portion of the side wall; a first trench narrow portion having a dimension in the second direction smaller than that of the first trench wide portion, the first gate electrode is located in the narrow portion of the first trench, the first field plate electrode is located in the first trench wide portion; The semiconductor device according to claim 1 .

16. The second gate trench is a second trench wide portion including the bottom wall and a portion of the side wall; a second trench narrow portion having a dimension in the second direction smaller than that of the second trench wide portion, the mesa wide portion is located between the first trench narrow portion and the second trench narrow portion, the mesa narrow portion is located between the first trench wide portion and the second trench wide portion; The semiconductor device according to claim 15.

17. the first field plate electrode includes a first field plate side surface; the first gate electrode includes a first gate side surface; the insulating layer includes a first field plate insulating portion located between the first field plate side surface and the sidewall; a first gate insulating portion located between the first gate side surface and the sidewall, a width in the second direction of the first gate insulating portion is smaller than a width in the second direction of the first field plate insulating portion; The semiconductor device according to claim 1 .

18. the dimension of the first gate insulating portion in the second direction is constant; a dimension of the first field plate insulating portion in the second direction is constant; 18. The semiconductor device according to claim 17.

19. The first gate trench is a first trench wide portion including the bottom wall and a portion of the side wall; a first trench narrow portion having a dimension in the second direction smaller than that of the first trench wide portion, the first field plate insulating portion is located in the first trench wide portion, the first gate insulating portion is located in the first trench narrow portion; 18. The semiconductor device according to claim 17.

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