Information processing apparatus

Abstract

To provide an information processor having a wiring pattern to which illegal access is difficult.SOLUTION: An information processing apparatus includes a substrate, a central processing unit (CPU) mounted on the substrate and configured to hold confidential data, a pair wiring including a pair of a signal wiring and a ground (GND) wiring or a pair of signal wirings drawn in at least two or more layers of the substrate, and a via electrically connecting the pair wirings of the layers, in which the pair wiring is a wiring extending in parallel in a spiral shape around the via.SELECTED DRAWING: Figure 10A

Description

[Technical Field]

[0001] The present invention relates to an information processing device. [Background technology]

[0002] In recent years, many information processing devices that internally store security information have been installed. In such information processing devices, it is necessary to detect unauthorized access to electronic components that require security information and take action to protect the security information. One such protection technology is described in Patent Document 1, for example. In Patent Document 1, an unauthorized access detection pattern is arranged in a zigzag pattern on printed pattern wiring, and when a hole is drilled into the board, the pattern is broken, detecting the unauthorized access and taking action to protect the security information. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-170422 Summary of the Invention [Problem to be solved by the invention]

[0004] When attempting unauthorized access to electronic components, one method involves drilling holes in a circuit board with a drill or other device and reading signals from wiring carrying security information. Patent Document 1 folds signal wiring for detecting unauthorized access, resulting in adjacent locations for the signal wiring. For example, in the example shown in FIG. 7, the signal wiring is folded back at the first protrusion 40f or the second protrusion 40g, resulting in adjacent signal wirings facing each other near the folds, or adjacent signal wirings facing each other at the straight portions 40c. This makes it easier for adjacent signal wirings for detecting unauthorized access to be connected to each other, invalidating the signal for detecting unauthorized access and making unauthorized access easier.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an information processing device having a wiring pattern that makes unauthorized access difficult. [Means for solving the problem]

[0006] In order to solve the above problem, one representative embodiment of an information processing device of the present invention is configured as an information processing device comprising: a substrate; a CPU that stores confidential data mounted on the substrate; a pair of signal wiring and GND wiring, or a pair of signal wiring pairs, laid on at least two layers of the substrate; and a via that electrically connects the pair of wirings on the layers, wherein the pair of wirings are wirings that run parallel to each other in a spiral shape centered on the via. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a wiring pattern that is difficult to access illegally.

[0008] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view of an information processing device according to an embodiment of the present invention; [Figure 2] FIG. 2 is an exploded perspective view of the information processing device shown in FIG. [Figure 3] FIG. 2 is a diagram illustrating a control relationship of the information processing device illustrated in FIG. [Figure 4] FIG. 3 is an exploded perspective view of the unauthorized access protection board shown in FIG. 2. [Figure 5] 5 is a diagram showing the positional relationship between the confidential data holding CPU shown in FIG. 4 and a board on which the confidential data holding CPU is mounted. FIG. [Figure 6] FIG. 2 is a diagram illustrating the configuration and connection relationship of a confidential data holding CPU. [Figure 7] 10 is a flowchart showing a processing procedure for detecting unauthorized access in a confidential data holding CPU. [Figure 8A]FIG. 1 is a diagram illustrating a drilling attack. [Figure 8B] FIG. 1 is a diagram illustrating a drilling attack. [Figure 9A] FIG. 1 is a diagram illustrating conductive glue attack. [Figure 9B] FIG. 1 is a diagram illustrating conductive glue attack. [Figure 9C] FIG. 1 is a diagram illustrating conductive glue attack. [Figure 10A] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10B] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10C] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10D] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10E] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10F] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10G] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10H] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10I] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10J] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10K] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10L] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 10M] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 11] FIG. 10 is a diagram illustrating types of vias. [Figure 12A] FIG. 10 is a diagram showing an example in which the protection range is expanded by using a wiring pattern. [Figure 12B] FIG. 10 is a diagram showing an example in which the protection range is expanded by using a wiring pattern. [Figure 13] 1A and 1B are diagrams illustrating an example of semiconductor layers constituting a laminated structure. [Figure 14] FIG. 10 is a diagram showing an example of a layer configuration when connected to other layers through vias. [Figure 15] FIG. 10 is a diagram illustrating an example of a via configuration. [Figure 16] FIG. 10 is a diagram showing another example of a wiring pattern of spiral wiring. [Figure 17] FIG. 10 is a diagram showing an example of a wiring pattern. [Figure 18] FIG. 10 is a diagram showing yet another example of a wiring pattern of spiral wiring. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention should not be construed as being limited to the description of the following examples. Those skilled in the art will readily understand that the specific configuration can be modified within the scope of the concept and spirit of the present invention.

[0011] In the configurations of the invention described below, the same or similar configurations or functions are denoted by the same reference numerals, and redundant explanations may be omitted.

[0012] In this specification, the terms "first," "second," "third," etc. are used to identify components and do not necessarily limit the number or order.

[0013] The position, size, shape, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. Therefore, the present invention is not limited to the position, size, shape, range, etc. disclosed in the drawings, etc. Unless otherwise specified, each component may be singular or plural.

[0014] In the following embodiments, processing performed by executing a program may be described. Here, a computer executes the program using a processor (e.g., a CPU or a GPU) and performs processing defined by the program using storage resources (e.g., a memory) and interface devices (e.g., a communication port). Therefore, the entity performing the processing by executing the program may be the processor. Similarly, the entity performing the processing by executing the program may be a controller, device, system, computer, or node having a processor. The entity performing the processing by executing the program may be any computing unit, and may include a dedicated circuit that performs specific processing. Here, the dedicated circuit may be, for example, an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a CPLD (Complex Programmable Logic Device).

[0015] A program may be installed on a computer from a program source. The program source may be, for example, a program distribution server or a computer-readable storage medium. When the program source is a program distribution server, the program distribution server may include a processor and a storage resource for storing the program to be distributed, and the processor of the program distribution server may distribute the program to be distributed to other computers. In addition, in an embodiment, two or more programs may be realized as one program, or one program may be realized as two or more programs.

[0016] In this specification, a contactless payment processing terminal for credit cards with a built-in IC chip will be described as an example of an information processing device. Note that the information processing device of the present invention is not limited to contactless payment processing terminals for credit cards, but may also be an information processing terminal that stores personal information of a user, an information processing terminal that stores confidential financial transaction information, or an information processing terminal that supports electronic money. In other words, the present invention is applicable to various media, devices, equipment, terminals, and other objects that require protection from unauthorized access.

[0017] 1 is a perspective view of an information processing device according to an embodiment of the present invention. The information processing device 1 has, on the surface of its housing, a touch panel liquid crystal screen 1a for receiving touch operations from a user, and a contactless communication unit 1b capable of communicating with a credit card, for example, by near field communication (NFC). A LAN cable 1c is connected to the back of the device. Information processed by the information processing device 1 is transmitted via the LAN cable 1c.

[0018] Fig. 2 is an exploded perspective view of the information processing device shown in Fig. 1. The information processing device 1 is composed of an upper housing 4, a lower housing 9, a touch panel liquid crystal display unit 5 constituting the touch panel liquid crystal screen 1a, a main board 8, an unauthorized access protection board 7, and a short-range contactless communication antenna 6. The upper housing 4 is a housing that covers the information processing device 1 from above. The lower housing 9 is a housing that covers the information processing device 1 from below.

[0019] The touch panel liquid crystal display unit 5 is a device that receives operations from the user via a touch panel and displays information to the user via a liquid crystal screen.

[0020] The main board 8 is equipped with a main CPU 8f and is a board that communicates with the touch panel, controls the short-range contactless communication antenna 6, communicates with the unauthorized access protection board 7, and communicates with a network such as the Internet via a LAN cable 1c.

[0021] The unauthorized access protection board 7 is a board that holds confidential data and is equipped with an unauthorized access detection and protection circuit.

[0022] The short-distance contactless communication antenna 6 is an antenna for performing short-distance contactless communication with a credit card.

[0023] The information processing device 1 is a device that reads data recorded on a credit card, combines it with data volatilely stored in a confidential data storage CPU 12a (described later), and communicates with a system on a network such as the Internet to process information. Specifically, the information processing device 1 has a function for performing contactless wireless communication with a credit card brought close to a short-range contactless communication antenna 6 of the information processing device 1. The top housing 4 and the bottom housing 9 serve to integrate and secure the main board 8, unauthorized access protection board 7, and short-range contactless communication antenna 6 so that they are not exposed to the outside. The top housing 4 and the bottom housing 9 are made of a resin such as ABS. While ABS is described as one example, materials that are less likely to deform, such as metal or wood, may also be used.

[0024] 3 is a diagram showing the control relationship of the information processing device 1. The touch panel liquid crystal display unit 5 notifies the user of the status of the information processing device 1 by receiving input from the user and displaying it on the screen. Although a touch panel has been described as one example of a screen that the touch panel liquid crystal display unit 5 has, the same function may be realized by providing a device with a function of providing visual or audible notification to the user, such as an LCD screen, light-emitting elements, or a speaker, and a device for acquiring input information from the user, such as a button or keypad.

[0025] The short-range contactless communication antenna 6 performs short-range contactless communication and reads necessary data from the credit card with which communication is to be performed. As an example, the short-range contactless communication antenna 6 is fixed to the upper housing 4 with adhesive tape. As an example, the short-range contactless communication antenna 6 is described as being configured using a flexible substrate with an antenna pattern. However, the antenna is not limited to an antenna pattern, and any other antenna-forming device may be used, such as a rigid substrate with a conductor pattern that forms the antenna or a loop of coated copper wire. Here, a credit card is described as an example of a communication target, but other devices may also be used, such as a transportation IC card with an embedded IC chip, a paper card, or an information processing terminal that accepts electronic money.

[0026] The main board 8 communicates with the outside world via a LAN connector 8e using data read by the short-range contactless communication antenna 6 and confidential credit card payment data stored in the unauthorized access protection board 7, and performs payment information processing. While a LAN connection is described here as an example, communication with the outside world can also be performed using wireless standards such as Wi-Fi, LTE, or Bluetooth, or other wired connection methods such as USB or RS232. The main board 8 also communicates with the touch panel to perform processing in response to operations such as selecting a payment method accepted by the user, and to notify the user of payment completion or failure.

[0027] The unauthorized access protection board 7 holds confidential data therein and is responsible for deleting the confidential data when unauthorized physical access is made from the outside.

[0028] Fig. 4 is an exploded perspective view of the unauthorized access protection board 7 shown in Fig. 2. Here, as an example, the unauthorized access protection board 7 is configured with a three-layer structure having three boards. The first board is the board 12 on which the confidential data holding CPU 12a holding the information to be held is mounted.

[0029] As an example, the second substrate is a square-shaped substrate 11 that surrounds the confidential data holding CPU 12a. The square-shaped substrate 11 may be configured with the four sides that make up the square as separate substrates. When a square-shaped substrate 11 is used, there are no joints between the substrates, and the confidential data holding CPU 12a can be surrounded and covered without the wiring for detecting unauthorized access being interrupted. When the four sides that make up the square are configured as separate substrates, there are no hollow portions, which has the effect of reducing the unit cost when manufacturing the substrate.

[0030] The third substrate is a cover substrate 10 that is placed over the second substrate to form a lid. The first to third substrates are fixed to the second substrate by, for example, soldering or screwing, and are electrically connected by, for example, pads or connectors provided on the substrates. While a configuration that surrounds the confidential data holding CPU 12a has been described as an example, a structure in which wiring for detecting unauthorized access can be arranged in only one direction or in part of the circuit board may also be employed. However, adopting a structure in which wiring for detecting unauthorized access can be arranged to surround the confidential data holding CPU 12a in all directions as much as possible is more effective in detecting unauthorized access from multiple directions.

[0031] FIG. 5 shows the positional relationship between the confidential data holding CPU 12a shown in FIG. 4 and the substrate 12 on which the confidential data holding CPU 12a is mounted. FIG. 6 is a diagram showing the configuration and connection relationship of the confidential data holding CPU 12a. The confidential data to be protected is stored in a volatile manner in the backup SRAM 81a of the confidential data holding CPU 12a. The backup SRAM 81a is powered by the battery 12b to maintain volatile storage. The unauthorized access detection block 81c also functions by power supplied from the battery 12b. A signal for detecting unauthorized access is output from the confidential data holding CPU 12a and is wired so as to return to the input of the confidential data holding CPU 12a via a signal wiring for detecting unauthorized access.

[0032] A pair of unauthorized access detection signal and GND wires is drawn from the confidential data storage CPU 12a and wired to form a spiral wiring pattern covering the entire substrate. This wiring path is shown in Figure 6 as unauthorized access detection signal and GND wires 16a, 16b, and 16c. As an example, the unauthorized access detection signal and GND wire pair 16a is connected to the pads of the substrate by soldering, forming a spiral wiring pattern composed of unauthorized access detection signal and GND wire pairs not only on the substrate 12 but also on the square-shaped substrate 11 and the cover substrate 10. The configuration and layout of Figure 5 are merely an example, and the positional relationship may be changed.

[0033] 7 is a flowchart showing the procedure for detecting unauthorized access in the confidential data holding CPU 12a. Confidential data is written in advance, for example, during assembly (S101), and the confidential data holding CPU 12a enables an unauthorized access detection function for outputting an unauthorized access detection signal to the unauthorized access detection signal wiring and GND wiring (S102). The confidential data holding CPU 12a outputs the unauthorized access detection signal and constantly monitors whether the output unauthorized access detection signal is returned to the input pin normally (S103).

[0034] If the output signal for detecting unauthorized access returns normally (S103; YES), the confidential data holding CPU 12a continues monitoring. On the other hand, if the output signal for detecting unauthorized access does not return normally (S103; NO), the confidential data holding CPU 12a recognizes that unauthorized access has occurred, deletes the confidential data from the confidential data holding CPU 12a, and terminates abnormally. There are two types of unauthorized access attacks: drilling attack and conductive glue attack. The unauthorized access detection operation shown in Figure 7 detects unauthorized access and deletes confidential data.

[0035] 8A and 8B illustrate a drilling attack as an example of an unauthorized access attack. A drilling attack is an attack in which a hole is drilled into a substrate to attempt unauthorized access to an IC chip that stores confidential data. As shown in FIG. 8A, this attack involves drilling a hole in a substrate 17 with a drill 19, allowing a signal probe 20 to be applied to pads 18a and signal lines of an IC chip 18. The substrate 17 is, for example, a substrate 12 on which a confidential data-storing CPU 12a is mounted. The substrate 17 is composed of one or more conductive layers 17a and one or more non-conductive layers 17b, and the IC chip 18 is mounted on the surface of the topmost conductive layer 17a, supported by pads 18a.

[0036] For example, as shown in Figure 8B, if a signal probe 20 is applied to a pad 18a related to IC chip operation or confidential data input / output, such as a CPU software rewrite pin or debug pin, confidential data may be extracted from the IC chip. Therefore, one method for detecting unauthorized access is to wire a signal line for detecting unauthorized access as shown in Figure 9A and use the unauthorized access detection operation shown in Figure 7 to detect unauthorized access. If the signal line for detecting unauthorized access is wired as shown in Figure 9A, the signal line for detecting unauthorized access will be disconnected when a drilling attack is performed, making it possible to detect unauthorized access.

[0037] 9A, 9B, and 9C illustrate a conductive glue attack as an example of an unauthorized access attack. A conductive glue attack uses conductive glue or similar material to short-circuit an area covered by unauthorized access detection signal lines, thereby invalidating disconnection detection. In FIG. 9A, two types of unauthorized access detection signal lines 21a and 21b are snaked on a substrate 21, resulting in a folded unauthorized access detection signal line. In this wiring configuration, as shown in FIG. 9B, the resist is removed from adjacent unauthorized access signal lines, conductive glue 22 is poured in, and if a conductive glue attack is performed, the unauthorized access detection signal line in region 23 shown in FIG. 9B will no longer function. That is, if the end 911 of the open wiring opposite the end 910 of the folded unauthorized access detection signal lines 21a and 21b is closed by conductive glue 22, a short circuit is formed by an electrical loop 912, indicated by a dotted line, and disconnection detection will be invalidated. In this state, an attacker can launch a drilling attack on area 23 where the disabled unauthorized access detection signal line is wired, as shown in Fig. 9C. Therefore, as will be described below, this embodiment is configured to make such attacks difficult by wiring the unauthorized access detection signal line in such a way that a short circuit is not formed.

[0038] An example of a wiring pattern for the present embodiment, shown in FIG. 10A , is applied to the substrate 12 on which the confidential data storage CPU 12a is mounted and the square-shaped substrate 11. FIG. 10A is a diagram showing an example of the wiring pattern for the present embodiment. In FIG. 10A , the wiring width and spacing are 0.1 mm. In this embodiment, the signal lines for unauthorized access detection are routed in a spiral wiring pattern. As shown in FIGS. 9A to 9C , the signal lines for unauthorized access detection are routed in a folded pattern, preventing adjacent locations of the signal lines for unauthorized access detection. This makes it difficult to connect the signal lines for unauthorized access detection using conductive glue or the like. FIG. 10A shows a substrate 24, which is the substrate 12 on which the confidential data storage CPU 12a is mounted, in which the signal lines for unauthorized access detection and the GND wiring run parallel to each other, forming a spiral wiring. The signal lines for unauthorized access detection and the GND wiring are connected to other conductor layers through vias 24c and 24d in FIG. 10A . In such a laminated substrate, by arranging the CPU at a position where the spiral wiring patterns on each layer overlap, the above-mentioned attacks can be made even more difficult.

[0039] The method of running the unauthorized access detection signal line and the GND wiring in parallel in Fig. 10A is merely one example, and instead of the GND wiring, a different unauthorized access detection signal line may be run in parallel on board 29 as shown in Fig. 17. In Fig. 17, the wiring pattern on board 29 is such that unauthorized access detection signal wirings 29a and 29b run in parallel in a spiral shape and are connected to other conductor layers at signal line vias 29c and 29d.

[0040] When the signal line for detecting unauthorized access and the GND wiring are run parallel to each other, only one signal line is required for detecting unauthorized access, which has the advantage of saving CPU hardware resources and reducing power consumption. Another advantage is that there is no need to consider crosstalk between parallel signal lines. When different signal lines for detecting unauthorized access are run parallel to each other, there are two signal lines for detecting unauthorized access, which means that two types of signals must be output by the CPU, but the advantage is that unauthorized access can be detected even if either of the two parallel lines is disconnected.

[0041] Fig. 10A is merely an example, and the corners may be rounded as shown in Fig. 10B (one rounded corner 1001 is shown as an example in Fig. 10B), or a spiral shape may be formed like a circle as shown in Fig. 10C. Drawing a square as shown in Fig. 10A has the advantage that wiring can be laid out without gaps when covering a wide area, compared to a circular shape.

[0042] Furthermore, the wiring of such unauthorized access detection signal lines may be rectangular as shown in FIGS. 10D and 10E, or may have an L-shaped spiral as shown in FIGS. 10F and 10G. These figures illustrate wiring patterns formed on a substrate 25, which is a substrate 12 on which a confidential data storage CPU 12a is mounted. FIGS. 10D, 10E, 10F, and 10G illustrate wiring patterns for the unauthorized access detection signal lines and GND lines, including an unauthorized access detection signal line 25a, a GND line 25b, an unauthorized access detection signal line 25c, a GND line 25d, vias 25e, 25f, 25g, 25h, 25i, 25j, and a substrate outline 25k. The wiring patterns in FIGS. 10D and 10E are connected by the respective vias. The wiring patterns in FIGS. 10F and 10G are similarly connected by the respective vias.

[0043] Furthermore, the wiring of the unauthorized access detection signal line may be other wiring patterns. For example, as shown in Figures 10H and 10I, it may be a wiring pattern in which square spirals are laid out in a rectangular shape. Figures 10H and 10I illustrate a wiring pattern including unauthorized access detection signal line 25a, GND line 25b, unauthorized access detection signal line 25c, GND line 25d, vias 25e, 25f, 25g, 25h, 25i, 25j, board outline 25k, vias 25l, 25m, 25n, and 25o. In Figures 10H and 10I, connections are similarly made through the respective vias.

[0044] Furthermore, the wiring of the unauthorized access detection signal line may be other wiring patterns. For example, as shown in FIGS. 10J and 10K, it may be a wiring pattern of square spirals arranged in an L-shape. FIGS. 10J and 10K illustrate a wiring pattern including unauthorized access detection signal line 25a, GND line 25b, unauthorized access detection signal line 25c, GND line 25d, vias 25e, 25f, 25g, 25h, 25i, 25j, board outline 25k, vias 25l, and 25m. In FIGS. 10J and 10K, connections are made through the respective vias in the same manner.

[0045] Furthermore, the wiring of the unauthorized access detection signal line shown so far may have a laminated structure with partial overlaps where the spirals are offset. FIG. 10L shows, as an example, the unauthorized access detection signal line and GND wiring shown in FIG. 10A, which are two-layer laminated wiring patterns, connected via vias 24c and 24d with approximately half of the wiring overlapping. This laminated structure allows the centers of the spirals of the semiconductor layers to be positioned at different locations. As a result, the centers of the unauthorized access detection signal line and GND wiring in each semiconductor layer, or the wiring patterns of different unauthorized access detection signal lines running parallel to each other (e.g., the positions of the vias at the center of the spirals) are different in the lamination direction. This makes it more complicated to configure an electrical loop to form a short circuit, making attacks by attackers more difficult.

[0046] The above-described stacked structure may be a combination of the same-shaped unauthorized access detection signal lines as shown in FIG. 10L, or any of the previously described unauthorized access detection signal line wirings. For example, as shown in FIG. 10M, the wiring pattern of the unauthorized access detection signal line and GND wiring shown in FIG. 10B and the unauthorized access detection signal line and GND wiring shown in FIG. 10C may be partially overlapped. That is, the combinations of wiring patterns described above may also be considered to include various combinations of unauthorized access detection signal lines running parallel to different unauthorized access detection signal lines, or combinations of different unauthorized access detection signal lines running parallel to each other. A stacked structure consisting of a combination of different types of wiring patterns is more complex than a stacked structure consisting of a combination of the same type of wiring patterns, making attacks by attackers even more difficult.

[0047] By arranging the wiring in this way, drilling attacks such as those shown in FIG. 8 can be detected by disconnecting the unauthorized access detection signal wiring 24a. Furthermore, conductive glue attacks such as those shown in FIG. 9 can be detected by shorting the unauthorized access detection signal line and the GND wiring, which prevents the unauthorized access detection signal from returning normally. The number of turns of the wiring shown in FIGS. 10A to 10M is merely an example and may be increased or decreased depending on the size of the area where unauthorized access is to be detected and wiring constraints. For example, the wiring width and spacing between the unauthorized access detection signal line and the GND wiring shown in FIG. 10A are merely examples and may be adjusted depending on manufacturing constraints. However, keeping the values ​​as small as possible has the advantage of making attacks more difficult. In particular, it is preferable for the value to be smaller than the diameter of the drill used in the anticipated attack.

[0048] FIG. 11 shows the types of vias used for electrical connection between conductor layers of a substrate. FIG. 11 describes vias formed in a substrate 50, which is a substrate 12 on which a confidential data storage CPU 12a is mounted. Vias are broadly divided into three types, as shown in FIG. 11: through vias 50d, blind vias 50e, and through vias 50f. The through vias 50d are formed by drilling holes penetrating the substrate 50 using through via holes 50g, and are characterized by having holes exposed on both sides of the substrate. The blind vias 50e are formed by using prepreg via holes 50h and, if necessary, core via holes 50i, and are characterized by having holes exposed only on one side of the substrate. The buried vias 50f are formed by using prepreg via holes 50h and, if necessary, core via holes 50i, and are characterized by having holes not exposed on the surface of the substrate.

[0049] 10A to 10H, buried vias or blind vias are used as examples of vias. Although through vias may be used, the use of buried or blind vias has the advantage of preventing the holes that make up the vias from being exposed on the surface of the substrate, thereby reducing the risk that the vias or the holes in the vias will be used in attacks.

[0050] The substrate 12 on which the confidential data storage CPU 12a is mounted and the square substrate 11 are configured with, for example, the wiring pattern shown in Figures 12A and 12B and signal wiring for detecting unauthorized access in the layer structure shown in Figure 13.

[0051] 12A and 12B are diagrams showing an example in which a semiconductor layer having a wiring pattern of wiring in this embodiment is connected to another semiconductor layer through a via, thereby expanding the protection range. Fig. 12A shows a wiring pattern 1201 of wiring in a certain semiconductor layer. Fig. 12B shows a wiring pattern 1202 of wiring in a semiconductor layer different from the semiconductor layer shown in Fig. 12A.

[0052] 12A and 12B are configured with the laminated structure shown in Fig. 13, and the layers are connected to each other. The wiring pattern of the wiring shown in Fig. 12A is formed on a substrate 51, which is a substrate 12 on which a confidential data storage CPU 12a is mounted, and is routed to a semiconductor layer 51e that constitutes the laminated structure shown in Fig. 13. Fig. 12B is routed to a layer of a semiconductor layer 51f that constitutes the laminated structure shown in Fig. 13. In Fig. 13, a prepreg 51a, a core 51b that serves as an insulating layer, a general signal conductor layer 51c, a GND layer 51d, a conductor layer 51e for detecting unauthorized access, and a signal wiring 51f for detecting unauthorized access form the laminated structure of the substrate 51.

[0053] The semiconductor layer is connected to the other semiconductor layer via vias 251e and 251f, and vias 251g and 251h shown in Figure 12A. At the center of the spiral wiring pattern, the wiring moves to another conductor layer via the via, and then forms another spiral wiring pattern starting from the new via. By repeating this process, the protection range is expanded.

[0054] FIG. 14 shows an example of a layer configuration when connecting to other layers through the vias described above, as in FIGS. 12A and 12B. For example, this shows the layer configuration of a board 26, which is a board 12 on which a confidential data storage CPU 12a is mounted. FIG. 14 is merely an example, and additional layers may be added, including a pair of signal wiring and GND wiring for unauthorized access detection, and layers for GND signal wiring and power supply. In the board 26 shown in FIG. 14, the pair of layers, the semiconductor layer 26a comprising the signal wiring for unauthorized access detection and the GND layer 26b comprising the GND wiring, is sandwiched between layers covered with the GND layer 26b, which has the advantage of shielding electromagnetic noise generated by the spirally wired signal wiring for unauthorized access detection. As shown in FIG. 14, the pair of layers, the signal wiring for unauthorized access detection 26a and the GND wiring 26b, is sandwiched between layers covered with GND, which also has the advantage of making the wiring of the signal wiring for unauthorized access detection less visible when the board is analyzed using an X-ray device or other device. Therefore, it is desirable to arrange the GND layer thickly or in multiple layers.

[0055] Fig. 15 is a diagram showing an example of a via configuration. The use of buried vias as shown in Fig. 15 has the advantage that the conductor connected to the signal line for detecting unauthorized access is not exposed on the surface of the board. In Fig. 15, for example, a buried via is formed by prepreg via hole 27e and core via hole 27f in board 27, which is board 12 on which confidential data storage CPU 12a is mounted, and GND layer 27b, which is composed of signal wiring for detecting unauthorized access on conductor layer 27a, and a conductor layer on which a pair of spiral wiring of the GND wiring is provided, are connected without being exposed on the surface of the board. In Figure 15, a laminated structure is formed of GND layer 27b, prepreg 27c, conductor layer 27a, prepreg 27c, GND layer 27b, core 27d which serves as an insulating layer, GND layer 27b, prepreg 27c, conductor layer 27a, prepreg 27c, GND layer 27b, and conductor layer 27a, prepreg 27c, GND layer 27b. Conductor layer 27a, prepreg 27c, and GND layer 27b are connected via prepreg via hole 27e. GND layer 27b, core 27d, GND layer 27b, and prepreg 27c are connected via core via hole 27f. Prepreg 27c, conductor layer 27a, and prepreg 27c are connected via prepreg via hole 27e.

[0056] The square-shaped substrate 11 may have a wiring pattern of wiring shown in FIG. 16. FIG. 16 shows an example of a wiring pattern of spiral wiring composed of pairs of signal wiring and GND wiring in the stacking direction of the substrate, which is perpendicular to the direction along the substrate (i.e., the substrate surface). In FIG. 16, the square-shaped substrate 11 is shown as substrate 28. As shown in FIG. 16, buried vias are used to form spiral wiring across layers. As already explained, the square-shaped substrate 11 is a substrate that is placed on the substrate 12 on which the confidential data holding CPU 12a is mounted, among the unauthorized access protection substrates 7 having the stacked structure shown in FIG. 4, and surrounds the confidential data holding CPU 12a. Therefore, the spiral wiring pattern explained so far is applied to the stacking direction. This prevents the wire break detection from being invalidated even when conductive glue attacks or drilling attacks shown in FIGS. 8A, 8B, and 9A to 9C are performed in the horizontal direction of the stacked substrates (i.e., the stacking surface S of the substrates). In Figure 16, it can be seen that substrate 28 has conductor layer 28a and conductor layer 28b, and that these conductor layers, prepreg via hole 27e, and core via hole 27f form a wiring pattern of spiral wiring on the stacking surface S as a wiring pattern in which conductor layers run parallel to each other and via holes run parallel to each other.

[0057] As a result, in this embodiment, unauthorized access detection is enabled to function also on the side of the confidential data holding CPU 12a. In Fig. 16, for example, an electrical loop 1601 shown by a dotted line can be used to prevent a short circuit from forming, which would invalidate the disconnection detection. 4 and 5, in this embodiment, attacks on the confidential data holding CPU 12a from all directions can be detected by surrounding the confidential data holding CPU 12a with the cover substrate 10, the square substrate 11, and the substrate 12. For example, in the example shown in Fig. 16, a spiral wiring pattern is formed on the four stacked surfaces S that form the side of the substrate 28, and a spiral wiring pattern is also formed on the upper and lower substrate surfaces of the substrate 28 (or the substrate surfaces of each stacked layer), making it possible to detect attacks on the confidential data holding CPU 12a from the top, bottom, left, and right directions.

[0058] Furthermore, an example of a wiring pattern that does not form a vortex in the configuration shown in Fig. 16 is shown in Fig. 18. The wiring pattern shown in Fig. 18 is a wiring pattern with an uneven shape (a deformed vortex, so to speak) in which the conductor layers and via holes that form the laminated structure run side by side and the via holes run side by side, instead of the wiring pattern shown in Fig. 16. In Fig. 18, for example, a substrate 27 that is a substrate 12 on which a confidential data holding CPU 12a is mounted is configured with a laminated structure having a conductor layer 287, a GND layer 27b, a prepreg 27c, a core 27d, a prepreg via hole 27e, and a core via hole 27f.

[0059] Of the above-mentioned concave and convex shapes, the concave shapes are composed of, for example, arm wirings forming partial wiring patterns 1801a and 1801b, which are portions formed by prepreg via holes 27e and / or core via holes 27f, and bottom wirings forming partial wiring pattern 1802, which is a portion formed by GND layer 27b. By connecting such concave shapes via GND layer 1803 similar to GND layer 27b, a wiring pattern similar to the outer edge of the wiring pattern of the spiral wiring described above is formed.

[0060] Of the above-described concave-convex shapes, the convex shapes are composed of, for example, arm wiring forming partial wiring patterns 1804a and 1804b, which are portions formed by prepreg via holes 27e and / or core via holes 27f, and top wiring forming partial wiring pattern 1805, which is a portion formed by conductor layer 287. Such convex shapes are connected via partial wiring pattern 1805 to form a wiring pattern similar to the inner edge of the spiral wiring pattern described above. In this example, the concave-shaped wiring pattern is expressed as the outer edge of the spiral wiring pattern, and the convex-shaped wiring pattern is expressed as the inner edge of the spiral wiring pattern, but these expressions may be interchanged. That is, a similar configuration can be obtained even if the concave-shaped wiring pattern is expressed as the inner edge of the spiral wiring pattern, and the convex-shaped wiring pattern is expressed as the outer edge of the spiral wiring pattern.

[0061] With this configuration, even if it is difficult to form a spiral shape in the stacking direction (for example, if a certain level of thickness in the stacking direction cannot be secured), unauthorized access detection can be performed on the side of the confidential data holding CPU 12a.

[0062] 10A, 17, etc., the information processing device of this embodiment includes a substrate (e.g., substrate 12 on which confidential data-holding CPU 12a is mounted), a CPU (e.g., confidential data-holding CPU 12a) mounted on the substrate, a pair of signal wiring (e.g., unauthorized access detection signal line 24a) and GND wiring (e.g., GND wiring 24b) or a pair of signal wiring (e.g., unauthorized access detection signal lines 29a and 29b) laid on at least two layers of the substrate, and vias (e.g., vias 24c, 24d, 29c, 29d) electrically connecting the pair of wirings between layers, and the pair of wirings has wiring running parallel to the via in a spiral shape around the via. This configuration provides wiring with a spiral wiring pattern centered on a via accessible to the CPU, making it difficult to connect the signal wiring for unauthorized access detection even in the event of unauthorized access such as a conductive glue attack or a drilling attack.

[0063] 10A-10C, 12, etc., the substrate has a pair of signal wiring and GND wiring (for example, a pair of unauthorized access detection signal line 24a and GND wiring 24b) wired as the paired wiring, and the wiring running parallel to the signal wiring is a GND wiring. This makes it possible to provide a wiring pattern of signal wiring and GND wiring that makes it difficult to connect the signal wiring for unauthorized access detection even if the unauthorized access is received.

[0064] 10D-10I, the pair wiring is arranged in an area that is substantially the same as the outline of the board, which allows the board surface to be used to its full potential for the wiring, thereby making the unauthorized access more difficult.

[0065] 13 and the like, the substrate has a structure in which at least a layer in the region covered by the wiring (for example, the semiconductor layer 51e) is sandwiched between GND layers (for example, the GND layer 51d), thereby suppressing noise within the substrate and making the unauthorized access difficult.

[0066] 4-6, 16, etc., the wiring of the pair wiring is wiring that covers the CPU, which makes it difficult to make the unauthorized access from the side of the CPU, for example.

[0067] 16, the covering wiring is the pair wiring (for example, the pair wiring wired to the conductor layers 28a, 28b and the spiral pair wiring formed in the stacking direction including the vias) running in a spiral shape in the stacking direction of the substrate through the vias (for example, the prepreg via hole 27e, the core via hole 27f). With this configuration, it is possible to make the unauthorized access from the side of the CPU covered by the square substrate 11 difficult.

[0068] 4-6, 10A, etc., the CPU is located at the overlapping position of the spirals of the layers of the spirally running parallel wiring, which makes the unauthorized access even more difficult.

[0069] 10L, 10M, etc., the pair wiring is arranged such that the centers of the vortices are shifted between the layers, which makes it even more difficult for an attacker to launch an attack.

[0070] 11, 15, 16, etc., the vias are blind vias or buried vias. This configuration prevents the holes that make up the vias from being exposed on the surface of the substrate, reducing the risk that the vias or the holes in the vias will be used in attacks.

[0071] 10M, the paired wirings in each of the layers are configured with different spiral wiring patterns, so that each layer has a stacked structure with different spiral wiring patterns, making the unauthorized access even more difficult.

[0072] The present invention is not limited to the above-described embodiments as they are, and in the implementation stage, the components can be modified and embodied within the scope of the gist of the present invention, or multiple components disclosed in the above-described embodiments can be appropriately combined. [Explanation of symbols]

[0073] 1. Information processing equipment 4 Top case 7. Tamper-protection board 8 Main board 9 Bottom case 10 Lid substrate 11 Square board 12 PCB 12a Confidential Data Retention CPU 12b battery 12c main board connector 15 Unauthorized Access Protection Area 16 Spiral Pattern 17 PCB 17a Conductor layer 17b Non-conductive layer 18 IC chip 18a pad 19 Drill 20 Signal Probes 21 PCB 21a, 21b Signal wiring for detecting unauthorized access 22 Conductive glue 23 Disabled unauthorized access detection signal area 24 PCB 24a Signal wiring for detecting unauthorized access 24b GND wiring 24c Beer 24d, 24e, 24f GND wiring vias 50 boards 50a Conductor layer 50b prepreg 50c Core 50d through via 50e blind via 50f Berry Beer 50g through via hole 50h Prepreg Beer Hall 50i Core Beer Hall 25 boards 25a, 25c Signal wiring for detecting unauthorized access 25b, 25d GND wiring 25e~25h via 51 PCB 51a prepreg 51b Core 51c General signal conductor layer 51d GND layer 51e, 51f Conductor layer for detecting unauthorized access 26 PCB 26a Conductor layer 26b GND layer 27 Circuit Board 27a Conductor layer 27b GND layer 27c prepreg 27d Core 27e Prepreg Beer Hall 27th floor Core Beer Hall 28 PCB 28a, 28b Conductor layers 29 Circuit Board 29a, 29b Signal wiring for detecting unauthorized access 29c, 29d Signal line vias

Claims

1. a substrate; a CPU mounted on the substrate and holding confidential data; a pair of signal wiring and GND wiring, or a pair of signal wiring, laid on at least two layers of the substrate; and a via that electrically connects the pair wirings between layers, The pair wirings are wirings that run in parallel in a spiral shape with the via at the center.

1. An information processing device comprising:

2. The substrate is provided with a pair of signal wiring and GND wiring as the pair wiring, and a wiring running parallel to the signal wiring is a GND wiring.

2. The information processing apparatus according to claim 1, wherein:

3. The pair wirings are arranged in an area substantially identical to the outer shape of the substrate.

2. The information processing apparatus according to claim 1, wherein:

4. The substrate has a structure in which at least a layer in an area covered by the wiring is sandwiched between GND layers.

2. The information processing apparatus according to claim 1, wherein:

5. The wiring of the pair wiring is a wiring that covers the CPU.

2. The information processing apparatus according to claim 1, wherein:

6. the CPU is disposed at an overlapping position of the spirals of the layers of the spirally running parallel wiring; 2. The information processing apparatus according to claim 1, wherein:

7. The pair wirings are wired such that the centers of the spirals of the layers are shifted from each other.

2. The information processing apparatus according to claim 1, wherein:

8. The covering wiring is the pair wiring that runs parallel to each other in a spiral shape in the stacking direction of the substrate through the via.

6. The information processing apparatus according to claim 5,

9. The via is a blind via or a buried via.

2. The information processing apparatus according to claim 1, wherein:

10. The pair wirings in each of the layers are configured with different spiral wiring patterns.

2. The information processing apparatus according to claim 1, wherein:

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