Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit capable of continuing an operation in an analog circuit even while a scan test is executed in a digital circuit.SOLUTION: The semiconductor integrated circuit 1 includes a circuit under test 100 that generates an output signal for controlling the operation of an analog circuit in response to an input signal, a test control unit 146 that controls a scan test in the circuit under test 100, and a holding unit 170 that holds the output signal. The test control section 146 performs a scan test on the circuit under test 100 when the analog circuit is in an active state. While the scan test is executed, the holding unit 170 holds the output signal after the signal for requesting the execution of the scan test is transmitted to the semiconductor integrated circuit 1 and before the scan test is started, and outputs the held output signal so that the analog circuit can maintain the active state.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] Conventionally, a scan test for diagnosing faults in logic circuits and the like in digital circuits has been known (see Patent Document 1). Patent Document 1 discloses a semiconductor integrated circuit including a logic circuit and a plurality of scan flip-flop circuits capable of forming a scan chain for performing a scan test on the logic circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-165780

[0004] [overview] However, the inventors have come to recognize the following problem: Some applications require that an analog circuit, which is to be controlled by a digital circuit that is the target of a scan test, continue to operate while a scan test is being performed. However, with the technology described in Patent Document 1, normal operation of the digital circuit is stopped while a scan test is being performed, and operation of the analog circuit cannot continue.

[0005] The present disclosure has been made in light of these circumstances, and one of its exemplary purposes is to provide a semiconductor integrated circuit that enables operation of an analog circuit to continue even while a scan test is being performed on a digital circuit.

[0006] A semiconductor integrated circuit according to one aspect of the present disclosure includes a circuit under test that is a digital circuit to be subjected to a scan test and generates an output signal for controlling the operation of an analog circuit in response to an input signal, a test control unit that controls the scan test in the circuit under test, and a holding unit that holds the output signal. The test control unit executes a scan test in the circuit under test in response to a signal requesting execution of a scan test being transmitted to the semiconductor integrated circuit when the analog circuit is in an active state. While the scan test is being performed, the holding unit holds the output signal after the signal requesting execution of the scan test was transmitted to the semiconductor integrated circuit but before the scan test was started, and outputs the held output signal so that the analog circuit can maintain the active state.

[0007] Any combination of the above components and conversion of the expression of the present disclosure between methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a semiconductor integrated circuit according to the first embodiment. [Figure 2] FIG. 2 is a block diagram of a digital block according to the embodiment. [Figure 3] FIG. 3 is a block diagram of a circuit under test according to the embodiment. [Figure 4] FIG. 4 is a block diagram for explaining an example of the configuration of the circuit under test, the first holding section, the second holding section, and the output selecting section. [Figure 5] FIG. 5 is a diagram illustrating an example of a circuit configuration of a scan flip-flop circuit. [Figure 6] FIG. 6 is a timing chart of each voltage in the semiconductor integrated circuit according to the first embodiment. [Figure 7] FIG. 7 is a timing chart showing an example of processing up to the scan test in the digital block according to the embodiment. [Figure 8]FIG. 8 is a flowchart showing an example of processing in the digital block according to the embodiment, from when a scan test is performed until the operation of the digital block returns to normal operation. [Figure 9] FIG. 9 is a flowchart showing an example of the flow of a scan test process according to the embodiment. [Figure 10] FIG. 10 is a block diagram of a digital block according to the second embodiment. [Figure 11] FIG. 11 is a diagram for explaining a process in which the third holding unit according to the embodiment acquires internal data of the circuit under test and a process in which the third holding unit returns the internal data to the circuit under test. [Figure 12] FIG. 12 is a timing chart showing an example of processing up to the scan test in the digital block according to the embodiment. [Figure 13] FIG. 13 is a flowchart showing an example of processing in the digital block according to the embodiment, from when a scan test is performed until the operation of the digital block returns to normal operation. [Figure 14] FIG. 14 is a block diagram illustrating a first holding unit according to the first modified example. [Figure 15] FIG. 15 is a block diagram of a second holding unit according to the second modified example.

[0009] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] A semiconductor integrated circuit according to one embodiment includes a circuit under test that is a digital circuit to be subjected to a scan test and that generates an output signal for controlling the operation of an analog circuit in response to an input signal, a test control unit that controls the scan test in the circuit under test, and a holding unit that holds the output signal. The test control unit executes a scan test in the circuit under test in response to a signal requesting execution of a scan test being transmitted to the semiconductor integrated circuit when the analog circuit is in an active state. While the scan test is being performed, the holding unit holds the output signal that was received after the signal requesting execution of the scan test was transmitted to the semiconductor integrated circuit but before the scan test was started, and outputs the held output signal so that the analog circuit can maintain the active state.

[0011] According to this configuration, by using the output signal output from the holding section, it is possible to continue operation in the analog circuit even while a scan test is being performed on the circuit under test.

[0012] In one embodiment, the holding unit may include a first holding unit that holds an input signal and a second holding unit that holds an output signal, and the first holding unit may hold the input signal corresponding to the output signal held in the second holding unit while the scan test is being performed.

[0013] In one embodiment, the circuit under test may have a plurality of scan flip-flop circuits and a logic circuit forming a scan chain. The scan flip-flop circuit may include a test data input terminal to which test data for a scan test is input and a normal data input terminal to which normal data different from the test data is input. The scan flip-flop circuit may be configured to be switchable between a first mode in which the normal data input terminal is enabled and the test data input terminal is disabled, and a second mode in which the normal data input terminal is disabled and the test data input terminal is enabled. The first holding unit and the second holding unit may each be configured using a scan flip-flop circuit that does not contribute to the scan chain.

[0014] In one embodiment, the second holding unit may include a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain. The signal holding circuit may be provided so that an output signal is input to the normal data input terminal and no data is input to the test data input terminal, and may hold the output signal in response to switching from the first mode to the second mode.

[0015] In one embodiment, the second holding unit may include a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain, and a multiplexer that selects one of the output signal of the signal holding circuit and the output signal generated by the circuit under test and inputs the selected signal to a data input terminal of the signal holding circuit. The multiplexer may select the output signal of the signal holding circuit while the scan test is being performed, thereby causing the output signal generated by the circuit under test to be held in the signal holding circuit in the first mode.

[0016] In one embodiment, the first holding unit may include a multiplexer having two input terminals and a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain. The multiplexer may be provided so that an input signal is input to one of the two input terminals and an output signal of the signal holding circuit is input to the other of the two input terminals. The multiplexer may select the output signal of the signal holding circuit while a scan test is being performed, thereby causing the input signal to be held in the signal holding circuit in the first mode.

[0017] In one embodiment, the first holding unit may include a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain. The signal holding circuit may hold an input signal by inputting a signal with and without a falling edge to a clock input terminal while a scan test is being performed.

[0018] In one embodiment, the semiconductor integrated circuit may further include an output selection section that selects one of the output signal generated by the circuit under test and the output signal held by the holding section, and outputs the selected signal. The output selection section may select the output signal held by the holding section while a scan test is being performed.

[0019] In one embodiment, the semiconductor integrated circuit may further include a communication interface that receives a signal requesting execution of a scan test. The circuit under test may include the communication interface.

[0020] In one embodiment, the semiconductor integrated circuit may further include a state control unit that controls a state of the circuit under test. The state control unit may cause the circuit under test to execute a predetermined process so that the circuit under test can generate an output signal for putting the analog circuit into an active state after the scan test is completed.

[0021] In one embodiment, the semiconductor integrated circuit may further include a third holding unit that holds internal data of the circuit under test. The internal data may be composed of internal signals of a plurality of scan flip-flop circuits that form a scan chain. The third holding unit may acquire and hold internal data corresponding to the output signal held in the second holding unit from the scan chain. The internal data held in the third holding unit may be returned to the scan chain after the scan test is completed.

[0022] In one embodiment, the semiconductor integrated circuit may further include a judgment unit that judges whether the result of the scan test is pass or fail, and a communication interface that transmits the judgment result if the judgment unit judges that the result is fail.

[0023] In one embodiment, the analog circuit may comprise a DC-to-voltage converter, and the active state may be a state in which the DC-to-voltage converter outputs a predetermined voltage.

[0024] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0025] In this specification, "component A is connected to component B" includes not only a case where component A and component B are directly physically connected, but also a case where component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0026] Similarly, "component C is connected (provided) between component A and component B" includes not only a case where component A and component C, or component B and component C, are directly connected, but also a case where they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0027] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0028] In this specification, "mono-integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are mono-integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate to adjust the circuit constants.

[0029] (First embodiment) FIG. 1 is a block diagram of a semiconductor integrated circuit 1 according to a first embodiment. The semiconductor integrated circuit 1 according to this embodiment is a PMIC (Power Management Integrated Circuit) for a vehicle. Note that the semiconductor integrated circuit 1 is not limited to a PMIC, and may be an integrated circuit capable of implementing various functions. The semiconductor integrated circuit 1 according to this embodiment includes a digital block 10, an analog block 20, and input / output pins T.

[0030] The digital block 10 has various digital circuits. The digital block 10 according to this embodiment executes various processes while transmitting and receiving various signals via input / output pins T. The digital block 10 receives an input signal S via, for example, SPI (Serial Peripheral Interface) communication. IN_SPI Receives or outputs signal S OUT_SPI or send messages.

[0031] The digital block 10 outputs a digital output signal S required for each analog circuit in the analog block 20. BUCK1 ,S BUCK2 ,S LDO1 ,S LDO2 and executes a Built-in Self Test (BIST), specifically a scan test. The detailed configuration of the digital block 10 will be described later with reference to FIG.

[0032] The analog block 20 has various analog circuits. In this embodiment, the analog block 20 has multiple DC voltage converters. These DC voltage converters convert the voltage generated by a primary power supply (not shown) (or a voltage obtained by stepping down this voltage) in accordance with the power supply voltage supplied from the system battery to generate a DC voltage. The generated DC voltage may be supplied to, for example, a vehicle MCU (Micro Controller Unit).

[0033] The DC voltage converter according to this embodiment is a first DC / DC converter 22, a second DC / DC converter 24, a first linear regulator 26, and a second linear regulator 28. In this embodiment, an example will be described in which the first DC / DC converter 22 and the second DC / DC converter 24 are each a step-down DC / DC converter, and the first linear regulator 26 and the second linear regulator 28 are each an LDO (Low Dropout) linear regulator.

[0034] The first DC / DC converter 22, the second DC / DC converter 24, the first linear regulator 26, and the second linear regulator 28 each receive a digital output signal S from the digital block 10. BUCK1 ,S BUCK2 ,S LDO1 ,S LDO2 output voltage V BUCK1 ,V BUCK2 ,V LDO1 ,V LDO2 The first DC / DC converter 22, the second DC / DC converter 24, the first linear regulator 26 and the second linear regulator 28 each generate a response signal S indicating their state as necessary. RES1 ,S RES2 ,S RES3 ,S RES4 may be transmitted to the digital block 10.

[0035] 2 is a block diagram of a digital block 10 according to the first embodiment. The digital block 10 has various digital circuits, specifically, a circuit under test 100, which is a digital circuit to be subjected to a scan test, and a test circuit 140 that performs processing related to the scan test. In this embodiment, the test circuit 140 is not subjected to the scan test.

[0036] The circuit under test 100 receives an input signal S IN1 output signal S for controlling the operation of analog circuits according to OUT1 The circuit under test 100 generates a state control signal S STT1 Various processes are performed according to the input signal S IN1Output signal S according to OUT1 and generate test data D TEST Scan data according to SCAN The output signal S generated by the circuit under test 100 is OUT1 is input to a second holding unit 170 and an output selection unit 174, which will be described later.

[0037] 3 is a block diagram of a circuit under test 100 according to the first embodiment. The circuit under test 100 includes a second state control section 102 and an output signal generation section 110.

[0038] The second state control unit 102 outputs the state control signal S STT1 For example, the second state control section 102 controls the state of the circuit under test 100 based on the state control signal S STT2 to the output signal generating unit 110, and outputs the output signal S to the output signal generating unit 110 so that the analog circuit is in an active state. DOUT Generate.

[0039] The output signal generating section 110 according to this embodiment includes a first output signal generating section 112, a second output signal generating section 114, a third output signal generating section 116, and a fourth output signal generating section 118. The first output signal generating section 112, the second output signal generating section 114, the third output signal generating section 116, and the fourth output signal generating section 118 each generate an output signal S BUCK1 ,S BUCK2 ,S LDO1 ,S LDO2 The output signal S BUCK1 ,S BUCK2 ,S LDO1 ,S LDO2 is the output signal S of the circuit under test 100. DOUT Configure.

[0040] 2, the following describes the configuration and functions of the test circuit 140. The test circuit 140 includes a communication interface 142, a first state control unit 144, a test control unit 146, a determination unit 148, a hold control unit 150, a first hold unit 160, a second hold unit 170, and an output selection unit 174.

[0041] The communication interface 142 transmits and receives various signals. The communication interface 142 according to this embodiment transmits and receives an input signal S IN_SPI and outputs signal S OUT_SPI Transmits the input signal S IN_SPI may include, for example, a signal requesting execution of a scan test (hereinafter also referred to as a "test request signal") and an input signal of the circuit under test 100. OUT_SPI may be, for example, a signal indicating the result of the scan test (e.g., a failed result). STA1 to the first state control section 144, and the input signal S IN2 can be transmitted to the first holding portion 160.

[0042] The communication interface 142 may receive a test request signal from an MCU (not shown), for example, when all analog circuits in the analog block 20 are in an active state. Here, the active state refers to a state in which the analog circuits are performing the functions they should perform. For example, if the analog circuits constitute a DC voltage converter, the active state refers to a state in which the DC voltage converter generates a predetermined output voltage and supplies the generated output voltage to another LSI (Large Scale Integration) or the like.

[0043] For example, in the case of a step-down DC / DC converter, if the output voltage generated by stepping down the input voltage is within a predetermined voltage range, the DC / DC converter can be in an active state. Similarly, in the case of a linear regulator, if the generated output voltage is within a predetermined voltage range, the linear regulator can be in an active state.

[0044] The first state control section 144 controls the state of the circuit under test 100 and transmits signals related to the scan test. For example, the first state control section 144 controls the state control signal S STT1 to the circuit under test 100 to control the state of the circuit under test 100. The first state control section 144 also transmits the test request signal SSTA2 to the test control section 146. Furthermore, the first state control section 144 can transmit the input signal S IN2 and the second holding section 170 holds the output signal S generated by the circuit under test 100. OUT1 A request signal S REQ1 can be transmitted to the holding control unit 150.

[0045] After the scan test is completed, the first state control unit 144 outputs an output signal S OUT1 When a scan test is performed, the internal data of the circuit under test 100 is changed, and in this state, the input signal S IN1 is input to the circuit under test 100, an appropriate output signal S OUT1 Therefore, in this embodiment, after the scan test is completed, the circuit under test 100 is made to execute the process that is executed when the semiconductor integrated circuit 1 is started up. As a result, the internal data of the circuit under test 100 generates the output signal S for putting the analog circuit into an active state. OUT1 , the circuit under test 100 is in a state suitable for generating the input signal S IN1 Depending on the OUT1 It is possible to generate

[0046] The test control section 146 controls the scan test in the circuit under test 100. Specifically, the test control section 146 controls the test data D TEST to the circuit under test 100, and transmits the scan data D SCAN When the scan test is completed, the test control unit 146 outputs a signal S END may be transmitted to the first state control unit 144.

[0047] When the analog circuit of the analog block 20 is in an active state, the test control section 146 executes a scan test on the circuit under test 100 in response to a signal requesting execution of a scan test being transmitted to the semiconductor integrated circuit 1. Specifically, the test control section 146 executes a scan test on the circuit under test 100 in response to a test request signal S STA2 In response to receiving the command, the scan test on the circuit under test 100 is started.

[0048] In this embodiment, the test control unit 146 starts a scan test on the circuit under test 100 when all analog circuits in the analog block 20 (i.e., the first DC / DC converter 22, the second DC / DC converter 24, the first linear regulator 26, and the second linear regulator 28) are in an active state.

[0049] The judging section 148 judges whether the scan test result of the circuit under test 100 is pass or fail. In this embodiment, the judging section 148 judges whether the scan data D output from the circuit under test 100 is pass or fail. SCAN Specifically, the pass / fail judgment is based on the scan data D SCAN and the correct data D to be output from the circuit under test 100. ANS and pass / fail is determined based on the comparison result.

[0050] For example, the determination unit 148 determines whether the scan data D SCAN and correct answer data D ANS If they match, the scan test result is judged as passed, and the scan data D SCAN and correct answer data D ANS If they do not match, the result of the scan test may be judged as a failure. For example, if a logic circuit in the circuit under test 100 has a stuck-at fault in which the output is fixed to high or low, the result of the scan test may be judged as a failure. The judgment unit 148 outputs a signal S DET may be communicated to the communication interface 142 and the test control unit 146.

[0051] The holding control unit 150 holds the input signal SIN2 and the output signal S OUT1 Specifically, the hold control unit 150 controls the hold of the control signal S CON1 to the first holding unit 160, and the first holding unit 160 receives the input signal S IN2 , or the input signal S held by the first holding unit 160. IN1 The released input signal S IN1 is input to the circuit under test 100.

[0052] The holding control unit 150 receives the control signal S CON2 to the second holding unit 170, and outputs the output signal S OUT1 When the first and second holding units 160 and 170 have completed holding the signals, the holding control unit 150 outputs a signal S NOT1 to the first state control unit 144. Furthermore, the hold control unit 150 transmits a selection signal S SEL1 can be transmitted to the output selection unit 174.

[0053] In response to a signal requesting execution of a scan test being transmitted to the semiconductor integrated circuit 1, the holding control unit 150 outputs an output signal S OUT1 is held in the second holding unit 170, and the output signal S OUT1 The input signal S corresponding to IN2 The holding control unit 150 holds the request signal S REQ1 In response to receiving the output signal S, the first holding unit 160 and the second holding unit 170 may hold the signal. OUT1 The input signal S corresponding to IN2 is its output signal S OUT1 The input signal S used in the circuit under test 100 to generate IN2 is.

[0054] The second holding section 170 holds the output signal S generated by the circuit under test 100. OUT1During the execution of the scan test, the second holding unit 170 holds the output signal S after a signal requesting the execution of the scan test is transmitted to the semiconductor integrated circuit 1 and before the scan test is started. OUT1 The output signal S is maintained so that the analog circuit can remain active while OUT2 The output signal S OUT2 is input to the output selection unit 174.

[0055] The second holding unit 170 is configured from a circuit that is not a target of the scan test. Therefore, the second holding unit 170 holds the output signal S OUT2 While maintaining the output signal S OUT2 This output signal S OUT2 By using this in analog circuits, it is possible to continue operating the analog circuits even while scan testing is being performed.

[0056] The output selection section 174 selects the output signal S generated by the circuit under test 100. OUT1 and the output signal S held by the second holding unit 170 OUT2 and outputs the selected output signal S DOUT While the scan test is being performed, the output selection unit 174 outputs the output signal S held by the second holding unit 170. OUT2 This allows the output signal S DOUT It is possible to continue the operation of the analog circuit using

[0057] The first holding unit 160 receives the input signal S IN2 The first holding section 160 according to this embodiment holds the output signal S held in the second holding section 170 while the scan test is being performed. OUT2 The input signal S corresponding to IN2 This allows the input signal S to be input to the circuit under test 100 after the scan test is completed to be stored. IN1 can be input from the first holding unit 160.

[0058] 4 is a block diagram for explaining an example configuration of the circuit under test 100, the first holding section 160, the second holding section 170, and the output selecting section 174. Note that a simplified version of the circuit under test 100 is shown in FIG.

[0059] The circuit under test 100 is configured by combining multiple scan flip-flop circuits and various logic circuits. The circuit under test 100 shown in FIG. 4 includes multiple scan flip-flop circuits 122, 124, and 126 that form a scan chain and a NOR circuit 128. Note that the logic circuit included in the circuit under test 100 is not limited to a NOR circuit and may be various known logic circuits, such as an AND circuit, an OR circuit, and a NOT circuit. The circuit under test 100 may also include multiple logic circuits. The number of scan flip-flop circuits that form the scan chain is not limited to three, but may be two, four, or more.

[0060] The scan flip-flop circuits 122, 124, and 126 include a test data input terminal (SD) to which test data for a scan test is input, and a normal data input terminal (D) to which normal data different from the test data is input. The scan flip-flop circuits 122, 124, and 126 are configured to be switchable between a capture mode (first mode) in which the normal data input terminal is enabled and the test data input terminal is disabled, and a shift mode (second mode) in which the normal data input terminal is disabled and the test data input terminal is enabled.

[0061] 5 is a diagram showing an example of the circuit configuration of the scan flip-flop circuit 130. The scan flip-flop circuits 122, 124, and 126 included in the circuit under test 100 and other scan flip-flop circuits shown in this specification have a configuration similar to that of the scan flip-flop circuit 130 shown in FIG.

[0062] As shown in FIG. 5, the scan flip-flop circuit 130 according to this embodiment includes a multiplexer 132 and a D flip-flop 134.

[0063] The multiplexer 132 has an input terminal corresponding to the normal data input terminal and an input terminal corresponding to the test data input terminal. SEL3 and selects a signal input to one of the normal data input terminal and the test data input terminal based on the selected signal S MUX2 The selection signal S SEL3 may be input from, for example, the test control unit 146 or the holding control unit 150. The output signal S MUX2 is input to the data input terminal of the D flip-flop 134. The D flip-flop 134 receives the signal S MUX2 and the output signal Q OUT Output.

[0064] 4, the configuration of the circuit under test 100 will be described. A first input terminal of the NOR circuit 128 is connected to the output terminal of the scan flip-flop circuit 122, a second input terminal of the NOR circuit 128 is connected to the output terminal of the scan flip-flop circuit 124, and an output terminal of the NOR circuit 128 is connected to the normal data input terminal of the scan flip-flop circuit 126. When the NOR circuit 128 operates normally, the NOR circuit 128 outputs a signal S obtained by NORing the output signal Q1 of the scan flip-flop circuit 122 and the output signal Q2 of the scan flip-flop circuit 124. NOR The signal S is output. NOR The output signal Q3 of the scan flip-flop circuit 126, which is normally input to the data input terminal, is the output signal S of the circuit under test 100. OUT1 (Q3=S OUT1 ).

[0065] The output terminal of the scan flip-flop circuit 122 is connected to the test data input terminal of the scan flip-flop circuit 124, and the output terminal of the scan flip-flop circuit 124 is connected to the test data input terminal of the scan flip-flop circuit 126. The three scan flip-flop circuits 122, 124, and 126 form a scan chain in the shift mode.

[0066] When the scan chain is formed, test data D is input to the test data input terminal of the scan flip-flop circuit 122. TEST By inputting the test data D TEST When a scan chain is formed, the scan data D SCAN Scan data D is output. SCAN is composed of output signals Q1 to Q3 of the scan flip-flop circuits 122, 124, and 126.

[0067] The first holding section 160 includes a multiplexer 162 having two input terminals, and a signal holding circuit 164 configured with a scan flip-flop circuit that does not contribute to the scan chain. The output terminal of the signal holding circuit 164 is connected to the normal data input terminal of the scan flip-flop circuit 122 of the circuit under test 100. The output signal Q0 of the signal holding circuit 164 is connected to the normal data input terminal of the scan flip-flop circuit 122 of the circuit under test 100. IN1 is input to the circuit under test 100 (Q0=S IN1 ).

[0068] The signal hold circuit 164 and the scan flip-flop circuit 122 form a synchronizer composed of two stages of scan flip-flop circuits. In this embodiment, an example in which the synchronizer is composed of two stages of scan flip-flop circuits will be described, but the synchronizer may be composed of three or more stages of scan flip-flop circuits. In this case, the first stage of scan flip-flop circuits may form the signal hold circuit, and the second and subsequent stages of scan flip-flop circuits may contribute to the scan chain of the circuit under test.

[0069] The multiplexer 162 receives the input signal S at one of its two input terminals. IN2 The multiplexer 162 is provided so that an output signal Q0 of the signal holding circuit 164 is input to the other of the two input terminals. The output terminal of the multiplexer 162 is connected to the normal data input terminal of the signal holding circuit 164. The signal selected by the multiplexer 162 is, for example, a control signal S from the holding control unit 150. CON1 The selection signal S included in SEL2 may be determined by

[0070] The signal holding circuit 164 holds the input signal S IN2 The signal hold circuit 164 is in capture mode when it holds the input signal S. The multiplexer 162 selects the output signal Q0 of the signal hold circuit 164 while the scan test is being performed. IN2 When the multiplexer 162 selects the output signal Q0, the signal S MUX1 , Q0 loops in the first holding unit 160, and the input signal S IN2 is held in the signal holding circuit 164.

[0071] The second holding unit 170 includes a signal holding circuit 172 configured from a scan flip-flop circuit that does not contribute to the scan chain.

[0072] The signal holding circuit 172 is provided so that the output signal Q3 of the circuit under test 100 is input to the data input terminal, and no data is input to the test data input terminal. OUT2 is input to the output selection unit 174. The signal hold circuit 172 holds the output signal Q3 in response to switching from the capture mode to the shift mode. Since no data is input to the test data input terminal of the signal hold circuit 172, the internal signal of the signal hold circuit 172 does not change in the shift mode, and the output signal Q3 can be held.

[0073] The output selection section 174 is configured as a multiplexer having two input terminals. One of the two input terminals receives the output signal Q3 of the circuit under test 100, and the other input terminal receives the output signal S held by the signal holding circuit 172. OUT2 The signal selected by this multiplexer is the control signal S CON2 The selection signal S included in SEL1 may be determined by

[0074] In normal operation, the multiplexer operates such that the circuit under test 100 receives the input signal S IN1 (output signal Q0) OUT1 (output signal Q3) and select the output signal S DOUT to the analog circuit. This allows the analog circuit to output the input signal S IN2 On the other hand, the multiplexer can operate in response to the output signal S held by the signal holding circuit 172 while the scan test is being performed. OUT2 This allows the output signal S generated by the circuit under test 100 to be output even during the scan test. OUT1 Based on this, it becomes possible to continue the operation of the analog circuit.

[0075] 6 is a timing chart of each voltage in the semiconductor integrated circuit 1 according to the first embodiment. SYS , the output voltage V of the first DC / DC converter 22 BUCK1 , the output voltage V of the second DC / DC converter 24 BUCK2 , the output voltage V of the first linear regulator 26 LDO1 and the output voltage V of the second linear regulator 28 LDO2 6 shows the voltages from when the semiconductor integrated circuit 1 starts to start up until all analog circuits are in the active state.

[0076] Before timing t1, the semiconductor integrated circuit 1 is in a reset state (RST), and the battery output voltage V SYSAt timing t1, the semiconductor integrated circuit 1 starts up, and the battery output voltage V SYS rises to reach a predetermined voltage V1, and a scan test (D_BIST) is performed on the circuit under test 100. The scan test will be described in detail later.

[0077] At timing t2, the scan test is completed, the "START UP" process is performed, and the output signal S of the digital block 10 DOUT In response to this, the output voltages of the analog circuits rise in a predetermined order, and by timing t3, the output voltages of all the analog circuits reach the predetermined voltages (V2 to V5).

[0078] After timing t3, the "ACTIVE" process is performed, and all analog circuits are set to the active state. In this embodiment, it is possible to perform a scan test again while maintaining all analog circuits in the active state.

[0079] 7 is a timing chart showing an example of processing up to the scan test in the digital block 10 according to the first embodiment. When this processing starts, all analog circuits are assumed to be in an active state. When this processing starts, the circuit under test 100, the first holding section 160, the second holding section 170, and each scan flip-flop circuit of the circuit under test 100 are in a capture mode, and the output selection section 174 selects the output signal S generated by the circuit under test 100. OUT1 is assumed to be selected.

[0080] First, the communication interface 142 receives a request to execute a scan test (S101). At this time, the communication interface 142 transmits a test request signal S STA1 to the first state control unit 144.

[0081] Next, the first state control section 144 controls the input signal S IN2 is held in the first holding section 160, and the output signal SOUT1 The holding control section 150 then requests the second holding section 170 to hold the input signal S IN2 is held in the first holding section 160, and the output signal S OUT1 is held by the second holding unit 170 (S105).

[0082] Next, the holding control unit 150 calculates the output signal S held by the second holding unit 170. OUT2 Next, the output selection unit 174 requests the output selection unit 174 to select the output signal S held in the second holding unit 170 (S107). OUT2 Select to output the selected output signal S DOUT to the analog circuit (S109). As a result, even if a scan test is performed, the analog circuit does not receive the output signal S DOUT It is possible to keep the analog circuitry active using

[0083] Next, the holding control section 150 receives the input signal S IN2 and the output signal S of the circuit under test 100 OUT1 The first state control unit 144 then notifies the first state control unit 144 that the holding of the data has been completed (S111). Next, the first state control unit 144 requests the test control unit 146 to execute a scan test (S113). Next, the scan test process is performed (S115).

[0084] FIG. 8 is a flowchart showing an example of processing in the digital block 10 according to the first embodiment, from when a scan test is performed until the operation of the digital block 10 returns to normal operation.

[0085] When the scan test process (S115) is completed, the determination unit 148 notifies the test control unit 146 of the pass / fail determination result of the scan test (S201). At this time, if the result of the scan test is a fail, the determination unit 148 may notify the communication interface 142 of the determination result. This allows the communication interface 142 to notify the outside that the result of the scan test is a fail. Next, the test control unit 146 notifies the first state control unit 144 that the scan test has been completed (S203).

[0086] Next, the first state control unit 144 outputs an output signal S OUT1 In this embodiment, the first state control unit 144 causes the circuit under test 100 to execute the processes of "START UP" and "ACTIVE."

[0087] Next, the first state control unit 144 converts the input signal S held in the first holding unit 160 IN1 Next, the holding control unit 150 requests the first holding unit 160 to release the input signal S IN1 (S209). The released input signal S IN1 is input to the circuit under test 100. As a result, the circuit under test 100 receives the input signal S released from the first holding section 160. IN1 Output signal S according to OUT1 will be generated.

[0088] Next, the holding control section 150 detects the output signal S generated by the circuit under test 100. OUT1 The output selection section 174 selects the output signal S generated by the circuit under test 100 (S211). OUT1 Select to output the selected output signal S DOUT to the analog circuit (S213). Next, the hold control unit 150 notifies that normal operation is now possible (S215).

[0089] FIG. 9 is a flowchart showing an example of the flow of the scan test process (S115) according to the first embodiment.

[0090] First, the test control section 146 sets each scan flip-flop circuit of the circuit under test 100 to a shift mode (S121). As a result, a scan chain is formed by the plurality of scan flip-flop circuits of the circuit under test 100. Next, the test control section 146 inputs test data D TEST (S123).

[0091] Next, the test control section 146 sets each scan flip-flop circuit of the circuit under test 100 to a capture mode (S125). At this time, for example, the scan flip-flop circuit 126 captures the output signal S NOR Next, the test control section 146 puts each scan flip-flop circuit of the circuit under test 100 into shift mode (S127).

[0092] Next, the determination unit 148 determines the scan data D output from the scan chain. SCAN Next, the test control section 146 sets each scan flip-flop circuit of the circuit under test 100 to a capture mode (S131). Next, the judging section 148 acquires the scan data D acquired in S129. SCAN The result of the scan test is determined based on the result (S133).

[0093] The configuration and operation of the semiconductor integrated circuit 1 according to this embodiment have been described above. According to the semiconductor integrated circuit 1 according to this embodiment, the test control section 146 executes a scan test on the circuit under test 100 in response to a signal requesting execution of a scan test being transmitted to the semiconductor integrated circuit 1 when the analog circuit is in an active state. Furthermore, while the scan test is being executed, the second holding section 170 holds the output signal S OUT1The output signal S is maintained so that the analog circuit can remain active while OUT2 Output.

[0094] According to this configuration, the output signal S output from the second holding unit 170 OUT2 By using this, it is possible to continue operation of the analog circuit even while a scan test is being performed on the circuit under test 100. Furthermore, when the semiconductor integrated circuit 1 is a PMIC as in this embodiment, it is possible to perform a scan test while the primary power supply is turned on, and it is possible to reliably ensure functional safety while the analog circuit is operating.

[0095] (Second embodiment) 10 is a block diagram of a digital block 12 according to the second embodiment. The digital block 12 according to the second embodiment differs from the digital block 10 according to the first embodiment mainly in that the test circuit 141 further includes a third holding unit 180 that holds internal data of the circuit under test 100. The semiconductor integrated circuit according to the second embodiment may have a configuration similar to that of the analog block 20 according to the first embodiment.

[0096] The first state control unit 145 according to this embodiment receives the input signal S IN2 is held in the first holding unit 160, and the output signal S OUT1 In addition to storing the internal data D INT The request signal S REQ2 The internal data D of the circuit under test 100 can be transmitted to the holding control section 152. INT is composed of internal signals of a plurality of scan flip-flop circuits that form the scan chain of the circuit under test 100.

[0097] The hold control unit 152 according to this embodiment outputs a control signal S CON3When the first holding unit 160, the second holding unit 170, and the third holding unit 180 have completed holding the signal or data, the third holding unit 180 generates a signal S NOT2 can be transmitted to the first state control unit 145.

[0098] The third holding unit 180 has a plurality of flip-flop circuits. The third holding unit 180 may include a static random-access memory (SRAM) or the like as necessary, for example, when the amount of data to be held is large. When an SRAM is used, the third holding unit 180 may be provided outside the semiconductor integrated circuit.

[0099] The third holding unit 180 holds the output signal S OUT1 Internal data D corresponding to INT is acquired from the scan chain and held. The output signal S OUT1 Internal data D corresponding to INT is its output signal S OUT1 The internal data D INT This internal data D INT is data after a signal requesting execution of a scan test has been transmitted to the semiconductor integrated circuit and before the scan test is started. The third holding unit 180 holds the internal data D INT Continue to hold.

[0100] The internal data held by the third holding section 180 is returned to the scan chain after the scan test is completed. This allows the internal state of the circuit under test 100 to be returned to the state before the scan test was started. As a result, the circuit under test 100 receives the input signal S IN1 Depending on the OUT1 will be able to generate.

[0101] FIG. 11 shows a configuration in which the third holding section 180 according to the second embodiment holds the internal data D INT and the third holding unit 180 acquires the internal data DINT 10 is a diagram for explaining a process of returning the signal to the circuit under test 100.

[0102] Internal data D of the circuit under test 100 INT When the third holding unit 180 acquires the data, the scan flip-flop circuits 122, 124, and 126 are each placed in a shift mode and form a scan chain. When the scan chain is formed, the output signals Q1 to Q3 of the scan flip-flop circuits 122, 124, and 126 are output in order from the output terminal of the scan flip-flop circuit 126, and the internal data D INT The third holder 180 holds the same.

[0103] The internal data D held by the third holding unit 180 INT When returning the internal data D to the circuit under test 100, the scan flip-flop circuits 122, 124, and 126 form a scan chain, and the internal data D is output from the scan data input terminal of the scan flip-flop circuit 122. INT Specifically, scan data D is input from the scan data input terminal of the scan flip-flop circuit 122. INT By inputting the output signals Q3, Q2 and Q1 in this order, the internal data D INT is returned to the circuit under test 100.

[0104] 12 is a timing chart showing an example of processing up to the scan test in the digital block 12 according to the second embodiment. When this processing starts, all analog circuits are assumed to be in an active state. When this processing starts, the circuit under test 100, the first holding section 160, the second holding section 170, and each scan flip-flop circuit of the circuit under test 100 are operating in a capture mode, and the output selection section 174 selects the output signal S generated by the circuit under test 100 as the OUT1 is assumed to be selected.

[0105] First, the communication interface 142 receives a request to execute a scan test (S301). Next, in response to the communication interface 142 receiving the request for the scan test, the first state control unit 145 controls the input signal S IN2 is held in the first holding section 160, and the output signal S OUT1 is held in the second holding section 170, and the internal data D INT The holding control section 152 then requests the third holding section 180 to hold the input signal S IN2 is held in the first holding section 160, and the output signal S OUT1 is held in the second holding section 170, and the internal data D INT is held by the third holding unit 180 (S305).

[0106] Next, the holding control unit 152 calculates the output signal S held by the second holding unit 170. OUT2 Next, the output selection unit 174 requests the output selection unit 174 to select the output signal S held in the second holding unit 170 (S307). OUT2 Select to output the selected output signal S DOUT is output to the analog circuit (S309).

[0107] Next, the holding control section 152 receives the input signal S IN2 , and the output signal S of the circuit under test 100 OUT1 and the internal signal D of the circuit under test 100 INT The first state control unit 145 then notifies the first state control unit 145 that the holding of the data has been completed (S311). Next, the first state control unit 145 requests the test control unit 146 to execute a scan test (S313). Next, the scan test process is performed (S315). The scan test process (S315) is substantially the same as the scan test process (S115) according to the first embodiment, and therefore a description thereof will be omitted here.

[0108] FIG. 13 is a flowchart showing an example of processing in the digital block 12 according to the second embodiment, from when a scan test is performed until the operation of the digital block 12 returns to normal operation.

[0109] When the scan test process (S315) is completed, the determination unit 148 notifies the test control unit 146 of the pass / fail determination result of the scan test (S401). Next, the test control unit 146 notifies the first state control unit 145 that the scan test has been completed (S403).

[0110] Next, the first state control unit 145 reads the internal data D of the circuit under test 100 held in the third holding unit 180. INT The holding control section 152 then requests the holding control section 152 to return the internal data D of the scan chain of the circuit under test 100 held in the third holding section 180 to the scan chain of the circuit under test 100 (S405). INT is returned to the circuit under test 100 (S407).

[0111] Thereafter, the processes of S409 to S415 are carried out, but since these processes are substantially the same as the processes of S209 to S215 according to the first embodiment, a description thereof will be omitted here.

[0112] The configuration and operation of the digital block 12 according to the second embodiment have been described above. According to the digital block 12 according to this embodiment, the third holding unit 180 holds the output signal S OUT1 Internal data D corresponding to INT The internal data D held in the third holding unit 180 is acquired from the scan chain and held. INT is returned to the scan chain after the scan test is completed.

[0113] According to this configuration, the circuit under test 100 can be restored simply by returning the internal data held in the third holding unit 180 to the scan flip-flop circuits that form the scan chain. Therefore, unlike the first embodiment, there is no need to make the circuit under test 100 execute startup processing after the scan test is completed, and the circuit under test 100 can be restored at high speed.

[0114] (First Modification) 14 is a block diagram illustrating a first holding section 161 according to the first modification. The first holding section 161 according to the first modification may be provided in a digital block, replacing the first holding section 160 according to the above embodiment. As shown in FIG. 14, the first holding section 161 according to the first modification includes a signal holding circuit 164 configured with a scan flip-flop circuit that does not contribute to the scan chain of the circuit under test 100, and an AND circuit 166.

[0115] The first input terminal of the AND circuit 166 receives the selection signal S SEL4 The second input terminal of the AND circuit 166 receives the inverted clock signal S CLK is input to the AND circuit 166. AND is input to the clock signal input terminal of the signal holding circuit 164. The selection signal S SEL4 may be generated by the retention control units 150 and 152.

[0116] Selection signal S SEL4 is low, the output signal S of the AND circuit 166 AND is the clock signal S CLK Selection signal S SEL4 is high, the output signal S of the AND circuit 166 AND becomes a signal that does not include rising edges and falling edges, specifically, becomes a low signal. The signal holding circuit 164 holds a signal that does not include falling edges and falling edges (output signal S AND) is input, the input signal S IN Hold.

[0117] (Second Modification) 15 is a block diagram of a second holding unit 171 according to the second modification. The second holding unit 171 according to the second modification may be provided in a digital block, replacing the second holding unit 170 according to the above embodiment. As shown in FIG. 15, the second holding unit 171 according to the second modification includes a multiplexer 176 and a signal holding circuit 178 configured with a scan flip-flop circuit that does not contribute to the scan chain.

[0118] The multiplexer 176 selects one of the output signal Q4 of the signal holding circuit 178 and the output signal Q3 generated by the circuit under test 100, and outputs the selected signal S MUX3 is input to the data input terminal of the signal hold circuit 178. While the scan test is being performed, the multiplexer 176 selects the output signal Q4 of the signal hold circuit 178, thereby causing the output signal Q3 generated by the circuit under test 100 to be held in the signal hold circuit 178 in the capture mode. The signal selected by the multiplexer 176 is, for example, the selection signal S generated by the hold control units 150 and 152. SEL5 may be determined by

[0119] (Third Modification) In the above embodiment, an example has been described in which the communication interface 142 is not subject to scan testing. However, the present invention is not limited to this, and the communication interface 142 may be a digital circuit that is subject to scan testing. In other words, the circuit under test may include a communication interface.

[0120] (Fourth Modification) The processes described with reference to the above flowcharts may be executed in a different order as needed, and multiple processes may be executed in parallel.

[0121] (supplement) Although the embodiments according to the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention. For example, one or more elements of one embodiment can be combined with one or more elements of another embodiment.

[0122] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0123] (Item 1) A semiconductor integrated circuit, a circuit under test, which is a digital circuit to be subjected to scan testing, that generates an output signal for controlling the operation of an analog circuit in response to an input signal; a test control unit that controls a scan test in the circuit under test; a holding unit that holds the output signal, the test control unit executes a scan test on the circuit under test in response to a signal requesting execution of the scan test being transmitted to the semiconductor integrated circuit when the analog circuit is in an active state; the holding unit holds the output signal after a signal requesting execution of the scan test has been transmitted to the semiconductor integrated circuit and before the scan test is started, while the scan test is being executed, and outputs the held output signal so that the analog circuit can maintain an active state. Semiconductor integrated circuit.

[0124] (Item 2) the holding unit includes a first holding unit that holds the input signal and a second holding unit that holds the output signal; the first holding unit holds the input signal corresponding to the output signal held in the second holding unit while the scan test is being performed. Item 1. The semiconductor integrated circuit according to item 1.

[0125] (Item 3) the circuit under test has a plurality of scan flip-flop circuits and a logic circuit forming a scan chain; the scan flip-flop circuit includes a test data input terminal to which test data for the scan test is input, and a normal data input terminal to which normal data different from the test data is input, and is configured to be switchable between a first mode in which the normal data input terminal is enabled and the test data input terminal is disabled, and a second mode in which the normal data input terminal is disabled and the test data input terminal is enabled; the first holding unit and the second holding unit are each configured using a scan flip-flop circuit that does not contribute to the scan chain. Item 2. The semiconductor integrated circuit according to item 2.

[0126] (Item 4) the second holding unit includes a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain; the signal holding circuit is provided so that the output signal is input to the normal data input terminal and no data is input to the test data input terminal, and holds the output signal in response to switching from the first mode to the second mode. Item 3. The semiconductor integrated circuit according to item 3.

[0127] (Item 5) the second holding unit includes a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain, and a multiplexer that selects one of the output signal of the signal holding circuit and the output signal generated by the circuit under test, and inputs the selected signal to a data input terminal of the signal holding circuit; the multiplexer selects the output signal of the signal hold circuit while the scan test is being performed, thereby causing the signal hold circuit in a first mode to hold the output signal generated by the circuit under test; Item 3. The semiconductor integrated circuit according to item 3.

[0128] (Item 6) the first holding unit includes a multiplexer having two input terminals and a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain; the multiplexer is provided so that the input signal is input to one of the two input terminals and the output signal of the signal hold circuit is input to the other of the two input terminals, and while the scan test is being performed, the multiplexer selects the output signal of the signal hold circuit to hold the input signal in the signal hold circuit in a first mode. 6. The semiconductor integrated circuit according to any one of items 3 to 5.

[0129] (Item 7) the first holding unit includes a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain; the signal hold circuit holds the input signal by inputting a signal having a falling edge and not having a falling edge to a clock input terminal while the scan test is being performed; 6. The semiconductor integrated circuit according to any one of items 3 to 5.

[0130] (Item 8) an output selection unit that selects one of the output signal generated by the circuit under test and the output signal held by the holding unit, and outputs the selected signal; the output selection unit selects the output signal held by the holding unit while the scan test is being executed. 8. The semiconductor integrated circuit according to any one of items 1 to 7.

[0131] (Item 9) a communication interface for receiving a signal requesting execution of the scan test; the circuit under test includes the communication interface; 9. The semiconductor integrated circuit according to any one of items 1 to 8.

[0132] (Item 10) a state control unit for controlling the state of the circuit under test; the state control unit causes the circuit under test to execute a predetermined process so that the circuit under test can generate an output signal for putting the analog circuit into an active state after the scan test is completed; 10. The semiconductor integrated circuit according to any one of items 1 to 9.

[0133] (Item 11) a third holding unit for holding internal data of the circuit under test; the internal data is composed of internal signals of a plurality of scan flip-flop circuits forming the scan chain; the third holding unit acquires from the scan chain internal data corresponding to the output signal held in the second holding unit and holds the internal data; The internal data held in the third holding unit is returned to the scan chain after the scan test is completed. 8. The semiconductor integrated circuit according to any one of items 3 to 7.

[0134] (Item 12) a determination unit that determines whether a result of the scan test is pass or fail; and a communication interface for transmitting the judgment result when the judgment result of the judgment unit is unacceptable. 12. The semiconductor integrated circuit according to any one of items 1 to 11.

[0135] (Item 13) the analog circuit constitutes a DC voltage converter; The active state is a state in which the DC voltage converter outputs a predetermined voltage. 13. The semiconductor integrated circuit according to any one of items 1 to 12. [Explanation of symbols]

[0136] 1 Semiconductor integrated circuit, 10, 12 Digital block, 20 Analog block, 22 First DC / DC converter, 24 Second DC / DC converter, 26 First linear regulator, 28 Second linear regulator, 100 Circuit under test, 102 Second state control unit, 110 Output signal generation unit, 120 Synchronizer, 122, 124, 126, 130 Scan flip-flop circuit, 128 NOR circuit, 132 Multiplexer, 134 D flip-flop, 140, 141 Test circuit, 142 Communication interface, 144, 145 First state control unit, 146 Test control unit, 148 Judgment unit, 150, 152 Hold control unit, 160, 161 First hold unit, 162 Multiplexer, 164 Signal hold circuit, 166 AND circuit, 170, 171 Second hold unit, 172, 178 Signal holding circuit, 174 output selection unit, 176 multiplexer, 180 third holding unit.

Claims

1. A semiconductor integrated circuit, a circuit under test, which is a digital circuit to be subjected to scan testing, that generates an output signal for controlling the operation of an analog circuit in response to an input signal; a test control unit that controls a scan test in the circuit under test; a holding unit that holds the output signal, the test control unit executes a scan test on the circuit under test in response to a signal requesting execution of the scan test being transmitted to the semiconductor integrated circuit when the analog circuit is in an active state; the holding unit holds the output signal after a signal requesting execution of the scan test has been transmitted to the semiconductor integrated circuit and before the scan test is started, while the scan test is being executed, and outputs the held output signal so that the analog circuit can maintain an active state. Semiconductor integrated circuit.

2. the holding unit includes a first holding unit that holds the input signal and a second holding unit that holds the output signal; the first holding unit holds the input signal corresponding to the output signal held in the second holding unit while the scan test is being performed.

2. The semiconductor integrated circuit according to claim 1.

3. the circuit under test has a plurality of scan flip-flop circuits and a logic circuit forming a scan chain; the scan flip-flop circuit includes a test data input terminal to which test data for the scan test is input, and a normal data input terminal to which normal data different from the test data is input, and is configured to be switchable between a first mode in which the normal data input terminal is enabled and the test data input terminal is disabled, and a second mode in which the normal data input terminal is disabled and the test data input terminal is enabled; the first holding unit and the second holding unit are each configured using a scan flip-flop circuit that does not contribute to the scan chain.

3. The semiconductor integrated circuit according to claim 2.

4. the second holding unit includes a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain; the signal holding circuit is provided so that the output signal is input to the normal data input terminal and no data is input to the test data input terminal, and holds the output signal in response to switching from the first mode to the second mode.

4. The semiconductor integrated circuit according to claim 3.

5. the second holding unit includes a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain, and a multiplexer that selects one of an output signal from the signal holding circuit and an output signal generated by the circuit under test, and inputs the selected signal to a data input terminal of the signal holding circuit; the multiplexer selects the output signal of the signal hold circuit while the scan test is being performed, thereby causing the signal hold circuit in the first mode to hold the output signal generated by the circuit under test; 4. The semiconductor integrated circuit according to claim 3.

6. the first holding unit includes a multiplexer having two input terminals and a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain; the multiplexer is provided so that the input signal is input to one of the two input terminals and the output signal of the signal hold circuit is input to the other of the two input terminals, and while the scan test is being performed, the multiplexer selects the output signal of the signal hold circuit to hold the input signal in the signal hold circuit in a first mode.

4. The semiconductor integrated circuit according to claim 3.

7. the first holding unit includes a signal holding circuit configured with a scan flip-flop circuit that does not contribute to the scan chain; the signal hold circuit holds the input signal by inputting a signal having a falling edge and not having a falling edge to a clock input terminal while the scan test is being performed; 4. The semiconductor integrated circuit according to claim 3.

8. an output selection unit that selects one of the output signal generated by the circuit under test and the output signal held by the holding unit, and outputs the selected signal; the output selection unit selects the output signal held by the holding unit while the scan test is being executed.

2. The semiconductor integrated circuit according to claim 1.

9. a communication interface for receiving a signal requesting execution of the scan test; the circuit under test includes the communication interface; 2. The semiconductor integrated circuit according to claim 1.

10. a state control unit for controlling the state of the circuit under test; the state control unit causes the circuit under test to execute a predetermined process so that the circuit under test can generate an output signal for putting the analog circuit into an active state after the scan test is completed; 2. The semiconductor integrated circuit according to claim 1.

11. a third holding unit for holding internal data of the circuit under test; the internal data is composed of internal signals of a plurality of scan flip-flop circuits forming the scan chain; the third holding unit acquires from the scan chain internal data corresponding to the output signal held by the second holding unit and holds the internal data; The internal data held in the third holding unit is returned to the scan chain after the scan test is completed.

4. The semiconductor integrated circuit according to claim 3.

12. a determination unit that determines whether a result of the scan test is pass or fail; and a communication interface for transmitting the judgment result when the judgment result of the judgment unit is unacceptable.

2. The semiconductor integrated circuit according to claim 1.

13. the analog circuit constitutes a DC voltage converter; The active state is a state in which the DC voltage converter outputs a predetermined voltage.

2. The semiconductor integrated circuit according to claim 1.

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