Semiconductor device

Abstract

To provide a semiconductor device capable of reducing thermal stress acting on an insulating base material.SOLUTION: The semiconductor device includes a substrate 40,50, a semiconductor element 30, and a resin molded body 20. The insulating base 41,51 of the substrate 40,50 has an exposed surface that is exposed between adjacent wirings of the surface metal body 42,52. The portion located between the insulating base materials 4151 and includes a bonded portion 90, an element portion 91, and a joint portion 92. The element portion 91 and the joint portion 92 each include a solder 93. The total thickness of the solder 93 is larger in the joint portion 92 than in the element portion 91.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] TECHNICAL FIELD The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a substrate having wiring arranged on the surface of an insulating layer (insulating base material) and a heat dissipation layer arranged on the back surface of the insulating layer, a semiconductor element connected to the wiring, and a resin molded body that encapsulates the substrate and the semiconductor element. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 119226 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device described in Patent Document 1 includes two substrates arranged to sandwich a semiconductor element. For example, the insulating base is exposed between the wiring connected to the upper arm IGBT and the wiring connected to the lower arm IGBT. When the insulating base is made of resin, the resin molded body adheres closely to the insulating base, thereby ensuring an insulation distance through solid insulation.

[0005] In molding a resin molded body, a curing process such as heating is required to complete the reaction of unreacted portions. The resin molded body is completely hardened by the curing process, and the linear expansion coefficient of the resin molded body after the curing process is smaller than that before the curing process. Before the curing process, the linear expansion coefficient of the resin molded body is larger than that of the insulating substrate containing the wiring and resin. Therefore, when the resin temperature drops before the curing process, i.e., when the resin molded body shrinks, thermal stress may concentrate at the triple points of the insulating substrate, wiring, and resin molded body. Further improvements are required in semiconductor devices in terms of the above and other aspects not mentioned.

[0006] One object of the present disclosure is to provide a semiconductor device that can reduce thermal stress acting on an insulating substrate. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the disclosure includes: a substrate (40, 50) having an insulating base material (41, 51) containing a resin, a front surface metal body (42, 52) arranged on the front surface of the insulating base material and patterned, and a rear surface metal body (43, 53) arranged on the rear surface of the insulating base material; a semiconductor element (30) having main electrodes (31, 32) respectively provided on a first main surface (301) and a second main surface (302) opposite the first main surface in the plate thickness direction, the semiconductor element (30) being electrically connected to the surface metal body; a resin molding (20) that encapsulates the substrate and the semiconductor element; Equipped with The substrate includes a first substrate arranged to face the first main surface and having a first insulating substrate that is an insulating substrate and a first surface metal body that is a surface metal body, and a second substrate arranged to face the second main surface and having a second insulating substrate that is an insulating substrate and a second surface metal body that is a surface metal body, At least one of the first insulating base material and the second insulating base material has an exposed surface (411, 511) exposed between adjacent wirings of the surface metal body, The portion located between the first insulating base material and the second insulating base material includes an adhesive portion (90) including a resin molded body adhered to the exposed surface, an element portion (91) in which a semiconductor element is interposed between the first surface metal body and the second surface metal body, and a joint portion (92) that electrically connects the portions of the first surface metal body and the second surface metal body that are at the same potential, The difference in shrinkage between the joint portion and the adhesive portion is smaller than the difference in shrinkage between the element portion and the adhesive portion.

[0008] In the disclosed semiconductor device, the difference in shrinkage between the adhesive portion and the joint portion is smaller than that between the element portion, which reduces the thermal stress acting on the insulating base material compared to a configuration in which the difference in shrinkage between the adhesive portion and the joint portion is larger than that between the element portion and the joint portion.

[0009] Another aspect of the disclosed semiconductor device includes: a substrate (40, 50) having an insulating base material (41, 51) containing a resin, a front surface metal body (42, 52) arranged on the front surface of the insulating base material and patterned, and a rear surface metal body (43, 53) arranged on the rear surface of the insulating base material; a semiconductor element (30) having main electrodes (31, 32) respectively provided on a first main surface (301) and a second main surface (302) opposite the first main surface in the plate thickness direction, the semiconductor element (30) being electrically connected to the surface metal body; a resin molding (20) that encapsulates the substrate and the semiconductor element; Equipped with The substrate includes a first substrate arranged to face the first main surface and having a first insulating substrate that is an insulating substrate and a first surface metal body that is a surface metal body, and a second substrate arranged to face the second main surface and having a second insulating substrate that is an insulating substrate and a second surface metal body that is a surface metal body, At least one of the first insulating base material and the second insulating base material has an exposed surface (411, 511) exposed between adjacent wirings of the surface metal body, The portion located between the first insulating base material and the second insulating base material includes an adhesive portion (90) including a resin molded body adhered to the exposed surface, an element portion (91) in which a semiconductor element is interposed between the first surface metal body and the second surface metal body, and a joint portion (92) that electrically connects the portions of the first surface metal body and the second surface metal body that are at the same potential, The element portion and the joint portion each include solder (93); The total thickness of the solder is greater in the joint portion than in the element portion.

[0010] In the disclosed semiconductor device, the amount of shrinkage of the joint portion can be made closer to the amount of shrinkage of the adhesive portion during the formation of the resin molded body, compared to a configuration in which the total thickness of the solder at the joint portion is equal to or less than the thickness of the element portion, thereby reducing the thermal stress acting on the insulating base material.

[0011] Another aspect of the disclosed semiconductor device includes: a substrate (40, 50) having an insulating base material (41, 51) containing a resin, a front surface metal body (42, 52) arranged on the front surface of the insulating base material and patterned, and a rear surface metal body (43, 53) arranged on the rear surface of the insulating base material; a semiconductor element (30) having main electrodes (31, 32) respectively provided on a first main surface (301) and a second main surface (302) opposite the first main surface in the plate thickness direction, the semiconductor element (30) being electrically connected to the surface metal body; a resin molding (20) that encapsulates the substrate and the semiconductor element; Equipped with The substrate includes a first substrate arranged to face the first main surface and having a first insulating substrate that is an insulating substrate and a first surface metal body that is a surface metal body, and a second substrate arranged to face the second main surface and having a second insulating substrate that is an insulating substrate and a second surface metal body that is a surface metal body, At least one of the first insulating base material and the second insulating base material has an exposed surface (411, 511) exposed between adjacent wirings of the surface metal body, The portion located between the first insulating base material and the second insulating base material includes an adhesive portion (90) including a resin molded body adhered to the exposed surface, an element portion (91) in which a semiconductor element is interposed between the first surface metal body and the second surface metal body, and a joint portion (92) that electrically connects the portions of the first surface metal body and the second surface metal body that are at the same potential, The joint portion includes a metal member (94) and a solder (93) interposed between the metal member and the surface metal body, The metal member extends to a position overlapping with the exposed surface in a plan view in the plate thickness direction.

[0012] In the disclosed semiconductor device, the amount of shrinkage of the joint portion can be made closer to the amount of shrinkage of the adhesive portion during the formation of the resin molded body, compared to a configuration in which the metal member does not overlap the exposed surface, thereby reducing the thermal stress acting on the insulating base material.

[0013] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims are intended to exemplarily indicate the corresponding parts of the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a diagram showing a power conversion circuit and a drive system to which the semiconductor device according to the first embodiment is applied; [Figure 2] FIG. 1 is a perspective view illustrating an example of a semiconductor device. [Figure 3] 1 is a three-dimensional cross-sectional view of a semiconductor device; [Figure 4] FIG. 2 is a plan view showing the substrate on the drain electrode side. [Figure 5] FIG. 2 is a plan view showing the substrate on the source electrode side. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7]FIG. 7 is an enlarged cross-sectional view of region VII shown in FIG. 6. [Figure 8] FIG. 10 is a diagram showing a reference example in which the solder thickness of the joint is thin. [Figure 9] FIG. 10 is a diagram showing the effect of solder thickness at a joint portion. [Figure 10] FIG. 10 is a diagram illustrating a simulation result. [Figure 11] FIG. 10 is a diagram illustrating a simulation result. [Figure 12] FIG. 10 is a diagram illustrating a simulation result. [Figure 13] FIG. 13 is an enlarged view of FIG. [Figure 14] FIG. 10 is a cross-sectional view showing an example of a semiconductor device according to a second embodiment. [Figure 15] FIG. [Figure 16] FIG. [Figure 17] FIG. 10 is a cross-sectional view showing an example of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0016] (First embodiment) The semiconductor device of this embodiment is applied to, for example, a mobile body using a rotating electric machine as a drive source. Examples of the mobile body include electric vehicles such as battery electric vehicles (BEV), hybrid electric vehicles (HEV), and plug-in hybrid electric vehicles (PHEV), electric flying bodies such as drones and electric vertical take-off and landing aircraft (eVTOL), ships, construction machinery, and agricultural machinery. BEV is an abbreviation for Battery Electric Vehicle. HEV is an abbreviation for Hybrid Electric Vehicle. eVTOL is an abbreviation for electronic Vertical Take-Off and Landing aircraft. An example of application to a vehicle will be described below.

[0017] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion circuit 4.

[0018] The DC power supply 2 is a DC voltage source formed, for example, by a rechargeable secondary battery. The secondary battery may be a lithium-ion battery, a nickel-metal hydride battery, or the like. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion circuit 4 converts power between the DC power supply 2 and the motor generator 3.

[0019] <Power conversion circuit> 1 shows an example of a power conversion circuit 4. The power conversion circuit 4 shown in FIG.

[0020] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0021] The inverter 6 is a DC-AC conversion circuit. In accordance with switching control by the control circuit, the inverter 6 converts a DC voltage into a three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0022] The inverter 6 is configured to include upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. Hereinafter, the upper arm 9H and the lower arm 9L may be simply referred to as arms 9H and 9L.

[0023] The connection point between the upper arm 9H and the lower arm 9L, i.e., the midpoint of the upper / lower arm circuit 9, is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms 9H, 9L. Each arm 9H, 9L is configured with a switching element. The number of switching elements constituting each arm 9H, 9L is not particularly limited. There may be one or more. When there are more than one switching elements, the multiple switching elements connected in parallel to each other are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0024] The illustrated switching element is an n-channel MOSFET 11. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0025] A freewheeling diode 12 is connected in antiparallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11 or an external diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0026] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in anti-parallel.

[0027] The power conversion circuit 4 may include a converter. The converter is a DC-DC conversion circuit configured to be able to convert a DC voltage into a DC voltage of a different value, for example. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage step-up and step-down. The power conversion circuit 4 may also include a filter capacitor. The filter capacitor is provided between the DC power supply 2 and the converter.

[0028] The power conversion circuit 4 may include a snubber circuit. The snubber circuit is connected in parallel to the upper and lower arm circuits 9. The snubber circuit reduces the inductance of the upper and lower arm circuits 9. The snubber circuit absorbs a transient high voltage, known as a switching surge, that occurs when switching elements (MOSFETs 11) that constitute the upper and lower arm circuits 9. This enables the inverter 6 to perform high-speed switching.

[0029] The power conversion circuit 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0030] The power conversion circuit 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0031] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0032] <Semiconductor device> FIG. 2 is a perspective view showing an example of a semiconductor device. FIG. 3 is a three-dimensional cross-sectional view of the semiconductor device. FIG. 3 shows a cross-section along line VI-VI in FIG. 2. FIG. 4 is a plan view showing the substrate on the drain electrode side. FIG. 5 is a plan view showing the substrate on the source electrode side. FIGS. 4 and 5 show a surface metal body of the substrate. FIGS. 4 and 5 also show a semiconductor element, a conductive spacer, a relay member, a P terminal, an N terminal, and an O terminal. FIG. 6 is a two-dimensional cross-sectional view along line VI-VI in FIG. 2.

[0033] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the Y direction. The direction perpendicular to both the Z direction and the Y direction is referred to as the X direction. The X direction, Y direction, and Z direction are mutually perpendicular. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction is sometimes simply referred to as the planar view.

[0034] The semiconductor device 15 constitutes the upper and lower arm circuits 9, i.e., the inverter 6. The illustrated semiconductor device 15 constitutes one of the upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuit 9. The semiconductor device 15 may also be referred to as a semiconductor module, a power module, or the like. As shown in FIGS. 2 to 6 , the semiconductor device 15 includes a resin molded body 20, a semiconductor element 30, substrates 40 and 50, a conductive spacer 60, a relay member 70, and an external connection terminal 80.

[0035] The resin molded body 20 encapsulates some of the other elements that make up the semiconductor device 15. The remaining parts of the other elements are exposed to the outside of the resin molded body 20. The resin molded body 20 is formed using a resin material. The illustrated resin molded body 20 is molded by a transfer molding method using epoxy resin as the material. Such a resin molded body 20 may be referred to as a molded resin, an encapsulating resin body, or the like.

[0036] The resin molded body 20 has a generally rectangular shape in plan view. The resin molded body 20 has one surface 201, a back surface 202, and side surfaces 203, 204, 205, and 206 as surfaces forming its outer contour. The back surface 202 is the surface opposite to the one surface 201 in the Z direction. The one surface 201 and the back surface 202 are, for example, flat surfaces. The side surface 204 is the surface opposite to the side surface 203 in the Y direction. The side surface 206 is the surface opposite to the side surface 205 in the X direction.

[0037] The semiconductor element 30 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 30 may also be called a power element or a semiconductor chip.

[0038] The illustrated semiconductor element 30 includes the n-channel MOSFET 11 formed on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure such that a main current flows in the thickness direction of the semiconductor element 30 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 30 has main electrodes of a switching element on main surfaces 301 and 302. The main surface 302 is the surface opposite to the main surface 301 in the Z direction. The main surface 301 corresponds to the first main surface, and the main surface 302 corresponds to the second main surface. The semiconductor element 30 has, as main electrodes, a drain electrode 31 on the main surface 301 and a source electrode 32 on the main surface 302. If the diode 12 is a parasitic diode, the source electrode 32 also serves as an anode electrode, and the drain electrode 31 also serves as a cathode electrode. The diode 12 may be configured on a chip separate from the MOSFET 11. The drain electrode 31 is the main electrode on the high potential side, and the source electrode 32 is the main electrode on the low potential side.

[0039] The semiconductor element 30 has a generally rectangular shape in plan view. The semiconductor element 30 has a pad 33 formed on a main surface 302 at a position different from the source electrode 32. The source electrode 32 and the pad 33 are exposed from a protective film (not shown) provided on the main surface 302 of the semiconductor substrate. The drain electrode 31 is formed on almost the entire main surface 301. The source electrode 32 is formed on a portion of the main surface 302 of the semiconductor element 30. The pad 33 is an electrode for signals. The pad 33 includes a pad for a gate electrode. The illustrated pad 33 is formed at an end on the opposite side in the Y direction from the region where the source electrode 32 is formed.

[0040] The semiconductor device 15 includes a plurality of semiconductor elements 30. The plurality of semiconductor elements 30 may include a plurality of types of semiconductor elements with different specifications. As in the illustrated semiconductor device 15, all of the semiconductor elements 30 may have a common configuration. The plurality of semiconductor elements 30 include a semiconductor element 30H that constitutes an upper arm 9H and a semiconductor element 30L that constitutes a lower arm 9L. The semiconductor element 30H may be referred to as an upper arm element, and the semiconductor element 30L may be referred to as a lower arm element.

[0041] The semiconductor elements 30H, 30L are aligned in the Y direction. The semiconductor elements 30H, 30L are arranged at approximately the same position as each other in the Z direction. The drain electrodes 31 of the semiconductor elements 30H, 30L face the substrate 40. The source electrodes 32 of the semiconductor elements 30H, 30L face the substrate 50. If the number of switching elements constituting each arm 9H, 9L is, for example, two, the semiconductor device 15 includes two semiconductor elements 30H, 30L. The two semiconductor elements 30H are aligned in the X direction. Similarly, the two semiconductor elements 30L are aligned in the X direction.

[0042] The semiconductor element 30H is disposed such that the pad 33 is located on the side surface 203 side relative to the source electrode 32. The semiconductor element 30L is disposed such that the pad 33 is located on the side surface 204 side relative to the source electrode 32.

[0043] The substrates 40, 50 are arranged to sandwich the multiple semiconductor elements 30 in the Z direction. The substrates 40, 50 are arranged so that at least a portion of each substrate faces each other in the Z direction. The substrates 40, 50 contain all of the multiple semiconductor elements 30 in a planar view. The substrate 40 is arranged on the drain electrode 31 side. The substrate 50 is arranged on the source electrode 32 side. The substrate 40 is electrically connected to the drain electrode 31 and provides a wiring function. The substrate 50 is electrically connected to the source electrode 32 and provides a wiring function. The substrates 40, 50 provide a heat dissipation function that dissipates heat generated by the semiconductor elements 30.

[0044] The substrate 40 includes an insulating substrate 41, a front metal body 42, and a back metal body 43. The substrate 50 includes an insulating substrate 51, a front metal body 52, and a back metal body 53. The insulating substrates 41 and 51 are resin substrates containing resin as a material. Exemplary insulating substrates 41 and 51 contain epoxy resin as a material. The insulating substrate 41 electrically separates the front metal body 42 and the back metal body 43. The insulating substrate 51 electrically separates the front metal body 52 and the back metal body 53.

[0045] The front surface metal bodies 42, 52 and the back surface metal bodies 43, 53 are provided as metal plates or metal foils. The front surface metal bodies 42, 52 and the back surface metal bodies 43, 53 are made of a metal with good electrical and thermal conductivity, such as Cu or Al. The front surface metal bodies 42, 52 are patterned. The front surface metal bodies 42, 52 may have a plating film of Ni, Au, or the like on the metal surface. The front surface metal body 42 has a P wiring 421 and a relay wiring 422. The P wiring 421 and the relay wiring 422 are electrically separated by a predetermined gap 41G (spacing). This gap is filled with a resin molded body 20.

[0046] The P wiring 421 is connected to the P terminal 81 and the drain electrode 31 of the semiconductor element 30H. The P wiring 421 electrically connects the P terminal 81 and the drain electrode 31 of the semiconductor element 30H. The relay wiring 422 is connected to the drain electrode 31 of the semiconductor element 30L, the relay member 70, and the O terminal 83. The relay wiring 422 electrically connects the O terminal 83 and the drain electrode 31 of the semiconductor element 30L. The illustrated P wiring 421 has a substantially rectangular shape in plan view. The relay wiring 422 has a substantially rectangular shape in plan view. The P wiring 421 and the relay wiring 422 are arranged side by side in the Y direction.

[0047] The P terminal 81 is connected to the P wiring 421 near the end on the side surface 203 side. The O terminal 83 is connected to the relay wiring 422 near the end on the side surface 204 side. The drain electrode 31 of the semiconductor element 30H is connected to the P wiring 421 at a position closer to the relay wiring 422 than the joint of the P terminal 81. The drain electrode 31 of the semiconductor element 30L is connected to the relay wiring 422 at a position closer to the P wiring 421 than the joint of the O terminal 83. The relay member 70 is connected to the relay wiring 422 at a position closer to the P wiring 421 than the semiconductor element 30L.

[0048] The surface metal body 52 has an N wiring 521 and a relay wiring 522. The N wiring 521 and the relay wiring 522 are electrically separated by a predetermined gap 51G (spacing). This gap is filled with a resin molding 20. The N wiring 521 is connected to the N terminal 82 and the source electrode 32 of the semiconductor element 30L. The N wiring 521 electrically connects the N terminal 82 and the source electrode 32 of the semiconductor element 30L. The relay wiring 522 is connected to the source electrode 32 of the semiconductor element 30H and the relay member 70. The relay wiring 522 electrically connects the source electrode 32 of the semiconductor element 30H and the drain electrode 31 of the semiconductor element 30L via the relay member 70.

[0049] The illustrated N wiring 521 has a substantially U-shape in plan view. The N wiring 521 has a base extending in the X direction and a pair of extension portions that are connected to the base and extend in the Y direction from both ends of the base. The relay wiring 522 is disposed between the pair of extension portions of the N wiring 521. The relay wiring 522 has a polygonal shape that is the same as or similar to a baseball home base in a plan view. The base of the N wiring 521 and the relay wiring 522 are aligned in the Y direction. The extension portions of the N wiring 521 and the relay wiring 522 are aligned in the X direction.

[0050] The source electrode 32 of the semiconductor element 30L is connected to the base of the N wiring 521. The N terminal 82 is connected to an extended portion of the N wiring 521. The semiconductor element 30L is connected to the N wiring 521 near the end portion on the side surface 204 side. The N terminal 82 is connected to the N wiring 521 near the end portion on the side surface 203 side. The source electrode 32 of the semiconductor element 30H is connected to the relay wiring 522. The relay member 70 is connected to the relay wiring 522 at a position closer to the base of the N wiring 521 than the semiconductor element 30H.

[0051] The back surface metal bodies 43, 53 are electrically separated from the front surface metal bodies 42, 52 by the insulating base materials 41, 51. The illustrated back surface metal bodies 43, 53 are so-called solid conductors arranged over almost the entire back surface of the insulating base materials 41, 51. The back surface metal body 43 is exposed from one surface 201 of the resin molded body 20, and the back surface metal body 53 is exposed from the back surface 202. The back surface metal body 43 is exposed substantially flush with the one surface 201. The back surface metal body 53 is exposed substantially flush with the back surface 202.

[0052] The conductive spacer 60 functions as a spacer to ensure a predetermined distance between the semiconductor element 30 and the substrate 50. The conductive spacer 60 ensures a height required for electrically connecting the corresponding signal terminal 84 to the pad 33 of the semiconductor element 30, for example. The conductive spacer 60 is located midway along the electrical and thermal conduction path between the source electrode 32 of the semiconductor element 30 and the substrate 50, providing wiring and heat dissipation functions. The conductive spacer 60 includes a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 60 may have a plating film on its surface. The conductive spacer 60 is a generally rectangular columnar body having approximately the same size as the source electrode 32 in a planar view.

[0053] The conductive spacers 60 may be referred to as terminals, terminal blocks, metal blocks, etc. The semiconductor device 15 includes the same number of conductive spacers 60 as the semiconductor elements 30. The semiconductor device 15 includes two conductive spacers 60. One of the conductive spacers 60 electrically connects the source electrode 32 of the semiconductor element 30H to the relay wiring 522. The other conductive spacer 60 electrically connects the source electrode 32 of the semiconductor element 30L to the N wiring 521.

[0054] The relay member 70 electrically connects the relay wires 422 and 522. That is, the relay member 70 electrically connects the upper arm 9H and the lower arm 9L. The relay member 70 is provided between the semiconductor element 30H and the semiconductor element 30L. The relay member 70 extends in the Z direction. One end of the relay member 70 is connected to the relay wire 422, and the other end is connected to the relay wire 522. The illustrated relay member 70 is arranged in an overlapping region of the relay wires 422 and 522 in a plan view.

[0055] The relay member 70 may include a metal member provided separately from the surface metal members 42, 52. For example, the metal member is a metal column made of a metal with good conductivity such as Cu. The relay member 70 may include a bonding material such as solder. The relay member 70 may include a protrusion that is continuous and integral with the surface metal members 42, 52. In other words, at least a portion of the relay member 70 may be provided integrally with the surface metal members 42, 52 as part of the substrates 40, 50. A portion of the relay member 70 may be provided as part of the substrate 40, and another portion of the relay member 70 may be provided as part of the substrate 50.

[0056] The external connection terminals 80 are terminals for electrically connecting the semiconductor device 15 to an external device. The external connection terminals 80 are formed using a metal material with good conductivity, such as Cu. The external connection terminals 80 are, for example, a plate material. The external connection terminals 80 are sometimes referred to as leads. The external connection terminals 80 include a P terminal 81, an N terminal 82, an O terminal 83, and a signal terminal 84. The P terminal 81, the N terminal 82, and the O terminal 83 are sometimes referred to as main terminals because they are electrically connected to main electrodes of the semiconductor element 30. The P terminal 81 and the N terminal 82 are sometimes referred to as power supply terminals.

[0057] The P terminal 81 is connected to the P wiring 421 near one end in the Y direction. A portion of the P terminal 81 is covered by the resin molded body 20, and another portion protrudes outside the resin molded body 20. The joint portion of the P terminal 81 with the P wiring 421 is covered by the resin molded body 20. The illustrated P terminal 81 extends approximately in the Y direction. The P terminal 81 protrudes from the side surface 203. The semiconductor device 15 includes two P terminals 81.

[0058] The N terminal 82 is connected to an extending portion of the N wiring 521. A portion of the N terminal 82 is covered by the resin molded body 20, and another portion protrudes outside the resin molded body 20. The joint portion of the N terminal 82 with the N wiring 521 is covered by the resin molded body 20. The illustrated N terminal 82 extends generally in the Y direction, the same direction as the P terminal 81. The N terminal 82 protrudes from the side surface 203. The semiconductor device 15 has two N terminals 82 individually connected to extending portions of the N wiring 521.

[0059] The O terminal 83 is connected to the relay wiring 422 near one end in the Y direction. A portion of the O terminal 83 is covered by the resin molded body 20, and another portion protrudes outside the resin molded body 20. The joint portion of the O terminal 83 with the relay wiring 422 is covered by the resin molded body 20. The illustrated O terminal 83 extends generally in the Y direction, in the opposite direction to the P terminal 81 and the N terminal 82. The O terminal 83 protrudes from the side surface 204.

[0060] The signal terminals 84 are electrically connected to the pads 33 of the corresponding semiconductor elements 30. The signal terminals 84 include a signal terminal connected to the pads 33 of the semiconductor element 30H and a signal terminal connected to the pads 33 of the semiconductor element 30L. The illustrated signal terminals 84 are connected to the corresponding pads 33 via bonding wires (not shown). The signal terminals 84 extend generally in the Y direction in plan view. A portion of the signal terminals 84, including the connection portion with the pads 33, is covered by the resin molded body 20, and another portion protrudes from the resin molded body 20.

[0061] The signal terminal 84 connected to the pad 33 of the semiconductor element 30H protrudes from the side surface 203 to the outside of the resin molded body 20. The external connection terminals 80 protruding from the side surface 203 are arranged in the following order in the X direction: N terminal 82, P terminal 81, signal terminal 84, P terminal 81, and N terminal 82. Adjacent P terminals 81 and N terminals 82 run side by side with their side surfaces facing each other. The signal terminal 84 connected to the pad 33 of the semiconductor element 30L protrudes from the side surface 204 to the outside of the resin molded body 20. The external connection terminals 80 protruding from the side surface 204 are arranged in the following order in the X direction: O terminal 83, signal terminal 84, and O terminal 83.

[0062] The P terminal 81, the N terminal 82, and the O terminal 83 may be connected to the corresponding surface metal bodies 42, 52 by a joining material. The joining material may be solder or a sintered material. The P terminal 81, the N terminal 82, and the O terminal 83 may be solid-state joined to the corresponding surface metal bodies 42, 52. Examples of solid-state joining include ultrasonic joining, room-temperature joining, friction stir joining, diffusion joining, and friction welding.

[0063] As described above, in the semiconductor device 15, the resin molded body 20 encapsulates the plurality of semiconductor elements 30 that constitute one phase of the upper and lower arm circuits 9. The resin molded body 20 integrally encapsulates the plurality of semiconductor elements 30, a portion of the substrate 40, a portion of the substrate 50, the plurality of conductive spacers 60, the relay member 70, and a portion of the external connection terminals 80. The resin molded body 20 encapsulates the insulating base materials 41, 51 and the surface metal bodies 42, 52 of the substrates 40, 50.

[0064] The semiconductor element 30 is disposed between the substrates 40 and 50 in the Z direction. The semiconductor element 30 is sandwiched between the substrates 40 and 50, which are disposed opposite each other. This allows heat from the semiconductor element 30 to be dissipated to both sides in the Z direction. The semiconductor device 15 has a double-sided heat dissipation structure. The back surface metal body 43 is exposed from the resin molded body 20, approximately flush with one surface 201. The back surface metal body 53 is exposed from the resin molded body 20, approximately flush with the back surface 202. The exposed structure of the back surface metal bodies 43 and 53 can improve heat dissipation.

[0065] <Exposed surfaces, triple points, adhesive joints, element parts, and joint parts> FIG. 7 is an enlarged view of region VII indicated by the dashed line in FIG.

[0066] As shown in FIGS. 4 to 7 , the insulating base material 41 has an exposed surface 411 exposed from the front surface metal body 42. The exposed surface 411 is a portion of the surface of the insulating base material 41 facing the front surface metal body 42 that is exposed by the gap 41G between adjacent wirings. The exposed surface 411 is exposed by the gap 41G between the P wiring 421 and the relay wiring 422. The insulating base material 51 has an exposed surface 511 exposed from the front surface metal body 52. ​​The exposed surface 511 is a portion of the surface of the insulating base material 51 facing the front surface metal body 52 that is exposed by the gap 51G between adjacent wirings. The exposed surface 511 is exposed by the gap 51G between the N wiring 521 and the relay wiring 522.

[0067] As illustrated in FIG. 7 , the semiconductor device 15 has a triple point 901 where the resin molded body 20, the insulating base material 51, and the surface metal body 52 overlap. The triple point 901 is formed by the insulating base material 51 having an exposed surface 511. The triple point 901 is the overlapping portion of the resin molded body 20, the insulating base material 51, and the surface metal body 52. ​​The triple point 901 includes a triple point between the resin molded body 20, the insulating base material 51, and the N wiring 521, and a triple point between the resin molded body 20, the insulating base material 51, and the relay wiring 522. Although not shown, the semiconductor device 15 has a triple point 901 where the resin molded body 20, the insulating base material 41, and the surface metal body 42 overlap. The triple point 901 includes a triple point between the resin molded body 20, the insulating base material 41, and the P wiring 421, and a triple point between the resin molded body 20, the insulating base material 41, and the relay wiring 422.

[0068] In a configuration having a triple junction 901, thermal stress tends to concentrate at the triple junction 901. In other words, thermal stress tends to concentrate on the insulating base materials 41, 51. When molding the resin molded body 20, a curing process such as heating is required to terminate the reaction of unreacted portions. The resin molded body 20 is completely hardened by the curing process, and the linear expansion coefficient of the resin molded body 20 after the curing process is smaller than that before the curing process. Before the curing process, the linear expansion coefficient of the resin molded body 20 is larger than that of the surface metal bodies 42, 52 (wiring) and the insulating base materials 41, 51 containing resin.

[0069] For this reason, when the temperature of the resin molded body 20 drops after the pressure is held but before the curing process, the resin molded body 20 shrinks (thermal shrinkage), and thermal stress tends to concentrate at the triple junction 901. In order to reduce the thermal stress that concentrates at the triple junction 901, the illustrated semiconductor device 15 has the following configuration. The semiconductor device 15 has an adhesive portion 90, an element portion 91, and a joint portion 92. The adhesive portion 90, the element portion 91, and the joint portion 92 are all portions located between the insulating base material 41 and the insulating base material 51.

[0070] The adhesive portion 90 is a portion between the insulating base material 41 and the insulating base material 51 that includes the resin molding 20 that is adhered to the exposed surfaces 411, 511. The adhesive portion 90 is a portion that overlaps with the gaps 41G, 51G in a plan view. The adhesive portion 90 illustrated in FIG. 7 is a portion that overlaps with the gap 51G and includes the resin molding 20 and the front surface metal body 42 (relay wiring 422). The resin molding 20 extends from the portion that contacts the front surface metal body 42 to the portion that contacts the exposed surface 511.

[0071] Although not shown, the adhesive portion 90 on the gap 41G side is the portion that overlaps the gap 41G and includes the resin molding 20 and the surface metal body 52 (relay wiring 522). The resin molding 20 extends from the portion that contacts the exposed surface 411 to the portion that contacts the surface metal body 52.

[0072] The element portion 91 is a portion between the insulating base material 41 and the insulating base material 51 where the semiconductor element 30 is interposed between the surface metal body 42 and the surface metal body 52. ​​The element portion 91 is a portion that overlaps with the source electrode 32 of the semiconductor element 30 in a plan view. The element portion 91 illustrated in FIG. 7 is a portion that overlaps with the source electrode 32 of the semiconductor element 30L, and includes the surface metal body 42, the surface metal body 52, the semiconductor element 30L, a conductive spacer 60, and solder 93. The solder 93 includes solder interposed between the drain electrode 31 of the semiconductor element 30L and the surface metal body 42 (relay wiring 422), solder interposed between the source electrode 32 of the semiconductor element 30L and the conductive spacer 60, and solder interposed between the conductive spacer 60 and the surface metal body 52 (N wiring 521).

[0073] Although not shown, the element portion 91 on the semiconductor element 30H side is a portion that overlaps with the source electrode 32 of the semiconductor element 30H, and includes the surface metal body 42, the surface metal body 52, the semiconductor element 30H, the conductive spacer 60, and solder 93. The solder 93 includes solder interposed between the drain electrode 31 of the semiconductor element 30H and the surface metal body 42 (P wiring 421), solder interposed between the source electrode 32 of the semiconductor element 30H and the conductive spacer 60, and solder interposed between the conductive spacer 60 and the surface metal body 52 (relay wiring 522).

[0074] The joint 92 is a portion between the insulating base material 41 and the insulating base material 51 that electrically connects the portions of the surface metal body 42 and the surface metal body 52 that are at the same potential. The joint 92 is a portion that includes the relay 70. In a plan view, the joint 92 is a portion that overlaps with the relay 70 extending in the Z direction. The joint 92 illustrated in FIG. 7 is a portion that overlaps with the relay 70 and includes the surface metal body 42, the surface metal body 52, a metal member 94, and solder 93. The metal member 94 is a block made of a metal with good conductivity, such as Cu. The solder 93 includes solder interposed between the metal member 94 and the surface metal body 42 (relay wiring 422) and solder interposed between the metal member 94 and the surface metal body 52 (relay wiring 522). The metal member 94 and the solder 93 constitute the relay 70.

[0075] In the illustrated semiconductor device 15, the total thickness of the solder 93 in the joint portion 92 is thicker than the total thickness of the solder 93 in the element portion 91. The total thickness of the solder 93 in the joint portion 92 is the sum of the thickness of the solder interposed between the metal member 94 and the surface metal body 42 and the thickness of the solder interposed between the metal member 94 and the surface metal body 52. ​​For example, the total thickness of the solder 93 in the element portion 91 on the semiconductor element 30L side is the sum of the thickness of the solder interposed between the semiconductor element 30L and the surface metal body 42, the solder interposed between the semiconductor element 30L and the conductive spacer 60, and the solder interposed between the conductive spacer 60 and the surface metal body 52.

[0076] 6 and 7, the total thickness of the solder 93 of the joint portion 92 is greater than the thickness of the metal member 94. The joint portion 92 is provided closer to the adhesive portion 90 than the element portion 91.

[0077] <Summary of the First Embodiment> The semiconductor device 15 of this embodiment includes substrates 40, 50, a semiconductor element 30, and a resin molded body 20. The insulating base materials 41, 51 of the substrates 40, 50 have exposed surfaces 411, 511. The portion between the insulating base materials 41, 51 includes an adhesive portion 90, an element portion 91, and a joint portion 92. The element portion 91 and the joint portion 92 each include solder 93. The total thickness of the solder 93 at the joint portion 92 is thicker than that of the element portion 91. One of the substrates 40, 50 corresponds to the first substrate, and the other corresponds to the second substrate. Of the insulating base materials 41, 51, the insulating base material of the first substrate corresponds to the first insulating base material, and the insulating base material of the second substrate corresponds to the second insulating base material. Of the surface metal bodies 42, 52, the surface metal body of the first substrate corresponds to the first surface metal body, and the surface metal body of the second substrate corresponds to the second surface metal body.

[0078] In the illustrated semiconductor device 15, the linear expansion coefficient of the resin molded body 20 after the curing treatment is 14×10 -6 / K, and the linear expansion coefficient of the resin molded body 20 before curing is 20×10 -6 / K. The linear expansion coefficient of the insulating base materials 41 and 51 is about 14×10 -6 / K, and the linear expansion coefficient of Cu constituting the surface metal bodies 42 and 52 is 16.5×10 -6 / K. The linear expansion coefficient of solder 93 is 21 x 10 -6 / K. The linear expansion coefficient of Sn, the main component of Solder 93, is 23 × 10 -6 / K. The linear expansion coefficient of Cu constituting the metal member 94 is 16.5×10 -6 / K.

[0079] In other words, by thickening the solder 93 of the joint 92 having a predetermined length, the overall linear expansion coefficient of the joint 92 approaches the linear expansion coefficient of the resin molded body 20 before the curing treatment. By thickening the total thickness of the solder 93 of the joint 92, the amount of contraction of the joint 92 approaches the amount of contraction of the adhesive portion 90 when the temperature of the resin molded body 20 drops before the curing treatment. FIGS. 8 and 9 are conceptual diagrams of the amount of contraction. The arrows in the diagram indicate the amount of contraction. FIG. 8 shows a reference example. When the solder 93 of the joint 92 is thin, as in the semiconductor device 15R of the reference example, the difference in the amount of contraction between the joint 92 and the adhesive portion 90 is large. FIG. 9 shows the present example. When the solder 93 of the joint 92 is thick, as in the semiconductor device 15 of the present example, the difference in the amount of contraction between the joint 92 and the adhesive portion 90 is small.

[0080] By making the total thickness of the solder 93 at the joint portion 92 thicker than the total thickness of the solder 93 at the element portion 91, when the temperature of the resin molded body 20 drops before the curing process, the amount of shrinkage at the joint portion 92 approaches the amount of shrinkage at the adhesive portion 90 rather than the amount of shrinkage at the element portion 91. The difference in the amount of shrinkage between the joint portion 92 and the adhesive portion 90 is smaller than the difference in the amount of shrinkage between the element portion 91 and the adhesive portion 90. Therefore, compared to a configuration in which the total thickness of the solder 93 at the joint portion 92 is below the element portion 91, it is possible to reduce the thermal stress acting on the insulating base materials 41, 51 (triple point 901) when the resin molded body 20 shrinks before the curing process.

[0081] The semiconductor device 15 of this embodiment includes substrates 40, 50, a semiconductor element 30, and a resin molded body 20. The insulating base materials 41, 51 of the substrates 40, 50 have exposed surfaces 411, 511. The portion located between the insulating base materials 41, 51 includes an adhesive portion 90, an element portion 91, and a joint portion 92. The difference in shrinkage between the joint portion 92 and the adhesive portion 90 is smaller than the difference in shrinkage between the element portion 91 and the adhesive portion 90.

[0082] This effectively reduces the thermal stress acting on the insulating substrates 41, 51 (triple point 901) when the resin molded body 20 shrinks before the curing process, compared to a configuration in which the difference in shrinkage between the joint portion 92 and the adhesive portion 90 is greater than or equal to the difference in shrinkage between the element portion 91 and the adhesive portion 90.

[0083] As shown in the example, the joint portion 92 may be provided closer to the adhesive portion 90 than the element portion 91. By providing the joint portion 92, which has a smaller difference in shrinkage amount from the adhesive portion 90, closer to the adhesive portion 90, the thermal stress acting on the insulating base materials 41 and 51 can be effectively reduced.

[0084] FIG. 10 shows the simulation results. In the simulation, the joint portion 92 was positioned closer to the adhesive portion 90 than the element portion 91. The horizontal axis shows the difference in shrinkage rate (shrinkage difference) between the joint portion 92 and the adhesive portion 90. The vertical axis shows the shrinkage difference between the element portion 91 and the adhesive portion 90. Also, the denser the dots, the higher the thermal stress acting on the insulating base materials 41, 51. The simulation results clearly show that the thermal stress can be reduced by making the difference in shrinkage amount between the joint portion 92 and the adhesive portion 90 smaller than the difference in shrinkage amount between the element portion 91 and the adhesive portion 90.

[0085] The ratio Ra of the shrinkage of the joint portion 92 to the adhesive portion 90 may be set to 0.75 or more and 0.90 or less. Figure 11 shows the simulation results. The horizontal axis shows the ratio Ra of the shrinkage of the joint portion 92 to the shrinkage of the adhesive portion 90. The vertical axis shows the thermal stress ratio when the thermal stress of a configuration in which the joint portion 92 includes only the metal member 94 is set to 1. The simulation results clearly show that the thermal stress acting on the insulating base materials 41, 51 can be reduced by setting the shrinkage ratio Ra to 0.75 or more and 0.90 or less. The shrinkage ratio Ra may be set to 0.80 or more and 0.90 or less.

[0086] As shown in the example, in order to make the difference in shrinkage between the joint portion 92 and the adhesive portion 90 smaller than the difference in shrinkage between the element portion 91 and the adhesive portion 90, the total thickness of the solder 93 may be made thicker at the joint portion 92 than at the element portion 91.

[0087] By making the total thickness of the solder 93 at the joint portion 92 thicker than the total thickness of the solder 93 at the element portion 91, when the temperature of the resin molded body 20 drops before the curing process, the amount of shrinkage at the joint portion 92 approaches the amount of shrinkage at the adhesive portion 90 rather than the amount of shrinkage at the element portion 91. The difference in the amount of shrinkage between the joint portion 92 and the adhesive portion 90 is smaller than the difference in the amount of shrinkage between the element portion 91 and the adhesive portion 90. Therefore, compared to a configuration in which the total thickness of the solder 93 at the joint portion 92 is below the element portion 91, it is possible to reduce the thermal stress acting on the insulating base materials 41, 51 (triple point 901) when the resin molded body 20 shrinks before the curing process.

[0088] In the joint portion 92, the ratio Rb of the thickness of the metal member 94 to the total thickness of the solder 93 may be set to 0.1 or more and 10 or less. FIG. 12 shows the simulation results. The horizontal axis represents the ratio Rb of the thickness of the metal member 94 to the total thickness of the solder 93. The vertical axis represents the thermal stress ratio when the thermal stress of a joint portion 92 including only the metal member 94 is set to 1. As shown in FIG. 12, it is clear that when the thickness ratio Rb is set to 0.1 or more and 10 or less, the thermal stress ratio becomes smaller than 1. In other words, by adjusting the thickness of the solder 93, the thermal stress acting on the insulating base materials 41, 51 can be reduced.

[0089] In the joint portion 92, the ratio Rb of the thickness of the metal member 94 to the total thickness of the solder 93 may be set to 0.18 or more and 4 or less. FIG. 13 is an enlarged view of FIG. 12. The simulation results clearly show that when the thickness ratio Rb is set to 0.18 or more and 4 or less, the thermal stress ratio becomes smaller. In other words, the thermal stress acting on the insulating base materials 41 and 51 can be effectively reduced.

[0090] As shown in the example, in the joint portion 92, the total thickness of the solder 93 may be made thicker than the thickness of the metal member 94. As described above, the linear expansion coefficient of the solder 93 is 21×10 -6 / K, and the linear expansion coefficient of Cu constituting the metal member 94 is 16.5×10 -6 / K. Therefore, by thickening the solder 93, which has a higher linear expansion coefficient than the metal member 94, the linear expansion coefficient of the entire joint portion 92 can be made closer to the linear expansion coefficient of the resin molded body 20 before the curing treatment, and the thermal stress acting on the insulating base materials 41, 51 can be reduced.

[0091] <Modification> The joint portion 92 including the solder 93 may include at least the solder 93 as the relay member 70. For example, the joint portion 92 may include the solder 93 and a protrusion provided on at least one of the surface metal bodies 42, 52.

[0092] Although an example has been shown in which the difference in shrinkage between the joint portion 92 and the adhesive portion 90 is made smaller than the difference in shrinkage between the element portion 91 and the adhesive portion 90 by thickening the solder 93 of the joint portion 92, the present invention is not limited to this. Although not shown, the metal member 94 of the joint portion 92 may be configured so that its shrinkage is closer to that of the resin molded body 20 than that of the conductive spacer 60 of the element portion 91. For example, the conductive spacer 60 contains Cu. The metal member 94 contains a material with a linear expansion coefficient larger than that of the conductive spacer 60, such as Al. The linear expansion coefficient of Cu constituting the conductive spacer 60 is 16.5×10 -6 / K. The linear expansion coefficient of the aluminum constituting the metal member 94 is 2.4 × 10 -5 / K. By using a material having a higher linear expansion coefficient than the conductive spacer 60 as the metal member 94, it is possible to make the difference in the amount of shrinkage between the metal member 94 and the resin molded body 20 smaller than the difference in the amount of shrinkage between the conductive spacer 60 and the resin molded body 20. In other words, it is possible to make the difference in the amount of shrinkage between the joint portion 92 and the adhesive portion 90 smaller than the difference in the amount of shrinkage between the element portion 91 and the adhesive portion 90.

[0093] (Second embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In the preceding embodiment, the solder at the joint portion is thick. Alternatively, or in addition, the metal member at the joint portion may be extended to a position where it overlaps with the exposed surface.

[0094] Fig. 14 is a cross-sectional view showing an example of a semiconductor device according to this embodiment. Fig. 14 corresponds to Fig. 6. As in the previous embodiment, the joint portion 92 includes solder interposed between the metal member 94 and the surface metal body 42 (relay wiring 422) and solder interposed between the metal member 94 and the surface metal body 52 (relay wiring 522). The metal member 94 has a base portion 941 and an extension portion 942. The base portion 941 corresponds to the metal member 94 shown in the previous embodiment and extends in the Z direction.

[0095] The extension portion 942 is continuous with the base portion 941. The extension portion 942 extends in the Y direction toward the semiconductor element 30L. The extension portion 942 extends to a position overlapping the exposed surface 511 in plan view. The illustrated metal member 94 is substantially L-shaped in the YZ plane. The extension portion 942 is continuous with the vicinity of the end of the base portion 941 on the substrate 40 side. The extension portion 942 crosses the exposed surface 511 in plan view. The solder 93 is interposed between the base portion 941 and the extension portion 942 and the surface metal body 42 (relay wiring 422). The solder 93 is interposed between the base portion 941 and the surface metal body 42 (relay wiring 422). The total thickness of the solder 93 in the joint portion 92 is equal to or less than the total thickness of the solder 93 in the element portion 91. The other configurations are similar to those described in the preceding embodiment.

[0096] <Summary of the second embodiment> The semiconductor device 15 of this embodiment includes substrates 40, 50, a semiconductor element 30, and a resin molded body 20. The insulating base materials 41, 51 of the substrates 40, 50 have exposed surfaces 411, 511. The portion located between the insulating base materials 41, 51 includes an adhesive portion 90, an element portion 91, and a joint portion 92. The joint portion 92 includes a metal member 94 and solder 93. The metal member 94 extends to a position overlapping the exposed surface 511 in a plan view.

[0097] Because the metal member 94 that constitutes the joint portion 92 is disposed within the region of the adhesive portion 90, the adhesive portion 90 essentially includes the surface metal body 42, the resin molded body 20, and the extension portion 942. The extension portion 942 reduces the thickness of the resin molded body 20 in the adhesive portion 90. This allows the amount of shrinkage of the joint portion 92 to be closer to the amount of shrinkage of the adhesive portion 90 when the resin molded body 20 is formed, compared to a configuration in which the metal member 94 does not overlap the exposed surface 511. This allows the thermal stress acting on the insulating base material 51 to be reduced.

[0098] <Modification> 14, the extension portion 942 may be configured to continue to the vicinity of the end portion of the base portion 941 on the substrate 50 side. The extension portion 942 may be configured to extend in the Y direction toward the semiconductor element 30H. The extension portion 942 may be configured to extend to a position overlapping with the exposed surface 411 in a plan view. This can reduce thermal stress acting on the insulating base material 41.

[0099] The shape and arrangement of the metal member 94 are not limited to the above example. For example, as shown in FIG. 15 , the extension portion 942 may have a portion overlapping the exposed surface 411 and a portion overlapping the exposed surface 511. The extension portion 942 in FIG. 15 has a portion extending toward the semiconductor element 30H side and a portion extending toward the semiconductor element 30L side. The extension portion 942 has a substantially cross shape in the YZ plane. This can reduce thermal stress acting on the insulating base materials 41 and 51.

[0100] 16 , in an arrangement in which the relay wirings 422 and 522 do not overlap, the extension portion 942 of the metal member 94 may extend obliquely. In plan view, the exposed surfaces 411 and 511 overlap to a certain extent, and the extension portion 942 crosses the exposed surfaces 411 and 511. This makes it possible to reduce the thermal stress acting on the insulating base materials 41 and 51.

[0101] (Third embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, a configuration was shown in which thermal stress acting on the exposed surface between adjacent wirings in the insulating substrate was reduced. Alternatively, or in addition, thermal stress acting on the exposed surface of the outer periphery of the insulating substrate may be reduced.

[0102] FIG. 17 is a cross-sectional view showing an example of a semiconductor device according to this embodiment. FIG. 17 corresponds to FIG. 6 and shows an enlarged view of the periphery of a semiconductor element 30H. As shown in FIG. 17, the front surface metal bodies 42, 52 extend to the outer peripheral edges of the corresponding insulating base materials 41, 51. The front surface metal bodies 42, 52 cover the outer peripheral edges of the corresponding insulating base materials 41, 51. The back surface metal bodies 43, 53 do not cover the outer peripheral edges of the corresponding insulating base materials 41, 51. The outer peripheral edges of the insulating base materials 41, 51 are exposed on the back surface metal bodies 43, 53 side, not on the front surface metal bodies 42, 52 side. The other configurations are similar to those described in the preceding embodiments.

[0103] <Summary of the third embodiment> According to the semiconductor device 15 of this embodiment, the thickness of the resin molded body 20 located on the outer periphery of the insulating base material 41, 51 can be reduced. This reduces the amount of shrinkage of the resin molded body 20 when it is formed, compared to a configuration in which the outer periphery of the insulating base material 41, 51 is exposed on the surface metal body 42, 52 side. This reduces the thermal stress acting on the outer periphery of the insulating base material 41, 51.

[0104] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0105] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0106] When an element or layer is referred to as being "on," "coupled," "connected," or "bonded," it may be directly on, coupled, connected, or bonded to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly bonded" to another element or layer, no intervening elements or layers are present. Other terms used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. That is, reference to A and / or B means at least one of A and B.

[0107] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0108] Although the semiconductor device 15 is exemplified as a 2-in-1 package that provides the upper and lower arm circuits 9 for one phase, the semiconductor device 15 is not limited to this. The semiconductor device 15 may be, for example, a 6-in-1 package.

[0109] (Disclosure of technical ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be written in a multiple dependent form, with the subsequent clause referring to the preceding clause as an alternative. Furthermore, some clauses may be written in a multiple dependent form, referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0110] <Technical philosophy 1> a substrate (40, 50) having an insulating base material (41, 51) containing a resin, a patterned front surface metal body (42, 52) disposed on the front surface of the insulating base material, and a back surface metal body (43, 53) disposed on the back surface of the insulating base material; a semiconductor element (30) having main electrodes (31, 32) respectively provided on a first main surface (301) and a second main surface (302) opposite to the first main surface in the thickness direction, the semiconductor element (30) being electrically connected to the surface metal body; a resin molding (20) that seals the substrate and the semiconductor element; Equipped with the substrate includes a first substrate disposed opposite the first main surface and having a first insulating substrate that is the insulating substrate and a first surface metal body that is the surface metal body, and a second substrate disposed opposite the second main surface and having a second insulating substrate that is the insulating substrate and a second surface metal body that is the surface metal body, At least one of the first insulating base material and the second insulating base material has an exposed surface (411, 511) exposed between adjacent wirings of the surface metal body, The portion located between the first insulating base material and the second insulating base material includes an adhesive portion (90) including the resin molded body adhered to the exposed surface, an element portion (91) in which the semiconductor element is interposed between the first surface metal body and the second surface metal body, and a joint portion (92) that electrically connects the same potential portions of the first surface metal body and the second surface metal body, a difference in shrinkage between the joint portion and the adhesive portion being smaller than a difference in shrinkage between the element portion and the adhesive portion.

[0111] <Technical philosophy 2> The semiconductor device according to Technical Idea 1, wherein the joint portion is provided closer to the adhesive portion than the element portion.

[0112] <Technical philosophy 3> The semiconductor device according to Technical Idea 1 or 2, wherein a ratio Ra of the amount of shrinkage of the joint portion to the adhesive portion is 0.75 or more and 0.90 or less.

[0113] <Technical philosophy 4> The element portion and the joint portion each include solder (93); The semiconductor device according to any one of Technical Concepts 1 to 3, wherein the total thickness of the solder is thicker in the joint portion than in the element portion.

[0114] <Technical philosophy 5> the joint portion includes a metal member (94), and the solder interposed between the metal member and the first surface metal body and between the metal member and the second surface metal body, The semiconductor device according to Technical Idea 4, wherein the ratio of the thickness of the metal member to the total thickness of the solder is 0.1 or more and 10 or less.

[0115] <Technical philosophy 6> The semiconductor device according to Technical Idea 5, wherein the ratio of the thickness of the metal member to the total thickness of the solder is 0.18 or more and 4 or less.

[0116] <Technical philosophy 7> The semiconductor device according to Technical Idea 6, wherein the total thickness of the solder is greater than the thickness of the metal member.

[0117] <Technical philosophy 8> The element portion includes a conductive spacer (60) interposed between the semiconductor element and the surface metal body, The joint portion includes a metal member (94), The semiconductor device according to any one of Technical Ideas 1 to 3, wherein the difference in shrinkage between the metal member and the resin molded body is smaller than the difference in shrinkage between the conductive spacer and the resin molded body.

[0118] <Technical philosophy 9> The joint portion includes a metal member (94) and a solder (93) interposed between the metal member and the surface metal body, The semiconductor device according to any one of Technical Concepts 1 to 3, wherein the metal member extends to a position overlapping the exposed surface in a plan view in the plate thickness direction. [Explanation of symbols]

[0119] 1... drive system, 2... DC power supply, 3... motor generator, 3a... winding, 4... power conversion circuit, 5... smoothing capacitor, 6... inverter, 7... P line, 8... N line, 9... upper and lower arm circuits, 9H... upper arm, 9L... lower arm, 10... output line, 11... MOSFET, 12... diode, 15... semiconductor device, 20... resin molded body, 201... one surface, 202... back surface, 203, 204, 205, 206... side surface, 30, 30H, 30L... semiconductor element, 301, 302... main surface, 31... drain electrode, 32... source Electrode, 33...Pad, 40, 50...Substrate, 41, 51...Insulating base material, 411, 511...Exposed surface, 41G, 51G...Gap, 42, 52...Front surface metal body, 421...P wiring, 521...N wiring, 422, 522...Relay wiring, 43, 53...Back surface metal body, 60...Conductive spacer, 70...Relay member, 80...External connection terminal, 81...P terminal, 82...N terminal, 83...O terminal, 84...Signal terminal, 90...Adhesive portion, 901...Triple junction, 91...Element portion, 92...Joint portion, 93...Solder, 94...Metal member, 941...Base portion, 942...Extended portion

Claims

1. a substrate (40, 50) having an insulating base material (41, 51) containing a resin, a patterned front surface metal body (42, 52) arranged on the front surface of the insulating base material, and a back surface metal body (43, 53) arranged on the back surface of the insulating base material; a semiconductor element (30) having main electrodes (31, 32) respectively provided on a first main surface (301) and a second main surface (302) opposite to the first main surface in the plate thickness direction, the semiconductor element (30) being electrically connected to the surface metal body; a resin molding (20) that seals the substrate and the semiconductor element; Equipped with the substrate includes a first substrate disposed opposite the first main surface and having a first insulating substrate that is the insulating substrate and a first surface metal body that is the surface metal body, and a second substrate disposed opposite the second main surface and having a second insulating substrate that is the insulating substrate and a second surface metal body that is the surface metal body, At least one of the first insulating substrate and the second insulating substrate has an exposed surface (411, 511) exposed between adjacent wirings of the surface metal body, The portion located between the first insulating base material and the second insulating base material includes an adhesive portion (90) including the resin molded body adhered to the exposed surface, an element portion (91) in which the semiconductor element is interposed between the first surface metal body and the second surface metal body, and a joint portion (92) that electrically connects the same potential portions of the first surface metal body and the second surface metal body, a difference in shrinkage between the joint portion and the adhesive portion being smaller than a difference in shrinkage between the element portion and the adhesive portion.

2. The semiconductor device according to claim 1 , wherein the joint portion is provided closer to the adhesive portion than the element portion.

3. 3. The semiconductor device according to claim 2, wherein a ratio Ra of the amount of shrinkage of said joint portion to said adhesive portion is 0.75 or more and 0.90 or less.

4. The element portion and the joint portion each include solder (93); 4. The semiconductor device according to claim 1, wherein the total thickness of the solder is greater in the joint portion than in the element portion.

5. The joint portion includes a metal member (94), and the solder interposed between the metal member and the first surface metal body and between the metal member and the second surface metal body, 5. The semiconductor device according to claim 4, wherein a ratio of the thickness of said metal member to the total thickness of said solder is 0.1 or more and 10 or less.

6. 6. The semiconductor device according to claim 5, wherein a ratio of the thickness of said metal member to the total thickness of said solder is 0.18 or more and 4 or less.

7. 7. The semiconductor device according to claim 6, wherein a total thickness of said solder is greater than a thickness of said metal member.

8. The element portion includes a conductive spacer (60) interposed between the semiconductor element and the surface metal body, The joint portion includes a metal member (94), 4. The semiconductor device according to claim 1, wherein a difference in shrinkage between said metal member and said resin molded body is smaller than a difference in shrinkage between said conductive spacer and said resin molded body.

9. The joint portion includes a metal member (94) and a solder (93) interposed between the metal member and the surface metal body, 4. The semiconductor device according to claim 1, wherein the metal member extends to a position overlapping the exposed surface in a plan view in the thickness direction.

10. a substrate (40, 50) having an insulating base material (41, 51) containing a resin, a patterned front surface metal body (42, 52) arranged on the front surface of the insulating base material, and a back surface metal body (43, 53) arranged on the back surface of the insulating base material; a semiconductor element (30) having main electrodes (31, 32) respectively provided on a first main surface (301) and a second main surface (302) opposite to the first main surface in the plate thickness direction, the semiconductor element (30) being electrically connected to the surface metal body; a resin molding (20) that seals the substrate and the semiconductor element; Equipped with the substrate includes a first substrate disposed opposite the first main surface and having a first insulating substrate that is the insulating substrate and a first surface metal body that is the surface metal body, and a second substrate disposed opposite the second main surface and having a second insulating substrate that is the insulating substrate and a second surface metal body that is the surface metal body, At least one of the first insulating substrate and the second insulating substrate has an exposed surface (411, 511) exposed between adjacent wirings of the surface metal body, The portion located between the first insulating base material and the second insulating base material includes an adhesive portion (90) including the resin molded body adhered to the exposed surface, an element portion (91) in which the semiconductor element is interposed between the first surface metal body and the second surface metal body, and a joint portion (92) that electrically connects the same potential portions of the first surface metal body and the second surface metal body, The element portion and the joint portion each include solder (93); The semiconductor device, wherein the total thickness of the solder is greater in the joint portion than in the element portion.

11. a substrate (40, 50) having an insulating base material (41, 51) containing a resin, a patterned front surface metal body (42, 52) arranged on the front surface of the insulating base material, and a back surface metal body (43, 53) arranged on the back surface of the insulating base material; a semiconductor element (30) having main electrodes (31, 32) respectively provided on a first main surface (301) and a second main surface (302) opposite to the first main surface in the plate thickness direction, the semiconductor element (30) being electrically connected to the surface metal body; a resin molding (20) that seals the substrate and the semiconductor element; Equipped with the substrate includes a first substrate disposed opposite the first main surface and having a first insulating substrate that is the insulating substrate and a first surface metal body that is the surface metal body, and a second substrate disposed opposite the second main surface and having a second insulating substrate that is the insulating substrate and a second surface metal body that is the surface metal body, At least one of the first insulating substrate and the second insulating substrate has an exposed surface (411, 511) exposed between adjacent wirings of the surface metal body, The portion located between the first insulating base material and the second insulating base material includes an adhesive portion (90) including the resin molded body adhered to the exposed surface, an element portion (91) in which the semiconductor element is interposed between the first surface metal body and the second surface metal body, and a joint portion (92) that electrically connects the same potential portions of the first surface metal body and the second surface metal body, The joint portion includes a metal member (94) and a solder (93) interposed between the metal member and the surface metal body, The metal member extends to a position overlapping the exposed surface in a plan view in the thickness direction of the semiconductor device.

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