Semiconductor package

Abstract

In some embodiments, a package-on-package (PoP) or a 2. 5D POP structure may include a die, a redistribution layer, a bridge die, and a sub-semiconductor package.SOLUTION: A first redistribution structure, a sub-semiconductor package on the first redistribution structure, the sub-semiconductor package including a second redistribution structure, a bridge die on the second redistribution structure, a first molding material on the second redistribution structure and covering the bridge die, a third redistribution structure on the first molding material and on the bridge die, a first semiconductor die on the third redistribution structure, and a second semiconductor die on the third redistribution structure and on a side of the first semiconductor die, the second semiconductor die being electrically connected to the first semiconductor die through the bridge die; And a third molding material covering the sub-semiconductor package on the first redistribution structure and including a second molding material covering the first semiconductor die and the second semiconductor die on the third redistribution structure.SELECTED DRAWING: Figure 24

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package that can improve the reliability of a rewiring structure. [Background technology]

[0002] Semiconductor technology has been developed in which a processor is divided into chiplets according to its intended use or the process to be applied. When a processor is manufactured by dividing it into chiplets, cheaper older processes can be applied to the chiplets that do not require the latest processes, thereby reducing manufacturing costs.If a defect occurs in a chiplet that has been manufactured using an older process, only the chiplet that has been manufactured using the older process can be discarded, thereby improving processor yield. Additionally, fabricating processors in chiplets can overcome the performance limitations of traditional single processor chips. The chiplets are connected to each other by redistribution layer (RDL) structures underneath the chiplets and silicon bridges underneath the redistribution structures, and the chiplets transmit signals between each other via the redistribution structures and silicon bridges.

[0003] In such a structure, the silicon bridge is disposed between the connecting members (e.g., solder balls or bumps) below the rewiring structure and is exposed to the outside together with the connecting members, but the exposed silicon bridge is at risk of being damaged by the external environment. In addition, the redistribution structure disposed between the chiplet and the silicon bridge must additionally include a routing path for the silicon bridge, resulting in a layer structure of five or more layers. However, forming a redistribution structure having a layer structure of five or more layers increases the difficulty of manufacturing and reduces the reliability of the redistribution structure. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems with conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package that can include a sub-semiconductor package including a semiconductor die (chiplet) that functions as a processor, a rewiring structure, a bridge die, and a passive component die in a package-on-package (PoP) structure or within a 2.5D semiconductor package structure. [Means for solving the problem]

[0005] a first molding material that covers the first semiconductor die and the second semiconductor die; a second molding material that covers the first semiconductor die and the second semiconductor die; a third molding material that covers the first semiconductor die and the second semiconductor die; a second semiconductor die that is electrically connected to the first semiconductor die via the bridge die; a third molding material that covers the first semiconductor die and the second semiconductor die; a second semiconductor die that is electrically connected to the first semiconductor die via the bridge die; a third molding material that covers the first semiconductor die and the second semiconductor die on the third rewiring structure;

[0006] Further, in order to achieve the above object, a semiconductor package according to the present invention includes a first rewiring structure and a sub-semiconductor package disposed on the first rewiring structure, wherein the sub-semiconductor package includes a second rewiring structure, a bridge die disposed on the second rewiring structure, a plurality of first connection members disposed on the second rewiring structure and on the side of the bridge die, a first molding material disposed on the second rewiring structure and covering the bridge die and the plurality of first connection members, a third rewiring structure disposed on the first molding material, on the bridge die, and on the plurality of first connection members, and a third rewiring structure disposed on the first molding material, on the bridge die, and on the plurality of first connection members. a first semiconductor die disposed on the sub-semiconductor package; a second semiconductor die disposed on the third redistribution structure and on a side of the first semiconductor die, wherein the second semiconductor die is electrically connected to the first semiconductor die via the bridge die; a second molding material disposed on the third redistribution structure and covering the first semiconductor die and the second semiconductor die; a plurality of second connection members disposed on the first redistribution structure; a third molding material disposed on the first redistribution structure and covering the sub-semiconductor package and the plurality of second connection members; and a fourth redistribution structure disposed on the third molding material and on the plurality of second connection members. and a third semiconductor die disposed on the fourth rewiring structure.

[0007] In order to achieve the above object, the present invention provides a semiconductor package comprising: a first rewiring structure; a sub-semiconductor package disposed on the first rewiring structure; wherein the sub-semiconductor package comprises: a second rewiring structure; a bridge die disposed on the second rewiring structure; a plurality of first connection members disposed on the second rewiring structure; a first molding material disposed on the second rewiring structure and covering the bridge die and the plurality of first connection members; a third rewiring structure disposed on the first molding material, the bridge die, and the plurality of first connection members; a first semiconductor die disposed on the body, a second semiconductor die disposed on the third rewiring structure and on the side of the first semiconductor die, wherein the second semiconductor die is electrically connected to the first semiconductor die via the bridge die; a second molding material disposed on the third rewiring structure and covering the first semiconductor die and the second semiconductor die; a third semiconductor die disposed on the first rewiring structure and on the side of the sub-semiconductor package; and a third molding material disposed on the first rewiring structure and covering the sub-semiconductor package and the third semiconductor die. [Effects of the Invention]

[0008] According to the semiconductor package of the present invention, the bridge die and the passive element die are disposed in the sub-semiconductor package and can be covered by a molding material in the sub-semiconductor package and a molding material that covers the sub-semiconductor package. This allows the bridge die and passive element die to be doubly covered with molding material without being exposed to the outside, protecting them from the external environment. Additionally, the semiconductor die and the passive component die may be disposed within a sub-semiconductor package. This allows the distance between the semiconductor die and the passive element die to be minimized, thereby improving the power integrity (PI) of the semiconductor package. Additionally, the bridge die and the passive component die may be disposed within a sub-semiconductor package. This allows connection bumps to be placed in spaces that were previously occupied by bridge dies and surface mount devices (SMDs) and where connection bumps could not be placed, ensuring design margins for realizing signal transmission paths and power transmission paths within the lower rewiring structure.

[0009] Furthermore, the sub-semiconductor package including the semiconductor die, the redistribution structure, the bridge die, and the passive component die can be applied to various platforms. Additionally, the bridge die and the passive component die may be disposed within a sub-semiconductor package, and the sub-semiconductor package may be disposed on a front rewiring structure. This eliminates the need to form routing paths for the bridge die within the front rewiring structure, reducing the total number of layers in the front rewiring structure. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a schematic configuration of a sub-semiconductor package according to an embodiment of the present invention. [Figure 2] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 3] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 4] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 5] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 6] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 7] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 8]2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 9] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 10] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 11] 2A to 2C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 1. [Figure 12] 1 is a cross-sectional view showing a schematic configuration of a sub-semiconductor package according to an embodiment of the present invention. [Figure 13] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 14] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 15] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 16] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 17] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 18] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 19] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 20] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 21] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 22]13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 23] 13A to 13C are cross-sectional views sequentially illustrating a method for manufacturing a sub-semiconductor package according to the embodiment of FIG. 12. [Figure 24] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 25] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 26] 26 is a plan view showing the upper surface of the semiconductor package according to the embodiment of FIG. 25. [Figure 27] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, specific examples of embodiments for carrying out a semiconductor package according to the present invention will be described with reference to the drawings.

[0012] As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In order to clearly explain the present invention from the drawings, parts unnecessary for the explanation are omitted, and the same reference numerals are used throughout the specification to refer to the same or similar components. Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. Throughout this specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "indirectly connected" via another member. Furthermore, when a part is said to "comprise" a certain component, this does not mean that it can further include other components, but does not exclude other components, unless otherwise specified.

[0013] Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "above" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when one part is said to be "directly above" another, it means that there is no other part in between. Also, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" in the opposite direction of gravity. Also, throughout the specification, "in a plane" means a portion of the subject matter viewed from above, and "in cross section" means a portion of the subject matter viewed from the side along a vertical cross section.

[0014] Hereinafter, sub-semiconductor packages (100A, 100B), a method for manufacturing the sub-semiconductor packages (100A, 100B), and semiconductor packages (200A, 200B, 200C) according to embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a schematic configuration of a sub-semiconductor package 100A according to an embodiment of the present invention. Referring to FIG. 1, the sub-semiconductor package 100A includes a connection structure 110, a lower rewiring structure (second rewiring structure) 120, a bridge die 130, a passive element die 140, a first connection member 150, a first molding material 160, an upper rewiring structure (third rewiring structure) 170, a first semiconductor die 180, a second semiconductor die 190, and a second molding material 161.

[0015] In one embodiment, the sub-semiconductor package 100A includes a System In Package (SIP). The sub-semiconductor package 100A is a semiconductor package that includes two or more processor dies and can operate as a single chip. In one embodiment, the sub-semiconductor package 100A is a semiconductor package manufactured by a chip (die) last process. In one embodiment, the sub-semiconductor package 100A can be manufactured based on Fan Out Wafer Level Package (FOWLP) or Fan Out Panel Level Package (FOPLP) technology.

[0016] The connection structure 110 is disposed on the lower surface of the lower rewiring structure 120 . The connection structure 110 includes a conductive pad 111 and a connection bump 112 . Each of the conductive pads 111 is disposed between each of the connection bumps 112 and each of the first redistribution vias 122 of the lower redistribution structure 120 . Each of the conductive pads 111 electrically connects each of the first redistribution vias 122 of the lower redistribution structure 120 to each of the connection bumps 112 . Each of the connection bumps 112 is disposed below each of the conductive pads 111 . 24, 25 and 27, the connection bumps 112 electrically connect the sub-semiconductor package 100A to the front rewiring structure 220 of the semiconductor packages (200A, 200B, 200C).

[0017] The lower redistribution structure 120 is disposed on the connection structure 110 . The lower redistribution structure 120 includes a first dielectric 121 , a first redistribution via 122 within the first dielectric 121 , a first redistribution line 123 and a second redistribution via 124 , and a first bonding pad 125 on the first dielectric 121 . In other embodiments, lower redistribution structures 120 including fewer or greater numbers of redistribution lines, redistribution vias, and bonding pads may be within the scope of the present invention. The first dielectric 121 protects and insulates the first redistribution via 122, the first redistribution line 123, and the second redistribution via . On the top surface of the first dielectric 121, a first bonding pad 125, a first adhesive member 132, a second adhesive member 142, and a first molding material 160 are disposed. The connection structure 110 is disposed on the lower surface of the first dielectric 121 .

[0018] Each of the first redistribution vias 122 is disposed between each of the first redistribution lines 123 and each of the conductive pads 111 . Each of the first redistribution vias 122 electrically connects each of the first redistribution lines 123 to each of the conductive pads 111 in the vertical direction. Each of the first redistribution lines 123 is disposed between each of the first redistribution vias 122 and each of the second redistribution vias 124 . Each of the first redistribution lines 123 electrically connects each of the second redistribution vias 124 to each of the first redistribution vias 122 in the horizontal direction. Each of the second redistribution vias 124 is disposed between each of the first redistribution lines 123 and each of the first bonding pads 125 . Each of the second redistribution vias 124 electrically connects each of the first bonding pads 125 to each of the first redistribution lines 123 in the vertical direction. Each of the first bonding pads 125 is disposed between each of the second rewiring vias 124 and each of the first connection members 150 . Each of the first bonding pads 125 electrically connects each of the first connection members 150 to each of the second redistribution vias 124 in the vertical direction. The first rewiring via 122 and the second rewiring via 124 each have a shape in which the width increases from the bottom to the top.

[0019] The bridge die 130 is disposed on the lower redistribution structure 120 . In one embodiment, bridge die 130 includes a silicon bridge die. The bridge die 130 electrically connects the first semiconductor die 180 to the second semiconductor die 190 through the upper rewiring structure 170 . In one embodiment, first semiconductor die 180 and second semiconductor die 190 may be dissimilar dies, with bridge die 130 providing a connection between them. Signals between the first semiconductor die 180 and the second semiconductor die 190 are routed through the bridge die 130 . The bridge die 130 is attached onto and within the lower redistribution structure 120 by a first adhesive member 132 . A first adhesive member 132 is attached onto the upper surface of the lower redistribution structure 120 , and the bridge die 130 is attached onto the first adhesive member 132 . The bridge die 130 is connected to the upper rewiring structure 170 via the first connection terminal 131 . Each of the first connection terminals 131 is disposed between the bridge die 130 and each of the third redistribution vias 172 of the upper redistribution structure 170 . Each of the first connection terminals 131 electrically connects each of the third redistribution vias 172 of the upper redistribution structure 170 to the bridge die 130 in the vertical direction. The bridge die 130 overlaps a portion of the connecting structure 110 .

[0020] A passive component die 140 is disposed on the lower redistribution structure 120 . The passive element die 140 may have a configuration equivalent to a surface-mounted device (SMD), which is disposed between external connection members in a conventional semiconductor package and is exposed to the outside together with the external connection members. A plurality of passive component dies 140 are included in the sub-semiconductor package 100A. Passive component die 140 is electrically connected to first semiconductor die 180 and second semiconductor die 190 via upper redistribution structure 170 . In one embodiment, the passive component die 140 can provide additional functionality or programming to the entire sub-semiconductor package 100A. In one embodiment, the passive component die 140 may include a resistor, an inductor, a capacitor, or a jumper. In one embodiment, the passive component die 140 may include an integrated stack capacitor (ISC). In one embodiment, the passive component die 140 can function as a decoupling capacitor. When the passive component die 140 functions as a decoupling capacitor, the passive component die 140 protects the first semiconductor die 180 and the second semiconductor die 190 from noise during the power transfer process.

[0021] A passive component die 140 is attached over and within the lower redistribution structure 120 by a second adhesive member 142 . A second adhesive member 142 is attached onto the top surface of the lower redistribution structure 120 , and the passive component die 140 is attached onto the second adhesive member 142 . The passive component die 140 is connected to the upper redistribution structure 170 via the second connection terminal 141 . Each of the second connection terminals 141 is disposed between the passive component die 140 and each of the third redistribution vias 172 of the upper redistribution structure 170 . Each of the second connection terminals 141 electrically connects each of the third redistribution vias 172 of the upper redistribution structure 170 to the passive component die 140 in a vertical direction. The passive component die 140 overlaps a portion of the connection structure 110 .

[0022] Conventional bridge dies and surface-mounted devices (SMDs) are arranged alongside connection bumps exposed to the outside, occupying the space where the connection bumps are arranged. However, according to the present invention, by arranging the bridge die 130 and the passive element die 140 within the sub-semiconductor package 100A, connection bumps can be arranged in the space occupied by the conventional bridge die and surface-mounted device (SMD) where connection bumps could not be arranged, thereby ensuring design margins for realizing signal transmission paths and power transmission paths within the rewiring structure of the semiconductor package 200A.

[0023] The first connection member 150 is disposed on the lower rewiring structure 120 . In one embodiment, the first connecting member 150 includes a conductive post. The first connecting member 150 is disposed around the bridge die 130 and around the passive component die 140 . In one embodiment, the first connecting member 150 surrounds each of the bridge die 130 and the passive component die 140 in a plan view. The first connecting member 150 is disposed on the side of the bridge die 130 and on the side of the passive component die 140 . Each of the first connection members 150 is disposed between each of the first bonding pads 125 of the lower redistribution structure 120 and each of the third redistribution vias 172 of the upper redistribution structure 170 . Each of the first connection members 150 electrically connects each of the third redistribution vias 172 of the upper redistribution structure 170 to each of the first bonding pads 125 of the lower redistribution structure 120 . The first connecting member 150 is disposed through the first molding material 160 . The side surface of first connection member 150 is surrounded by first molding material 160 .

[0024] The first molding material 160 is disposed on the lower rewiring structure 120 and covers the first bonding pad 125, the bridge die 130, the first connecting terminal 131, the first adhesive member 132, the passive element die 140, the second connecting terminal 141, and the second adhesive member 142. The first molding material 160 protects the first bonding pads 125, the bridge die 130, the first connecting terminals 131, the first adhesive members 132, the passive component die 140, the second connecting terminals 141, and the second adhesive members 142 from the external environment.

[0025] The upper rewiring structure 170 is disposed on the first connection terminal 131 , the second connection terminal 141 , the first connection member 150 , and the first molding material 160 . The upper redistribution structure 170 includes a second dielectric 171 , a third redistribution via 172 within the second dielectric 171 , a second redistribution line 173 and a fourth redistribution via 174 , and a second bonding pad 175 on the second dielectric 171 . In other embodiments, upper redistribution structure 170 including fewer or greater numbers of redistribution lines, redistribution vias, and bonding pads may be within the scope of the present invention.

[0026] The second dielectric 171 protects and insulates the third redistribution via 172, the second redistribution line 173, and the fourth redistribution via 174. A second bonding pad 175 and a second molding material 161 are disposed on the top surface of the second dielectric 171 . On the lower surface of the second dielectric 171, the first connection terminal 131, the second connection terminal 141, the first connection member 150, and the first molding material 160 are arranged.

[0027] Each of the third rewiring vias 172 is arranged between each of the first connection terminals 131 and each of the second rewiring lines 173, between each of the second connection terminals 141 and each of the second rewiring lines 173, or between each of the first connection members 150 and each of the second rewiring lines 173. Each of the third rewiring vias 172 electrically connects each of the second rewiring lines 173 to each of the first connection terminals 131, each of the second rewiring lines 173 to each of the second connection terminals 141, or each of the second rewiring lines 173 to each of the first connection members 150. Each of the second redistribution lines 173 is disposed between each of the third redistribution vias 172 and each of the fourth redistribution vias 174 . Each of the second redistribution lines 173 electrically connects each of the fourth redistribution vias 174 to each of the third redistribution vias 172 in the horizontal direction. Each of the fourth redistribution vias 174 is disposed between each of the second redistribution lines 173 and each of the second bonding pads 175 . Each of the fourth redistribution vias 174 electrically connects each of the second bonding pads 175 to each of the second redistribution lines 173 in the vertical direction. Each of the second bonding pads 175 is disposed between each of the fourth rewiring vias 174 and each of the first connection bumps 182, or between each of the fourth rewiring vias 174 and each of the second connection bumps 192. Each of the second bonding pads 175 electrically connects each of the first connection bumps 182 to each of the fourth redistribution vias 174 or each of the second connection bumps 192 to each of the fourth redistribution vias 174 in the vertical direction. The third rewiring via 172 and the fourth rewiring via 174 each have a shape in which the width increases from the bottom to the top.

[0028] A first semiconductor die 180 is disposed on the upper redistribution structure 170 . First semiconductor die 180 is positioned side by side with second semiconductor die 190 . In one embodiment, the first semiconductor die 180 may include an application processor (AP). The first semiconductor die 180 may be a chiplet manufactured by dividing an application processor (AP) according to the application or the process to be applied. In one embodiment, first semiconductor die 180 may be a chiplet that corresponds to at least one functional block of an application processor (AP). In one embodiment, first semiconductor die 180 may include at least one of a central processing unit (CPU), a graphic processing unit (GPU), a signal processor, a network processor, and a codec.

[0029] Each of the first connection pads 181 is disposed between each of the traces of the first semiconductor die 180 and each of the first connection bumps 182 . Each of the first connection pads 181 electrically connects a respective one of the traces of the first semiconductor die 180 to a respective one of the first connection bumps 182 . Each of the first connection bumps 182 is disposed between each of the first connection pads 181 and each of the second bonding pads 175 . Each of the first connection bumps 182 electrically connects each of the first connection pads 181 to each of the second bonding pads 175 .

[0030] A second semiconductor die 190 is disposed on the upper redistribution structure 170 . The second semiconductor die 190 is positioned side by side with the first semiconductor die 180 . In one embodiment, the second semiconductor die 190 may include an application processor (AP). The second semiconductor die 190 may be a chiplet manufactured by dividing an application processor (AP) according to the application or the process to be applied. In one embodiment, second semiconductor die 190 may be a chiplet corresponding to at least one functional block of an application processor (AP). In one embodiment, the second semiconductor die 190 may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a signal processor, a network processor, and a codec.

[0031] Each of the second connection pads 191 is disposed between a respective one of the traces of the second semiconductor die 190 and a respective one of the second connection bumps 192 . Each of the second connection pads 191 electrically connects a respective one of the traces of the second semiconductor die 190 to a respective one of the second connection bumps 192 . Each of the second connection bumps 192 is disposed between each of the second connection pads 191 and each of the second bonding pads 175 . Each of the second connection bumps 192 electrically connects each of the second connection pads 191 to each of the second bonding pads 175 .

[0032] According to the present invention, a sub-semiconductor package 100A can be provided that includes a passive component die 140, a first semiconductor die 180, and a second semiconductor die 190. This allows the distance between the passive element die 140 and the first semiconductor die 180, and the distance between the passive element die 140 and the second semiconductor die 190 to be minimized, thereby improving the power integrity (PI) of the semiconductor package 200A. The second molding material 161 is disposed on the upper rewiring structure 170 and covers the second bonding pads 175, the first semiconductor die 180, the first connection pads 181, the first connection bumps 182, the second semiconductor die 190, the second connection pads 191, and the second connection bumps 192. Second molding material 161 protects second bonding pads 175, first semiconductor die 180, first connection pads 181, first connection bumps 182, second semiconductor die 190, second connection pads 191, and second connection bumps 192 from the external environment. The top surface of the first semiconductor die 180 and the top surface of the second semiconductor die 190 are exposed to the outside from the second molding material 161 .

[0033] 2 to 11 are cross-sectional views sequentially illustrating a method for manufacturing the sub-semiconductor package 100A according to the embodiment of the present invention shown in FIG. 2 to 11 are cross-sectional views sequentially illustrating a method for manufacturing the sub-semiconductor package 100B to which the chip-last process is applied. FIG. 2 is a cross-sectional view showing a step of forming a lower rewiring structure 120 on a carrier (C).

[0034] Referring to FIG. 2, a lower rewiring structure 120 is formed on a carrier (C). First, provide a carrier (C). In one embodiment, the carrier (C) may comprise a silicon-based material such as glass or silicon oxide, an organic material, or other material such as aluminum oxide, any combination of these materials, or the like. After that, a first dielectric 121 is formed on the carrier (C). In one embodiment, the first dielectric 121 comprises a photoimageable dielectric (PID) used in a redistribution process. In one embodiment, the photosensitive dielectric (PID) may include a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, a polybenzoxazole, a silicone-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In one embodiment, the first dielectric layer 121 is formed by a spin coating process.

[0035] After forming the first dielectric 121, the first dielectric 121 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form the first redistribution via 122. After forming the first redistribution via 122, a first dielectric 121 is additionally formed on the first redistribution via 122 and the first dielectric 121, and the additionally formed first dielectric 121 is selectively etched to form an opening, and a conductive material is filled in the opening to form the first redistribution line 123. After forming the first redistribution line 123, the first dielectric 121 is additionally formed on the first redistribution line 123 and the first dielectric 121, the additionally formed first dielectric 121 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form a second redistribution via 124. After forming the second redistribution via 124, photoresist is additionally deposited on the second redistribution via 124 and the first dielectric 121, and the photoresist is selectively exposed and developed to form a photoresist pattern including a via hole. The via hole is filled with a conductive material to form a first bonding pad 125. In the sub-semiconductor package 100A according to this embodiment, which is manufactured by the chip-last process, the first rewiring via 122 and the second rewiring via 124 each have a shape in which the width increases from the bottom to the top.

[0036] In one embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the first bonding pad 125 may each include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the first bonding pad 125 are each formed by a sputtering process. In another embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the first bonding pad 125 may be formed by forming a seed metal layer and then performing an electroplating process.

[0037] FIG. 3 is a cross-sectional view showing a step of forming a first connection member 150 on the lower rewiring structure 120. As shown in FIG. Referring to FIG. 3, a first connection member 150 is formed on the first bonding pad 125 of the lower redistribution structure 120 . In one embodiment, the first connection member 150 is formed by a sputtering process. In another embodiment, the first connection member 150 may be formed by forming a seed metal layer and then performing an electrolytic plating process. In one embodiment, the first connecting member 150 may include at least one of copper, aluminum, tungsten, nickel, gold, silver, chromium, antimony, tin, titanium, and alloys thereof.

[0038] FIG. 4 is a cross-sectional view illustrating the step of attaching a bridge die 130 and a passive component die 140 onto a lower redistribution structure 120. As shown in FIG. Referring to FIG. 4, a bridge die 130 and a passive component die 140 are attached on the lower redistribution structure 120 . The bridge die 130 is attached onto the lower rewiring structure 120 by a first adhesive member 132 and is physically fixed to the lower rewiring structure 120 . In one embodiment, the first adhesive member 132 includes a die attach film (DAF). The passive component die 140 is attached onto the lower redistribution structure 120 by a second adhesive member 142 and is physically secured to the lower redistribution structure 120 . In one embodiment, the second adhesive member 142 comprises a die attach film (DAF).

[0039] FIG. 5 is a cross-sectional view showing a step of molding the bridge die 130, the first connecting terminal 131, the passive element die 140, the second connecting terminal 141, and the first connecting member 150 on the lower rewiring structure 120. As shown in FIG. Referring to FIG. 5, the bridge die 130 , the first connection terminals 131 , the passive element die 140 , the second connection terminals 141 , and the first connection members 150 are molded in a first molding material 160 on the lower redistribution structure 120 . In one embodiment, the process of molding the first molding material 160 may include a compression molding or transfer molding process. In one embodiment, first molding material 160 includes Epoxy Molding Compound (EMC).

[0040] FIG. 6 is a cross-sectional view showing a step of performing a chemical mechanical planarization (CMP) process on the first molding material 160. As shown in FIG. Referring to FIG. 6, in order to level the top surface of the first molding material 160, a chemical mechanical planarization (CMP) process is performed to flatten the top surface of the first molding material 160. After performing a chemical mechanical planarization (CMP) process, the top surfaces of the first connection terminals 131, the second connection terminals 141, and the first connection members 150 are exposed.

[0041] FIG. 7 is a cross-sectional view showing a step of forming an upper rewiring structure 170 on the first connection terminal 131, the second connection terminal 141, the first connection member 150, and the first molding material 160. As shown in FIG. Referring to FIG. 7, a second dielectric 171 is formed on the first connection terminal 131, the second connection terminal 141, the first connection member 150, and the first molding material 160. In one embodiment, the second dielectric 171 comprises a photosensitive dielectric (PID) used in a redistribution process. In one embodiment, the second dielectric layer 171 is formed by a spin coating process. After forming the second dielectric 171, the second dielectric 171 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form a third redistribution via 172. After forming the third redistribution via 172, a second dielectric 171 is additionally formed on the third redistribution via 172 and the second dielectric 171, and the additionally formed second dielectric 171 is selectively etched to form an opening, and a conductive material is filled in the opening to form a second redistribution line 173. After forming the second redistribution line 173, a second dielectric 171 is additionally formed on the second redistribution line 173 and the second dielectric 171, the additionally formed second dielectric 171 is selectively etched to form a via hole, and a conductive material is filled in the via hole to form a fourth redistribution via 174. After forming the fourth redistribution via 174, photoresist is additionally deposited on the fourth redistribution via 174 and the second dielectric 171, and the photoresist is selectively exposed and developed to form a photoresist pattern including a via hole. The via hole is filled with a conductive material to form a second bonding pad 175.

[0042] In one embodiment, the third redistribution via 172, the second redistribution line 173, the fourth redistribution via 174, and the second bonding pad 175 may each include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the third redistribution via 172, the second redistribution line 173, the fourth redistribution via 174, and the second bonding pad 175 are each formed by a sputtering process. In another embodiment, the third redistribution via 172, the second redistribution line 173, the fourth redistribution via 174, and the second bonding pad 175 may each be formed by forming a seed metal layer and then performing an electroplating process.

[0043] FIG. 8 is a cross-sectional view illustrating a step of mounting a first semiconductor die 180 and a second semiconductor die 190 on an upper redistribution structure 170. As shown in FIG. Referring to FIG. 8, a first semiconductor die 180 and a second semiconductor die 190 are mounted on the upper redistribution structure 170 . In one embodiment, the first semiconductor die 180 and the second semiconductor die 190 are each bonded onto the upper redistribution structure 170 using a flip-chip bonding process. The first semiconductor die 180 is bonded to the second bonding pad 175 of the upper redistribution structure 170 by the first connection bump 182, and the second semiconductor die 190 is bonded to the second bonding pad 175 of the upper redistribution structure 170 by the second connection bump 192, thereby electrically connecting the first semiconductor die 180 and the upper redistribution structure 170, and the second semiconductor die 190 and the upper redistribution structure 170. In one embodiment, the first connection bump 182 and the second connection bump 192 may each include at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0044] FIG. 9 is a cross-sectional view showing a step of molding the first semiconductor die 180, the first connection pads 181, the first connection bumps 182, the second semiconductor die 190, the second connection pads 191, and the second connection bumps 192 on the upper rewiring structure 170. Referring to FIG. 9, the first semiconductor die 180, the first connection pads 181, the first connection bumps 182, the second semiconductor die 190, the second connection pads 191, and the second connection bumps 192 are molded on the upper rewiring structure 170 with a second molding material 161. In one embodiment, the molding with second molding material 161 includes a compression molding or transfer molding process. In one embodiment, second molding material 161 includes epoxy molding compound (EMC).

[0045] FIG. 10 is a cross-sectional view showing a step of performing a chemical mechanical planarization (CMP) process on the second molding material 161. As shown in FIG. Referring to FIG. 10, in order to level the top surface of the second molding material 161, a chemical mechanical planarization (CMP) process is performed to flatten the top surface of the second molding material 161. After performing a chemical mechanical planarization (CMP) process, the top surface of the first semiconductor die 180 and the top surface of the second semiconductor die 190 are exposed.

[0046] FIG. 11 is a cross-sectional view showing a step of removing the carrier (C) from the lower rewiring structure 120. As shown in FIG. Referring to FIG. 11, the carrier (C) is removed from the lower surface of the lower redistribution structure 120. Thereafter, as shown in FIG. 1, the connection structure 110 is formed on the lower surface of the lower redistribution structure 120 . A conductive pad 111 is formed below the first redistribution via 122 of the lower redistribution structure 120 . In one embodiment, the conductive pads 111 may include at least one of copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, and alloys thereof. In one embodiment, the conductive pads 111 are formed by a sputtering process or by forming a seed metal layer and then performing an electrolytic plating process. Thereafter, a connection bump 112 is formed under the conductive pad 111 . In one embodiment, the connection bumps 112 may include at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0047] FIG. 12 is a cross-sectional view showing a schematic configuration of a sub-semiconductor package 100B according to an embodiment of the present invention. Referring to FIG. 12, the sub-semiconductor package 100B includes a connection structure 110, a lower rewiring structure 120, a bridge die 130, a passive component die 140, a first connection member 150, a first molding material 160, an upper rewiring structure 170, a first semiconductor die 180, a second semiconductor die 190, and a second molding material 161.

[0048] In one embodiment, the sub-semiconductor package 100B includes a system-in-package (SIP). The sub-semiconductor package 100B is a semiconductor package that includes two or more processor dies and can operate as a single chip. In one embodiment, the sub-semiconductor package 100B may be a semiconductor package manufactured by a chip (die) first process. In one embodiment, the sub-semiconductor package 100B can be manufactured based on fan-out wafer level package (FOWLP) or fan-out panel level package (FOPLP) technology.

[0049] The lower redistribution structure 120 includes a first dielectric 121 , and a first redistribution via 122 , a first redistribution line 123 , and a second redistribution via 124 within the first dielectric 121 . In other embodiments, lower redistribution structures 120 including fewer or greater numbers of redistribution lines and redistribution vias may be within the scope of the present invention. A first connecting member 150 and a first molding material 160 are disposed on the upper surface of the first dielectric 121 . The first rewiring via 122 and the second rewiring via 124 each have a shape in which the width decreases from the bottom to the top.

[0050] The bridge die 130 is disposed on the lower redistribution structure 120 . The bridge die 130 is positioned to be spaced apart from the lower redistribution structure 120 . A first molding material 160 is filled between the bridge die 130 and the lower redistribution structure 120 . The bridge die 130 is connected to the upper redistribution structure 170 via the third connection pads 133 , the third connection bumps 134 and the fourth bonding pads 177 . Each of the third connection pads 133 is disposed between the bridge die 130 and each of the third connection bumps 134 . Each of the third connection pads 133 electrically connects each of the third connection bumps 134 to the bridge die 130 in a vertical direction. Each of the third connection bumps 134 is disposed between each of the third connection pads 133 and each of the fourth bonding pads 177 . Each of the third connection bumps 134 electrically connects each of the fourth bonding pads 177 to each of the third connection pads 133 . Each of the fourth bonding pads 177 connecting to the bridge die 130 is disposed between each of the third connection bumps 134 and each of the third redistribution vias 172 of the upper redistribution structure 170 . Each of the fourth bonding pads 177 connected to the bridge die 130 electrically connects each of the third redistribution vias 172 of the upper redistribution structure 170 to each of the third connection bumps 134 .

[0051] A passive component die 140 is disposed on the lower redistribution structure 120 . The passive component die 140 is spaced apart from the lower redistribution structure 120 . A first molding material 160 is filled between the passive component die 140 and the lower redistribution structure 120 . The passive component die 140 is connected to the upper redistribution structure 170 via the fourth connection pads 143 , the fourth connection bumps 144 and the fourth bonding pads 177 . Each of the fourth connection pads 143 is disposed between the passive component die 140 and each of the fourth connection bumps 144 . Each of the fourth connection pads 143 electrically connects each of the fourth connection bumps 144 to the passive component die 140 in a vertical direction. Each of the fourth connection bumps 144 is disposed between each of the fourth connection pads 143 and each of the fourth bonding pads 177 . Each of the fourth connection bumps 144 electrically connects each of the fourth bonding pads 177 to each of the fourth connection pads 143 . The fourth bonding pads 177 connecting to the passive component die 140 are disposed between the fourth connecting bumps 144 and the third redistribution vias 172 of the upper redistribution structure 170, respectively. Each of the fourth bonding pads 177 connected to the passive component die 140 electrically connects each of the third redistribution vias 172 of the upper redistribution structure 170 to each of the fourth connection bumps 144 .

[0052] Each of the first connection members 150 is disposed between each of the second redistribution vias 124 of the lower redistribution structure 120 and each of the third bonding pads 176 of the upper redistribution structure 170 . Each of the first connection members 150 electrically connects each of the third bonding pads 176 of the upper redistribution structure 170 to each of the second redistribution vias 124 of the lower redistribution structure 120 .

[0053] The first molding material 160 is disposed on the lower rewiring structure 120 and covers the bridge die 130, the third connection pad 133, the third connection bump 134, the passive element die 140, the fourth connection pad 143, the fourth connection bump 144, the first connection member 150, the third bonding pad 176, and the fourth bonding pad 177. The first molding material 160 protects the bridge die 130, the third connection pad 133, the third connection bump 134, the passive element die 140, the fourth connection pad 143, the fourth connection bump 144, the first connection member 150, the third bonding pad 176, and the fourth bonding pad 177 from the external environment.

[0054] The upper rewiring structure 170 is disposed on the first connection member 150 and the first molding material 160 . The upper redistribution structure 170 includes a second dielectric 171, a third redistribution via 172 within the second dielectric 171, a second redistribution line 173 and a fourth redistribution via 174, and a third bonding pad 176 and a fourth bonding pad 177 below the second dielectric 171. In other embodiments, upper redistribution structure 170 including fewer or greater numbers of redistribution lines, redistribution vias, and bonding pads may be within the scope of the present invention.

[0055] The second dielectric 171 protects and insulates the third redistribution via 172, the second redistribution line 173, and the fourth redistribution via 174. On the upper surface of the second dielectric 171, the third connection terminal 183, the fourth connection terminal 193, and the second molding material 161 are disposed. A third bonding pad 176, a fourth bonding pad 177, and a first molding material 160 are disposed on the lower surface of the second dielectric 171.

[0056] Each of the third bonding pads 176 is disposed between each of the first connection members 150 and each of the third rewiring vias 172 . Each of the third bonding pads 176 electrically connects each of the third rewiring vias 172 to each of the first connection members 150 . Each of the fourth bonding pads 177 is disposed between each of the third connection bumps 134 and each of the third rewiring vias 172, or between each of the fourth connection bumps 144 and each of the third rewiring vias 172. Each of the fourth bonding pads 177 electrically connects each of the third rewiring vias 172 to each of the third connection bumps 134 or each of the third rewiring vias 172 to each of the fourth connection bumps 144 .

[0057] Each of the third redistribution vias 172 is disposed between each of the third bonding pads 176 and each of the second redistribution lines 173, or between each of the fourth bonding pads 177 and each of the second redistribution lines 173. Each of the third redistribution vias 172 electrically connects each of the second redistribution lines 173 to each of the third bonding pads 176 or each of the second redistribution lines 173 to each of the fourth bonding pads 177 . Each of the second redistribution lines 173 is disposed between each of the third redistribution vias 172 and each of the fourth redistribution vias 174 . Each of the second redistribution lines 173 electrically connects each of the fourth redistribution vias 174 to each of the third redistribution vias 172 in the horizontal direction. Each of the fourth rewiring vias 174 is disposed between each of the second rewiring lines 173 and each of the third connection terminals 183, or between each of the second rewiring lines 173 and each of the fourth connection terminals 193. Each of the fourth redistribution vias 174 electrically connects each of the third connection terminals 183 to each of the second redistribution lines 173 or each of the fourth connection terminals 193 to each of the second redistribution lines 173 in the vertical direction. The third rewiring via 172 and the fourth rewiring via 174 each have a shape in which the width decreases from the bottom to the top.

[0058] Each of the third connection terminals 183 is disposed between a respective one of the wirings of the first semiconductor die 180 and a respective one of the fourth rewiring vias 174 . Each of the third connection terminals 183 electrically connects a respective one of the wirings of the first semiconductor die 180 to a respective one of the fourth rewiring vias 174 . Each of the fourth connection terminals 193 is disposed between a respective one of the wirings of the second semiconductor die 190 and a respective one of the fourth rewiring vias 174 . Each of the fourth connection terminals 193 electrically connects a respective one of the wirings of the second semiconductor die 190 to a respective one of the fourth rewiring vias 174 .

[0059] The second molding material 161 is disposed on the upper redistribution structure 170 and covers the first semiconductor die 180 , the third connecting terminal 183 , the second semiconductor die 190 , and the fourth connecting terminal 193 . The second molding material 161 protects the first semiconductor die 180, the third connecting terminal 183, the second semiconductor die 190, and the third connecting terminal 183 from the external environment. The same applies as the contents described for the sub-semiconductor package 100A of the embodiment in FIG. 1 except for the contents described for the sub-semiconductor package 100B of the embodiment in FIG.

[0060] 13 to 23 are cross-sectional views sequentially illustrating a method for manufacturing the sub-semiconductor package 100B according to the embodiment of FIG. 13 to 23 are cross-sectional views sequentially illustrating a method for manufacturing the sub-semiconductor package 100B to which the chip-first process is applied. FIG. 13 is a cross-sectional view showing a step of attaching a first semiconductor die 180 and a second semiconductor die 190 onto a carrier (C).

[0061] Referring to FIG. 13, a first semiconductor die 180 and a second semiconductor die 190 are attached onto a carrier (C). First, provide a carrier (C). In one embodiment, the carrier (C) may comprise a silicon-based material such as glass or silicon oxide, an organic material, or other material such as aluminum oxide, any combination of these materials, or the like. The first semiconductor die 180 is attached to the carrier (C) so that the surface opposite to the surface on which the third connection terminals 183 are arranged is in contact with the carrier (C). The second semiconductor die 190 is attached to the carrier (C) so that the surface opposite to the surface on which the fourth connection terminals 193 are arranged is in contact with the carrier (C). In one embodiment, the first semiconductor die 180 and the second semiconductor die 190 are each attached onto the carrier (C) by a die attach film (not shown).

[0062] FIG. 14 is a cross-sectional view showing a step of molding the first semiconductor die 180, the third connecting terminal 183, the second semiconductor die 190, and the fourth connecting terminal 193 on a carrier (C). Referring to FIG. 14, the first semiconductor die 180, the third connection terminal 183, the second semiconductor die 190, and the fourth connection terminal 193 are molded in the second molding material 161 on the carrier (C). In one embodiment, the molding with second molding material 161 includes a compression molding or transfer molding process. In one embodiment, second molding material 161 includes epoxy molding compound (EMC).

[0063] FIG. 15 is a cross-sectional view showing a step of performing a chemical mechanical planarization (CMP) process on the second molding material 161. As shown in FIG. Referring to FIG. 15, in order to level the top surface of the second molding material 161, a chemical mechanical planarization (CMP) process is performed to flatten the top surface of the second molding material 161. After performing a chemical mechanical planarization (CMP) process, the top surfaces of the third and fourth connection terminals 183 and 193 are exposed.

[0064] FIG. 16 is a cross-sectional view showing a step of forming the upper rewiring structure 170 on the third connection terminal 183, the fourth connection terminal 193, and the second molding material 161. As shown in FIG. Referring to FIG. 16, a second dielectric 171 is formed on the third connection terminal 183, the fourth connection terminal 193, and the second molding material 161. In one embodiment, the second dielectric 171 comprises a photosensitive dielectric (PID) used in a redistribution process. In one embodiment, the second dielectric layer 171 is formed by a spin coating process. After forming the second dielectric 171, the second dielectric 171 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form a fourth redistribution via 174. After forming the fourth redistribution via 174, a second dielectric 171 is additionally formed on the fourth redistribution via 174 and the second dielectric 171, and the additionally formed second dielectric 171 is selectively etched to form an opening, and the opening is filled with a conductive material to form a second redistribution line 173.

[0065] After forming the second redistribution line 173, a second dielectric 171 is additionally formed on the second redistribution line 173 and the second dielectric 171, the additionally formed second dielectric 171 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form a third redistribution via 172. After forming the third redistribution via 172, photoresist is additionally deposited on the third redistribution via 172 and the second dielectric 171, and the photoresist is selectively exposed and developed to form a photoresist pattern including via holes. The via holes are filled with a conductive material to form the third bonding pad 176 and the fourth bonding pad 177. During manufacturing using the chip-first process, the third redistribution via 172 and the fourth redistribution via 174 each have a shape in which the width increases from bottom to top, and in the final product sub-semiconductor package 100B, the third redistribution via 172 and the fourth redistribution via 174 each have a shape in which the width decreases from bottom to top.

[0066] In one embodiment, the third redistribution via 172, the second redistribution line 173, the fourth redistribution via 174, the third bonding pad 176, and the fourth bonding pad 177 may each include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the third redistribution via 172, the second redistribution line 173, the fourth redistribution via 174, the third bonding pad 176, and the fourth bonding pad 177 are each formed by a sputtering process. In another embodiment, the third redistribution via 172, the second redistribution line 173, the fourth redistribution via 174, the third bonding pad 176, and the fourth bonding pad 177 may each be formed by forming a seed metal layer followed by an electroplating process.

[0067] FIG. 17 is a cross-sectional view showing a step of forming the first connection member 150 on the upper rewiring structure 170. As shown in FIG. Referring to FIG. 17, the first connection member 150 is formed on the third bonding pad 176 of the upper redistribution structure 170 . In one embodiment, the first connection member 150 is formed by a sputtering process. In another embodiment, the first connection member 150 may be formed by forming a seed metal layer and then performing an electrolytic plating process. In one embodiment, the first connecting member 150 may include at least one of copper, aluminum, tungsten, nickel, gold, silver, chromium, antimony, tin, titanium, and alloys thereof.

[0068] FIG. 18 is a cross-sectional view illustrating a step of mounting the bridge die 130 and the passive component die 140 on the upper redistribution structure 170. As shown in FIG. Referring to FIG. 18, the bridge die 130 and the passive component die 140 are mounted on the upper rewiring structure 170 . In one embodiment, the bridge die 130 and the passive component die 140 are each bonded onto the upper redistribution structure 170 using a flip-chip bonding process. The bridge die 130 is bonded to the fourth bonding pad 177 of the upper redistribution structure 170 by the third connection bump 134, and the passive component die 140 is bonded to the fourth bonding pad 177 of the upper redistribution structure 170 by the fourth connection bump 144, thereby electrically connecting the bridge die 130 and the upper redistribution structure 170, and the passive component die 140 and the upper redistribution structure 170. In one embodiment, the third connection bump 134 and the fourth connection bump 144 may each include at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0069] Figure 19 is a cross-sectional view showing a step of molding the bridge die 130, the third connection pad 133, the third connection bump 134, the passive element die 140, the fourth connection pad 143, the fourth connection bump 144, and the first connection member 150 on the upper rewiring structure 170. Referring to FIG. 19, on the lower rewiring structure 120, the bridge die 130, the third connection pad 133, the third connection bump 134, the passive element die 140, the fourth connection pad 143, the fourth connection bump 144, and the first connection member 150 are molded in the first molding material 160. In one embodiment, molding with first molding material 160 includes a compression molding or transfer molding process. In one embodiment, first molding material 160 comprises epoxy molding compound (EMC).

[0070] FIG. 20 is a cross-sectional view showing a step of performing a chemical mechanical planarization (CMP) process on the first molding material 160. As shown in FIG. Referring to FIG. 20, in order to level the top surface of the first molding material 160, a chemical mechanical planarization (CMP) process is performed to flatten the top surface of the first molding material 160. After performing a chemical mechanical planarization (CMP) process, the top surface of the first connection member 150 is exposed.

[0071] FIG. 21 is a cross-sectional view showing a step of forming the lower rewiring structure 120 on the first connection member 150 and the first molding material 160. As shown in FIG. Referring to FIG. 21, a second dielectric 171 is formed on the first connecting member 150 and the first molding material 160. In one embodiment, the first dielectric 121 comprises a photosensitive dielectric (PID) used in a redistribution process. In one embodiment, the first dielectric layer 121 is formed by a spin coating process. After forming the first dielectric 121, the first dielectric 121 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form the second redistribution via 124. After forming the second redistribution via 124, the first dielectric 121 is additionally formed on the second redistribution via 124 and the first dielectric 121, and the additionally formed first dielectric 121 is selectively etched to form an opening, and the opening is filled with a conductive material to form the first redistribution line 123. After forming the first redistribution line 123, the first dielectric 121 is additionally formed on the first redistribution line 123 and the first dielectric 121, the additionally formed first dielectric 121 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form the first redistribution via 122. During manufacturing using the chip-first process, the first rewiring via 122 and the second rewiring via 124 each have a shape in which the width increases from bottom to top, and in the final product sub-semiconductor package 100B, the first rewiring via 122 and the second rewiring via 124 each have a shape in which the width decreases from bottom to top.

[0072] In one embodiment, the first redistribution via 122, the first redistribution line 123, and the second redistribution via 124 may each include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the first redistribution via 122, the first redistribution line 123, and the second redistribution via 124 are each formed by a sputtering process. In another embodiment, the first redistribution via 122, the first redistribution line 123, and the second redistribution via 124 may be formed by forming a seed metal layer and then performing an electrolytic plating process.

[0073] FIG. 22 is a cross-sectional view showing a step of forming a connection structure 110 on the lower rewiring structure 120. As shown in FIG. Referring to FIG. 22, a connection structure 110 is formed on a lower rewiring structure 120 . A conductive pad 111 is formed on the first redistribution via 122 of the lower redistribution structure 120 . In one embodiment, the conductive pads 111 may include at least one of copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, and alloys thereof. In one embodiment, the conductive pads 111 are formed by a sputtering process or by forming a seed metal layer and then performing an electrolytic plating process. Thereafter, the connection bumps 112 are formed under the conductive pads 111 . In one embodiment, the connection bumps 112 may include at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0074] FIG. 23 is a cross-sectional view showing a step of removing the carrier (C) from the lower rewiring structure 120. As shown in FIG. Referring to FIG. 23, the carrier (C) is removed from the lower rewiring structure 120.

[0075] FIG. 24 is a cross-sectional view showing a schematic configuration of a semiconductor package 200A according to an embodiment of the present invention. Referring to FIG. 24, the semiconductor package 200A includes an external connection structure 210, a front rewiring structure (first rewiring structure) 220, a sub-semiconductor package (or sub-semiconductor package 100B) 100A, a second connection member 250, a third molding material 260, a rear rewiring structure (fourth rewiring structure) 270, a third semiconductor die 280, and a fourth molding material 261. In one embodiment, the semiconductor package 200A includes a package on package (PoP). In one embodiment, the semiconductor package 200A can be manufactured based on fan-out wafer level package (FOWLP) or fan-out panel level package (FOPLP) technology.

[0076] The external connection structure 210 is disposed on the bottom surface of the front rewiring structure 220 . The external connection structure 210 includes a conductive pad 211 and an external connection bump 212 . Each of the conductive pads 211 is disposed between each of the external connection bumps 212 and each of the fifth redistribution vias 222 of the front side redistribution structure 220 . Each of the conductive pads 211 electrically connects each of the fifth redistribution vias 222 of the front redistribution structure 220 to each of the external connection bumps 212 . The external connection bumps 212 electrically connect the semiconductor package 200A to an external device (not shown). In one embodiment, the conductive pads 211 may include at least one of copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, and alloys thereof. In one embodiment, the external connection bumps 212 may include at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0077] The front rewiring structure 220 includes a third dielectric 221, a fifth rewiring via 222 within the third dielectric 221, a third rewiring line 223 and a sixth rewiring via 224, and a fifth bonding pad 225 and a sixth bonding pad 226 on the third dielectric 221. In other embodiments, a frontside redistribution structure 220 including fewer or greater numbers of redistribution lines, redistribution vias, and bonding pads may be within the scope of the present invention.

[0078] The third dielectric 221 protects and insulates the fifth redistribution via 222, the third redistribution line 223, and the sixth redistribution via 224. A fifth bonding pad 225, a sixth bonding pad 226, and a third molding material 260 are disposed on the top surface of the third dielectric 221. The connection structure 110 is disposed on the lower surface of the third dielectric 221 . In one embodiment, the third dielectric 221 comprises a photosensitive dielectric (PID) used in a redistribution process.

[0079] Each of the fifth redistribution vias 222 is disposed between each of the conductive pads 211 and each of the third redistribution lines 223 . Each of the fifth redistribution vias 222 electrically connects each of the third redistribution lines 223 to each of the conductive pads 211 . Each of the third redistribution lines 223 is disposed between each of the fifth redistribution vias 222 and each of the sixth redistribution vias 224 . Each of the third redistribution lines 223 electrically connects each of the sixth redistribution vias 224 to each of the fifth redistribution vias 222 . Each of the sixth redistribution vias 224 is disposed between each of the third redistribution lines 223 and each of the fifth bonding pads 225, or between each of the third redistribution lines 223 and each of the sixth bonding pads 226. Each of the sixth redistribution vias 224 electrically connects each of the fifth bonding pads 225 to each of the third redistribution lines 223 or each of the sixth bonding pads 226 to each of the third redistribution lines 223 .

[0080] Each of the fifth bonding pads 225 is disposed between each of the sixth rewiring vias 224 and each of the second connection members 250 . The fifth bonding pads 225 electrically connect the second connection members 250 to the sixth rewiring vias 224, respectively. Each of the sixth bonding pads 226 is disposed between each of the sixth rewiring vias 224 and each of the connection bumps 112 of the sub-semiconductor package 100A. Each of the sixth bonding pads 226 electrically connects each of the connection bumps 112 of the sub-semiconductor package 100A to each of the sixth rewiring vias 224. In one embodiment, the fifth redistribution via 222, the third redistribution line 223, the sixth redistribution via 224, the fifth bonding pad 225, and the sixth bonding pad 226 may each include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof.

[0081] The sub-semiconductor package 100A is disposed on the front rewiring structure 220. The sub-semiconductor package 100A is disposed side by side with the second connection member 250. The sub-semiconductor package 100A can be substituted for the sub-semiconductor package 100B in FIG. The contents of the sub-semiconductor package 100A or 100B described in relation to FIG. 1 or FIG. 12 are similarly applied to the sub-semiconductor package 100A or 100B.

[0082] The second connection member 250 is disposed on the front rewiring structure 220 . In one embodiment, the second connecting member 250 includes a conductive post. The second connection member 250 is disposed around the periphery of the sub-semiconductor package 100A. The second connection member 250 is disposed on the side of the sub-semiconductor package 100A. Each of the second connection members 250 is disposed between a corresponding one of the fifth bonding pads 225 of the front redistribution structure 220 and a corresponding one of the seventh redistribution vias 272 of the rear redistribution structure 270 . Each of the second connection members 250 electrically connects each of the seventh redistribution vias 272 of the rear redistribution structure 270 to each of the fifth bonding pads 225 of the front redistribution structure 220 . The second connecting member 250 is disposed through the third molding material 260 . The side surface of second connection member 250 is surrounded by third molding material 260 . In one embodiment, the second connecting member 250 may include at least one of copper, aluminum, tungsten, nickel, gold, silver, chromium, antimony, tin, titanium, and alloys thereof.

[0083] According to this embodiment, the bridge die 130 and the passive component die 140 are disposed within a sub-semiconductor package 100A, and the sub-semiconductor package 100A is disposed on the front rewiring structure 220. This eliminates the need to form routing paths for the bridge die 130 within the front redistribution structure 220, thereby reducing the total number of layers in the front redistribution structure 220.

[0084] The third molding material 260 is disposed on the front rewiring structure 220 and covers the sub-semiconductor package 100A and the second connecting member 250. The third molding material 260 protects the sub-semiconductor package 100A and the second connecting member 250 from the external environment. In one embodiment, third molding material 260 comprises epoxy molding compound (EMC). According to this embodiment, the bridge die 130 and the passive component die 140 are disposed in the sub-semiconductor package 100A and are covered by a first molding material 160 in the sub-semiconductor package 100A and a third molding material 260 that covers the sub-semiconductor package 100A. As a result, the bridge die 130 and the passive element die 140 are not exposed to the outside, but are doubly covered by the first molding material 160 and the third molding material 260, and are protected from the external environment.

[0085] The rear redistribution structure 270 includes a fourth dielectric 271, a seventh redistribution via 272 within the fourth dielectric 271, a fourth redistribution line 273 and an eighth redistribution via 274, and a seventh bonding pad 275 on the fourth dielectric 271. In other embodiments, a backside redistribution structure 270 including fewer or more redistribution lines, redistribution vias, and bond pads may be within the scope of the present invention.

[0086] The fourth dielectric 271 protects and insulates the seventh redistribution via 272, the fourth redistribution line 273, and the eighth redistribution via 274. A seventh bonding pad 275 and a fourth molding material 261 are disposed on the top surface of the fourth dielectric 271 . The second connecting member 250 and the third molding material 260 are disposed on the lower surface of the fourth dielectric 271 . In one embodiment, the fourth dielectric 271 comprises a photosensitive dielectric (PID) used in a redistribution process.

[0087] Each of the seventh redistribution vias 272 is disposed between each of the second connection members 250 and each of the fourth redistribution lines 273. Each of the seventh redistribution vias 272 electrically connects each of the fourth redistribution lines 273 to each of the second connection members 250 . Each of the fourth redistribution lines 273 is disposed between each of the seventh redistribution vias 272 and each of the eighth redistribution vias 274 . Each of the fourth redistribution lines 273 electrically connects each of the eighth redistribution vias 274 to each of the seventh redistribution vias 272 . Each of the eighth redistribution vias 274 is disposed between each of the fourth redistribution lines 273 and each of the seventh bonding pads 275 . Each of the eighth redistribution vias 274 electrically connects each of the seventh bonding pads 275 to each of the fourth redistribution lines 273 . Each of the seventh bonding pads 275 is disposed between each of the eighth rewiring vias 274 and each of the fifth connection bumps 282 . Each of the seventh bonding pads 275 electrically connects each of the fifth connection bumps 282 to each of the eighth rewiring vias 274 . In one embodiment, the seventh redistribution via 272, the fourth redistribution line 273, the eighth redistribution via 274, and the seventh bonding pad 275 may each include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof.

[0088] A third semiconductor die 280 is disposed on the backside redistribution structure 270 . In one embodiment, the third semiconductor die 280 includes a memory die. In one embodiment, the third semiconductor die 280 may include DRAM or High Bandwidth Memory (HBM). The third semiconductor die 280 is connected to the back redistribution structure 270 via the fifth connection pads 281 and the fifth connection bumps 282 . Each of the fifth connection pads 281 is disposed between the third semiconductor die 280 and each of the fifth connection bumps 282 . Each of the fifth connection pads 281 electrically connects the third semiconductor die 280 to each of the fifth connection bumps 282 in a vertical direction. Each of the fifth connection bumps 282 is disposed between each of the seventh bonding pads 275 and each of the fifth connection pads 281 . Each of the fifth connection bumps 282 electrically connects each of the fifth connection pads 281 to each of the seventh bonding pads 275 . In one embodiment, the fifth connection bump 282 may include at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0089] A fourth molding material 261 is disposed on the rear redistribution structure 270 and covers the third semiconductor die 280 , the fifth connection pads 281 , and the fifth connection bumps 282 . The fourth molding material 261 protects the third semiconductor die 280, the fifth connection pads 281, and the fifth connection bumps 282 from the external environment. In one embodiment, fourth molding material 261 includes epoxy molding compound (EMC). The top surface of the third semiconductor die 280 is exposed to the outside from the fourth molding material 261 .

[0090] FIG. 25 is a cross-sectional view showing a schematic configuration of a semiconductor package 200B according to an embodiment of the present invention, and FIG. 26 is a plan view showing the upper surface of the semiconductor package 200B according to the embodiment of FIG. In FIG. 26, the sub-semiconductor package 100A and the second connecting member 250 are indicated by dotted lines. 25 and 26, a semiconductor package 200B includes an asymmetric package-on-package (PoP). The second connection member 250 is disposed on one side of the sub-semiconductor package 100A. The sub-semiconductor package 100A can be substituted for the sub-semiconductor package 100B in FIG.

[0091] The semiconductor package 200B includes a heat dissipation structure 290. A heat dissipation structure 290 is disposed on the back redistribution structure 270 and on the side of the third semiconductor die 280 . The heat dissipation structure 290 dissipates heat generated within the sub-semiconductor package 100A or within the semiconductor package 200B, improving the thermal characteristics of the semiconductor package 200B. In one embodiment, the heat dissipation structure 290 includes a heat spreader.

[0092] The heat dissipation structure 290 is attached onto the rear rewiring structure 270 by a third adhesive member 291 . In one embodiment, the third adhesive member 291 may include adhesive tape, silver paste, epoxy resin, polyimide, or thermal interface materials (TIM). A thermal interface material (TIM) is a material inserted to improve thermal coupling between the backside redistribution structure 270 and the heat dissipation structure 290, which are devices that dissipate heat. The thermal interface material (TIM) fills the air gap at the contact surface between the rear redistribution structure 270 and the heat dissipation structure 290 to reduce thermal contact resistance. In one embodiment, the thermal interface material (TIM) may include a thermal paste, a thermal pad, a phase change material (PCM), grease, or a metallic material.

[0093] Electrical signals between the sub-semiconductor package 100A and the third semiconductor die 280 are routed via the second connection member 250, and the footprint of the second connection member 250 is included within the footprint of the third semiconductor die 280 in order to set the signal transmission path between the sub-semiconductor package 100A and the third semiconductor die 280 in the semiconductor package 200B having an asymmetric structure to the shortest distance and improve the signal characteristics of the semiconductor package 200B. In order to set the shortest path for heat generated in the sub-semiconductor package 100A to dissipate to the outside via the heat dissipation structure 290 and improve the heat generation characteristics of the semiconductor package 200B, the footprint of the sub-semiconductor package 100A overlaps the footprint of the heat dissipation structure 290. The contents described for the semiconductor package 200A according to the embodiment of FIG. 24 are similarly applied to the semiconductor package 200B according to the embodiment of FIGS. 25 and 26 , except for the contents described for the semiconductor package 200B according to the embodiment of FIGS.

[0094] FIG. 27 is a cross-sectional view showing a schematic configuration of a semiconductor package 200C according to an embodiment of the present invention. Referring to FIG. 27, the sub-semiconductor package 100A and the third semiconductor die 280 are disposed on the front rewiring structure 220. The sub-semiconductor package 100A and the third semiconductor die 280 are disposed side by side on the front rewiring structure 220. The sub-semiconductor package 100A can be substituted for the sub-semiconductor package 100B in FIG.

[0095] The third semiconductor die 280 is connected to the front redistribution structure 220 via fifth connection pads 281 and fifth connection bumps 282 . Each of the fifth connection pads 281 is disposed between the third semiconductor die 280 and each of the fifth connection bumps 282 . Each of the fifth connection pads 281 electrically connects the third semiconductor die 280 to each of the fifth connection bumps 282 in a vertical direction. Each of the fifth connection bumps 282 is disposed between each of the fifth bonding pads 225 and each of the fifth connection pads 281 . Each of the fifth connection bumps 282 electrically connects each of the fifth connection pads 281 to each of the fifth bonding pads 225 .

[0096] The third molding material 260 is disposed on the front rewiring structure 220 and covers the sub-semiconductor package 100A, the third semiconductor die 280, the fifth connection pads 281, and the fifth connection bumps 282. The third molding material 260 protects the sub-semiconductor package 100A, the third semiconductor die 280, the fifth connection pads 281, and the fifth connection bumps 282 from the external environment. In one embodiment, third molding material 260 comprises epoxy molding compound (EMC). The top surface of the sub-semiconductor package 100A and the top surface of the third semiconductor die 280 are exposed to the outside from the third molding material 260. The contents described for the semiconductor package 200A according to the embodiment of FIG. 24 apply in the same manner except for the contents described for the semiconductor package 200C according to the embodiment of FIG. 27.

[0097] According to the semiconductor package of the present invention, the sub-semiconductor package 100A including the bridge die 130, the passive component die 140, the first semiconductor die 180, and the second semiconductor die 190 is not limited to the embodiments of Figures 24, 25, and 27, and can be applied to various platforms.

[0098] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0099] 100A, 100B Sub-semiconductor Package 110 Connection structure 111 Conductive Pad 112 Connection Bump 120 Lower rerouting structure 121 First Dielectric 122 1st rewiring via 123 First Rewiring Line 124 Second rewiring via 125 1st bonding pad 130 Bridge Die 131 First connection terminal 132 first adhesive member 133 Third connection pad 134 3rd connection bump 140 passive element die 141 Second connection terminal 142 second adhesive member 150 first connecting member 160 First molding material 161 Second molding material 170 Upper rerouting structure 171 Second Dielectric 172 3rd rewiring via 173 Second Rewiring Line 174 4th rewiring via 175 Second bonding pad 176 3rd bonding pad 177 4th bonding pad 180 First semiconductor die 181 First connection pad 182 First connection bump 183 Third connection terminal 190 Second semiconductor die 191 Second connection pad 192 Second connection bump 193 4th connection terminal 200A, 200B, 200C semiconductor packages 210 External connection structure 220 Front rewiring structure 221 Third Dielectric 222 5th rewiring via 223 Third Rewiring Line 224 6th rewiring via 225 5th bonding pad 226 6th bonding pad 250 second connecting member 260 Third molding material 261 4th molding material 270 Rear rewiring structure 271 Fourth Dielectric 272 7th rewiring via 273 4th Rewiring Line 274 8th Rerouting Via 275 7th bonding pad 280 Third Semiconductor Die 281 5th Connection Pad 282 5th Connection Bump 290 Heat dissipation structure 291 Third adhesive member

Claims

1. a first redistribution structure; a sub-semiconductor package disposed on the first rewiring structure; Here, the sub-semiconductor package is a second redistribution structure; a bridge die disposed on an upper surface of the second redistribution structure; a first molding material disposed on an upper surface of the second redistribution structure and covering the bridge die; a plurality of connection structures disposed on a lower surface of the second redistribution structure and connected to the first redistribution structure; a third rewiring structure disposed on the first molding material and on the bridge die; a first semiconductor die disposed on the third redistribution structure; a second semiconductor die disposed on the third redistribution structure and to the side of the first semiconductor die; wherein the second semiconductor die is electrically connected to the first semiconductor die via the bridge die; a second molding material covering the first semiconductor die and the second semiconductor die over the third redistribution structure; a third molding material covering the sub-semiconductor package on the first rewiring structure.

2. The semiconductor package of claim 1 , wherein the sub-semiconductor package further comprises a first adhesive member between the second redistribution structure and the bridge die.

3. the sub-semiconductor package further includes a passive component die disposed on an upper surface of the second redistribution structure and beside the bridge die; the first molding material covers the passive component die over the second redistribution structure; The semiconductor package of claim 1 , wherein the bridge die and the passive component die overlap some of the plurality of connection structures.

4. 4. The semiconductor package of claim 3, wherein the passive component die includes an integrated stack capacitor.

5. The semiconductor package of claim 3 , wherein the sub-semiconductor package further comprises a second adhesive member between the second redistribution structure and the passive component die.

6. The semiconductor package of claim 1 , wherein the first semiconductor die and the second semiconductor die each include an application processor (AP).

7. The semiconductor package of claim 1 , wherein the bridge die comprises a silicon bridge.

8. a first redistribution structure; a sub-semiconductor package disposed on the first rewiring structure; Here, the sub-semiconductor package is a second redistribution structure; a bridge die disposed on the second redistribution structure; a plurality of first connection members disposed on the second rewiring structure and on the side of the bridge die; a first molding material disposed on the second rewiring structure and covering the bridge die and the plurality of first connection members; a third rewiring structure disposed on the first molding material, on the bridge die, and on the plurality of first connection members; a first semiconductor die disposed on the third redistribution structure; a second semiconductor die disposed on the third redistribution structure and to the side of the first semiconductor die; wherein the second semiconductor die is electrically connected to the first semiconductor die via the bridge die; a second molding material disposed on the third redistribution structure and covering the first semiconductor die and the second semiconductor die; a plurality of second connection members disposed on the first rewiring structure; a third molding material disposed on the first rewiring structure and covering the sub-semiconductor package and the plurality of second connection members; a fourth rewiring structure disposed on the third molding material and on the plurality of second connection members; a third semiconductor die disposed on the fourth rewiring structure.

9. 10. The semiconductor package of claim 8, further comprising a heat dissipation structure disposed on the fourth redistribution structure and on a side of the third semiconductor die.

10. 10. The semiconductor package of claim 9, further comprising a thermal interface material (TIM) between the fourth redistribution structure and the heat dissipation structure.

11. The semiconductor package according to claim 8 , wherein the plurality of second connection members are arranged around the periphery of the sub-semiconductor package.

12. The semiconductor package according to claim 9 , wherein the plurality of second connection members are disposed on one side of the sub-semiconductor package.

13. The semiconductor package of claim 12 , wherein the footprints of the plurality of second connection members are contained within the footprint of the third semiconductor die.

14. The semiconductor package of claim 12 , wherein the footprint of the sub-semiconductor package overlaps with the footprint of the heat dissipation structure.

15. The semiconductor package according to claim 9 , wherein the heat dissipation structure includes a heat spreader.

16. The semiconductor package according to claim 8 , wherein the plurality of first connection members include conductive posts.

17. The semiconductor package according to claim 8 , wherein the plurality of second connection members include conductive posts.

18. The semiconductor package of claim 8 , wherein the third semiconductor die comprises a memory die.

19. a first redistribution structure; a sub-semiconductor package disposed on the first rewiring structure; Here, the sub-semiconductor package is a second redistribution structure; a bridge die disposed on the second redistribution structure; a plurality of first connection members disposed on the second rewiring structure; a first molding material disposed on the second rewiring structure and covering the bridge die and the plurality of first connection members; a third rewiring structure disposed on the first molding material, on the bridge die, and on the plurality of first connection members; a first semiconductor die disposed on the third redistribution structure; a second semiconductor die disposed on the third redistribution structure and to the side of the first semiconductor die; wherein the second semiconductor die is electrically connected to the first semiconductor die via the bridge die; a second molding material disposed on the third redistribution structure and covering the first semiconductor die and the second semiconductor die; a third semiconductor die disposed on the first rewiring structure and to the side of the sub-semiconductor package; a third molding material disposed on the first rewiring structure and covering the sub-semiconductor package and the third semiconductor die.

20. 20. The semiconductor package of claim 19, wherein a top surface of the sub-semiconductor package and a top surface of the third semiconductor die are exposed to the outside from the third molding material.

Images