Semiconductor light emitting device and method for manufacturing semiconductor light emitting device

Abstract

To improve reliability of a semiconductor light-emitting element.SOLUTION: The semiconductor light-emitting device 10 includes a laminated film which is provided on a p-side contact electrode 30 and in which a first TiN layer and an Rh layer are alternately laminated, a second TiN layer which is provided on the laminated film, a p-side current diffusion layer 34 which has a p-side connection opening 34a exposing the Rh layer and covers the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, and the p-side current diffusion layer 34 at a position different from the pad opening, a protective layer which has a pad opening provided in the p-side connection opening and is formed of a dielectric material, and a p-side junction layer 46 which is provided on the protective layer outside the pad opening and in contact with the Rh layer of the p-side current diffusion layer 34.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the same. [Background technology]

[0002] The semiconductor light emitting device has an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on a substrate, and is bonded to a submount substrate via, for example, an AuSn layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-204885 Summary of the Invention [Problem to be solved by the invention]

[0004] If AuSn used for bonding to the submount substrate diffuses into the semiconductor layer, it may lead to a decrease in light emission efficiency.

[0005] The present invention has been made in view of these problems, and has an object to provide a technique for improving the reliability of semiconductor light-emitting devices. [Means for solving the problem]

[0006] a current spreading layer including a contact opening that exposes the Rh layer and that is formed on the contact electrode; a protective layer having a pad opening in the contact opening, the protective layer covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer at a position different from the pad opening; a pad electrode in contact with the Rh layer of the current spreading layer at the contact opening and that is formed on the protective layer outside the pad opening; and a bonding layer including AuSn and that is formed on the pad electrode.

[0007] Another aspect of the present invention is a method for manufacturing a semiconductor light-emitting device, comprising the steps of: forming an active layer on an n-type semiconductor layer; forming a p-type semiconductor layer on the active layer; removing portions of the p-type semiconductor layer and the active layer to expose an upper surface of the n-type semiconductor layer; forming a contact electrode in contact with the upper surface of the p-type semiconductor layer or in contact with the upper surface of the n-type semiconductor layer; forming a current spreading layer on the contact electrode, the current spreading layer including a laminated film formed by alternating first TiN layers and Rh layers and a second TiN layer on the laminated film; forming a protective layer made of a dielectric material to cover the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer; removing the protective layer on the current spreading layer to form a pad opening; removing the second TiN layer in the pad opening to form a connection opening exposing the Rh layer of the current spreading layer; forming a pad electrode in contact with the Rh layer of the current spreading layer in the connection opening and provided on the protective layer outside the pad opening; and forming a bonding layer on the pad electrode containing AuSn. [Effects of the Invention]

[0008] According to the present invention, the reliability of the semiconductor light emitting element can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor light emitting device according to an embodiment. [Figure 2] 3 is a cross-sectional view schematically showing the configuration of a p-side contact electrode, a p-side current diffusion layer, and a p-side pad electrode. FIG. [Figure 3] 3 is a cross-sectional view schematically showing the configuration of an n-side contact electrode, an n-side current diffusion layer, and an n-side pad electrode. FIG. [Figure 4] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 5] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 6] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 7] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 8] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 9] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 10] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 11] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 12] 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor light-emitting device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the description, the same elements are designated by the same reference numerals, and redundant explanations will be omitted as appropriate. To facilitate understanding of the description, the dimensional ratios of the components in each drawing do not necessarily correspond to the dimensional ratios of the actual light-emitting element.

[0011] The semiconductor light-emitting device according to this embodiment is configured to emit "deep ultraviolet light" with a central wavelength λ of about 360 nm or less, and is a so-called DUV-LED (Deep UltraViolet-Light Emitting Diode) chip. In order to output deep ultraviolet light of such a wavelength, an aluminum gallium nitride (AlGaN)-based semiconductor material with a bandgap of about 3.4 eV or more is used. In this embodiment, in particular, the case of emitting deep ultraviolet light with a central wavelength λ of about 240 nm to 320 nm is shown.

[0012] In this specification, the "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and includes semiconductor materials containing other materials such as indium nitride (InN). Therefore, the "AlGaN-based semiconductor material" referred to in this specification can be represented by the composition of In 1-x-y Al x Ga y N (0 < x + y ≤ 1, 0 < x < 1, 0 < y < 1), and includes AlGaN or InAlGaN. The "AlGaN-based semiconductor material" in this specification has, for example, a molar fraction of each of AlN and GaN of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

[0013] In addition, in order to distinguish materials that do not contain AlN, they may be referred to as "GaN-based semiconductor materials". "GaN-based semiconductor materials" include GaN and InGaN. Similarly, in order to distinguish materials that do not contain GaN, they may be referred to as "AlN-based semiconductor materials". "AlN-based semiconductor materials" include AlN and InAlN.

[0014] 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor light emitting device 10 according to an embodiment. The semiconductor light emitting device 10 includes a substrate 20, a base layer 22, an n-type semiconductor layer 24, an active layer 26, a p-type semiconductor layer 28, a p-side contact electrode 30, an n-side contact electrode 32, a p-side current spreading layer 34, an n-side current spreading layer 36, a first protective layer 38, a second protective layer 40, a p-side pad electrode 42, an n-side pad electrode 44, a p-side junction layer 46, and an n-side junction layer 48.

[0015] 1, the direction indicated by arrow A may be referred to as the "vertical direction" or "thickness direction." Furthermore, when viewed from the substrate 20, the direction away from the substrate 20 may be referred to as the upper side, and the direction toward the substrate 20 may be referred to as the lower side.

[0016] The substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The first main surface 20a is a crystal growth surface for growing each layer from the base layer 22 to the p-type semiconductor layer 28. The substrate 20 is made of a material that is transparent to the deep ultraviolet light emitted by the semiconductor light emitting device 10, such as sapphire (Al2O3). A fine uneven pattern with a depth and pitch of submicron (1 μm or less) is formed on the first main surface 20a. Such a substrate 20 is also called a patterned sapphire substrate (PSS). The second main surface 20b is a light extraction surface for extracting the deep ultraviolet light emitted by the active layer 26 to the outside. The substrate 20 may be made of AlN or AlGaN. The substrate 20 may be a normal substrate in which the first main surface 20a is an unpatterned flat surface.

[0017] The base layer 22 is provided on the first main surface 20a of the substrate 20. The base layer 22 is an underlayer (template layer) for forming the n-type semiconductor layer 24. The base layer 22 is, for example, an undoped AlN layer, and more specifically, an AlN layer grown at high temperature (HT-AlN; High Temperature-AlN). The base layer 22 may include an undoped AlGaN layer formed on the AlN layer. When the substrate 20 is an AlN substrate or an AlGaN substrate, the base layer 22 may be composed of only an undoped AlGaN layer. That is, the base layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

[0018] The n-type semiconductor layer 24 is provided on the upper surface 22a of the base layer 22. The n-type semiconductor layer 24 is made of an n-type AlGaN-based semiconductor material and is doped with, for example, Si as an n-type impurity. The n-type semiconductor layer 24 has a composition ratio selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the n-type semiconductor layer 24 is configured so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The n-type semiconductor layer 24 has a band gap larger than the wavelength of the deep ultraviolet light emitted by the active layer 26, for example, the band gap is 4.3 eV or more. The n-type semiconductor layer 24 is preferably configured so that the molar fraction of AlN is 80% or less, i.e., the band gap is 5.5 eV or less, and more preferably, the molar fraction of AlN is 70% or less (i.e., the band gap is 5.2 eV or less). The n-type semiconductor layer 24 has a thickness of 1 μm or more and 3 μm or less, for example, a thickness of approximately 2 μm.

[0019] The n-type semiconductor layer 24 has an impurity concentration of Si of 1×10 18 / cm 3 5x10 or more 19 / cm 3 The n-type semiconductor layer 24 is configured so that the Si concentration is 5×10 18 / cm 3 3x10 or more 19 / cm 3 It is preferable to configure it so that it is 7×10 18 / cm3 Over 2×10 19 / cm 3 In one embodiment, the Si concentration of the n-type semiconductor layer 24 is preferably 1×10 19 / cm 3 It is around, specifically 8 x 10 18 / cm 3 Over 1.5 x 10 19 / cm 3 The range is as follows:

[0020] The n-type semiconductor layer 24 has a first upper surface 24a and a second upper surface 24b. The first upper surface 24a is a portion where the active layer 26 is formed, and the second upper surface 24b is a portion where the active layer 26 is not formed.

[0021] The active layer 26 is provided on the first upper surface 24a of the n-type semiconductor layer 24. The active layer 26 is made of an AlGaN-based semiconductor material, and is sandwiched between the n-type semiconductor layer 24 and the p-type semiconductor layer 28 to form a double heterostructure. The active layer 26 is configured to have a band gap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 355 nm or less, and the AlN composition ratio is selected so that deep ultraviolet light with a wavelength of 320 nm or less can be output, for example.

[0022] The active layer 26 has, for example, a single-layer or multi-layer quantum well structure and includes a barrier layer made of an undoped AlGaN-based semiconductor material and a well layer made of an undoped AlGaN-based semiconductor material. The active layer 26 includes, for example, a first barrier layer in direct contact with the n-type semiconductor layer 24 and a first well layer provided on the first barrier layer. One or more pairs of a barrier layer and a well layer may be additionally provided between the first well layer and the p-type semiconductor layer 28. Each of the barrier layer and the well layer has a thickness of 1 nm or more and 20 nm or less, for example, a thickness of 2 nm or more and 10 nm or less.

[0023] An electron blocking layer may be further provided between the active layer 26 and the p-type semiconductor layer 28. The electron blocking layer is made of an undoped AlGaN-based semiconductor material, for example, with an AlN molar fraction of 40% or more, preferably 50% or more. The electron blocking layer may be made of an AlN-based semiconductor material that does not contain GaN, or may be made of an AlN-based semiconductor material with an AlN molar fraction of 80% or more. The electron blocking layer has a thickness of 1 nm or more and 10 nm or less, for example, a thickness of 2 nm or more and 5 nm or less.

[0024] The p-type semiconductor layer 28 is formed on the active layer 26. The p-type semiconductor layer 28 is a p-type AlGaN-based semiconductor material layer or a p-type GaN-based semiconductor material layer, for example, an AlGaN layer or a GaN layer doped with magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 28 has a thickness of, for example, 20 nm or more and 400 nm or less.

[0025] The p-type semiconductor layer 28 may be composed of multiple layers. The p-type semiconductor layer 28 may have, for example, a p-type cladding layer and a p-type contact layer. The p-type cladding layer is a p-type AlGaN layer with a higher AlN ratio than the p-type contact layer, and is provided so as to be in direct contact with the active layer 26. The p-type contact layer is a p-type AlGaN layer or p-type GaN layer with a lower AlN ratio than the p-type cladding layer. The p-type contact layer is provided on the p-type cladding layer and is provided so as to be in direct contact with the p-side contact electrode 30. The p-type cladding layer may have a p-type first cladding layer and a p-side second cladding layer.

[0026] The composition ratio of the p-type first cladding layer is selected so as to transmit deep ultraviolet light emitted by the active layer 26. The p-type first cladding layer is configured, for example, so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type first cladding layer is, for example, similar to or greater than the AlN ratio of the n-type semiconductor layer 24. The AlN ratio of the p-type cladding layer may be 70% or more, or 80% or more. The p-type first cladding layer has a thickness of 10 nm or more and 100 nm or less, for example, a thickness of 15 nm or more and 70 nm or less.

[0027] The p-type second cladding layer is provided on the p-type first cladding layer. The p-type second cladding layer is a p-type AlGaN layer with a medium AlN ratio, which is lower than that of the p-type first cladding layer and higher than that of the p-type contact layer. The p-type second cladding layer is formed, for example, so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type second cladding layer is formed, for example, so that it is approximately ±10% of the AlN ratio of the n-type semiconductor layer 24. The p-type second cladding layer has a thickness of 5 nm or more and 250 nm or less, for example, a thickness of 10 nm or more and 150 nm or less. Note that the p-type second cladding layer does not necessarily have to be provided, and the p-type cladding layer may be composed of only the p-type first cladding layer.

[0028] The p-type contact layer is a p-type AlGaN layer or p-type GaN layer with a relatively low AlN ratio. The p-type contact layer is configured to have an AlN ratio of 20% or less to obtain good ohmic contact with the p-side contact electrode 30, and is preferably formed to have an AlN ratio of 10% or less, 5% or less, or 0%. That is, the p-type contact layer can be formed of a p-type GaN-based semiconductor material that is substantially free of AlN. As a result, the p-type contact layer can absorb deep ultraviolet light emitted by the active layer 26. The p-type contact layer is preferably formed thin to minimize the absorption of deep ultraviolet light emitted by the active layer 26. The p-type contact layer has a thickness of 5 nm to 30 nm, for example, a thickness of 10 nm to 20 nm.

[0029] The p-side contact electrode 30 is provided on the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 is made of a material that can make ohmic contact with the p-type semiconductor layer 28 (e.g., a p-type contact layer) and has high reflectivity for deep ultraviolet light emitted by the active layer 26. The p-side contact electrode 30 includes an Rh layer that is in direct contact with the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 is made of, for example, only an Rh layer. The thickness of the Rh layer included in the p-side contact electrode 30 is 50 nm or more and 200 nm or less, for example, 70 nm or more and 150 nm or less.

[0030] The n-side contact electrode 32 is provided on the second upper surface 24b of the n-type semiconductor layer 24. The n-side contact electrode 32 includes a first Ti layer, an Al layer, a second Ti layer, and a TiN layer that are stacked in this order. The configuration of the n-side contact electrode 32 will be described in detail later with reference to FIG. 3.

[0031] The p-side current spreading layer 34 is provided on the p-side contact electrode 30. The p-side current spreading layer 34 is in contact with the p-side contact electrode 30 and may cover the entire p-side contact electrode 30. The p-side current spreading layer 34 includes a laminated film in which first TiN layers and Rh layers are alternately stacked, and a second TiN layer provided on the laminated film. The p-side current spreading layer 34 has a p-side connection opening 34a where the second TiN layer is partially removed to expose the Rh layer. The configuration of the p-side current spreading layer 34 will be described in detail later with reference to FIG. 2.

[0032] The n-side current diffusion layer 36 is provided on the n-side contact electrode 32. The n-side current diffusion layer 36 is in contact with the n-side contact electrode 32 and may cover the entire n-side contact electrode 32. The n-side current diffusion layer 36 may have a configuration similar to that of the p-side current diffusion layer 34, including a laminated film in which first TiN layers and Rh layers are alternately stacked, and a second TiN layer provided on the laminated film. The n-side current diffusion layer 36 has an n-side connection opening 36a where the second TiN layer is partially removed to expose the Rh layer. The configuration of the n-side current diffusion layer 36 will be described in detail later with reference to FIG. 3.

[0033] The first protective layer 38 is provided to cover the entire upper surface of the device. The first protective layer 38 covers the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36. The first protective layer 38 has a first p-side pad opening 38p provided on the p-side current diffusion layer 34 and a first n-side pad opening 38n provided on the n-side current diffusion layer 36. The first protective layer 38 covers the p-side current diffusion layer 34 at a location different from the first p-side pad opening 38p and covers the n-side current diffusion layer 36 at a location different from the first n-side pad opening 38n. The first protective layer 38 is in contact with the base layer 22 on the outer periphery of the n-type semiconductor layer 24. The first protective layer 38 is in contact with the upper surface 22a of the base layer 22, in contact with the second upper surface 24b and the side surface 24c of the n-type semiconductor layer 24, in contact with the side surface 26b of the active layer 26, in contact with the upper surface 28a and the side surface 28b of the p-type semiconductor layer 28, in contact with the p-side current spreading layer 34, and in contact with the n-side current spreading layer 36.

[0034] The first protective layer 38 is made of an oxide dielectric material such as silicon oxide (SiO), aluminum oxide (AlO), or hafnium oxide (HfO). The first protective layer 38 is preferably made of SiO. The thickness of the first protective layer 38 is 300 nm or more and 1500 nm or less, for example, 600 nm or more and 1000 nm or less.

[0035] The second protective layer 40 is provided to cover the entire upper surface of the device and the entire surface of the first protective layer 38. The second protective layer 40 has a second p-side pad opening 40p provided on the p-side current spreading layer 34 and a second n-side pad opening 40n provided on the n-side current spreading layer 36. The second protective layer 40 covers the first protective layer 38 at locations different from the second p-side pad opening 40p and the second n-side pad opening 40n. The second protective layer 40 is also provided on the inside of each of the first p-side pad opening 38p and the first n-side pad opening 38n. The second protective layer 40 covers the inner circumferential surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p and the inner circumferential surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 contacts the base layer 22 at the outer periphery of the first protective layer 38. The second protective layer 40 is in contact with the upper surface 22a of the base layer 22, the inner circumferential surfaces 38a and 38b of the first protective layer 38, the upper surface 34b of the p-side current diffusion layer 34, and the upper surface 36b of the n-side current diffusion layer 36.

[0036] The second protective layer 40 is made of silicon nitride (SiN x The thickness of the second protective layer 40 is 50 nm or more and 500 nm or less, for example, 100 nm or more and 400 nm or less.

[0037] The p-side pad electrode 42 and the n-side pad electrode 44 are portions to be joined when the semiconductor light emitting element 10 is mounted on a submount or the like. The p-side pad electrode 42 and the n-side pad electrode 44 include, for example, a Ni / Au or Ti / Au laminate structure. The p-side pad electrode 42 and the n-side pad electrode 44 may be configured not to contain platinum group elements such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or platinum (Pt). The p-side pad electrode 42 and the n-side pad electrode 44 each have a thickness of 100 nm or more, for example, 200 nm or more and 1000 nm or less.

[0038] The p-side pad electrode 42 is provided on the p-side current diffusion layer 34 and is in contact with the upper surface 34b of the p-side current diffusion layer 34 at the second p-side pad opening 40p. The p-side pad electrode 42 is in contact with the Rh layer of the p-side current diffusion layer 34 at the p-side connection opening 34a. The p-side pad electrode 42 is electrically connected to the p-side contact electrode 30 via the p-side current diffusion layer 34. The p-side pad electrode 42 is provided so as to cover the second p-side pad opening 40p and is provided on the second protective layer 40 outside the second p-side pad opening 40p.

[0039] The n-side pad electrode 44 is provided on the n-side current diffusion layer 36 and is in contact with the upper surface 36b of the n-side current diffusion layer 36 at the second n-side pad opening 40n. The n-side pad electrode 44 is in contact with the Rh layer of the n-side current diffusion layer 36 at the n-side connection opening 36a. The n-side pad electrode 44 is electrically connected to the n-side contact electrode 32 via the n-side current diffusion layer 36. The n-side pad electrode 44 is provided so as to cover the second n-side pad opening 40n and is provided on the second protective layer 40 outside the second n-side pad opening 40n.

[0040] The p-side bonding layer 46 and the n-side bonding layer 48 are bonding layers for bonding the semiconductor light emitting element 10 to a submount. The p-side bonding layer 46 and the n-side bonding layer 48 contain, for example, Au and Sn. The p-side bonding layer 46 and the n-side bonding layer 48 may contain AuSn, which is a mixed crystal of Au and Sn, or may have a stacked structure of an Au layer and an Sn layer.

[0041] 2 schematically illustrates the configurations of the p-side contact electrode 30, p-side current spreading layer 34, and p-side pad electrode 42. The p-side current spreading layer 34 includes a Ti layer 50, a laminated film 56 in which first TiN layers 52 and Rh layers 54 are alternately stacked, and a second TiN layer 58. The p-side pad electrode 42 includes an adhesion layer 42a made of Ni or Ti, and an Au layer 42b.

[0042] The Ti layer 50 of the p-side current spreading layer 34 is in contact with the p-side contact electrode 30. The thickness of the Ti layer 50 of the p-side current spreading layer 34 is not less than 10 nm and not more than 200 nm, for example, not less than 20 nm and not more than 150 nm. The p-side current spreading layer 34 does not need to include the Ti layer 50, and the stacked film 56 of the p-side current spreading layer 34 (e.g., the first TiN layer 52) may be in contact with the p-side contact electrode 30.

[0043] The stacked film 56 of the p-side current spreading layer 34 is provided on the Ti layer 50. The stacked film 56 of the p-side current spreading layer 34 includes a first TiN layer 52 and an Rh layer 54. The stacked film 56 may have a plurality of first TiN layers 52 and a plurality of Rh layers 54 that are alternately stacked. The first TiN layer 52 is made of conductive TiN. The thickness of the first TiN layer 52 is 10 nm to 200 nm, for example, 50 nm to 150 nm. The thickness of the Rh layer 54 is 10 nm to 200 nm, for example, 20 nm to 150 nm.

[0044] The second TiN layer 58 of the p-side current spreading layer 34 is provided on the laminated film 56. The second TiN layer 58 is in contact with the Rh layer 54 constituting the uppermost layer of the laminated film 56. The second TiN layer 58 is made of conductive TiN. The thickness of the second TiN layer 58 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The second TiN layer 58 has a p-side connection opening 34a that exposes the Rh layer 54 constituting the uppermost layer of the laminated film 56. The p-side connection opening 34a is provided at a position communicating with the first p-side pad opening 38p.

[0045] The first protective layer 38 is provided on the p-side current spreading layer 34 outside the p-side connection opening 34a. The first protective layer 38 is in contact with the second TiN layer 58 of the p-side current spreading layer 34. The first protective layer 38 is not provided inside the p-side connection opening 34a and is not in contact with the upper surface 34b of the p-side current spreading layer 34 exposed at the p-side connection opening 34a (i.e., the uppermost Rh layer 54).

[0046] The second protective layer 40 is in contact with an inner circumferential surface 38a that defines the first p-side pad opening 38p of the first protective layer 38. The second protective layer 40 is in contact with an inner circumferential surface 34c that defines the p-side connection opening 34a of the p-side current spreading layer 34. The second protective layer 40 is in contact with an upper surface 34b of the p-side current spreading layer 34 (i.e., the uppermost Rh layer 54) that is exposed inside the p-side connection opening 34a.

[0047] The adhesive layer 42a of the p-side pad electrode 42 is in contact with the p-side current spreading layer 34 inside the second p-side pad opening 40p. The adhesive layer 42a of the p-side pad electrode 42 is in contact with the Rh layer 54 constituting the uppermost layer of the laminated film 56. The adhesive layer 42a of the p-side pad electrode 42 is not in contact with the second TiN layer 58 of the p-side current spreading layer 34. The adhesive layer 42a of the p-side pad electrode 42 is not in contact with the first protective layer 38. The Au layer 42b of the p-side pad electrode 42 is provided on the adhesive layer 42a. The p-side bonding layer 46 (not shown in FIG. 2) is provided on the Au layer 42b of the p-side pad electrode 42.

[0048] 3 schematically illustrates the configurations of the n-side contact electrode 32, n-side current spreading layer 36, and n-side pad electrode 44. The n-side contact electrode 32 includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66. The n-side current spreading layer 36 includes a Ti layer 70, a stacked film 76 in which first TiN layers 72 and Rh layers 74 are alternately stacked, and a second TiN layer 78. The n-side pad electrode 44 includes an adhesion layer 44a made of Ni or Ti and an Au layer 44b.

[0049] The Ti layer 70 of the n-side current spreading layer 36 is in contact with the TiN layer 66 of the n-side contact electrode 32. The thickness of the Ti layer 70 of the n-side current spreading layer 36 is not less than 10 nm and not more than 200 nm, for example, not less than 20 nm and not more than 150 nm. The n-side current spreading layer 36 does not need to include the Ti layer 70, and the stacked film 76 of the n-side current spreading layer 36 (e.g., the first TiN layer 72) may be in contact with the n-side contact electrode 32.

[0050] The stacked film 76 of the n-side current spreading layer 36 is provided on the Ti layer 70. The stacked film 76 of the n-side current spreading layer 36 includes a first TiN layer 72 and a Rh layer 74. The stacked film 76 may have a plurality of first TiN layers 72 and a plurality of Rh layers 74 that are alternately stacked. The first TiN layer 72 is made of conductive TiN. The thickness of the first TiN layer 72 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The thickness of the Rh layer 74 is 10 nm or more and 200 nm or less, for example, 20 nm or more and 150 nm or less.

[0051] The second TiN layer 78 of the n-side current spreading layer 36 is provided on the laminated film 76. The second TiN layer 78 is made of conductive TiN. The thickness of the second TiN layer 78 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The second TiN layer 78 has an n-side connection opening 36a that exposes the Rh layer 74 that constitutes the uppermost layer of the laminated film 76. The n-side connection opening 36a is provided at a position that communicates with the first n-side pad opening 38n.

[0052] The first protective layer 38 is provided on the n-side current spreading layer 36 outside the n-side connection opening 36a. The first protective layer 38 is in contact with the second TiN layer 78 of the n-side current spreading layer 36. The first protective layer 38 is not provided inside the n-side connection opening 36a and is not in contact with the upper surface 36b of the n-side current spreading layer 36 exposed at the n-side connection opening 36a (i.e., the uppermost Rh layer 74).

[0053] The second protective layer 40 is in contact with the inner circumferential surface 38b that defines the first n-side pad opening 38n of the first protective layer 38. The second protective layer 40 is in contact with the inner circumferential surface 36c that defines the n-side connection opening 36a of the n-side current spreading layer 36. The second protective layer 40 is in contact with the upper surface 36b of the n-side current spreading layer 36 (i.e., the uppermost Rh layer 74) that is exposed inside the n-side connection opening 36a.

[0054] The adhesive layer 44a of the n-side pad electrode 44 is in contact with the n-side current spreading layer 36 inside the second n-side pad opening 40n. The adhesive layer 44a of the n-side pad electrode 44 is in contact with the Rh layer 74 constituting the uppermost layer of the laminated film 76. The adhesive layer 44a of the n-side pad electrode 44 is not in contact with the second TiN layer 78 of the n-side current spreading layer 36. The adhesive layer 44a of the n-side pad electrode 44 is not in contact with the first protective layer 38. The Au layer 44b of the n-side pad electrode 44 is provided on the adhesive layer 44a. The n-side bonding layer 48 (not shown in FIG. 3) is provided on the Au layer 44b of the n-side pad electrode 44.

[0055] Next, a description will be given of a manufacturing method of the semiconductor light emitting device 10. Figures 4 to 11 are diagrams that schematically show the manufacturing process of the semiconductor light emitting device 10. First, in Figure 4, a base layer 22, an n-type semiconductor layer 24, an active layer 26, and a p-type semiconductor layer 28 are formed in this order on the first main surface 20a of the substrate 20.

[0056] The substrate 20 is, for example, a patterned sapphire substrate. The base layer 22 includes, for example, an HT-AlN layer and an undoped AlGaN layer. The n-type semiconductor layer 24, the active layer 26, and the p-type semiconductor layer 28 are semiconductor layers made of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and can be formed using a well-known epitaxial growth method such as metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).

[0057] 4, a mask 80 is formed on the upper surface 28a of the p-type semiconductor layer 28 using, for example, a known lithography technique. With the mask 80 formed, the p-type semiconductor layer 28 and the active layer 26 in areas not overlapping with the mask 80 are removed by dry etching or the like to expose the second upper surface 24b of the n-type semiconductor layer 24. This etching step forms the side surface 28b of the p-type semiconductor layer 28, the side surface 26b of the active layer 26, and the second upper surface 24b of the n-type semiconductor layer 24. Thereafter, the mask 80 is removed.

[0058] 5, a p-side contact electrode 30 is formed on the upper surface 28a of the p-type semiconductor layer 28 using, for example, known lithography techniques. The p-side contact electrode 30 includes an Rh layer that is in direct contact with the upper surface 28a of the p-type semiconductor layer 28. The Rh layer of the p-side contact electrode 30 is formed by a vapor deposition method. By forming the Rh layer by a vapor deposition method, damage to the upper surface 28a of the p-type semiconductor layer 28 can be suppressed compared to when a sputtering method is used, and the contact resistance of the p-side contact electrode 30 can be improved.

[0059] After the p-side contact electrode 30 is formed, the p-side contact electrode 30 is annealed. The p-side contact electrode 30 is annealed at a temperature of 500°C or higher and 650°C or lower by, for example, an RTA (Rapid Thermal Annealing) method. The annealing of the p-side contact electrode 30 reduces the contact resistance of the p-side contact electrode 30. The annealing of the p-side contact electrode 30 increases the film density of the p-side contact electrode 30, and improves the reflectivity of the p-side contact electrode 30.

[0060] 5, an n-side contact electrode 32 is formed on the second upper surface 24b of the n-type semiconductor layer 24 using, for example, a known lithography technique. The n-side contact electrode 32 is in contact with the second upper surface 24b of the n-type semiconductor layer 24 and includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66 (see FIG. 3), which are stacked in this order. The first Ti layer 60, the Al layer 62, the second Ti layer 64, and the TiN layer 66 that constitute the n-side contact electrode 32 are formed by sputtering.

[0061] After the n-side contact electrode 32 is formed, the n-side contact electrode 32 is annealed. The n-side contact electrode 32 is annealed at a temperature of 500° C. or more and 650° C. or less by using, for example, an RTA method. By annealing the n-side contact electrode 32, the contact resistance of the n-side contact electrode 32 is reduced.

[0062] Next, as shown in FIG. 6 , a p-side current spreading layer 34 is formed on the p-side contact electrode 30, and an n-side current spreading layer 36 is formed on the n-side contact electrode 32, using, for example, a known lithography technique. The p-side current spreading layer 34 and the n-side current spreading layer 36 include a stacked film in which a Ti layer, a first TiN layer, and an Rh layer are alternately stacked, and a second TiN layer. The p-side current spreading layer 34 and the n-side current spreading layer 36 can be formed by sputtering. Alternatively, the p-side current spreading layer 34 and the n-side current spreading layer 36 may be formed separately.

[0063] 7, a mask 82 is formed on the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36 using, for example, known lithography techniques. With the mask 82 formed, the n-type semiconductor layer 24 in an area not overlapping with the mask 82 is removed by dry etching or the like to expose the top surface 22a of the base layer 22. This etching process forms the side surface 24c of the n-type semiconductor layer 24. Thereafter, the mask 82 is removed.

[0064] 8, a first protective layer 38 is formed to cover the entire upper surface of the device. The first protective layer 38 may be made of SiO2 and may be formed using a plasma-enhanced chemical vapor deposition (PECVD) method. The first protective layer 38 is formed to be in contact with the upper surface 22a of the base layer 22, the second upper surface 24b and side surface 24c of the n-type semiconductor layer 24, the side surface 26c of the active layer 26, the upper surface 28a and side surface 28c of the p-type semiconductor layer 28, the p-side current spreading layer 34, and the n-side current spreading layer 36.

[0065] Next, as shown in FIG. 9 , a mask 84 is formed on the first protective layer 38 using, for example, a known lithography technique. The mask 84 is formed except for a formation area W1p for the first p-side pad opening 38p, a formation area W1n for the first n-side pad opening 38n, and a first outer peripheral area W1a that exposes the upper surface 22a of the base layer 22. With the mask 84 formed, the first protective layer 38 in an area that does not overlap with the mask 84 is removed by dry etching. By removing the first protective layer 38 on the p-side current diffusion layer 34, the first p-side pad opening 38p that exposes the p-side current diffusion layer 34 is formed. By removing the first protective layer 38 on the n-side current diffusion layer 36, the first n-side pad opening 38n that exposes the n-side current diffusion layer 36 is formed. Furthermore, by removing the outer peripheral portion of the first protective layer 38 in the first outer peripheral area W1a, the upper surface 22a of the base layer 22 is exposed.

[0066] 9, in the formation range W1p of the first p-side pad opening 38p, the p-side current diffusion layer 34 is dry-etched to remove the second TiN layer 58 of the p-side current diffusion layer 34, thereby forming a p-side connection opening 34a that exposes the uppermost Rh layer 54. In addition, in the formation range W1n of the first n-side pad opening 38n, the n-side current diffusion layer 36 is dry-etched to remove the second TiN layer 78 of the n-side current diffusion layer 36, thereby forming an n-side connection opening 36a that exposes the uppermost Rh layer 74. Thereafter, the mask 84 is removed.

[0067] 10, a second protective layer 40 is formed to cover the entire upper surface of the element. xand can be formed using a PECVD method. The second protective layer 40 is formed so as to be in contact with the upper surface 22a of the base layer 22 and the surface of the first protective layer 38. At the first p-side pad opening 38p, the second protective layer 40 is in contact with the inner circumferential surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p. The second protective layer 40 is in contact with the inner circumferential surface 34c of the p-side current spreading layer 34 (i.e., the second TiN layer 58) that defines the p-side connection opening 34a, and is in contact with the upper surface 34b of the p-side current spreading layer 34 at the p-side connection opening 34a. At the first n-side pad opening 38n, the second protective layer 40 is in contact with the inner circumferential surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 contacts the inner surface 36c of the n-side current diffusion layer 36 (i.e., the second TiN layer 78) that defines the n-side connection opening 36a, and contacts the upper surface 36b of the n-side current diffusion layer 36 at the n-side connection opening 36a.

[0068] Next, as shown in FIG. 11 , a mask 86 is formed on the second protective layer 40 using, for example, a known lithography technique. The mask 86 is formed except for a formation area W2p for the second p-side pad opening 40p, a formation area W2n for the second n-side pad opening 40n, and a second peripheral area W2a for exposing the upper surface 22a of the base layer 22. With the mask 86 formed, the second protective layer 40 in the area not overlapping with the mask 86 is removed by dry etching or the like. By removing the second protective layer 40 on the p-side current diffusion layer 34, the second p-side pad opening 40p is formed, exposing the upper surface 34b of the p-side current diffusion layer 34. By removing the second protective layer 40 on the n-side current diffusion layer 36, the second n-side pad opening 40n is formed, exposing the upper surface 36b of the n-side current diffusion layer 36. Furthermore, by removing the outer peripheral portion of the second protective layer 40 in the second peripheral area W2a, the upper surface 22a of the base layer 22 is exposed. The second outer periphery range W2a becomes an element isolation region for separating elements by cutting the substrate 20 and the base layer 22. Thereafter, the mask 86 is removed.

[0069] Next, as shown in FIG. 1 , a p-side pad electrode 42 is formed in the second p-side pad opening 40p, connecting to the p-side current spreading layer 34, and an n-side pad electrode 44 is formed in the second n-side pad opening 40n, using, for example, a known lithography technique. The p-side pad electrode 42 is formed so as to overlap the second protective layer 40 outside the second p-side pad opening 40p. The n-side pad electrode 44 is formed so as to overlap the second protective layer 40 outside the second n-side pad opening 40n. The p-side pad electrode 42 and the n-side pad electrode 44 can be formed simultaneously or separately. Next, a p-side junction layer 46 is formed on the p-side pad electrode 42, and an n-side junction layer 48 is formed on the n-side pad electrode 44, using, for example, a known lithography technique. The p-side junction layer 46 and the n-side junction layer 48 can be formed simultaneously or separately.

[0070] Through the above steps, the semiconductor light emitting device 10 shown in FIG. 1 is completed.

[0071] Fig. 12 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device 100 according to an embodiment. The semiconductor light emitting device 100 includes a semiconductor light emitting element 10 and a submount 90. In Fig. 12, the semiconductor light emitting element 10 shown in Fig. 1 is turned upside down.

[0072] The submount 90 includes a submount substrate 92, a first mount electrode 94, and a second mount electrode 96. The first mount electrode 94 and the second mount electrode 96 are provided on the surface of the submount substrate 92. The first mount electrode 94 is connected to the p-side pad electrode 42 via the p-side bonding layer 46. The second mount electrode 96 is connected to the n-side pad electrode 44 via the n-side bonding layer 48.

[0073] According to this embodiment, the semiconductor light emitting element 10 is connected to the submount 90 via the p-side bonding layer 46 and the n-side bonding layer 48 containing AuSn, and therefore the heat generated by driving the semiconductor light emitting element 10 can be efficiently transferred to the submount 90. This allows the semiconductor light emitting element 10 to be efficiently cooled, improving the reliability of the semiconductor light emitting element 10.

[0074] According to the present embodiment, the Rh layer 54 included in the p-side current spreading layer 34 can prevent or block the diffusion of AuSn contained in the p-side bonding layer 46 toward the p-type semiconductor layer 28. In particular, by bringing the Rh layer 54 of the p-side current spreading layer 34, which has a diffusion prevention effect against AuSn, into direct contact with the p-side pad electrode 42, the diffusion prevention effect can be improved.

[0075] According to the present embodiment, the second protective layer 40 is in direct contact with the Rh layers 54, 74 of the p-side current diffusion layer 34 and the n-side current diffusion layer 36, thereby improving the sealing performance of the first protective layer 38 and the second protective layer 40.

[0076] The present invention has been described above based on the embodiments. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that various design changes and modifications are possible, and that such modifications are also within the scope of the present invention.

[0077] Several aspects of the present invention will now be described.

[0078] a contact electrode in contact with a second upper surface of the n-type semiconductor layer, the second upper surface being different from the first upper surface of the n-type semiconductor layer, or in contact with an upper surface of the p-type semiconductor layer; a laminated film provided on the contact electrode and including first TiN layers and Rh layers alternately stacked; a second TiN layer provided on the laminated film, the second TiN layer having a connection opening exposing the Rh layer; a protective layer made of a dielectric material, the protective layer having a pad opening provided in the connection opening and covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer at a position different from the pad opening; a pad electrode in contact with the Rh layer of the current spreading layer at the connection opening and provided on the protective layer outside the pad opening; and a bonding layer provided on the pad electrode and containing AuSn. According to the first aspect, by providing a bonding layer containing AuSn on the pad electrode, heat dissipation can be improved. Furthermore, by bringing the pad electrode into contact with the Rh layer, the Rh layer can effectively prevent the AuSn contained in the bonding layer from diffusing toward the semiconductor layer, thereby suppressing a decrease in light-emitting efficiency. This allows for the provision of a highly reliable semiconductor light-emitting device.

[0079] A second aspect of the present invention is the semiconductor light-emitting device according to the first aspect, wherein the protective layer includes: a first protective layer having a first pad opening provided in the connection opening, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer at a location different from the first pad opening, the first protective layer being made of silicon oxide; and a second protective layer having a second pad opening provided in the connection opening, covering the first protective layer at a location different from the second pad opening, the second protective layer being made of silicon nitride. According to the second aspect, by combining the first protective layer and the second protective layer, it is possible to improve the sealing performance of the semiconductor light-emitting device.

[0080] In a third aspect of the present invention, the second protective layer is in contact with inner circumferential surfaces of the connection opening and the first pad opening, and is in contact with the Rh layer in the connection opening. According to the third aspect, the second protective layer is in contact with the Rh layer of the current spreading layer, thereby improving the sealing performance of the first protective layer and the second protective layer.

[0081] A fourth aspect of the present invention is the semiconductor light-emitting device according to the second or third aspect, wherein the second protective layer is in contact with the second TiN layer at the connection opening. According to the fourth aspect, by adopting a structure in which the second protective layer is in contact with the second TiN layer of the current spreading layer, the sealing performance of the first and second protective layers can be improved.

[0082] A fifth aspect of the present invention provides a semiconductor device including the steps of: forming an active layer on an n-type semiconductor layer; forming a p-type semiconductor layer on the active layer; removing a portion of each of the p-type semiconductor layer and the active layer to expose an upper surface of the n-type semiconductor layer; forming a contact electrode in contact with the upper surface of the p-type semiconductor layer or in contact with the upper surface of the n-type semiconductor layer; forming a current spreading layer provided on the contact electrode, the current spreading layer including a stacked film in which first TiN layers and Rh layers are alternately stacked, and a second TiN layer provided on the stacked film; and removing a portion of each of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer. a step of forming a protective layer made of a dielectric material to cover the semiconductor layer and the current spreading layer, a step of removing the protective layer on the current spreading layer to form a pad opening, a step of removing the second TiN layer of the current spreading layer in the pad opening to form a connection opening in which the Rh layer is exposed, a step of forming a pad electrode on the protective layer outside the pad opening and in contact with the Rh layer of the current spreading layer in the connection opening, and a step of forming a bonding layer containing AuSn on the pad electrode. According to a fifth aspect, by removing the second TiN layer of the current spreading layer and bringing the pad electrode into contact with the Rh layer of the current spreading layer, the Rh layer can effectively prevent the AuSn contained in the bonding layer from diffusing toward the semiconductor layer, thereby suppressing a decrease in light emission efficiency.

[0083] A sixth aspect of the present invention is the method for manufacturing a semiconductor light-emitting element according to the fifth aspect, further comprising the step of forming a mask having an opening on the protective layer, wherein the step of forming the pad opening includes the step of dry-etching the protective layer through the opening in the mask, and the step of forming the connection opening includes the step of dry-etching the second TiN layer of the current spreading layer through the opening in the mask. In the sixth aspect, by forming the pad opening and the connection opening by dry etching using a common mask, the pad electrode can be brought into contact with the Rh layer of the current spreading layer, and the Rh layer can improve the effect of preventing AuSn diffusion. [Explanation of symbols]

[0084] 10...semiconductor light-emitting element, 24...n-type semiconductor layer, 24a...first upper surface, 24b...second upper surface, 26...active layer, 28...p-type semiconductor layer, 30...p-side contact electrode, 32...n-side contact electrode, 34...p-side current diffusion layer, 34a...p-side connection opening, 36...n-side current diffusion layer, 36a...n-side connection opening, 38...first protective layer, 38a...inner surface, 38p...first p-side pad opening, 38n...first n-side pad opening, 40...second protective layer, 40p...second p-side pad opening, 40n...second n-side pad opening, 42...p-side pad electrode, 44...n-side pad electrode, 52,72...first TiN layer, 54,74...Rh layer, 58,78...second TiN layer.

Claims

1. an n-type semiconductor layer; an active layer provided on a first upper surface of the n-type semiconductor layer; a p-type semiconductor layer provided on the active layer; a contact electrode in contact with a second upper surface different from the first upper surface of the n-type semiconductor layer or in contact with an upper surface of the p-type semiconductor layer; a current spreading layer provided on the contact electrode, the current spreading layer including a laminated film in which first TiN layers and Rh layers are alternately laminated, and a second TiN layer provided on the laminated film, the second TiN layer having a contact opening exposing the Rh layer; a protective layer made of a dielectric material, the protective layer having a pad opening provided in the connection opening, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer at locations different from the pad opening; a pad electrode in contact with the Rh layer of the current spreading layer in the connection opening and provided on the protective layer outside the pad opening; a bonding layer provided on the pad electrode and containing AuSn; Semiconductor light emitting element.

2. The protective layer is a first protective layer made of silicon oxide, the first protective layer having a first pad opening provided in the connection opening, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer at a location different from the first pad opening; a second protective layer made of silicon nitride, the second protective layer having a second pad opening provided in the connection opening and covering the first protective layer at a location different from the second pad opening; The semiconductor light emitting device according to claim 1 .

3. the second protective layer is in contact with inner circumferential surfaces of the connection opening and the first pad opening, and is in contact with the Rh layer in the connection opening; The semiconductor light emitting device according to claim 2 .

4. the second protective layer contacts the second TiN layer in the contact opening; The semiconductor light emitting device according to claim 2 .

5. forming an active layer on the n-type semiconductor layer; forming a p-type semiconductor layer on the active layer; removing a portion of each of the p-type semiconductor layer and the active layer to expose an upper surface of the n-type semiconductor layer; forming a contact electrode in contact with an upper surface of the p-type semiconductor layer or in contact with the upper surface of the n-type semiconductor layer; forming a current spreading layer provided on the contact electrode, the current spreading layer including a laminated film in which a first TiN layer and a Rh layer are alternately laminated, and a second TiN layer provided on the laminated film; forming a protective layer made of a dielectric material to cover the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer; removing the protective layer on the current spreading layer to form a pad opening; removing the second TiN layer in the pad opening to form a contact opening in which the Rh layer of the current spreading layer is exposed; forming a pad electrode in contact with the Rh layer of the current spreading layer in the connection opening and provided on the protective layer outside the pad opening; forming a bonding layer containing AuSn on the pad electrode; A method for manufacturing a semiconductor light-emitting device.

6. forming a mask having an opening on the protective layer; forming the pad opening includes dry etching the protection layer through the opening in the mask; the step of forming the contact opening includes the step of dry etching the second TiN layer of the current spreading layer through the opening of the mask. The method for manufacturing a semiconductor light-emitting device according to claim 5 .

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