Display device

Abstract

To suppress the occurrence of crosstalk by a method different from a conventional method.SOLUTION: The display apparatus 11 includes the first substrate 21 having the display area AA and the non-display area NAA, the first lines 27 disposed in the display area AA and extending in the first direction, the signal supplier disposed in the first end 21A of the non-display area NAA, the common electrodes 28 disposed in the display area AA, and the common lines 29 disposed in the non-display area NAA and connected to the common electrodes 28. Two first signal supplying parts 12 α and at least two second signal supplying parts 12 β sandwiched between two first signal supplying parts 12 α are included on both end sides of first end 21A. At least two common wirings 29 are disposed and connected to end sides of two first signal supplying parts 12 α, and the first signal supplying part 12 α supplies a common potential signal to the common wirings 29, and is disposed so that a first interval W1 between the first signal supplying part 12 α and the adjacent second signal supplying part 12 β is wider than a second interval W2 between the two adjacent second signal supplying parts 12 β.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a display device in which the occurrence of crosstalk is suppressed. [Background technology]

[0002] Conventionally, examples of display devices are known from the following Patent Documents 1 and 2. The display device described in Patent Document 1 is a liquid crystal display including an array substrate and a plurality of pixels arranged in row and column directions, each pixel including one or more independently driven constituent units, the row pitch of the constituent units being substantially the same as or larger than the column pitch of the constituent units, the array substrate including gate bus lines, a first insulating film on the gate bus lines, source bus lines and common bus lines on the first insulating film, a second insulating film on the source bus lines and common bus lines, and a transparent common electrode on the second insulating film, the gate bus lines extending in the row direction, the source bus lines and common bus lines extending in the column direction, and the common electrode being connected to the common bus line through a contact hole formed in the second insulating film within the display area.

[0003] The display device described in Patent Document 2 uses a driving method in which, when the counter electrodes are driven to invert the polarity in synchronization with the polarity inversion of the column electrodes, the column electrodes are brought into an electrically floating state immediately after the polarity inversion. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-182127

[0005] [Patent Document 2] Japanese Patent Application Publication No. 9-274470 Summary of the Invention [Problem to be solved by the invention]

[0006] In the display device described in Patent Document 1, a common bus line is provided adjacent to the source bus line within the display area, and the common bus line is connected to a common electrode through a contact hole on the gate bus line. However, depending on the display device, it may be difficult to provide a common bus line within the display area, and in such cases it is difficult to suppress the occurrence of crosstalk.

[0007] On the other hand, in the display device described in Patent Document 2, a group of switches is provided to place the column electrodes in an electrically floating state immediately after the polarity is inverted, and the operation of the group of switches is controlled. However, depending on the display device, it may be difficult to take measures such as providing the above-mentioned group of switches, and in such cases it is difficult to suppress the occurrence of crosstalk.

[0008] The technology described in this specification was developed based on the above circumstances, and aims to suppress the occurrence of crosstalk using a method different from conventional methods. [Means for solving the problem]

[0009] (1) A display device according to the technology described in this specification includes a first substrate having a main surface divided into a display area where an image is displayed and a non-display area where the image is not displayed, a first wiring arranged in the display area of ​​the first substrate and extending along a first direction, a signal supply unit arranged in the non-display area of ​​the first substrate at a first end in the first direction and connected to at least the first wiring to supply a signal to the first wiring, a common electrode arranged in the display area of ​​the first substrate, and a common wiring arranged in the non-display area of ​​the first substrate and connected to the common electrode, and the signal supply unit includes a first wiring arranged at the first end on both ends in a second direction that intersects with the first direction along the main surface. and at least two second signal supply units that are sandwiched between the two first signal supply units in the second direction at the first end and are spaced apart in the second direction, at least two of the common wirings are arranged at positions closer to the ends in the second direction than the two first signal supply units and are connected to the two first signal supply units, respectively, the first signal supply units supply a common potential signal to the common wiring, and the first signal supply units are arranged so that a first interval, which is an interval between the second signal supply units adjacent to each other in the second direction, is wider than a second interval, which is an interval between two second signal supply units adjacent to each other in the second direction.

[0010] (2) In addition to the above (1), the display device may further include a first wiring configuration portion made of a first conductive film, and a second wiring configuration portion made of a second conductive film having a lower sheet resistance than the first conductive film with a first insulating film interposed between the first wiring configuration portion and the first conductive film, and the first wiring configuration portion and the second wiring configuration portion may be connected through a first contact hole provided in the first insulating film, and the first wiring configuration portion may be connected to the first signal supply portion, and the second wiring configuration portion may be connected to the common electrode.

[0011] (3) In addition to (2), the display device may further include a second substrate arranged opposite the first substrate at a distance so as not to overlap with the first end portion, the first wiring configuration being arranged at least in a range that does not overlap with the second substrate, and the second wiring configuration being arranged in a range that overlaps with the second substrate.

[0012] (4) In addition to (3), the display device may further include a sealing portion extending along the outer peripheral edge of the second substrate and interposed between the first substrate and the second substrate, the first wiring configuration portion being arranged in a range overlapping both the second substrate and the sealing portion, and the second wiring configuration portion being arranged in a range not overlapping the sealing portion.

[0013] (5) In addition to the above (3) or (4), the display device may be such that the first conductive film contains at least one of molybdenum and tungsten, and the second conductive film contains aluminum.

[0014] (6) In addition to any one of (1) to (5), the display device may also have a configuration in which the first wirings are arranged at intervals in the second direction, and a smaller number of the first wirings than the second signal supply units are connected to the first signal supply unit.

[0015] (7) In addition to (6), the display device may further include a plurality of second wirings arranged in the display area of ​​the first substrate and extending along the second direction, and a third signal supply unit arranged alongside the display area in the non-display area of ​​the first substrate in the second direction, wherein the third signal supply unit is connected to the plurality of second wirings and supplies scanning signals to the plurality of second wirings, one of the two first signal supply units is connected to the third signal supply unit and supplies a signal to the third signal supply unit to control the supply of the scanning signal, and one of the first signal supply units may be connected to a smaller number of the first wirings than the other first signal supply unit. [Effects of the Invention]

[0016] According to the technology described in this specification, it is possible to suppress the occurrence of crosstalk using a method different from conventional methods. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and the like that constitute a liquid crystal display device according to Embodiment 1. [Figure 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, a flexible substrate, and the like according to Embodiment 1. [Figure 3] FIG. 1 is a circuit diagram showing the electrical configuration of an array substrate that constitutes a liquid crystal panel according to a first embodiment. [Figure 4] FIG. 1 is a plan view showing source lines, common lines, drivers, a seal portion, and the like in a liquid crystal panel according to a first embodiment; [Figure 5] 5 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vv in FIG. 4 . [Figure 6A] 10 is a graph showing a change in the potential of the common electrode in Reference Example 1 of Reference Experiment 1 according to Embodiment 1. [Figure 6B] 10 is a graph showing changes in the potential of the common electrode in Reference Example 2 of Reference Experiment 1 according to Embodiment 1. [Figure 7] Graph showing changes in crosstalk ratio in Reference Experiment 1 according to Embodiment 1. [Figure 8] Graph showing experimental results of Reference Example 1 of Reference Experiment 2 according to Embodiment 1 [Figure 9] Graph showing experimental results of Reference Example 2 of Reference Experiment 2 according to Embodiment 1 [Figure 10] FIG. 10 is a plan view showing source lines, common lines, drivers, seals, etc. in a liquid crystal panel according to a second embodiment. [Figure 11] FIG. 10 is a plan view showing source lines, common lines, drivers, seals, etc. in a liquid crystal panel according to a third embodiment. [Figure 12] 10 is a plan view of a liquid crystal panel, a driver, a flexible substrate, etc. according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] <Embodiment 1> Embodiment 1 will be described with reference to Figs. 1 to 9. In this embodiment, a liquid crystal display device 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in parts of each drawing, and each axis direction is depicted as being in the direction shown in each drawing. Also, the upper side of Figs. 2 and 5 is the front side, and the lower side of the drawings is the back side.

[0019] As shown in Fig. 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back surface) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect. The liquid crystal panel 11 has a display area AA in the central portion of a main surface 21S of an array substrate 21 (described later) where an image is displayed. In contrast, the liquid crystal panel 11 has a frame-shaped outer peripheral portion surrounding the display area AA on the main surface 21S which is a non-display area NAA where no image is displayed.

[0020] The liquid crystal panel 11 will be described with reference to FIG. 1 and FIG. 2. As shown in FIGS. 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. The front side of the pair of substrates 20 and 21 is an opposing substrate (second substrate) 20, and the back side is an array substrate (first substrate) 21. The opposing substrate 20 and the array substrate 21 are both formed by laminating various films on the inner surface of a glass substrate. On the inner surface of the array substrate 21, a common electrode 28 is provided, which is disposed across at least the entire display area AA, and common wiring 29 is connected to the common electrode 28. The common electrode 28 and the common wiring 29 will be described in detail later. A liquid crystal layer 22 containing liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied, is disposed between the pair of substrates 20 and 21. A seal portion 23 is disposed between the pair of substrates 20 and 21 to seal the liquid crystal layer 22. A polarizing plate 14 is attached to the outer surface of each of the substrates 20 and 21.

[0021] As shown in FIGS. 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 so that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end of the array substrate 21 in the short side direction (first direction) is a first end 21A that protrudes laterally and is exposed from the counter substrate 20. This first end 21A is entirely a non-display area NAA, and is equipped with a driver (signal supply unit) 12 for supplying various signals and a flexible substrate 13. The sealing portion 23 extends along the outer peripheral edge of the counter substrate 20 and is formed in a rectangular frame shape to surround the liquid crystal layer 22.

[0022] The driver 12 is an LSI chip having an internal drive circuit. The driver 12 is mounted on the first end 21A of the array substrate 21 by COG (Chip On Glass). The driver 12 processes various signals transmitted by the flexible substrate 13. As shown in FIGS. 1 and 2, the driver 12 is arranged adjacent to one side of the display area AA in the Y-axis direction, and is sandwiched between the flexible substrate 13 (described below) and the display area AA. The driver 12 has a horizontally elongated rectangular shape in plan view. Four drivers 12 are arranged linearly along the X-axis direction at intervals in the X-axis direction at the first end 21A. The driver 12 can supply various signals to the source wiring 27 and the like provided on the array substrate 21. The driver 12 is connected to at least the source wiring 27 and supplies image signals (signals) to the source wiring 27. The flexible substrate 13 has a configuration in which a large number of wiring patterns are formed on a base material made of an insulating and flexible synthetic resin material (such as a polyimide resin.) One end of the flexible substrate 13 is connected to the first end 21A of the array substrate 21, and the other end is connected to an external circuit board (such as a control board).

[0023] Next, the configuration of the display area AA of the array substrate 21 will be described with reference to FIG. 3. As shown in FIG. 3, at least TFTs (transistors, switching elements) 24 and pixel electrodes 25 are provided on the inner surface of the display area AA of the array substrate 21. The TFTs 24 and pixel electrodes 25 are arranged in a matrix (rows and columns) with multiple TFTs 24 and multiple pixel electrodes 25 spaced apart along the X-axis and Y-axis directions. Gate wiring (second wiring, scanning wiring) 26 and source wiring (first wiring, image wiring, signal wiring) 27, which are orthogonal to (intersect with) each other, are arranged around the TFTs 24 and pixel electrodes 25. The gate wiring 26 extends along the X-axis direction (a second direction that runs along the main surface 21S and intersects the first direction), with multiple gate wirings arranged at intervals along the Y-axis direction. The source wiring 27 extends along the Y-axis direction (a first direction), with multiple source wirings arranged at intervals along the X-axis direction. The TFT 24 has a gate electrode 24A connected to the gate line 26, a source electrode 24B connected to the source line 27, a drain electrode 24C connected to the pixel electrode 25, and a semiconductor portion 24D connected to the source electrode 24B and the drain electrode 24C. The TFT 24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate line 26. This scanning signal includes a potential higher than the threshold voltage of the TFT 24. Then, a potential related to an image signal supplied to the source electrode 24B by the source line 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential related to the image signal. The pixel electrode 25 is disposed in a region surrounded by the gate line 26 and the source line 27.

[0024] As shown in FIGS. 1 and 3, the liquid crystal panel 11 according to this embodiment includes pixel electrodes 25 and a common electrode 28 provided on an array substrate 21, and horizontally aligns liquid crystal molecules contained in a liquid crystal layer 22 by utilizing a transverse electric field generated between the pixel electrodes 25 and the common electrode 28. In other words, the liquid crystal panel 11 according to this embodiment is in a so-called in-plane switching (IPS) mode. In the IPS mode liquid crystal panel 11, the pixel electrodes 25 and the common electrode 28 may have, for example, a comb-like shape that interdigitates with each other in a plan view, but may also have other planar configurations. As shown in FIG. 1, the common electrode 28 is disposed over an area slightly larger than the display area AA, and its outer peripheral edge is located in the non-display area NAA.

[0025] As shown in FIG. 1, the common wiring 29 is arranged in the non-display area NAA of the array substrate 21, and one end is connected to the outer peripheral end of the common electrode 28 located in the non-display area NAA. The other end of the common wiring 29 is connected to a specific driver 12 among the four drivers 12. Here, of the four drivers 12 aligned along the X-axis direction, two drivers 12 located at both ends in the X-axis direction (the left and right ends in FIG. 1) are referred to as "first drivers (first signal supply units) 12α," and two drivers 12 located closer to the center in the X-axis direction than the two first drivers 12α are referred to as "second drivers (second signal supply units) 12β." The common wiring 29 is connected to the first drivers 12α and is not connected to the second drivers 12β. At least two common wirings 29 are arranged at positions closer to the ends in the X-axis direction than the two first drivers 12α. In this embodiment, at least four common wirings 29 are arranged, for example, two at each end of the first driver 12α in the X-axis direction. The two common wirings 29 arranged at the end of the first driver 12α in the X-axis direction include a common wiring 29 connected to an end position of the outer circumferential edge of the common electrode 28 in the X-axis direction that is closer to the driver 12 in the Y-axis direction (the lower side in FIG. 1), and a common wiring 29 connected to an end position of the outer circumferential edge of the common electrode 28 in the X-axis direction that is closer to the driver 12 in the Y-axis direction (the upper side in FIG. 1). In other words, four common wirings 29 are connected to the four corners of the outer circumferential edge of the common electrode 28. Two common wirings 29 are connected to each of the two first drivers 12α. The first driver 12α can supply a common potential signal to the connected common wirings 29. The common potential signal transmitted by the common wiring 29 is supplied to the common electrode 28, and the common electrode 28 is maintained at a common potential corresponding to the common potential signal.

[0026] In the liquid crystal panel 11 according to this embodiment, the common electrode 28 is provided on the array substrate 21, and therefore, compared to a VA (Vertical Alignment) mode liquid crystal panel in which the common electrode is provided on the counter substrate 20, the parasitic capacitance generated between the source line 27 and the common electrode 28 is large. For this reason, for example, when a checkerboard pattern of white pixels and black pixels is displayed in a predetermined range of the display area AA, a display defect called crosstalk is likely to occur in which the displayed grayscale differs from the original in areas adjacent to the pattern in the X-axis direction. It is believed that such crosstalk occurs due to instability of the potential of the common electrode 28 caused by the parasitic capacitance between the source line 27 and the common electrode 28.

[0027] Therefore, in the liquid crystal panel 11 according to this embodiment, as shown in FIG. 1, the four drivers 12 are arranged as follows. That is, the first driver 12α is arranged so that a first interval W1, which is an interval between the first driver 12α and the second driver 12β adjacent to each other in the X-axis direction, is wider than a second interval W2, which is an interval between two second drivers 12β adjacent to each other in the X-axis direction. Specifically, the first interval W1 is provided between one first driver 12α (at the left end of FIG. 1) and the adjacent second driver 12β (at the left side of FIG. 1). Similarly, the first interval W1 is provided between the other first driver 12α (at the right end of FIG. 1) and the adjacent second driver 12β (at the right side of FIG. 1). In contrast, a second interval W2, which is narrower than the first interval W1, is provided between the two second drivers 12β. With this configuration, compared to when the first driver 12α is spaced apart from the adjacent second driver 12β in the X-axis direction by the same distance as the second distance W2, the first driver 12α can be positioned closer to the end in the X-axis direction at the first end 21A by the difference between the first distance W1 and the second distance W2. Positioning the first driver 12α closer to the end in the X-axis direction at the first end 21A allows the length of the common wiring 29 running from the first driver 12α to the common electrode 28 to be shortened. The shorter the wiring length of the common wiring 29, the lower the wiring resistance of the common wiring 29, allowing the common electrode 28 to be stably maintained at a common potential. This reduces potential fluctuations in the common electrode 28 even when parasitic capacitance occurs between the source wiring 27 and the common electrode 28, thereby suppressing crosstalk.

[0028] As shown in FIGS. 4 and 5 , the common wiring 29 includes a first wiring portion 29A made of a first metal film (first conductive film) and a second wiring portion 29B made of a second metal film (second conductive film). The first metal film constituting the first wiring portion 29A is located at the innermost position among various films laminated on the inner surface of the glass substrate constituting the array substrate 21, and is a single-layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials. In this embodiment, the first metal film is made of, for example, MoWN (molybdenum tungsten nitride) and has excellent weather resistance, chemical resistance, and heat resistance. The first metal film has weather resistance at least higher than that of the second metal film described below. In the display area AA, the first metal film constitutes the gate wiring 26, the gate electrode 24A of the TFT 24, and the like.

[0029] The second metal film constituting the second wiring configuration portion 29B is located above the first metal film via the gate insulating film (first insulating film) 30, and is a single-layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials. In this embodiment, the second metal film is made of, for example, a Ti (titanium) / Al (aluminum) / Ti laminated film and has excellent conductivity. The second metal film has higher conductivity than the first metal film, and the sheet resistance of the second metal film is lower than the sheet resistance of the first metal film. In the display region AA, the second metal film constitutes the source line 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc.

[0030] The gate insulating film 30 located above the first metal film and below the second metal film is made of SiN x The gate insulating film 30 is made of an inorganic material such as silicon nitride (SiO2) or silicon oxide (SiO2) and is formed as a single layer or a multilayer film. In the display area AA, the gate insulating film 30 is interposed between the gate electrode 24A and the semiconductor portion 24D of the TFT 24, and is also interposed between the intersections of the gate wiring 26 and the source wiring 27, thereby keeping them in an insulated state. The semiconductor portion 24D of the TFT 24 is made of a semiconductor film located above the gate insulating film 30 and below the second metal film. The semiconductor film is made of, for example, an oxide semiconductor material or an amorphous silicon material.

[0031] As shown in FIGS. 4 and 5, one end of the first wiring configuration 29A is connected to the first driver 12α, and the other end is connected to the second wiring configuration 29B. Specifically, one end of the first wiring configuration 29A is connected to a terminal portion provided in the mounting region of the first driver 12α at the first end portion 21A of the array substrate 21. This terminal portion is connected to a bump provided on the first driver 12α via an anisotropic conductive film. The first wiring configuration 29A extends from the mounting region of the first driver 12α along the Y-axis direction toward the display region AA, then bends and extends in a diagonal direction inclined with respect to both the X-axis and Y-axis directions. The multiple source lines 27 connected to each driver 12 are routed so as to fan out from the driver 12 side toward the display region AA, and the fan-shaped portion extends in a diagonal direction similar to the first wiring configuration 29A.

[0032] As shown in FIGS. 4 and 5 , one end of the second wiring portion 29B is connected to the common electrode 28, and the other end is connected to the first wiring portion 29A. Specifically, one end of the second wiring portion 29B is connected to the outer peripheral edge of the common electrode 28. The second wiring portion 29B extends from the common electrode 28 along the Y-axis direction toward the first driver 12α, then bends and extends in a diagonal direction inclined with respect to both the X-axis and Y-axis directions. The other end of the second wiring portion 29B is arranged to overlap the other end of the first wiring portion 29A in a plan view. The other ends of the first wiring portion 29A and the second wiring portion 29B both extend in a diagonal direction. A first contact hole CH1 is opened and provided in the gate insulating film 30 at a position overlapping both the first wiring portion 29A and the second wiring portion 29B. The other ends of the first wiring portion 29A and the second wiring portion 29B are connected to each other through a first contact hole CH1 provided in the gate insulating film 30. The second wiring portion 29B is covered with a first interlayer insulating film (second insulating film) 31 provided on the upper layer side of the second metal film. The first interlayer insulating film 31 is made of SiN, similar to the gate insulating film 30.x It is made of inorganic materials such as SiO2 and is a single layer film or a laminated film.

[0033] With this configuration, the common potential signal output from the bump of the first driver 12α is transmitted from the terminal portion to the first wiring configuration portion 29A, then transmitted to the second wiring configuration portion 29B through the first contact hole CH1 in the gate insulating film 30, and then supplied to the common electrode 28. The second wiring configuration portion 29B of the common wiring 29 is made of the second metal film, which has a lower sheet resistance than the first metal film, and therefore the wiring resistance of the common wiring 29 can be reduced compared to when the common wiring 29 is made up of only the first wiring configuration portion 29A. Furthermore, by making the first interval W1 wider than the second interval W2 as described above, the two first drivers 12α are arranged closer to the end in the X-axis direction at the first end portion 21A, and therefore the wiring length of the first wiring configuration portion 29A routed from the mounting region (terminal portion) of the first driver 12α to the first contact hole CH1 can be effectively shortened. By shortening the wiring length of the first wiring component 29A made of the first metal film having a higher sheet resistance than the second metal film, the wiring resistance of the common wiring 29 can be effectively reduced.

[0034] As shown in FIG. 4 , the first wiring configuration 29A is disposed in a region of the array substrate 21 that does not overlap at least the counter substrate 20. Specifically, a portion of the first wiring configuration 29A extending from the mounting region of the first driver 12α along the Y-axis direction and a portion of a portion extending along a diagonal direction are disposed so as not to overlap with the counter substrate 20. Therefore, at least a portion of the first wiring configuration 29A is exposed and not covered by the counter substrate 20. In contrast, the first wiring configuration 29A uses a first metal film made of a material that is less conductive than the second metal film but highly weather-resistant. Therefore, even if the first wiring configuration 29A has an exposed portion that is not covered by the counter substrate 20, corrosion and the like are unlikely to occur over time. On the other hand, the second wiring configuration 29B is disposed in a region of the array substrate 21 that overlaps with the counter substrate 20. In this embodiment, the entire second wiring configuration 29B is disposed so as to overlap with the counter substrate 20. In other words, the second wiring configuration 29B is covered by the opposing substrate 20 and is prevented from being exposed, so even if a material that has better conductivity than the first metal film but lower weather resistance is used as the material for the second metal film, corrosion and the like are less likely to occur over time.

[0035] As shown in FIGS. 4 and 5 , the first wiring configuration 29A is also disposed in a region of the array substrate 21 that overlaps with both the counter substrate 20 and the seal portion 23. In FIG. 4 , the region where the seal portion 23 is formed is shown shaded. Specifically, a portion (including the other end) of the first wiring configuration 29A extending along a diagonal direction is disposed so as to overlap with both the counter substrate 20 and the seal portion 23. Therefore, at least a portion of the first wiring configuration 29A may be exposed to humidity or a corrosive medium via the seal portion 23. In contrast, the first wiring configuration 29A uses a first metal film made of a material that is less conductive than the second metal film but has high weather resistance. Therefore, even if the first wiring configuration 29A is disposed in a region that overlaps with both the counter substrate 20 and the seal portion 23 and is exposed to humidity or a corrosive medium via the seal portion 23, corrosion or the like is unlikely to occur over time. On the other hand, the second wiring configuration portion 29B is arranged in a range of the array substrate 21 that does not overlap with the sealing portion 23 (overlapping with the liquid crystal layer 22). In this embodiment, the entire area of ​​the second wiring configuration portion 29B is arranged so as not to overlap with the sealing portion 23. Therefore, the second wiring configuration portion 29B is less likely to be exposed to humidity or corrosive media via the sealing portion 23, and therefore even if a material that is superior in conductivity to the first metal film but has low weather resistance is used as the material for the second metal film, corrosion and the like are less likely to occur over time.

[0036] Next, the following Reference Experiment 1 was conducted. Reference Experiment 1 was conducted to gain knowledge about how the crosstalk rate changes when the number of drivers 12 attached to the liquid crystal panel 11 is changed. Specifically, in Reference Experiment 1, a liquid crystal panel 11 attached with three drivers 12 is used as Reference Example 1, and a liquid crystal panel 11 attached with four drivers 12 is used as Reference Example 2. Each liquid crystal panel 11 in Reference Examples 1 and 2 has the same configuration as the liquid crystal panel 11 described earlier in this paragraph, except for the arrangement of the drivers 12. In each of the liquid crystal panels 11 in Reference Examples 1 and 2, the drivers 12 are arranged at equal intervals in the X-axis direction at the first end 21A of the array substrate 21. The liquid crystal panel 11 in Reference Example 1 has a screen size of 15.1 inches. The liquid crystal panel 11 in Reference Example 2 has a screen size of 13.3 inches. The liquid crystal panel 11 of Reference Example 2 has four drivers 12, and therefore, compared to the liquid crystal panel 11 of Reference Example 1 which has three drivers 12, the drivers 12 located at both ends in the X-axis direction are positioned closer to the ends in the X-axis direction, and the wiring length of the common wiring 29 is shorter.

[0037] In Reference Experiment 1, in each of the liquid crystal panels 11 of Reference Examples 1 and 2 configured as described above, a solid pattern of intermediate-tone pixels (pixels with 64 gradations) was displayed in a strip-shaped first region located at the center of the display area AA in the X-axis direction and extending along the Y-axis, and two strip-shaped second regions located at both ends of the display area AA in the X-axis direction and extending along the Y-axis. Furthermore, a checkerboard pattern of white pixels (pixels with 255 gradations) and black pixels (pixels with 0 gradations) was displayed in two strip-shaped third regions located on either side of the first region in the X-axis direction and extending along the Y-axis. In this state, the luminance of a predetermined pixel included in the first region was measured. The luminance measured at this time is referred to as "first luminance." Furthermore, in Reference Experiment 1, a solid pattern of intermediate-tone pixels was displayed across the entire display area AA in each of the liquid crystal panels 11 of Reference Examples 1 and 2, and the luminance of the predetermined pixel was measured in this state. The luminance measured at this time is referred to as "second luminance." The value obtained by dividing the difference between the first luminance and the second luminance by the second luminance was then calculated as the "crosstalk rate." In Reference Experiment 1, a solid pattern of half-tone pixels (pixels with 64 gradations) was displayed in the first and second regions, and a checkerboard pattern of white pixels (pixels with 255 gradations) and black pixels (pixels with 0 gradations) was displayed in the third region, and the time required for the potential (voltage) of the common electrode 28 to recover to the desired optimal value (common potential, Vcom value) was measured. Specifically, the potential of the common electrode 28 rises when the source wiring 27 provided in the third region where the checkered pattern is displayed switches from a white (255 gradation) potential to a black (0 gradation) potential, or when the source wiring 27 switches from a black (0 gradation) potential to a white (255 gradation) potential. Therefore, in Reference Experiment 1, the elapsed time from the time when the potential of the common electrode 28 rises until the potential of the common electrode 28 reaches a desired optimal value is measured. The experimental results of Reference Experiment 1 are as shown in FIGS. 6A and 6B. FIG. 6A shows the experimental results of Reference Example 1, and FIG. 6B shows the experimental results of Reference Example 2. FIGS. 6A and 6B are graphs with the vertical axis representing voltage (unit: "V") and the horizontal axis representing elapsed time (unit: "μs").6A and 6B also show the potentials (voltages) of the gate line 26, the pixel electrode 25 and source line 27 in the first region, and the source line 27 in the third region, in addition to the potential of the common electrode 28. Fig. 7 is a graph in which the vertical axis represents the crosstalk rate (unit: "%)" and the horizontal axis represents the elapsed time (unit: "μs") until the potential of the common electrode 28 recovers to the desired optimum value. In Fig. 7, the plots of Reference Example 1 are indicated by "△" marks, and the plots of Reference Example 2 are indicated by "◯" marks.

[0038] The results of Reference Experiment 1 will be described. According to FIG. 6A, in Reference Example 1, the time elapsed from when the potential of the common electrode 28 was pushed up at the timing when the source line 27 provided in the third region switched from a white (255 gradation) potential to a black (0 gradation) potential, or from a black (0 gradation) potential to a white (255 gradation) potential, until it returned to the desired optimum value was 14.3 μs. In contrast, according to FIG. 6B, in Reference Example 2, the time elapsed until the potential of the common electrode 28 returned to the desired optimum value was 12.2 μs. Thus, it was found that the elapsed time in Reference Example 2 was about 2.1 μs shorter than in Reference Example 1, and crosstalk was suppressed. This is thought to be because, in Reference Example 2 in which four drivers 12 are installed, the wiring length of the common wiring 29 is shorter than in Reference Example 1 in which three drivers 12 are installed, and as a result the wiring resistance of the common wiring 29 is lower, so that the potential of the common electrode 28 is more likely to recover even if it is pushed up due to potential fluctuations via the parasitic capacitance with the source wiring 27, ultimately reducing the loss of the liquid crystal applied voltage between the pixel electrode 25 and the common electrode 28 and suppressing the crosstalk rate (see Figure 7).

[0039] Next, the following Reference Experiment 2 was conducted. In Reference Experiment 2, the liquid crystal panels 11 of Reference Examples 1 and 2 described in Reference Experiment 1 were used, and the values ​​of various parameters that are expected to affect the crosstalk rate were changed. The various parameters include the parasitic capacitance between the source line 27 and the common electrode 28, the wiring resistance of the common line 29, and the wiring resistance of the fan-shaped portion of the source line 27. In Reference Experiment 2, the various parameters are expressed as relative values, with the value in Reference Experiment 1 set as the reference value (1.0). For example, if the relative value of various parameters in Reference Experiment 2 is "2.0," this is twice the value of the various parameters in Reference Experiment 1. Reference Experiment 2 was conducted with the various parameters in Reference Examples 1 and 2 set to "1.0," "1.1," "1.5," and "2.0," respectively. Specifically, assuming that the parasitic capacitance between the source line 27 and the common electrode 28 in Reference Experiment 1 was approximately 32.1 fF, if the relative value of the parasitic capacitance (parameter) was 1.1, the parasitic capacitance would be approximately 35.3 fF; if the relative value of the parasitic capacitance was 1.5, the parasitic capacitance would be approximately 48.1 fF; and if the relative value of the parasitic capacitance was 2.0, the parasitic capacitance would be approximately 64.1 fF. The same applies to the wiring resistance of the common line 29 and the wiring resistance of the fan-shaped portion of the source line 27. In Reference Experiment 2, various parameters in Reference Examples 1 and 2 were varied, and the crosstalk rate was calculated after the experimental results of Reference Experiment 1 (the time elapsed from when the potential of the common electrode 28 rose to when the potential of the common electrode 28 reached the desired optimal value) had elapsed. Specifically, for Reference Example 1, the crosstalk rate was calculated after 14.3 μs had elapsed, which was the time elapsed from when the potential of the common electrode 28 rose until the potential of the common electrode 28 reached the desired optimum value. For Reference Example 2, the crosstalk rate was calculated after 12.2 μs had elapsed, which was the time elapsed from when the potential of the common electrode 28 rose until the potential of the common electrode 28 reached the desired optimum value. Note that when the relative values ​​of various parameters are "1.0," the crosstalk rate is 0%. The experimental results of Reference Experiment 2 are shown in FIGS. 8 and 9.Fig. 8 shows the experimental results of Reference Example 1, and Fig. 9 shows the experimental results of Reference Example 2. Figs. 8 and 9 are graphs in which the vertical axis represents the crosstalk rate (unit: "%)" and the horizontal axis represents the relative value of the parameter (unitless). In Figs. 8 and 9, the plot of the parasitic capacitance between the source wiring 27 and the common electrode 28 is indicated by a "●" mark, the plot of the wiring resistance of the common wiring 29 is indicated by a "▲" mark, and the plot of the wiring resistance of the fan-shaped portion of the source wiring 27 is indicated by a "■" mark.

[0040] The results of Reference Experiment 2 will be described. FIG. 8 shows that in Reference Example 1, increasing the relative value of the wiring resistance of the fan-shaped portion of the source wiring 27 hardly changes the crosstalk rate. However, the crosstalk rate tends to increase as the relative values ​​of the parasitic capacitance between the source wiring 27 and the common electrode 28 and the wiring resistance of the common wiring 29 increase. In particular, the crosstalk rate significantly increases as the relative value of the parasitic capacitance between the source wiring 27 and the common electrode 28 increases. Specifically, when the relative value of the parasitic capacitance between the source wiring 27 and the common electrode 28 is 2.0, the crosstalk rate is approximately 1.75%. On the other hand, FIG. 9 shows that in Reference Example 2, increasing the relative values ​​of the wiring resistance of the common wiring 29 and the wiring resistance of the fan-shaped portion of the source wiring 27 hardly changes the crosstalk rate. Furthermore, increasing the relative value of the parasitic capacitance between the source wiring 27 and the common electrode 28 only slightly increases the crosstalk rate. Specifically, when the relative value of the parasitic capacitance between the source line 27 and the common electrode 28 is "2.0," the crosstalk rate is approximately "0.25%." Thus, compared to Reference Example 1, Reference Example 2 can be said to generally suppress crosstalk even when various parameters are increased. Suppressing crosstalk also shortens the time required for the crosstalk rate to reach 0% after a solid pattern of half-tone pixels is displayed across the entire display area AA. This is presumably due primarily to the fact that Reference Example 2, in which four drivers 12 are installed, has a shorter common line 29 than Reference Example 1, in which three drivers 12 are installed, resulting in a lower reference value for the wiring resistance of the common line 29.

[0041] 1 and 4, in this embodiment, the first interval W1 between the first driver 12α and the second driver 12β adjacent to each other in the second direction is wider than the second interval W2 between two second drivers 12β adjacent to each other in the second direction. Therefore, compared to Reference Example 2 in which the four drivers 12 are arranged at equal intervals, the two first drivers 12α are arranged closer to the end in the X-axis direction at the first end 21A. In other words, the wiring resistance of the common wiring 29 according to this embodiment is expected to be even lower than the reference value of the wiring resistance of the common wiring 29 according to Reference Example 2. Therefore, based on the experimental results of Reference Experiments 1 and 2 described above, it is presumed that this embodiment will achieve better results in suppressing crosstalk than Reference Example 2.

[0042] As described above, the liquid crystal panel (display device) 11 of this embodiment includes: an array substrate (first substrate) 21 having a main surface 21S divided into a display area AA where an image is displayed and a non-display area NAA where an image is not displayed; source wirings (first wirings) 27 arranged in the display area AA of the array substrate 21 and extending along the first direction; a driver (signal supply unit) 12 arranged in the non-display area NAA of the array substrate 21 at a first end 21A in the first direction, connected to at least the source wirings 27 and supplying signals to the source wirings 27; a common electrode 28 arranged in the display area AA of the array substrate 21; and a common wiring 29 arranged in the non-display area NAA of the array substrate 21 and connected to the common electrode 28. The driver 12 also includes a common wiring 29 arranged at the first end 21A along the main surface 21S and intersecting the first direction. and at least two second drivers (second signal supply units) 12β that are sandwiched between the two first drivers 12α in the second direction at the first end 21A and are spaced apart in the second direction, at least two common wirings 29 are arranged at positions closer to the ends of the two first drivers 12α in the second direction and are connected to the two first drivers 12α, respectively, and the first drivers 12α supply a common potential signal to the common wiring 29, and the first drivers 12α are arranged such that a first interval W1 that is an interval between adjacent second drivers 12β in the second direction is wider than a second interval W2 that is an interval between two adjacent second drivers 12β in the second direction.

[0043] At least two common wirings 29 arranged closer to the ends in the second direction than the two first drivers 12α are supplied with common potential signals from the two first drivers 12α. The common electrode 28 is set to a common potential based on the common potential signals supplied by the at least two common wirings 29. The first interval W1 between the first driver 12α and the second driver 12β adjacent to it in the second direction is wider than the second interval W2 between the two second drivers 12β adjacent to it in the second direction. Therefore, compared to a case where the first interval is the same as the second interval W2, the two first drivers 12α are arranged closer to the ends in the second direction at the first end 21A. This shortens the wiring length of the common wirings 29 arranged from the first drivers 12α to the common electrode 28, thereby reducing the wiring resistance of the common wirings 29. By reducing the wiring resistance of the common wiring 29, the common electrode can be stably maintained at a common potential, thereby suppressing the occurrence of crosstalk due to potential fluctuations of the common electrode .

[0044] The common wiring 29 has a first wiring portion 29A made of a first metal film (first conductive film) and a second wiring portion 29B made of a second metal film (second conductive film) having a lower sheet resistance than the first metal film with a gate insulating film (first insulating film) 30 interposed between the first wiring portion 29A and the first metal film, and the first wiring portion 29A and the second wiring portion 29B are connected through a first contact hole CH1 provided in the gate insulating film 30, and the first wiring portion 29A is connected to the first driver 12α, and the second wiring portion 29B is connected to the common electrode 28. A common potential signal output from the first driver 12α is supplied to the common electrode 28 via the first wiring portion 29A and the second wiring portion 29B, which are connected through the first contact hole CH1 in the gate insulating film 30. The common wiring 29 includes the second wiring component 29B made of a second metal film having a lower sheet resistance than the first metal film, and therefore the wiring resistance of the common wiring 29 can be reduced compared to when the common wiring 29 is made of only the first wiring component 29A. As described above, by making the first interval W1 wider than the second interval W2, the two first drivers 12α are arranged closer to the ends in the second direction at the first end 21A, and therefore the wiring length of the first wiring component 29A connected to the first drivers 12α can be effectively shortened. By shortening the wiring length of the first wiring component 29A made of the first metal film having a higher sheet resistance than the second metal film, the wiring resistance of the common wiring 29 can be effectively reduced.

[0045] The display device also includes a counter substrate (second substrate) 20 disposed opposite the array substrate 21 at a distance so as not to overlap with the first end 21A. The first wiring configuration 29A is disposed at least in a region that does not overlap with the counter substrate 20, and the second wiring configuration 29B is disposed in a region that overlaps with the counter substrate 20. The first wiring configuration 29A uses a material for the first metal film that is less conductive than the second metal film but has high weather resistance, so that even if the first wiring configuration 29A is disposed in at least a region that does not overlap with the counter substrate 20 and is exposed in the non-display area NAA of the array substrate 21 and does not overlap with the counter substrate 20, corrosion and the like are unlikely to occur over time. The second wiring configuration 29B is disposed in a region that overlaps with the counter substrate 20 in the non-display area NAA of the array substrate 21 and is not exposed, so that even if the second metal film is disposed in a region that is more conductive than the first metal film but has low weather resistance, corrosion and the like are unlikely to occur over time.

[0046] The first wiring configuration portion 29A is also provided with a seal portion 23 extending along the outer peripheral edge of the counter substrate 20 and interposed between the array substrate 21 and the counter substrate 20, and the first wiring configuration portion 29A is also arranged in an area overlapping both the counter substrate 20 and the seal portion 23, while the second wiring configuration portion 29B is arranged in an area not overlapping with the seal portion 23. The first wiring configuration portion 29A is made of a first metal film material that is less conductive than the second metal film but has high weather resistance, so that even if the first wiring configuration portion 29A is arranged in an area overlapping both the counter substrate 20 and the seal portion 23 in the non-display area NAA of the array substrate 21 and exposed to humidity or a corrosive medium via the seal portion 23, corrosion and the like are unlikely to occur over time. The second wiring configuration portion 29B is arranged in an area of ​​the non-display area NAA of the array substrate 21 that does not overlap with the sealing portion 23 and is therefore less likely to be exposed to humidity or corrosive media. Therefore, even if a material that has superior conductivity compared to the first metal film but poor weather resistance is used as the material for the second metal film, corrosion, etc. is less likely to occur over time.

[0047] Furthermore, the first metal film contains at least one of molybdenum and tungsten, and the second metal film contains aluminum. By including at least one of molybdenum and tungsten in the first metal film, the weather resistance of the first wiring configuration portion 29A is higher than that of the second wiring configuration portion 29B. This makes it less susceptible to corrosion and other problems over time in the first wiring configuration portion 29A, even if the first wiring configuration portion 29A is disposed and exposed in at least a region of the non-display area NAA of the array substrate 21 that does not overlap with the counter substrate 20. By including aluminum in the second metal film, the sheet resistance of the second wiring configuration portion 29B can be made lower than the sheet resistance of the first wiring configuration portion 29A. This reduces the wiring resistance of the common wiring 29.

[0048] <Embodiment 2> A second embodiment will be described with reference to Fig. 10. In this second embodiment, a ratio of the source lines 127 connected to each driver 112 is set. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0049] As shown in FIG. 10 , the distribution ratio of the source wirings 127 connected to each driver 112 according to this embodiment is determined according to the arrangement. That is, a smaller number of source wirings 127 are connected to the first driver 112α located at the end in the X-axis direction at the first end 121A of the array substrate 121 than to the second driver 112β located toward the center. Specifically, the ratio of the number of source wirings 127 connected to the first driver 112α to the number of source wirings 127 connected to the second driver 112β is 2:3. Note that FIG. 10 illustrates the ratio of the number of source wirings 127 connected to each of the first driver 112α and the second driver 112β. That is, the number of source wirings 127 connected to the two first drivers 112α is 1 / 5 (2 / 10) of the total number of source wirings 127. The number of source wirings 127 connected to the two second drivers 112β is 3 / 10 of the total number of source wirings 127. In this way, the load on the first driver 112α for outputting an image signal to the source line 127 is reduced compared to that on the second driver 112β. This allows the first driver 112α to stably supply a common potential signal to the common line 129.

[0050] As described above, according to this embodiment, a plurality of source wirings 127 are arranged at intervals in the second direction, and a smaller number of source wirings 127 are connected to the first driver 112α than to the second driver 112β. Since the number of source wirings 127 connected to the first driver 112α is smaller than the number of source wirings 127 connected to the second driver 112β, the load on the first driver 112α is reduced. This allows a common potential signal to be stably supplied from the first driver 112α to the common wiring 129.

[0051] <Embodiment 3> A third embodiment will be described with reference to Fig. 11. In this third embodiment, a gate drive circuit 32 and the like are added to the second embodiment, and the ratio of the source wirings 227 connected to each driver 212 is changed. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0052] As shown in FIG. 11 , a gate drive circuit unit (third signal supply unit) 32 is provided in the non-display area NAA of the array substrate 221 according to this embodiment. The gate drive circuit units 32 are arranged adjacent to one side of the display area AA with a gap in the X-axis direction. The gate drive circuit units 32 are arranged so that some common wiring 229 is sandwiched between the gate drive circuit unit 32 and the display area AA. The gate drive circuit unit 32 is provided in a vertically elongated band-shaped range extending along the Y-axis direction. The gate drive circuit unit 32 is connected to all gate wiring 226 arranged in the display area AA and supplies scanning signals to each gate wiring 226. The gate drive circuit unit 32 is provided monolithically on the array substrate 221.

[0053] The non-display area NAA of the array substrate 221 is provided with connection wiring 33 connected to the gate drive circuit unit 32. One end of the connection wiring 33 is connected to the gate drive circuit unit 32, and the other end is connected to one of the two first drivers 212α, a first driver 212α1. Hereinafter, when distinguishing between the two first drivers 212α, the reference numeral of one of the first drivers 212α will be suffixed with "1" and the reference numeral of the other first driver 212α will be suffixed with "2." When referring to the first drivers 212α collectively without distinction, the reference numerals will be omitted. One of the first drivers 212α1 is disposed near the end position on the gate drive circuit unit 32 side (left side in FIG. 11 ) in the X-axis direction at the first end 221A of the array substrate 221. Various signals (such as a clock signal, an initialization signal, and a gate start pulse signal) for controlling the gate drive circuit unit 32 are supplied to the connection wiring 33 from the first driver 212α1. The gate drive circuit unit 32 operates based on various signals supplied by the connection wiring 33, and can supply scanning signals to the plurality of gate wirings 226 in a predetermined order. The connection wiring 33 is arranged at an end in the X-axis direction relative to the common wiring 229, and a plurality of connection wirings 33 are arranged parallel to the common wiring 229. The connection wiring 33 extends from the mounting region of one of the first drivers 212α1 at the first end 221A along the Y-axis direction toward the display area AA, where it is bent, extends diagonally toward the gate drive circuit unit 32, is bent again, extends along the Y-axis direction, and is connected to the end of the gate drive circuit unit 32 in the Y-axis direction. The connection wiring 33 is not connected to the other first driver 212α2.

[0054] In this embodiment, different numbers of source wirings 227 are connected to the two first drivers 212α. That is, a smaller number of source wirings 227 is connected to one first driver 212α1 than to the other first driver 212α2. Specifically, the ratio of the number of source wirings 227 connected to one first driver 212α1 to the number of source wirings 227 connected to the other first driver 212α2 is set to 1:2. Furthermore, the ratio of the number of source wirings 227 connected to the other first driver 212α2 to the number of source wirings 227 connected to the second driver 212β is set to 2:3. Note that FIG. 11 illustrates the ratios of the number of source wirings 227 connected to one first driver 212α1, the other first driver 212α2, and the second driver 212β. In this way, the number of source wirings 227 connected to one first driver 212α1 is 1 / 3 of the total number of source wirings 227, and the number of source wirings 227 connected to the other first driver 212α2 is 2 / 3 of the total number of source wirings 227. In addition, the number of source wirings 227 connected to the two second drivers 212β is 1 / 3 (3 / 9) of the total number of source wirings 227, respectively.

[0055] Here, one first driver 212α1 supplies various signals for controlling the gate drive circuit unit 32 to the connection wiring 33, and therefore has a higher load than the other first driver 212α2. In this regard, as described above, the number of source wirings 227 connected to one first driver 212α1 is made smaller than the number of source wirings 227 connected to the other first driver 212α2, so the load on one first driver 212α1 is reduced. This allows a common potential signal to be stably supplied from one first driver 212α1 to the common wiring 229.

[0056] As described above, this embodiment includes a plurality of gate wirings (second wirings) 226 arranged in the display area AA of the array substrate 221 and extending along the second direction, and a gate drive circuit unit (third signal supply unit) 32 arranged alongside the display area AA in the second direction in the non-display area NAA of the array substrate 221. The gate drive circuit unit 32 is connected to the plurality of gate wirings 226 and supplies scanning signals to the plurality of gate wirings 226. One first driver 212α1 of the two first drivers 212α is connected to the gate drive circuit unit 32 and supplies signals for controlling the supply of scanning signals to the gate drive circuit unit 32. A smaller number of source wirings 227 are connected to the one first driver 212α1 than to the other first driver 212α2. The gate drive circuit unit 32 supplies scanning signals to the plurality of gate wirings 226 based on signals supplied from the one first driver 212α1. Therefore, the one first driver 212α1 has a higher load than the other first driver 212α2. In this regard, since the number of source wirings 227 connected to one first driver 212α1 is smaller than the number of source wirings 227 connected to the other first driver 212α2, the load on one first driver 212α1 is reduced. This allows a common potential signal to be stably supplied from one first driver 212α1 to the common wiring 229.

[0057] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 12. In this fourth embodiment, the number of drivers 312 installed is changed from that in the first embodiment. Note that redundant explanations of the structure, operation, and effects similar to those in the first embodiment will be omitted.

[0058] As shown in FIG. 12 , five drivers 312 are arranged at intervals in the X-axis direction at a first end 321A of the array substrate 321 according to this embodiment. In this embodiment, of the five drivers 312 arranged along the X-axis direction, two drivers 312 located at both ends in the X-axis direction (the left and right ends in FIG. 12 ) are referred to as “first drivers 312α,” and three drivers 312 located closer to the center in the X-axis direction than the two first drivers 312α are referred to as “second drivers 312β.” The three second drivers 312β are arranged at equal intervals in the X-axis direction. Specifically, a second interval W302 is provided between the second driver 312β located at the center in the X-axis direction and the second driver 312β located on the left side in FIG. 12 . Of the three second drivers 312β, a second distance W302 is provided between the second driver 312β located in the center in the X-axis direction and the second driver 312β located on the right side in Fig. 12. In this manner, a second distance W302 is provided between each two second drivers 312β that are directly adjacent to each other in the X-axis direction (without passing through another second driver 312β), and this second distance W302 is narrower than the first distance W301 provided between the first driver 312α and the second driver 312β adjacent to it in the X-axis direction. Even with this configuration, the same functions and effects as those of the first embodiment can be obtained.

[0059] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0060] (1) The specific materials used for each metal film can be changed as appropriate to those not mentioned above. The first metal film may be a single layer film made of MoW (molybdenum tungsten) or a laminated film made of W (tungsten) / TaN (tantalum nitride) or the like. The second metal film may be a laminated film made of Ti / Cu (copper) / Ti or the like.

[0061] (2) The specific formation range of the first wiring component 29A can be changed as appropriate. For example, a part of the first wiring component 29A may be arranged in a range that overlaps with the counter substrate 20 but does not overlap with the sealing portion 23 (overlapping with the liquid crystal layer 22). Also, for example, the first wiring component 29A may be arranged only in a range that does not overlap with the counter substrate 20.

[0062] (3) The specific formation range of the second wiring component 29B can be changed as appropriate to other ranges than those described above. For example, a part of the second wiring component 29B may be disposed in a range that overlaps both the counter substrate 20 and the sealing portion 23.

[0063] (4) When a third metal film located above the second metal film is provided on the array substrate 21, 121, 221, 321, the second wiring configuration portion 29B may be formed of the third metal film. Also, the second wiring configuration portion 29B may be formed of the second metal film and the third metal film.

[0064] (5) In the configuration described in embodiment 2, the specific numerical values ​​relating to the ratio between the number of source wirings 127 connected to the first driver 112α and the number of source wirings 127 connected to the second driver 112β can be changed as appropriate to values ​​other than those mentioned above.

[0065] (6) In the configuration described in embodiment 3, the specific numerical value relating to the ratio between the number of source wirings 227 connected to one first driver 212α1 and the number of source wirings 227 connected to the other first driver 212α2 can be changed as appropriate, in addition to the above. Furthermore, the specific numerical value relating to the ratio between the number of source wirings 227 connected to the other first driver 212α2 and the number of source wirings 227 connected to the second driver 212β can be changed as appropriate, in addition to the above.

[0066] (7) As a modification of the third embodiment, two gate drive circuits 32 may be provided on either side of the display area AA in the X-axis direction. In this case, the array substrate 221 is provided with a connection wiring 33 connecting one gate drive circuit 32 and one first driver 212α1, as well as a connection wiring 33 connecting the other gate drive circuit 32 and the other first driver 212α2. The other first driver 212α2 supplies various signals to the other gate drive circuit 32 via the connection wiring. In this case, the same number of source wirings 227 may be connected to one first driver 212α1 and the other first driver 212α2, but this is not necessarily the case.

[0067] (8) In the configuration described in the fourth embodiment, the distance between the second driver 312β located in the center in the X-axis direction and the second driver 312β located on the left side in Fig. 12 may be different from the distance between the second driver 312β located in the center in the X-axis direction and the second driver 312β located on the right side in Fig. 12. Even in this case, the first distance W1 provided between the first driver 312α and the second driver 312β adjacent to it in the X-axis direction is configured to be the widest.

[0068] (9) The number of drivers 12, 112, 212, 312 attached to the array substrate 21, 121, 221, 321 may be six or more. In that case, the number of second drivers 12β, 112β, 212β, 312β is four or more ("N-2" if the total number of drivers 12, 112, 212, 312 is "N").

[0069] (10) The specific routing paths of the common wiring 29, 129, 229 at the first ends 21A, 121A, 221A, 321A of the array substrates 21, 121, 221, 321 can be changed as appropriate to those shown in the drawings. For example, the common wiring 29, 129, 229 may include a portion extending along the X-axis direction.

[0070] (11) The number of common wirings 29, 129, 229 connected to one first driver 12α, 112α, 212α, 312α may be three or more. For example, a common wiring 29, 129, 229 may be added to a side portion of the outer periphery of the common electrode 28 along the X-axis direction that is located on the driver 12, 112, 212, 312 side in the Y-axis direction, and that is connected to a central portion excluding both end positions in the X-axis direction.

[0071] (12) The array substrates 21, 121, 221, and 321 may be provided with a switch circuit section (SSD (Source Shared Driving) circuit) having a switch function for distributing image signals supplied from the drivers 12, 112, 212, and 312 to the source lines 27, 127, and 227.

[0072] (13) The display mode of the liquid crystal panel 11 may be FFS mode, Fringe Field Switching mode, Twisted Nematic mode, Vertical Alignment mode, or the like, in addition to FFS mode.

[0073] (14) The liquid crystal panel 11 may be a reflective or semi-transmissive type in addition to a transmissive type.

[0074] (15) In addition to the liquid crystal display device 10 having the liquid crystal panel 11, an organic EL (Electro Luminescence) display device having an organic EL display panel may also be used. [Explanation of symbols]

[0075] 11... liquid crystal panel (display device), 12, 112, 212, 312... driver (signal supply unit), 12α, 112α, 212α, 312α... first driver (first signal supply unit), 12β, 112β, 212β, 312β... second driver (second signal supply unit), 20... opposing substrate (second substrate), 21, 121, 221, 321... array substrate (first substrate), 21A, 121A, 221A, 321A... first end portion, 21S... main surface, 23... sealing portion, 26, 226... gate wiring ( 212α1...one first driver, 212α2...the other first driver, AA...display area, CH1...first contact hole, NAA...non-display area, W1, W301...first interval, W2, W302...second interval

Claims

1. a first substrate having a main surface divided into a display area where an image is displayed and a non-display area where the image is not displayed; a first wiring disposed in the display region of the first substrate and extending along a first direction; a signal supply unit that is arranged at a first end in the first direction in the non-display region of the first substrate, is connected to at least the first wiring, and supplies a signal to the first wiring; a common electrode disposed in the display area of ​​the first substrate; a common wiring disposed in the non-display area of ​​the first substrate and connected to the common electrode; the signal supply portion includes two first signal supply portions arranged at the first end portion along the main surface and on both ends in a second direction intersecting the first direction, and at least two second signal supply portions arranged at the first end portion sandwiched between the two first signal supply portions in the second direction and spaced apart in the second direction, At least two of the common wirings are arranged at positions closer to the ends of the two first signal supply units in the second direction, and are connected to the two first signal supply units, respectively; the first signal supply unit supplies a common potential signal to the common wiring; A display device in which the first signal supply units are arranged so that a first interval, which is the interval between adjacent second signal supply units in the second direction, is wider than a second interval, which is the interval between two adjacent second signal supply units in the second direction.

2. the common wiring has a first wiring component made of a first conductive film, and a second wiring component made of a second conductive film having a sheet resistance lower than that of the first conductive film with a first insulating film interposed between the first wiring component and the second conductive film, and the first wiring component and the second wiring component are connected to each other through a first contact hole provided in the first insulating film; the first wiring configuration section is connected to the first signal supply section, The display device according to claim 1 , wherein the second wiring structure is connected to the common electrode.

3. a second substrate disposed opposite the first substrate at a distance so as not to overlap the first end portion; the first wiring component is disposed at least in a range that does not overlap with the second substrate, The display device according to claim 2 , wherein the second wiring structure is disposed in a range overlapping with the second substrate.

4. a seal portion extending along an outer peripheral edge of the second substrate and interposed between the first substrate and the second substrate; the first wiring configuration portion is also disposed in a range overlapping both the second substrate and the sealing portion, The display device according to claim 3 , wherein the second wiring component is disposed in a range that does not overlap the sealing portion.

5. the first conductive film contains at least one of molybdenum and tungsten; 5. The display device according to claim 3, wherein the second conductive film contains aluminum.

6. a plurality of the first wirings are arranged at intervals in the second direction, 5. The display device according to claim 1, wherein a smaller number of the first wirings are connected to the first signal supplying section than to the second signal supplying section.

7. a plurality of second wirings arranged in the display region of the first substrate and extending along the second direction; a third signal supply unit arranged alongside the display area in the second direction in the non-display area of ​​the first substrate, the third signal supply unit is connected to the second wirings and supplies scanning signals to the second wirings; one of the two first signal supply units is connected to the third signal supply unit and supplies a signal for controlling supply of the scanning signal to the third signal supply unit; 7. The display device according to claim 6, wherein one of the first signal supply units is connected to a smaller number of the first wirings than the other of the first signal supply units.

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