Photoelectric conversion device and apparatus

Abstract

To provide a photoelectric conversion device capable of accurately removing noise.SOLUTION: A first scanning circuit that scans a plurality of pixels in a first mode in which an analog signal at a reset level and a first type of analog signal corresponding to signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output, and a second mode in which an analog signal corresponding to signal charges of the first photoelectric conversion unit is output in addition to the reset level and the first type of analog signal; A first AD conversion period related to an analog signal of a reset level in the first mode is included. In the case of transition from the second mode to the first mode, the second scanning circuit performs the additional signal transfer operation so that the number of times of the first signal transfer operation between the first AD conversion period and the AD conversion period immediately before the first AD conversion period is equal to the number of times of the second signal transfer operation between the first AD conversion period and the AD conversion period next to the first AD conversion period.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 describes an imaging device with a phase-difference autofocus function. Each pixel of this imaging device has a first photoelectric conversion unit and a second photoelectric conversion unit. When performing autofocus, the focus is detected based on the phase difference between the pixel signal from the first photoelectric conversion unit and the pixel signal from the second photoelectric conversion unit. The imaging device in Patent Document 1 is divided into a first area where only imaging is performed and a second area where autofocus and imaging are performed. By making the second area smaller, the autofocus processing is reduced and imaging speed is increased.

[0003] The pixels included in the first region output a pixel signal for resetting and a pixel signal for imaging. Each of the two pixel signals undergoes AD conversion and is transferred to a downstream signal processing circuit. Meanwhile, the pixels included in the second region output a pixel signal for resetting, a pixel signal for autofocusing, and a pixel signal for imaging. Each of the three pixel signals undergoes AD conversion and is transferred to a downstream signal processing circuit. The signal transfer operation is performed during transfer periods when AD conversion is not performed (transfer periods between AD conversions). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-211833 Summary of the Invention [Problem to be solved by the invention]

[0005] However, because the number of pixel signals output from each pixel differs between the first and second regions, the number of AD conversions and the number of signal transfer operations also differ. Therefore, when the region changes, the number of signal transfer operations during the transfer period between AD conversions may differ. Here, power supply fluctuations during signal transfer operations may cause noise to be included in pixel signals during AD conversion. Different numbers of signal transfer operations may result in pixel signals that are affected by different noise. In this case, when noise is removed using a reset pixel signal, the noise may not be removed accurately.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a photoelectric conversion device that can remove noise with high accuracy. [Means for solving the problem]

[0007] According to one disclosure of the present specification, there is provided a method for manufacturing a semiconductor device comprising: a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels; and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels; an AD conversion unit that converts each of the plurality of analog signals into a digital signal in each of a plurality of AD conversion periods; and a memory that holds the digital signals. and a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory in each of a plurality of transfer periods different from the plurality of AD conversion periods, wherein the plurality of AD conversion periods includes a first AD conversion period in which the analog signal of the reset level in the first mode is converted into the digital signal, and when transitioning from the second mode to the first mode, the second scanning circuit performs the additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately before the first AD conversion period is equal to the number of second signal transfer operations between the first AD conversion period and the AD conversion period next to the first AD conversion period.

[0008] According to one disclosure of the present specification, there is provided a scanning circuit for scanning a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges, a first scanning circuit for scanning the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels, and an AD converter for converting each of the plurality of analog signals into a digital signal in each of a plurality of AD conversion periods is provided. a memory for storing the digital signal; and a second scanning circuit for performing a signal transfer operation to output the digital signal from the memory in each of a plurality of transfer periods different from the plurality of AD conversion periods, wherein the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal of the reset level in the first mode into the digital signal, and when transitioning from the second mode to the first mode, the second scanning circuit performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately before the first AD conversion period is the same for each scan in the first mode.

[0009] According to one disclosure of the present specification, there is provided a scanning circuit for scanning a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges, a first scanning circuit for scanning the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels, and an AD converter for converting each of the plurality of analog signals into a digital signal in each of a plurality of AD conversion periods is provided. a memory for storing the digital signal; and a second scanning circuit for performing a signal transfer operation to output the digital signal from the memory in each of a plurality of transfer periods different from the plurality of AD conversion periods, wherein the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal of the reset level in the first mode into the digital signal, and when transitioning from the second mode to the first mode, the second scanning circuit performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period next to the first AD conversion period is the same for each scan in the first mode.

[0010] According to one disclosure of the present specification, there is provided a method for manufacturing a semiconductor memory device comprising: a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels; and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixels; an AD conversion unit that converts each of the plurality of analog signals into a digital signal in each of a plurality of AD conversion periods; a memory that holds the digital signals; and a scanning circuit that transfers the digital signals to the memory in each of a plurality of transfer periods different from the plurality of AD conversion periods. and a second scanning circuit that performs a signal transfer operation to output the digital signal from a first AD conversion period, wherein the plurality of AD conversion periods includes a first AD conversion period in which the analog signal at the reset level in the first mode is converted into the digital signal, and when transitioning from the second mode to the first mode, the second scanning circuit performs the additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately before the first AD conversion period is the same for each scan in the first mode, and performs the additional signal transfer operation so that the number of second signal transfer operations between the first AD conversion period and the AD conversion period next to the first AD conversion period is the same for each scan in the first mode. [Effects of the Invention]

[0011] According to the present invention, it is possible to realize a photoelectric conversion device that can remove noise with high precision. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram of an imaging device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a pixel according to the first embodiment. [Figure 3] FIG. 4 is a timing chart of an imaging device according to a first comparative example. [Figure 4] FIG. 10 is a timing chart of an imaging device according to a second comparative example. [Figure 5] FIG. 11 is a timing chart of an imaging device according to a third comparative example. [Figure 6] FIG. 11 is a timing chart of an imaging device according to a fourth comparative example. [Figure 7] FIG. 2 is a timing chart of the imaging device according to the first embodiment. [Figure 8] FIG. 10 is a timing chart of the imaging device according to the second embodiment. [Figure 9] FIG. 11 is a timing chart of an imaging device according to a fifth comparative example. [Figure 10] FIG. 10 is a timing chart of the imaging device according to the third embodiment. [Figure 11] FIG. 10 is a timing chart of the imaging device according to the fourth embodiment. [Figure 12] FIG. 11 is a block diagram of a device according to a fifth embodiment. [Figure 13] FIG. 13 is a block diagram of a device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the embodiments are not limited to image pickup devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measurement device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometry device (a device that measures the amount of incident light) can be used.

[0014] [First embodiment] FIG. 1 is a block diagram of an imaging device 100 according to this embodiment. The imaging device 100 includes a pixel array 1, a vertical scanning circuit (first scanning circuit) 2, a reference signal output circuit 3, a counter 4, a plurality of column signal processing circuits 5, a horizontal scanning circuit (second scanning circuit) 6, a signal processing circuit 7, and a timing control unit 8.

[0015] The pixel array 1 is connected to a vertical scanning circuit 2 and a plurality of column signal processing circuits 5. The plurality of column signal processing circuits 5 are connected to a reference signal output circuit 3, a counter 4, a horizontal scanning circuit 6, and a signal processing circuit 7. The timing control unit 8 is connected to the vertical scanning circuit 2, the reference signal output circuit 3, the counter 4, the plurality of column signal processing circuits 5, and the horizontal scanning circuit 6.

[0016] The pixel array 1 has a plurality of pixels 11 arranged in an array of a plurality of rows and a plurality of columns. The number of pixels 11 constituting the pixel array 1 is not particularly limited. For example, the pixel array 1 can be constituted by a plurality of pixels 11 arranged in an array of several thousand rows and several thousand columns, as in a general digital camera. Alternatively, the pixel array 1 may be constituted by a plurality of pixels 11 arranged in one row or one column. Furthermore, in this specification, the vertical scanning circuit 2, which is the first scanning circuit, performs scanning to select pixels row by row, but the first scanning circuit may also be a circuit that scans pixels column by column.

[0017] A control line 12 is arranged in each row of the pixel array 1, extending in a first direction (the horizontal direction in FIG. 1 ). The control line 12 is connected to each of the pixels 11 arranged in the first direction and serves as a signal line common to these pixels 11. The pixels 11 arranged in the same row are controlled by the same control line 12. Each of the control lines 12 may include multiple signal lines for supplying multiple types of control signals to the pixels 11. The control lines 12 in each row are connected to a vertical scanning circuit 2.

[0018] Each column of the pixel array 1 is provided with a column signal line 13 extending in a second direction (vertical direction in FIG. 1 ) intersecting the first direction. The column signal line 13 is connected to each of the pixels 11 aligned in the second direction and serves as a common signal line for these pixels 11. The column signal line 13 may include multiple signal lines for transferring signals output from the pixels 11. The column signal line 13 of each column is connected to each of multiple column signal processing circuits 5. Each pixel 11 converts incident light into an electrical signal and outputs the converted electrical signal to the column signal processing circuit 5 via the column signal line 13. More specifically, each pixel 11 outputs a reset signal (an analog signal at a reset level) before transferring the signal charge generated by the photoelectric conversion unit, and a pixel signal based on the signal charge generated by the photoelectric conversion unit. The circuit configuration of the pixel 11 will be described later with reference to FIG. 2.

[0019] The vertical scanning circuit 2 receives control signals output from the timing control unit 8, generates control signals for driving the pixels 11, and supplies the control signals to the pixels 11 via control lines 12. The vertical scanning circuit 2 may include logic circuits such as a shift register and an address decoder. The vertical scanning circuit 2 sequentially scans the pixels 11 in the pixel array 1 row by row, and outputs pixel signals from each pixel 11 to each of the plurality of column signal processing circuits 5 via column signal lines 13, thereby acquiring one frame of an image.

[0020] The reference signal output circuit 3 outputs a reference signal (ramp signal) whose voltage changes over time to each of the plurality of column signal processing circuits 5.

[0021] The counter 4 counts the clock signals and outputs the count value to each of the plurality of column signal processing circuits 5.

[0022] Each of the plurality of column signal processing circuits 5 is arranged for each column signal line 13, and includes a comparator 51 and a memory 52. ​​When the first scanning circuit is configured to select pixels on a column-by-column basis, the column signal processing circuits can be row signal processing circuits provided corresponding to the rows of pixels.

[0023] The comparator 51 compares the voltage of the reference signal from the reference signal output circuit 3 with the voltage of the pixel signal from the pixel 11, and changes the level of its output signal when the magnitude relationship between these voltages is inverted. When the level of the output signal from the comparator 51 changes, the column signal processing circuit 5 writes a count value, which is calculated from the time when the voltage of the reference signal started to change to the time when the level of the output signal from the comparator 51 changed, into the memory 52. ​​This performs AD conversion, which converts an analog signal into a digital signal. The count value of the reset signal is also written into the memory 52 in the same manner as for the pixel signal. The reference signal output circuit 3, counter 4, and column signal processing circuit 5 constitute an AD conversion unit.

[0024] The memory 52 holds the digital signals (count values). The memory 52 includes a plurality of unit memories, and holds the count values ​​of the reset signals and pixel signals.

[0025] The horizontal scanning circuit 6 receives a control signal output from the timing control unit 8 and outputs the digital signal held in the memory 52. ​​The horizontal scanning circuit 6 may include logic circuits such as a shift register and an address decoder. The horizontal scanning circuit 6 sequentially scans each of the multiple memories 52 and sequentially outputs the count values ​​of the reset signals and pixel signals held in each of the memories 52 to the signal processing circuit 7 via a common signal line 53. Note that, in a configuration in which the column signal processing circuit 5 is modified into a row signal processing circuit provided corresponding to the rows of pixels, the horizontal scanning circuit 6, which is the second scanning circuit, can be a scanning circuit that scans the row signal processing circuit on a row-by-row basis.

[0026] The signal processing circuit 7 processes the digital signal. The signal processing circuit 7 subtracts the count value of the reset signal from the count value of the pixel signal, extracts only the signal corresponding to the amount of incident light, and outputs it to the outside of the imaging device 100.

[0027] The timing control unit 8 controls the operation and timing of each component. The timing control unit 8 generates control signals that control the operation and timing of the vertical scanning circuit 2, the reference signal output circuit 3, the counter 4, the plurality of column signal processing circuits 5, and the horizontal scanning circuit 6, and supplies the generated control signals to these components. The timing control unit 8 can be configured by various electronic components such as a CPU and a memory.

[0028] FIG. 2 is a circuit diagram of a pixel 11 according to this embodiment. The pixel 11 includes a photoelectric conversion element (first photoelectric conversion unit) PD1, a photoelectric conversion element (second photoelectric conversion unit) PD2, transfer transistors M1 and M2, a reset transistor M3, an amplification transistor M4, and a selection transistor M5. The photoelectric conversion element PD1 and the photoelectric conversion element PD2 are provided corresponding to one microlens ML. Light that has passed through a common microlens ML is incident on the photoelectric conversion element PD1 and the photoelectric conversion element PD2. Light that has passed through a partial region of the exit pupil is incident on the photoelectric conversion element PD1, and light that has passed through another partial region of the exit pupil is incident on the photoelectric conversion element PD2. This enables phase difference focus detection using a signal corresponding to the signal charge generated by the photoelectric conversion element PD1 and a signal corresponding to the signal charge generated by the photoelectric conversion element PD2.

[0029] In this embodiment, the description will be given assuming that electrons, among the electron-hole pairs generated in the photoelectric conversion elements PD1 and PD2 by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 11 may be configured as an N-type MOS transistor. When each transistor is configured as an N-type MOS transistor, a high-level control signal supplied from the vertical scanning circuit 2 turns on the controlled transistor. Furthermore, a low-level control signal supplied from the vertical scanning circuit 2 turns off the controlled transistor. However, the signal charges are not limited to electrons; holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is opposite to that described in this embodiment. Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor or the intended function. Some or all of the names of the source and drain used in this embodiment may be reversed.

[0030] The photoelectric conversion element PD1 may be a photodiode that accumulates signal charges corresponding to incident light. The anode of the photoelectric conversion element PD1 is connected to the ground node, and the cathode of the photoelectric conversion element PD1 is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M3 and the gate of the amplification transistor M4.

[0031] The photoelectric conversion element PD2 may be a photodiode that accumulates signal charge corresponding to incident light. The anode of the photoelectric conversion element PD2 is connected to the ground node, and the cathode of the photoelectric conversion element PD2 is connected to the source of the transfer transistor M2. The drain of the transfer transistor M2 is connected to the source of the reset transistor M3 and the gate of the amplification transistor M4. While this embodiment describes a configuration in which two photoelectric conversion elements are provided for one microlens ML, this configuration is not limited thereto, and three or more photoelectric conversion elements may be provided. For example, one microlens ML may be provided with four photoelectric conversion elements arranged in two rows and two columns. In this case, the focus detection signal corresponds to the signal charge of only some of the four photoelectric conversion elements, typically the signal charge of the photoelectric conversion elements in one row and two columns or two rows and one column. The imaging signal corresponds to the signal charge of all four photoelectric conversion elements.

[0032] The input node FD, to which the drains of the transfer transistors M1 and M2, the source of the reset transistor M3, and the gate of the amplifier transistor M4 are connected, is a so-called floating diffusion region. The floating diffusion region includes a capacitance component (floating diffusion capacitance) and functions as a charge storage region that stores signal charges. The floating diffusion capacitance may include PN junction capacitance, wiring capacitance, etc.

[0033] The drain of the reset transistor M3 and the drain of the amplification transistor M4 are connected to a power supply voltage node that supplies a voltage VDD. The source of the amplification transistor M4 is connected to the drain of the selection transistor M5. The source of the selection transistor M5 is connected to a column signal line 13. A current source 9 is connected to the column signal line 13. The current source 9 supplies a bias current to the amplification transistor M4 via the column signal line 13.

[0034] In the pixel 11 configured as described above, a control signal TX_1 is supplied to the gate of the transfer transistor M1 from the vertical scanning circuit 2. When the control signal TX_1 is at a high level, the transfer transistor M1 is turned on, and when the control signal TX_1 is at a low level, the transfer transistor M1 is turned off.

[0035] A control signal TX_2 is supplied to the gate of the transfer transistor M2 from the vertical scanning circuit 2. When the control signal TX_2 is at a high level, the transfer transistor M2 is turned on, and when the control signal TX_2 is at a low level, the transfer transistor M2 is turned off.

[0036] A control signal RES is supplied to the gate of the reset transistor M3 from the vertical scanning circuit 2. When the control signal RES is at a high level, the reset transistor M3 is turned on, and when the control signal RES is at a low level, the reset transistor M3 is turned off.

[0037] A control signal SEL is supplied to the gate of the selection transistor M5 from the vertical scanning circuit 2. When the control signal SEL is at a high level, the selection transistor M5 is turned on, and when the control signal SEL is at a low level, the selection transistor M5 is turned off.

[0038] The photoelectric conversion element PD1 converts incident light into a signal charge in an amount corresponding to the amount of light (photoelectric conversion). When the transfer transistor M1 is turned on, it transfers the signal charge held by the photoelectric conversion element PD1 to the input node FD. The signal charge transferred from the photoelectric conversion element PD1 is held in the capacitance (floating diffusion capacitance) of the input node FD.

[0039] The photoelectric conversion element PD2 converts incident light into a signal charge in an amount corresponding to the amount of light (photoelectric conversion). When the transfer transistor M2 is turned on, it transfers the signal charge held by the photoelectric conversion element PD2 to the input node FD. The signal charge transferred from the photoelectric conversion element PD2 is held in the capacitance (floating diffusion capacitance) of the input node FD.

[0040] When signal charge is transferred only from photoelectric conversion element PD1 of photoelectric conversion elements PD1 and PD2, input node FD has a potential corresponding to the amount of signal charge transferred from photoelectric conversion element PD1 due to charge-voltage conversion by the floating diffusion capacitance. In this case, the pixel signal corresponding to the potential of input node FD becomes a pixel signal for focus detection used when detecting focus.

[0041] When signal charges are transferred from both photoelectric conversion elements PD1 and PD2, the input node FD has a potential corresponding to the amount of signal charges transferred from both photoelectric conversion elements PD1 and PD2 due to charge-voltage conversion by the floating diffusion capacitance. In this case, the pixel signal corresponding to the potential of the input node FD becomes an imaging pixel signal used when capturing an image.

[0042] The reset transistor M3 supplies a voltage (voltage VDD) for resetting the input node FD to the input node FD. When the reset transistor M3 is turned on, it resets the input node FD to a voltage corresponding to the voltage VDD.

[0043] The selection transistor M5 is switched on and off to selectively connect the pixels 11 in the row to be read out of the pixels 11 that make up the pixel array 1 to the column signal line 13. When the selection transistor M5 is turned on, it connects the amplification transistor M4 of the pixel 11 in the row to be read out to the column signal line 13.

[0044] The amplifier transistor M4 has a drain supplied with a voltage VDD and a source supplied with a bias current from a current source 9 via a selection transistor M5. The amplifier transistor M4 forms an amplifier circuit (source follower circuit) with its gate serving as an input node FD. The amplifier transistor M4 outputs a signal based on the signal charge at the input node FD to a column signal line 13 via the selection transistor M5. In this sense, the amplifier transistor M4 and the selection transistor M5 form an output section that outputs a pixel signal according to the amount of signal charge held at the input node FD.

[0045] As described above, pixel 11 can output a reset signal corresponding to the signal level at which the potential of input node FD is reset by reset transistor M3. Also, pixel 11 can output a pixel signal for focus detection based on the signal charge generated by photoelectric conversion performed in photoelectric conversion element PD1. Also, pixel 11 can output a pixel signal for imaging based on the signal charge generated by photoelectric conversion performed in photoelectric conversion elements PD1 and PD2.

[0046] By subtracting the pixel signal for focus detection from the pixel signal for imaging, it is possible to obtain a pixel signal for focus detection based on the signal charge generated by the photoelectric conversion performed by the photoelectric conversion element PD2. Then, the focus can be obtained based on the phase difference between the pixel signal for focus detection from the photoelectric conversion element PD1 and the pixel signal for focus detection from the photoelectric conversion element PD2.

[0047] The mode in which a reset signal and a pixel signal for imaging are output is called an imaging mode (first mode). The mode in which a reset signal, a pixel signal for focus detection, and a pixel signal for imaging are output is called an AF imaging mode (second mode). The vertical scanning circuit 2 intermittently scans in the AF imaging mode while scanning in the imaging mode.

[0048] Next, before describing the operation of the imaging device 100 according to this embodiment, the operation of an imaging device according to a comparative example will be described.

[0049] [First Comparative Example] Fig. 3 is a timing chart of the imaging device according to Comparative Example 1. Fig. 3 illustrates an example of scanning the Nth row and the (N+1)th row in the AF imaging mode.

[0050] At time t1, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the row to be read (the Nth row). The reset transistor M3 turns on, and the input node FD is reset to a voltage corresponding to the voltage VDD. This causes the pixels 11 in the Nth row to output pixel signals (reset signals) at a reset level. Although not shown in FIG. 3, before time t1, the vertical scanning circuit 2 changes the control signal SEL from low to high for the pixels 11 in the row to be read (the Nth row). The selection transistor M5 turns on, and the pixels 11 in the Nth row are connected to the column signal line 13. Also, before time t1, the vertical scanning circuit 2 starts transferring the reset signal N_AF for the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0051] At time t2, the horizontal scanning circuit 6 completes the operation of transferring the reset signal N_AF for the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0052] Between times t3 and t4, the column signal processing circuit 5 performs AD conversion on the reset signals N_AF output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0053] At time t5, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S1 for focus detection in the (N-1)th row from the memory 52 to the signal processing circuit .

[0054] At time t6, the vertical scanning circuit 2 changes the control signal TX_1 from low to high for the pixels 11 in the Nth row. The transfer transistor M1 is turned on, and the signal charge held in the photoelectric conversion element PD1 is transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S1 for focus detection.

[0055] At time t7, the horizontal scanning circuit 6 finishes the operation of transferring the pixel signals S1 for focus detection in the (N-1)th row from the memory 52 to the signal processing circuit .

[0056] Between times t8 and t9, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0057] At time t10, the horizontal scanning circuit 6 starts the operation of transferring the imaging pixel signals S2 of the (N-1)th row from the memory 52 to the signal processing circuit .

[0058] At time t11, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the Nth row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S2 for imaging.

[0059] At time t12, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S2 of the (N-1)th row from the memory 52 to the signal processing circuit .

[0060] Between times t13 and t14, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0061] At time t15, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+1)th row to be read next, causing the pixels 11 in the (N+1)th row to output a reset signal N_AF.

[0062] At time t15, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit .

[0063] At time t16, the horizontal scanning circuit 6 finishes the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signal N_AF for the Nth row from time t15 to t16.

[0064] Between times t17 and t18, the column signal processing circuit 5 AD converts the reset signals N_AF output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0065] At time t19, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit .

[0066] At time t20, the vertical scanning circuit 2 changes the control signal TX_1 from low level to high level for the pixels 11 in the (N+1)th row, causing the pixels 11 in the (N+1)th row to output pixel signals S1 for focus detection.

[0067] At time t21, the horizontal scanning circuit 6 finishes the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the pixel signals S1 for focus detection of the Nth row from time t19 to t21.

[0068] Between times t22 and t23, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0069] At time t24, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S2 for imaging of the Nth row from the memory 52 to the signal processing circuit .

[0070] At time t25, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low level to high level for the pixels 11 in the (N+1)th row, causing the pixels 11 in the (N+1)th row to output pixel signals S2 for imaging.

[0071] At time t26, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S2 of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the imaging pixel signals S2 of the Nth row from time t24 to t26.

[0072] Between times t27 and t , the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0073] At time t29, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+2)th row to be read next, causing the pixels 11 in the (N+2)th row to output the reset signal N_AF.

[0074] The above-mentioned period from time t15 to t29 is a period during which signals output from the pixels 11 in the Nth row are transferred from the memory 52 to the signal processing circuit 7. During the period from time t15 to t29, the horizontal scanning circuit 6 transfers the reset signal N_AF for the Nth row during the transfer period (times t15 to t16), as described above. The transfer period (times t15 to t16) is a period different from the AD conversion period, and is located between the AD conversion period for the Nth row (times t13 to t14) and the AD conversion period for the (N+1)th row (times t17 to t18).

[0075] Furthermore, the horizontal scanning circuit 6 transfers the focus detection pixel signals S1 of the Nth row during a transfer period (times t19 to t21). The transfer period (times t19 to t21) is a period different from the AD conversion period, and is positioned between the AD conversion period of the (N+1)th row (times t17 to t18) and the AD conversion period of the (N+1)th row (times t22 to t23).

[0076] Furthermore, the horizontal scanning circuit 6 transfers the imaging pixel signals S2 of the Nth row during a transfer period (times t24 to t26). The transfer period (times t24 to t26) is a period different from the AD conversion period, and is positioned between the AD conversion period of the (N+1)th row (times t22 to t23) and the AD conversion period of the (N+1)th row (times t27 to t28).

[0077] In this way, the horizontal scanning circuit 6 transfers each signal (reset signal N_AF, focus detection pixel signal S1, and imaging pixel signal S2) output from the pixels 11 in the Nth row from the memory 52 to the signal processing circuit 7 during a transfer period different from the AD conversion period. Before AD conversion of each signal, a signal transfer operation, which is a series of transfer operations for sequentially outputting signals from each memory 52, is performed once. That is, the number of signal transfer operations is the same between AD conversion periods. Here, power supply fluctuations that occur when performing the signal transfer operation can cause noise during AD conversion. In such cases, since the number of signal transfer operations can be made the same, the influence of noise on each signal can be made equal. This allows noise in the focus detection pixel signal S1 and the imaging pixel signal S2 to be accurately removed using the reset signal N_AF. Therefore, the SN operation for removing noise can obtain signals in which the influence of noise caused by power supply fluctuations is effectively reduced.

[0078] [Second Comparative Example] Fig. 4 is a timing diagram of an imaging device according to a second comparative example. Fig. 4 illustrates an example of scanning the Nth and (N+1)th rows in AF imaging mode. In this example, the reset signal N_AF is transferred in two separate transfers. Note that the same content as that explained in Fig. 3 will be omitted or simplified as appropriate.

[0079] At time t1a, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the row to be read (the Nth row). The reset transistor M3 turns on, and the input node FD is reset to a voltage corresponding to the voltage VDD. This causes the pixels 11 in the Nth row to output a reset signal.

[0080] At time t2a, the horizontal scanning circuit 6 starts the operation of transferring the remaining reset signal N_AFb of the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0081] At time t3a, the horizontal scanning circuit 6 completes the operation of transferring the remaining reset signal N_AFb of the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0082] Between times t4a and t5a, the column signal processing circuit 5 performs AD conversion on the reset signals N_AF output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0083] At time t6a, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S1 for focus detection in the (N-1)th row from the memory 52 to the signal processing circuit .

[0084] At time t7a, the vertical scanning circuit 2 changes the control signal TX_1 from low to high for the pixels 11 in the Nth row. The transfer transistor M1 is turned on, and the signal charge held in the photoelectric conversion element PD1 is transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S1 for focus detection.

[0085] At time t8a, the horizontal scanning circuit 6 finishes the operation of transferring the pixel signals S1 for focus detection in the (N-1)th row from the memory 52 to the signal processing circuit .

[0086] Between times t9a and t10a, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0087] At time t11a, the horizontal scanning circuit 6 starts the operation of transferring the imaging pixel signals S2 of the (N-1)th row from the memory 52 to the signal processing circuit .

[0088] At time t12a, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S2 of the (N-1)th row from the memory 52 to the signal processing circuit .

[0089] At time t13a, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the Nth row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S2 for imaging.

[0090] At time t13a, the horizontal scanning circuit 6 starts the operation of transferring a part of the reset signal N_AFa of the Nth row from the memory 52 to the signal processing circuit .

[0091] At time t14a, the horizontal scanning circuit 6 finishes the operation of transferring the reset signals N_AFa of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signals N_AFa of the Nth row from time t13a to t14a.

[0092] Between times t15a and t16a, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0093] At time t17a, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+1)th row to be read next, causing the pixels 11 in the (N+1)th row to output a reset signal N_AF.

[0094] At time t18a, the horizontal scanning circuit 6 starts the operation of transferring the remaining reset signal N_AFb for the Nth row from the memory 52 to the signal processing circuit .

[0095] At time t19a, the horizontal scanning circuit 6 finishes the operation of transferring the remaining reset signals N_AFb for the Nth row from the memory 52 to the signal processing circuit 7. In this manner, the horizontal scanning circuit 6 transfers the remaining reset signals N_AFb for the Nth row from time t18a to t19a.

[0096] Between times t20a and t21a, the column signal processing circuit 5 AD converts the reset signals N_AF output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0097] At time t22a, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit .

[0098] At time t23a, the vertical scanning circuit 2 changes the control signal TX_1 from low level to high level for the pixels 11 in the (N+1)th row, causing the pixels 11 in the (N+1)th row to output pixel signals S1 for focus detection.

[0099] At time t24a, the horizontal scanning circuit 6 finishes the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the pixel signals S1 for focus detection of the Nth row from time t22a to t24a.

[0100] Between times t25a and t26a, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0101] At time t27a, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S2 for imaging of the Nth row from the memory 52 to the signal processing circuit .

[0102] At time t28a, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S2 of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the imaging pixel signals S2 of the Nth row from time t27a to t28a.

[0103] At time t29a, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the (N+1)th row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the (N+1)th row to output pixel signals S2 for imaging.

[0104] At time t29a, the horizontal scanning circuit 6 starts the operation of transferring a part of the reset signal N_AFa of the (N+1)th row from the memory 52 to the signal processing circuit .

[0105] At time t30a, the horizontal scanning circuit 6 completes the operation of transferring the reset signals N_AFa of the (N+1)th row from the memory 52 to the signal processing circuit 7.

[0106] Between times t31a and t32a, the column signal processing circuit 5 AD converts the imaging pixel signals S2 output from the pixels 11 in the (N+1)th row and stores the converted signals in the memory 52.

[0107] At time t33a, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+2)th row to be read next, causing the pixels 11 in the (N+2)th row to output a reset signal N_AF.

[0108] The above-mentioned period from time t13a to t29a is a period during which signals output from the pixels 11 of the Nth row are transferred from the memory 52 to the signal processing circuit 7. During the period from time t13a to t29a, the horizontal scanning circuit 6 transfers a portion of the reset signals N_AFa of the Nth row during the transfer period (times t13a to t14a), as described above. The transfer period (times t13a to t14a) is a period different from the AD conversion period, and is located between the AD conversion period for the Nth row (times t9a to t10a) and the AD conversion period for the Nth row (times t15a to t16a).

[0109] Furthermore, the horizontal scanning circuit 6 transfers the remaining reset signal N_AFb for the Nth row during a transfer period (times t18a to t19a). The transfer period (times t18a to t19a) is a period different from the AD conversion period, and is positioned between the AD conversion period for the Nth row (times t15a to t16a) and the AD conversion period for the (N+1)th row (times t20a to t21a).

[0110] Furthermore, the horizontal scanning circuit 6 transfers the focus detection pixel signals S1 of the Nth row during a transfer period (times t22a to t24a). The transfer period (times t22a to t24a) is a period different from the AD conversion period and is positioned between the AD conversion period of the (N+1)th row (times t20a to t21a) and the AD conversion period of the (N+1)th row (times t25a to t26a).

[0111] Furthermore, the horizontal scanning circuit 6 transfers the imaging pixel signals S2 of the Nth row during a transfer period (times t27a to t28a). The transfer period (times t27a to t28a) is a period different from the AD conversion period and is positioned between the AD conversion period of the (N+1)th row (times t25a to t26a) and the AD conversion period of the (N+1)th row (times t31a to t32a).

[0112] In this way, the horizontal scanning circuit 6 transfers each signal output from the pixels 11 in the Nth row (two-split reset signals N_AFa and N_AFb, focus detection pixel signal S1, and imaging pixel signal S2) from the memory 52 to the signal processing circuit 7 during a transfer period that is different from the AD conversion period. A signal transfer operation is performed at least once before each signal is AD converted. Therefore, noise due to power supply fluctuations during the signal transfer operation affects each AD conversion process in the same way. This allows noise in the focus detection pixel signal S1 and the imaging pixel signal S2 to be accurately removed using the reset signal N_AF.

[0113] [Third Comparative Example] Fig. 5 is a timing diagram of an imaging device according to a third comparative example. Fig. 5 illustrates an example of scanning the Nth and (N+1)th rows in AF imaging mode. In this example, the pixel signal S1 for focus detection and the pixel signal S2 for imaging are each transferred twice. Note that the same content as that explained in Fig. 3 will be omitted or simplified as appropriate.

[0114] At time t1b, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the row to be read (the Nth row). The reset transistor M3 turns on, and the input node FD is reset to a voltage corresponding to the voltage VDD. This causes the pixels 11 in the Nth row to output a reset signal.

[0115] At time t2b, the horizontal scanning circuit 6 starts an operation of transferring some of the focus detection pixel signals S1a of the (N−1)th row from the memory 52 to the signal processing circuit .

[0116] At time t3b, the horizontal scanning circuit 6 finishes the operation of transferring some of the focus detection pixel signals S1a of the (N-1)th row from the memory 52 to the signal processing circuit .

[0117] Between times t4b and t5b, the column signal processing circuit 5 performs AD conversion on the reset signals N_AF output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0118] At time t6b, the horizontal scanning circuit 6 starts the operation of transferring the remaining focus detection pixel signals S1b of the (N-1)th row from the memory 52 to the signal processing circuit .

[0119] At time t7b, the horizontal scanning circuit 6 finishes the operation of transferring the remaining focus detection pixel signals S1b of the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0120] At time t8b, the vertical scanning circuit 2 changes the control signal TX_1 from low to high for the pixels 11 in the Nth row. The transfer transistor M1 is turned on, and the signal charge held in the photoelectric conversion element PD1 is transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S1 for focus detection.

[0121] At time t8b, the horizontal scanning circuit 6 starts the operation of transferring some of the imaging pixel signals S2a of the (N-1)th row from the memory 52 to the signal processing circuit .

[0122] At time t9b, the horizontal scanning circuit 6 finishes the operation of transferring some of the imaging pixel signals S2a of the (N-1)th row from the memory 52 to the signal processing circuit .

[0123] Between times t10b and t11b, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0124] At time t12b, the horizontal scanning circuit 6 starts the operation of transferring the remaining imaging pixel signals S2b of the (N-1)th row from the memory 52 to the signal processing circuit .

[0125] At time t13b, the horizontal scanning circuit 6 finishes the operation of transferring the remaining imaging pixel signals S2b of the (N-1)th row from the memory 52 to the signal processing circuit .

[0126] At time t14b, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit 7.

[0127] At time t15b, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the Nth row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S2 for imaging.

[0128] At time t16b, the horizontal scanning circuit 6 finishes the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signal N_AF for the Nth row from time t14b to t16b.

[0129] Between times t17b and t18b, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0130] At time t19b, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+1)th row to be read next, causing the pixels 11 in the (N+1)th row to output the reset signal N_AF.

[0131] At time t20b, the horizontal scanning circuit 6 starts an operation of transferring some of the pixel signals S1a for focus detection in the Nth row from the memory 52 to the signal processing circuit .

[0132] At time t21b, the horizontal scanning circuit 6 finishes the operation of transferring some of the pixel signals S1a for focus detection in the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers some of the pixel signals S1a for focus detection in the Nth row from time t20b to t21b.

[0133] Between times t22b and t23b, the column signal processing circuit 5 performs AD conversion on the reset signals N_AF output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0134] At time t24b, the horizontal scanning circuit 6 starts the operation of transferring the remaining focus detection pixel signals S1b of the Nth row from the memory 52 to the signal processing circuit .

[0135] At time t25b, the horizontal scanning circuit 6 finishes the operation of transferring the remaining pixel signals S1b for focus detection in the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the remaining pixel signals S1b for focus detection in the Nth row from time t24b to t25b.

[0136] At time t26b, the vertical scanning circuit 2 changes the control signal TX_1 from low to high for the pixels 11 in the Nth row. The transfer transistor M1 is turned on, and the signal charge held in the photoelectric conversion element PD1 is transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S1 for focus detection.

[0137] At time t26b, the horizontal scanning circuit 6 starts the operation of transferring some of the imaging pixel signals S2a of the Nth row from the memory 52 to the signal processing circuit .

[0138] At time t27b, the horizontal scanning circuit 6 finishes the operation of transferring some of the imaging pixel signals S2a of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers some of the imaging pixel signals S2a of the Nth row from time t26b to t27b.

[0139] Between times t28b and t29b, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0140] At time t30b, the horizontal scanning circuit 6 starts the operation of transferring the remaining imaging pixel signals S2b of the Nth row from the memory 52 to the signal processing circuit .

[0141] At time t31b, the horizontal scanning circuit 6 finishes the operation of transferring the remaining imaging pixel signals S2b of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the remaining imaging pixel signals S2b of the Nth row from time t30b to t31b.

[0142] At time t32b, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N_AF of the (N+1)th row from the memory 52 to the signal processing circuit .

[0143] At time t33b, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the (N+1)th row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S2 for imaging.

[0144] At time t34b, the horizontal scanning circuit 6 finishes the operation of transferring the reset signal N_AF for the (N+1)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signal N_AF for the (N+1)th row from time t32b to t34b.

[0145] Between times t35b and t36b, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0146] At time t37b, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+2)th row to be read next, causing the pixels 11 in the (N+2)th row to output the reset signal N_AF.

[0147] The above-mentioned period from time t14b to t32b is a period during which signals output from the pixels 11 in the Nth row are transferred from the memory 52 to the signal processing circuit 7. During the period from time t14b to t32b, the horizontal scanning circuit 6 transfers the reset signal N_AF for the Nth row during the transfer period (t14b to t16b), as described above. The transfer period (t14b to t16b) is a period different from the AD conversion period, and is located between the AD conversion period for the Nth row (times t10b to t11b) and the AD conversion period for the Nth row (times t17b to t18b).

[0148] Furthermore, the horizontal scanning circuit 6 transfers some of the focus detection pixel signals S1a of the Nth row during a transfer period (t20b to t21b). The transfer period (t20b to t21b) is a period different from the AD conversion period, and is positioned between the AD conversion period of the Nth row (times t17b to t18b) and the AD conversion period of the (N+1)th row (times t22b to t23b).

[0149] Furthermore, the horizontal scanning circuit 6 transfers the remaining focus detection pixel signals S1b of the Nth row during a transfer period (t24b to t25b). The transfer period (t24b to t25b) is a period different from the AD conversion period, and is positioned between the AD conversion period for the (N+1)th row (times t22b to t23b) and the AD conversion period for the (N+1)th row (times t28b to t29b).

[0150] Furthermore, the horizontal scanning circuit 6 transfers some of the imaging pixel signals S2a of the Nth row during a transfer period (t26b to t27b). The transfer period (t26b to t27b) is a period different from the AD conversion period, and is positioned between the AD conversion period for the (N+1)th row (times t22b to t23b) and the AD conversion period for the (N+1)th row (times t28b to t29b).

[0151] Furthermore, the horizontal scanning circuit 6 transfers the remaining imaging pixel signals S2b of the Nth row during a transfer period (t30b to t31b). The transfer period (t30b to t31b) is a period different from the AD conversion period, and is positioned between the AD conversion period for the (N+1)th row (times t28b to t29b) and the AD conversion period for the (N+1)th row (times t35b to t36b).

[0152] In this way, the horizontal scanning circuit 6 transfers each signal output from the pixels 11 in the Nth row (reset signal N_AF, two-division focus detection pixel signals S1a and S1b, and two-division imaging pixel signals S2a and S2b) during a transfer period that is different from the AD conversion period. Before each signal is AD converted, a signal transfer operation is performed at least once. Therefore, noise due to power supply fluctuations during the signal transfer operation affects each AD conversion process in the same way. This allows noise in the focus detection pixel signal S1 and the imaging pixel signal S2 to be accurately removed using the reset signal N_AF.

[0153] [Fourth Comparative Example] Fig. 6 is a timing diagram of an imaging device according to a fourth comparative example. Fig. 6 illustrates an example in which the Nth row is scanned in AF imaging mode, and the pixels 11 in the (N+1)th and (N+2)th rows are scanned in imaging mode. That is, an example of transition from AF imaging mode to imaging mode is illustrated. Note that the same content as that explained in Fig. 3 will be omitted or simplified as appropriate.

[0154] At time t1c, the vertical scanning circuit 2 scans the pixels 11 in the AF imaging mode. The vertical scanning circuit 2 controls the control signal RES to change from low to high for the pixels 11 in the row to be read (the Nth row). The reset transistor M3 turns on, and the input node FD is reset to a voltage corresponding to the voltage VDD. As a result, the reset signal N_AF is output from the pixels 11 in the Nth row.

[0155] At time t1c, the horizontal scanning circuit 6 starts the operation of transferring the imaging pixel signals S of the (N-2)th row from the memory 52 to the signal processing circuit .

[0156] At time t2c, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S of the (N-2)th row from the memory 52 to the signal processing circuit .

[0157] Between times t3c and t4c, the column signal processing circuit 5 performs AD conversion on the reset signals N_AF output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0158] At time t5c, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N for the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0159] At time t6c, the vertical scanning circuit 2 changes the control signal TX_1 from low to high for the pixels 11 in the Nth row. The transfer transistor M1 is turned on, and the signal charge held in the photoelectric conversion element PD1 is transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S1 for focus detection.

[0160] At time t7c, the horizontal scanning circuit 6 completes the operation of transferring the reset signal N for the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0161] Between times t8c and t9c, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0162] At time t10c, the horizontal scanning circuit 6 starts the operation of transferring the imaging pixel signals S of the (N-1)th row from the memory 52 to the signal processing circuit .

[0163] At time t11c, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S of the (N-1)th row from the memory 52 to the signal processing circuit .

[0164] At time t12c, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit .

[0165] At time t13c, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the Nth row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S2 for imaging.

[0166] At time t14c, the horizontal scanning circuit 6 finishes the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signal N_AF for the Nth row from time t12c to t14c.

[0167] Between times t15c and t16c, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0168] At time t17c, the vertical scanning circuit 2 transitions from the AF imaging mode to the imaging mode. The vertical scanning circuit 2 controls the control signal RES for the pixels 11 in the (N+1)th row to be read next from low level to high level. This causes the reset signal N to be output from the pixels 11 in the (N+1)th row.

[0169] At time t18c, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit .

[0170] At time t19c, the horizontal scanning circuit 6 finishes the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the pixel signals S1 for focus detection of the Nth row from time t18c to t19c.

[0171] Between times t20c and t21c, the column signal processing circuit 5 AD converts the reset signals N output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0172] At time t22c, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S2 for imaging of the Nth row from the memory 52 to the signal processing circuit .

[0173] At time t23c, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low level to high level for the pixels 11 in the (N+1)th row, causing the pixels 11 in the (N+1)th row to output pixel signals S for imaging.

[0174] At time t24c, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S2 of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the imaging pixel signals S2 of the Nth row from time t22c to t24c.

[0175] Between times t25c and t26c, the column signal processing circuit 5 AD converts the imaging pixel signals S output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0176] At time t27c, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+2)th row to be read next, causing the pixels 11 in the (N+2)th row to output the reset signal N.

[0177] Between times t28c and t29c, the column signal processing circuit 5 AD converts the reset signals N output from the pixels 11 in the (N+2)th row, and stores the converted signals in the memory 52.

[0178] At time t30c, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N of the (N+1)th row from the memory 52 to the signal processing circuit .

[0179] At time t31c, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low level to high level for the pixels 11 in the (N+2)th row, causing the pixels 11 in the (N+2)th row to output pixel signals S for imaging.

[0180] At time t32c, the horizontal scanning circuit 6 finishes the operation of transferring the reset signal N for the (N+2)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signal N for the (N+1)th row from time t30c to t32c.

[0181] Between times t33c and t34c, the column signal processing circuit 5 AD converts the pixel signals S for imaging output from the pixels 11 in the (N+2)th row, and stores the converted signals in the memory 52.

[0182] At time t35c, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+3)th row to be read next, causing the pixels 11 in the (N+3)th row to output the reset signal N.

[0183] The above-mentioned period from time t12c to t30c is a period during which signals output from the pixels 11 in the Nth row are transferred from the memory 52 to the signal processing circuit 7. During the period from time t12c to t30c, the horizontal scanning circuit 6 transfers the reset signal N_AF for the Nth row during the transfer period (time t12c to t14c), as described above. The transfer period (time t12c to t14c) is a period different from the AD conversion period, and is located between the AD conversion period for the Nth row (time t8 to t9) and the AD conversion period for the Nth row (time t15c to t16c).

[0184] Furthermore, the horizontal scanning circuit 6 transfers the focus detection pixel signals S1 of the Nth row during a transfer period (times t18c to t19c). The transfer period (times t18c to t19c) is a period different from the AD conversion period, and is positioned between the AD conversion period of the Nth row (times t15c to t16c) and the AD conversion period of the (N+1)th row (times t20 to t21).

[0185] Furthermore, the horizontal scanning circuit 6 transfers the imaging pixel signals S2 of the Nth row during a transfer period (time t22c to t24c). The transfer period (time t22c to t24c) is a period different from the AD conversion period, and is positioned between the AD conversion period of the (N+1)th row (time t20c to t21c) and the AD conversion period of the (N+1)th row (time t25c to t26c).

[0186] Furthermore, the horizontal scanning circuit 6 transfers the reset signal N for the (N+1)th row during a transfer period (times t30c to t32c). The transfer period (times t30c to t32c) is a period different from the AD conversion period, and is positioned between the AD conversion period for the (N+2)th row (times t28c to t29c) and the AD conversion period for the (N+2)th row (times t33c to t34c).

[0187] Incidentally, when transitioning from AF imaging mode to imaging mode, no signal transfer operation is performed between the AD conversion period of the (N+1)th row (times t25c to t26c) and the AD conversion period of the (N+2)th row (times t28c to t29c). This is because the number of signals (three) when scanning in AF imaging mode is different from the number of signals (two) when scanning in imaging mode, so when transitioning from AF imaging mode to imaging mode, no signal transfer operation is performed during a specific AD conversion period. In this case, the impact of noise due to power supply fluctuations when performing the signal transfer operation may differ depending on the AD conversion process.

[0188] Here, no signal transfer operation is performed between the AD conversion period of the (N+1)th row (times t25c to t26c) and the AD conversion period of the (N+2)th row (times t28c to t29c). Therefore, the AD conversion process performed during the AD conversion period of the (N+2)th row (times t28c to t29c) is less susceptible to noise caused by power supply fluctuations during the signal transfer operation. Therefore, the imaging device according to this comparative example has a problem in that, when noise in the imaging pixel signal S is removed using the reset signal N that is AD converted during the AD conversion period of the (N+2)th row (times t28c to t29c), the noise cannot be removed accurately. A method for solving this problem will be described using FIGS. 7 and 8.

[0189] Fig. 7 is a timing chart of the imaging device 100 according to this embodiment. In Fig. 7, an example of transition from the AF imaging mode to the imaging mode will be described, similar to Fig. 6. Note that the same content as that described in Fig. 6 will be omitted or simplified as appropriate. The process from time t1d to time t27d in FIG. 7 is the same as the process from time t1c to time t27c in FIG.

[0190] At time t28d, the horizontal scanning circuit 6 starts a dummy transfer operation (additional signal transfer operation) to transfer the dummy signal Dm from the memory 52 to the signal processing circuit 7. The dummy transfer operation is a pseudo signal transfer operation, and is, for example, a series of transfer operations to sequentially output dummy signals held in the memory 52. ​​The dummy signal Dm is a signal different from the pixel signal from the pixel 11, and may be, for example, a signal written to the memory 52 by a dummy signal generation unit (not shown). The dummy transfer operation does not have to read out the signal held in the memory 52, and may simply be an operation to sequentially transfer signals in accordance with the scanning of the horizontal scanning circuit 6.

[0191] The reason for performing the dummy transfer operation is that, as described in Fig. 6, a signal transfer operation for transferring an actual signal to the signal processing circuit 7 is not performed during a specific AD conversion period due to a transition from the AF imaging mode to the imaging mode. By performing the dummy transfer operation during the specific AD conversion period, at least one signal transfer operation is performed before AD conversion processing is performed, even when a transition is made from the AF imaging mode to the imaging mode.

[0192] At time t29d, the horizontal scanning circuit 6 ends the dummy transfer operation of transferring the dummy signal Dm from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the dummy signal Dm from time t28d to time t29d. The process from time t30d to time t37d is the same as the process from time t28c to time t35c in FIG.

[0193] As described above, the horizontal scanning circuit 6 transfers the dummy signal Dm during the transfer period (times t28d to t29d). The transfer period (times t28d to t29d) is a period different from the AD conversion period and is positioned between the AD conversion period for the (N+1)th row (times t25d to t26d) and the AD conversion period for the (N+2)th row (times t30d to t31d).

[0194] In this way, by transferring the dummy signal Dm, the number of times the signal from the pixel 11 scanned in the AF imaging mode is transferred becomes four, and the number of times the signal from the pixel 11 scanned in the imaging mode is transferred becomes two. In this way, the number of times the signal from the pixel 11 scanned in the AF imaging mode is transferred becomes an integer multiple of two or more of the number of times the signal from the pixel 11 scanned in the imaging mode is transferred.

[0195] In the image pickup device 100 according to this embodiment, when transitioning from the AF image pickup mode to the image pickup mode, a dummy transfer operation is performed in the image pickup mode so that the number of first signal transfer operations is the same as the number of second signal transfer operations. Here, the number of first signal transfer operations is the number of signal transfer operations between an AD conversion period (times t30d to t31d) and an AD conversion period (times t25d to t26d) immediately preceding the AD conversion period. The number of second signal transfer operations is the number of signal transfer operations between an AD conversion period (times t30d to t31d) and an AD conversion period (times t35d to t36d) following the AD conversion period.

[0196] This allows the imaging device 100 to perform the same number of signal transfer operations between AD conversion periods in imaging mode. Therefore, noise caused by power supply fluctuations during signal transfer operations affects each AD conversion process in the same way. This allows noise in the imaging pixel signal S2 to be accurately removed using the reset signal N_AF.

[0197] Furthermore, in the imaging mode, the period from the end of the first signal transfer operation to the start of the AD conversion period (time t30d to t31d) can be the same as the period from the end of the second signal transfer operation to the start of the next AD conversion period (time t35d to t36d). This makes it possible to more uniformly distribute the effects of noise on each AD conversion process, thereby enabling noise to be removed with even greater precision.

[0198] [Second embodiment] Fig. 8 is a timing diagram of the imaging device 100 according to this embodiment. Fig. 8 illustrates an example of transitioning from the AF imaging mode to the imaging mode, similar to Fig. 6. In this example, the reset signal N_AF is transferred in two parts.

[0199] At time t1e, the vertical scanning circuit 2 scans the pixels 11 in the AF imaging mode. The vertical scanning circuit 2 controls the control signal RES to change from low to high for the pixels 11 in the row to be read (the Nth row). The reset transistor M3 is turned on, and the input node FD is reset to a voltage corresponding to the voltage VDD. This causes the pixels 11 in the Nth row to output a reset signal.

[0200] At time t2e, the horizontal scanning circuit 6 starts the operation of transferring a part of the reset signals Na of the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0201] At time t3e, the horizontal scanning circuit 6 finishes the operation of transferring the reset signals Na for the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0202] Between times t4e and t5e, the column signal processing circuit 5 performs AD conversion on the reset signals N_AF output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0203] At time t6e, the horizontal scanning circuit 6 starts the operation of transferring the remaining reset signals Nb of the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0204] At time t7e, the horizontal scanning circuit 6 completes the operation of transferring the remaining reset signals Nb of the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0205] At time t8e, the horizontal scanning circuit 6 starts the operation of transferring the imaging pixel signals S of the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0206] At time t9e, the vertical scanning circuit 2 changes the control signal TX_1 from low to high for the pixels 11 in the Nth row. The transfer transistor M1 is turned on, and the signal charge held in the photoelectric conversion element PD1 is transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S1 for focus detection.

[0207] At time t10e, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S of the (N-1)th row from the memory 52 to the signal processing circuit .

[0208] Between times t11e and t12e, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0209] At time t13e, the horizontal scanning circuit 6 starts the operation of transferring a part of the reset signals N_AFa of the Nth row from the memory 52 to the signal processing circuit .

[0210] At time t14e, the horizontal scanning circuit 6 finishes the operation of transferring the reset signals N_AFa of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signals N_AFa of the Nth row from time t13e to t14e.

[0211] At time t15e, the horizontal scanning circuit 6 starts the operation of transferring the remaining reset signal N_AFb for the Nth row from the memory 52 to the signal processing circuit .

[0212] At time t16e, the horizontal scanning circuit 6 finishes the operation of transferring the remaining reset signals N_AFb for the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the remaining reset signals N_AFb for the Nth row from time t15e to t16e.

[0213] At time t17e, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit .

[0214] At time t18e, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the Nth row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S2 for imaging.

[0215] At time t19e, the horizontal scanning circuit 6 finishes the operation of transferring the pixel signals S1 for focus detection of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the pixel signals S1 for focus detection of the Nth row from time t17e to t19e.

[0216] Between times t20e and t21e, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0217] At time t22e, the vertical scanning circuit 2 transitions from the AF imaging mode to the imaging mode. The vertical scanning circuit 2 controls the control signal RES for the pixels 11 in the (N+1)th row to be read next from low level to high level. This causes the reset signal N to be output from the pixels 11 in the (N+1)th row.

[0218] At time t23e, the horizontal scanning circuit 6 starts a dummy transfer operation to transfer the dummy signal Dm from the memory 52 to the signal processing circuit 7.

[0219] At time t24e, the horizontal scanning circuit 6 finishes the dummy transfer operation of transferring the dummy signal Dm from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the dummy signal Dm from time t23e to time t24e.

[0220] Between times t25e and t26e, the column signal processing circuit 5 AD converts the reset signals N output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0221] At time t27e, the horizontal scanning circuit 6 starts the operation of transferring the pixel signals S2 for imaging of the Nth row from the memory 52 to the signal processing circuit .

[0222] At time t28e, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low level to high level for the pixels 11 in the (N+1)th row, causing the pixels 11 in the (N+1)th row to output pixel signals S for imaging.

[0223] At time t29e, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S2 of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the imaging pixel signals S2 of the Nth row from time t27e to t29e.

[0224] Between times t30e and t31e, the column signal processing circuit 5 AD-converts the pixel signals S for imaging output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0225] At time t32e, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+2)th row to be read next, causing the pixels 11 in the (N+2)th row to output the reset signal N.

[0226] At time t33e, the horizontal scanning circuit 6 starts the operation of transferring a part of the reset signals Na of the (N+1)th row from the memory 52 to the signal processing circuit .

[0227] At time t34e, the horizontal scanning circuit 6 finishes the operation of transferring the reset signals Na of the (N+1)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signals Na of the (N+1)th row from time t33e to t34e.

[0228] Between times t35e and t36e, the column signal processing circuit 5 AD converts the reset signals N output from the pixels 11 in the (N+2)th row, and stores the converted signals in the memory 52.

[0229] At time t37e, the horizontal scanning circuit 6 starts the operation of transferring the remaining reset signals Nb of the (N+1)th row from the memory 52 to the signal processing circuit .

[0230] At time t38e, the horizontal scanning circuit 6 finishes the operation of transferring the remaining reset signals Nb of the (N+1)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the remaining reset signals Nb of the (N+1)th row from time t37e to t38e.

[0231] At time t39e, the horizontal scanning circuit 6 starts the operation of transferring the imaging pixel signals S of the (N+1)th row from the memory 52 to the signal processing circuit .

[0232] At time t40e, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low level to high level for the pixels 11 in the (N+2)th row, causing the pixels 11 in the (N+2)th row to output pixel signals S for imaging.

[0233] At time t41e, the horizontal scanning circuit 6 finishes the operation of transferring the imaging pixel signals S of the (N+1)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the imaging pixel signals S of the (N+1)th row from time t39e to t41e.

[0234] Between times t42e and t43e, the column signal processing circuit 5 AD-converts the imaging pixel signals S output from the pixels 11 in the (N+2)th row, and stores the converted signals in the memory 52.

[0235] At time t44e, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+3)th row to be read next, causing the pixels 11 in the (N+3)th row to output the reset signal N.

[0236] As described above, the horizontal scanning circuit 6 transfers the dummy signal Dm during the transfer period (times t23e to t24e). The transfer period (times t23e to t24e) is a period different from the AD conversion period, and is positioned between the AD conversion period for the Nth row (times t20e to t21e) and the AD conversion period for the (N+1)th row (times t25e to t26e).

[0237] According to the imaging device 100 of this embodiment, when transitioning from the AF imaging mode to the imaging mode, a dummy transfer operation is performed in the imaging mode so that the number of signal transfer operations is the same for each scan in the imaging mode. Here, the number of signal transfer operations is, for example, the number of signal transfer operations between an AD conversion period (times t25e to t26e) and an AD conversion period (times t20e to t21e) immediately before the AD conversion period. Also, the number of signal transfer operations is the number of signal transfer operations between an AD conversion period (times t35e to t36e) and an AD conversion period (times t30e to t31e) immediately before the AD conversion period.

[0238] This allows the imaging device 100 to perform the same number of signal transfer operations between an AD conversion period and the AD conversion period immediately preceding it in each scan in the imaging mode. This ensures that noise caused by power supply fluctuations during signal transfer operations affects the AD conversion process in the same way during each AD conversion period. This allows noise in the imaging pixel signal S2 to be accurately removed using the reset signal N_AF.

[0239] [Fifth Comparative Example] Fig. 9 is a timing diagram of an imaging device according to a fifth comparative example. Similar to Fig. 6, Fig. 9 illustrates an example of transitioning from the AF imaging mode to the imaging mode. In this example, the pixel signal S1 for focus detection and the pixel signal S2 for imaging are each transferred twice.

[0240] At time t1f, the vertical scanning circuit 2 scans the pixels 11 in the AF imaging mode. The vertical scanning circuit 2 controls the control signal RES to change from low to high for the pixels 11 in the row to be read (the Nth row). The reset transistor M3 is turned on, and the input node FD is reset to a voltage corresponding to the voltage VDD. This causes the pixels 11 in the Nth row to output a reset signal.

[0241] At time t1f, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N for the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0242] At time t2f, the horizontal scanning circuit 6 completes the operation of transferring the reset signal N for the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0243] At time t3f, the horizontal scanning circuit 6 starts the operation of transferring some of the imaging pixel signals Sa of the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0244] At time t4f, the horizontal scanning circuit 6 finishes the operation of transferring some of the imaging pixel signals Sa of the (N-1)th row from the memory 52 to the signal processing circuit 7.

[0245] Between times t5f and t6f, the column signal processing circuit 5 performs AD conversion on the reset signals N_AF output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0246] At time t7f, the vertical scanning circuit 2 changes the control signal TX_1 from low to high for the pixels 11 in the Nth row. The transfer transistor M1 is turned on, and the signal charge held in the photoelectric conversion element PD1 is transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S1 for focus detection.

[0247] At time t8f, the horizontal scanning circuit 6 starts the operation of transferring the remaining imaging pixel signals Sb of the (N−1)th row from the memory 52 to the signal processing circuit 7.

[0248] At time t9f, the horizontal scanning circuit 6 finishes the operation of transferring the remaining imaging pixel signals Sb of the (N-1)th row from the memory 52 to the signal processing circuit .

[0249] Between times t10f and t11f, the column signal processing circuit 5 performs AD conversion on the pixel signals S1 for focus detection output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0250] At time t12f, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit .

[0251] At time t13f, the horizontal scanning circuit 6 finishes the operation of transferring the reset signal N_AF for the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signal N_AF for the Nth row from time t12f to t13f.

[0252] At time t14f, the horizontal scanning circuit 6 starts the operation of transferring some of the pixel signals S1a for focus detection in the Nth row from the memory 52 to the signal processing circuit .

[0253] At time t15f, the horizontal scanning circuit 6 finishes the operation of transferring some of the pixel signals S1a for focus detection in the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers some of the pixel signals S1a for focus detection in the Nth row from time t14f to t15f.

[0254] At time t16f, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low to high for the pixels 11 in the Nth row. The transfer transistors M1 and M2 are turned on, and the signal charges held in the photoelectric conversion elements PD1 and PD2 are transferred to the input node FD. This causes the pixels 11 in the Nth row to output pixel signals S2 for imaging.

[0255] At time t17f, the horizontal scanning circuit 6 starts the operation of transferring the remaining focus detection pixel signals S1b of the Nth row from the memory 52 to the signal processing circuit .

[0256] At time t18f, the horizontal scanning circuit 6 finishes the operation of transferring the remaining pixel signals S1b for focus detection in the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the remaining pixel signals S1b for focus detection in the Nth row from time t17f to t18f.

[0257] Between times t19f and t20f, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S2 output from the pixels 11 in the Nth row, and stores the converted signals in the memory 52.

[0258] At time t21f, the vertical scanning circuit 2 transitions from the AF imaging mode to the imaging mode. The vertical scanning circuit 2 controls the control signal RES for the pixels 11 in the (N+1)th row to be read next from low level to high level. This causes the reset signal N to be output from the pixels 11 in the (N+1)th row.

[0259] At time t22f, the horizontal scanning circuit 6 starts the operation of transferring some of the imaging pixel signals S2a of the Nth row from the memory 52 to the signal processing circuit .

[0260] At time t23f, the horizontal scanning circuit 6 finishes the operation of transferring some of the imaging pixel signals S2a of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers some of the imaging pixel signals S2a of the Nth row from time t22f to t23f.

[0261] Between times t24f and t25f, the column signal processing circuit 5 AD converts the reset signals N output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0262] At time t26f, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low level to high level for the pixels 11 in the (N+1)th row, causing the pixels 11 in the (N+1)th row to output pixel signals S for imaging.

[0263] At time t27f, the horizontal scanning circuit 6 starts the operation of transferring the remaining imaging pixel signals S2b of the Nth row from the memory 52 to the signal processing circuit .

[0264] At time t28f, the horizontal scanning circuit 6 finishes the operation of transferring the remaining imaging pixel signals S2b of the Nth row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the remaining imaging pixel signals S2b of the Nth row from time t27f to t28f.

[0265] Between times t29f and t30f, the column signal processing circuit 5 AD converts the pixel signals S for imaging output from the pixels 11 in the (N+1)th row, and stores the converted signals in the memory 52.

[0266] At time t31f, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+2)th row to be read next, causing the pixels 11 in the (N+2)th row to output the reset signal N.

[0267] At time t31f, the horizontal scanning circuit 6 starts the operation of transferring the reset signal N of the (N+1)th row from the memory 52 to the signal processing circuit .

[0268] At time t32f, the horizontal scanning circuit 6 finishes the operation of transferring the reset signal N for the (N+1)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the reset signal N for the (N+1)th row from time t31f to t32f.

[0269] At time t33f, the horizontal scanning circuit 6 starts the operation of transferring some of the imaging pixel signals Sa of the (N+1)th row from the memory 52 to the signal processing circuit .

[0270] At time t34f, the horizontal scanning circuit 6 finishes the operation of transferring some of the imaging pixel signals Sa of the (N+1)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers some of the imaging pixel signals Sa of the (N+1)th row from time t33f to t34f.

[0271] Between times t35f and t36f, the column signal processing circuit 5 AD converts the reset signals N output from the pixels 11 in the (N+2)th row, and stores the converted signals in the memory 52.

[0272] At time t37f, the vertical scanning circuit 2 changes the control signals TX_1 and TX_2 from low level to high level for the pixels 11 in the (N+2)th row, causing the pixels 11 in the (N+2)th row to output pixel signals S for imaging.

[0273] At time t38f, the horizontal scanning circuit 6 starts the operation of transferring the remaining imaging pixel signals Sb of the (N+1)th row from the memory 52 to the signal processing circuit .

[0274] At time t39f, the horizontal scanning circuit 6 finishes the operation of transferring the remaining imaging pixel signals Sb of the (N+1)th row from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the remaining imaging pixel signals Sb of the (N+1)th row from time t38f to t39f.

[0275] Between times t40f and t41f, the column signal processing circuit 5 performs AD conversion on the imaging pixel signals S output from the pixels 11 in the (N+2)th row, and stores the converted signals in the memory 52.

[0276] At time t42f, the vertical scanning circuit 2 changes the control signal RES from low to high for the pixels 11 in the (N+3)th row to be read next, causing the pixels 11 in the (N+3)th row to output the reset signal N.

[0277] As described above, the horizontal scanning circuit 6 transfers the signals output from the pixels 11 in the Nth row (reset signal N_AF, two-division focus detection pixel signals S1a and S1b, and two-division imaging pixel signals S2a and S2b) between AD conversion periods. In addition, the horizontal scanning circuit 6 transfers the signals output from the pixels 11 in the (N+1)th row (reset signal N, two-division imaging pixel signals Sa and Sb) to the signal processing circuit 7 between AD conversion periods.

[0278] At least one signal transfer operation is performed before each signal is AD converted. However, the number of signal transfer operations between AD conversion periods differs. For example, one signal transfer operation is performed between the AD conversion period for the Nth row (times t19f to t20f) and the AD conversion period for the (N+1)th row (times t24f to t25f). On the other hand, two signal transfer operations are performed between the AD conversion period for the (N+1)th row (times t29f to t30f) and the AD conversion period for the (N+2)th row (times t35f to t36f). When the number of signal transfer operations differs, the influence of noise due to power supply fluctuations during signal transfer operations may differ depending on the AD conversion process. In particular, when the number of signal transfer lines increases and the peak current during signal transfer becomes even larger, the influence of power supply fluctuations during not only the signal transfer operation immediately before AD conversion but also the signal transfer operation immediately before that cannot be ignored. For this reason, the imaging device according to this comparative example has a problem in that it cannot accurately remove noise. A method for solving this problem will be described with reference to FIG.

[0279] [Third embodiment] Fig. 10 is a timing diagram of the imaging device 100 according to this embodiment. Similar to Fig. 9, Fig. 10 illustrates an example of transitioning from the AF imaging mode to the imaging mode. Then, the pixel signal S1 for focus detection and the pixel signal S2 for imaging are each transferred twice. The process from time t1g to time t20g is the same as the process from time t1f to time t20f in FIG.

[0280] At time t21g, the horizontal scanning circuit 6 starts a dummy transfer operation to transfer the dummy signal Dm from the memory 52 to the signal processing circuit 7.

[0281] At time t22g, the horizontal scanning circuit 6 finishes the dummy transfer operation of transferring the dummy signal Dm from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the dummy signal Dm from time t21g to t22g. The process from time t23g to time t43g is the same as the process from time t22f to time t42f in FIG.

[0282] As described above, the horizontal scanning circuit 6 transfers the dummy signal Dm during the transfer period (times t21g to t22g). The transfer period (times t21g to t22g) is a period different from the AD conversion period, and is positioned between the AD conversion period for the Nth row (times t19g to t20g) and the AD conversion period for the (N+1)th row (times t25g to t26g).

[0283] In the imaging device 100 according to this embodiment, when transitioning from the AF imaging mode to the imaging mode, a dummy transfer operation is performed so that the number of signal transfer operations is the same for each scan in the imaging mode. Here, the number of signal transfer operations is, for example, the number of signal transfer operations between the AD conversion period (times t25g to t26g) and the AD conversion period (times t19g to t20g) immediately before the AD conversion period. Furthermore, the number of signal transfer operations is the number of signal transfer operations between the AD conversion period (times t36g to t37g) and the AD conversion period (times t30g to t31g) immediately before the AD conversion period. This allows the number of signal transfer operations (2 times) to be the same. Therefore, the influence of noise on each AD conversion process can be made more uniform, allowing noise to be removed with greater precision.

[0284] The period from the end of multiple signal transfer operations to the start of the AD conversion period (time t25g to t26g, time t36g to t37g) is the same for each scan in the imaging mode, which allows noise to be removed with even greater precision.

[0285] [Fourth embodiment] 11 is a timing chart of the imaging device 100 according to this embodiment. In FIG. 11, an example will be described in which the accuracy of noise removal is further improved in the processing described in FIG.

[0286] 8, the dummy transfer operation is performed so that the number of signal transfer operations is the same for each scan in the imaging mode. Here, the number of signal transfer operations is the number of signal transfer operations between an AD conversion period (time t25e to t26e) and the AD conversion period (time t20e to t21e) immediately before the AD conversion period.

[0287] In addition, in Fig. 11, a dummy transfer operation is also performed so that the number of signal transfer operations in another AD conversion period is the same for each scan in the imaging mode. Here, the number of signal transfer operations in another AD conversion period is the number of signal transfer operations between the AD conversion period (time t25e to t26e) and the AD conversion period (time t30e to t31e) following the AD conversion period. This will be explained in detail below. The process from time t1h to time t26h is the same as the process from time t1e to time t26e in FIG.

[0288] At time t27h, the horizontal scanning circuit 6 starts a dummy transfer operation to transfer the dummy signal Dm from the memory 52 to the signal processing circuit 7.

[0289] At time t28h, the horizontal scanning circuit 6 finishes the dummy transfer operation of transferring the dummy signal Dm from the memory 52 to the signal processing circuit 7. In this way, the horizontal scanning circuit 6 transfers the dummy signal Dm from time t27h to time t28h. The process from time t29h to time t46h is the same as the process from time t27e to time t44e in FIG.

[0290] As described above, the horizontal scanning circuit 6 also transfers the dummy signal Dm during the transfer period (times t27h to t28h). The transfer period (times t27h to t28h) is a period different from the AD conversion period and is positioned between the AD conversion period for the (N+1)th row (times t25h to t26h) and the AD conversion period for the (N+1)th row (times t32h to t33h).

[0291] In the image pickup device 100 according to this embodiment, when transitioning from the AF image pickup mode to the image pickup mode, the horizontal scanning circuit 6 performs a dummy transfer operation in the image pickup mode so that the number of signal transfer operations is the same for each scan in the image pickup mode. Here, the number of signal transfer operations is the number of signal transfer operations between an AD conversion period (times t25h to t26h) and an AD conversion period (times t20h to t21h) immediately before the AD conversion period.

[0292] Furthermore, the horizontal scanning circuit 6 performs a dummy transfer operation so that the number of signal transfer operations in another AD conversion period is the same for each scan in the imaging mode. Here, the number of signal transfer operations is the number of signal transfer operations between the AD conversion period (time t25h to t26h) and the next AD conversion period (time t32h to t33h) of the current AD conversion period.

[0293] As a result, the number of first signal transfer operations (2) is the same as the number of second signal transfer operations (2). Here, the number of first signal transfer operations (2) is the number of signal transfer operations between the AD conversion period of the (N+1)th row (times t25h to t26h) and the AD conversion period of the (N+1)th row (times t32h to t33h). The number of second signal transfer operations (2) is the number of signal transfer operations between the AD conversion period of the (N+2)th row (times t37h to t38h) and the AD conversion period of the (N+2)th row (times t44h to t45h). Compared to the process described in FIG. 8, the influence of noise on each AD conversion process can be made more equal, and noise can be removed with greater precision.

[0294] The period from the end of the multiple first signal transfer operations to the start of the AD conversion period (times t32h to t33h) for the (N+1)th row may be the same as the period from the end of the multiple second signal transfer operations to the start of the AD conversion period (times t44h to t45h) for the (N+2)th row. In this way, the period from the end of the multiple signal transfer operations to the start of the AD conversion period is the same for each scan in the imaging mode. This allows noise to be removed with even greater precision.

[0295] [Fifth embodiment] The imaging devices according to the above-described embodiments can be applied to various devices, such as digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 12 shows a block diagram of a digital still camera as an example of such a device.

[0296] The device 70 shown in FIG. 12 includes a barrier 706, a lens 702, an aperture 704, and the imaging device 700 of the above-described embodiment. The device 70 also includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the imaging device 700. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 700 is configured as in the above-described embodiment, and converts the optical image formed by the lens 702 into image data (image signals). The signal processing unit 708 performs various corrections, data compression, etc. on the imaging data output from the imaging device 700. The timing generating unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. The device 70 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the imaging device 700. The device 70 further includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the imaging device 700. The mechanical device is a movable part (e.g., a robot arm) that operates in response to a signal from the imaging device 700.

[0297] [Sixth embodiment] 13(a) and 13(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. The device 80 includes an image capture device 800 according to the above-described embodiment and a signal processing device (processing device) that processes signals from the image capture device 800. The device 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the image capture device 800, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the device 80. The device 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information includes information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0298] The device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high collision possibility, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 80 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0299] In this embodiment, the device 80 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 13(b) shows the device when capturing an image of the area in front of the vehicle (image capturing range 850). A vehicle information acquisition device 810, which serves as an image capturing control means, sends an instruction to the device 80 or the image capturing device 800 to perform an image capturing operation. This configuration can further improve the accuracy of distance measurement.

[0300] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0301] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present invention.

[0302] 7, 8, and 10 illustrate an example in which the dummy transfer operation is performed once per scan of one row (one scan), and an example in which the dummy transfer operation is performed multiple times per scan of one row (one scan) is illustrated in Fig. 11. In this way, the number of times the dummy transfer operation is performed per scan of one row (one scan) is not limited.

[0303] 7, an example has been described in which the first signal transfer operation and the second signal transfer operation are each performed once. Here, the first signal transfer operation is the number of signal transfer operations performed between the AD conversion period (times t25d to t26d) of the (N+1)th row and the AD conversion period (times t30d to t31d) of the (N+2)th row. The second signal transfer operation is the number of signal transfer operations performed between the AD conversion period (times t30d to t31d) of the (N+2)th row and the AD conversion period (times t35d to t36d) of the (N+2)th row. This is not limiting, and the first signal transfer operation and the second signal transfer operation may each be performed multiple times. In this case, the first signal transfer operation and the second signal transfer operation may each be performed the same number of times. The period from the end of the multiple first signal transfer operations to the start of the AD conversion period (time t30d to t31d) for the (N+2)th row may be the same as the period from the end of the multiple second signal transfer operations to the start of the AD conversion period (time t35d to t36d) for the (N+2)th row.

[0304] 8, an example has been described in which the first signal transfer operation and the second signal transfer operation are each performed once. Here, the first signal transfer operation is the number of signal transfer operations performed between an AD conversion period (times t25e to t26e) and the AD conversion period (times t20e to t21e) immediately preceding the AD conversion period. The second signal transfer operation is the number of signal transfer operations performed between an AD conversion period (times t35e to t36e) and the AD conversion period (times t30e to t31e) immediately preceding the AD conversion period. This is not limiting, and the first signal transfer operation and the second signal transfer operation may each be performed multiple times. In this case, the first signal transfer operation and the second signal transfer operation may each be performed the same number of times.

[0305] 10, an example has been described in which the period from the end of multiple signal transfer operations to the start of the AD conversion period (times t25g to t26g, times t36g to t37g) is the same for each scan in the imaging mode, but the same is true for a single signal transfer operation. That is, the period from the end of one signal transfer operation to the start of the AD conversion period (times t25g to t26g, times t36g to t37g) is the same for each scan in the imaging mode.

[0306] 11, an example has been described in which the period from the end of multiple signal transfer operations to the start of the AD conversion period (times t32h to t33h, times t44h to t45h) is the same for each scan in the imaging mode, but the same is true for a single signal transfer operation. That is, the period from the end of one signal transfer operation to the start of the AD conversion period (times t32h to t33h, times t44h to t45h) is the same for each scan in the imaging mode.

[0307] Although the first to fourth embodiments have been described above with respect to a configuration in which multiple photoelectric conversion units are provided for one microlens ML, the present invention is not limited to this configuration. That is, a configuration in which one photoelectric conversion unit is provided for one microlens ML may also be used. In this case, one pixel can be considered to be provided with two microlenses ML. That is, in the configuration described herein, each of multiple pixels includes multiple photoelectric conversion units. The first scanning circuit included in the photoelectric conversion device operates in a first mode to output an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first and second photoelectric conversion units. The first scanning circuit also operates in a second mode to output an analog signal of a reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first and second photoelectric conversion units. The first to fourth embodiments of the present specification can be applied to a photoelectric conversion device having such a configuration.

[0308] The disclosure of the above embodiment includes the following configurations. (Configuration 1) a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; a photoelectric conversion device characterized in that, when transitioning from the second mode to the first mode, the second scanning circuit performs the additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately preceding the first AD conversion period is equal to the number of second signal transfer operations between the first AD conversion period and the AD conversion period following the first AD conversion period. (Configuration 2) The photoelectric conversion device according to configuration 1, characterized in that the period from the end of the first signal transfer operation to the start of the first AD conversion period is the same as the period from the end of the second signal transfer operation to the start of the next AD conversion period. (Configuration 3) the number of times of the first signal transfer operation and the number of times of the second signal transfer operation are each plural, The photoelectric conversion device described in configuration 1, characterized in that the period from the end of multiple first signal transfer operations to the start of the first AD conversion period is the same as the period from the end of multiple second signal transfer operations to the start of the next AD conversion period. (Configuration 4) a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; a second scanning circuit that performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately preceding the first AD conversion period is the same for each scan in the first mode when transitioning from the second mode to the first mode; (Configuration 5) 5. The photoelectric conversion device according to configuration 4, wherein the period from the end of the first signal transfer operation to the start of the first AD conversion period is the same for each scan in the first mode. (Configuration 6) the first signal transfer operation is performed a plurality of times; The photoelectric conversion device according to configuration 4, wherein the period from the end of the first signal transfer operation multiple times to the start of the first AD conversion period is the same for each scan in the first mode. (Configuration 7) a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; a second scanning circuit that performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period following the first AD conversion period is the same for each scan in the first mode when transitioning from the second mode to the first mode; (Configuration 8) 8. The photoelectric conversion device according to configuration 7, wherein the period from the end of the first signal transfer operation to the start of the next AD conversion period is the same for each scan in the first mode. (Configuration 9) the first signal transfer operation is performed a plurality of times; The photoelectric conversion device according to configuration 7, wherein the period from the end of the first signal transfer operation multiple times to the start of the next AD conversion period is the same for each scan in the first mode. (Configuration 10) a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; a second scanning circuit configured to perform an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately preceding the first AD conversion period is the same for each scan in the first mode, and to perform an additional signal transfer operation so that the number of second signal transfer operations between the first AD conversion period and the AD conversion period immediately following the first AD conversion period is the same for each scan in the first mode, when transitioning from the second mode to the first mode. (Configuration 11) The photoelectric conversion device described in configuration 10, characterized in that the period from the end of the first signal transfer operation to the start of the first AD conversion period is the same for each scan in the first mode, and the period from the end of the second signal transfer operation to the start of the next AD conversion period is the same for each scan in the first mode. (Configuration 12) the number of times of the first signal transfer operation and the number of times of the second signal transfer operation are each plural, The photoelectric conversion device described in configuration 10, characterized in that the period from the end of multiple first signal transfer operations to the start of the first AD conversion period is the same for each scan in the first mode, and the period from the end of multiple second signal transfer operations to the start of the next AD conversion period is the same for each scan in the first mode. (Configuration 13) 13. The photoelectric conversion device according to any one of configurations 1 to 12, wherein the number of times the additional signal transfer operation is performed is one per scan. (Configuration 14) 13. The photoelectric conversion device according to any one of the configurations 1 to 12, wherein the number of times of the additional signal transfer operation is a plurality of times in one scan. (Configuration 15) 15. The photoelectric conversion device according to any one of configurations 1 to 14, wherein the additional signal transfer operation is an operation of outputting a dummy signal different from the digital signal. (Configuration 16) 16. The photoelectric conversion device according to any one of configurations 1 to 15, wherein the first scanning circuit intermittently scans in the second mode while scanning in the first mode. (Configuration 17) 17. The photoelectric conversion device according to any one of structures 1 to 16, wherein the first photoelectric conversion unit and the second photoelectric conversion unit are provided corresponding to one microlens. (Configuration 18) The photoelectric conversion device according to any one of configurations 1 to 17, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. (Configuration 19) 19. The device according to claim 18, wherein the processing device acquires distance information from the photoelectric conversion device to an object. [Explanation of symbols]

[0309] 100...imaging device 2...Vertical scanning circuit (first scanning circuit) 6...Horizontal scanning circuit (second scanning circuit) 11...pixels 52...Memory

Claims

1. a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; When transitioning from the second mode to the first mode, the second scanning circuit performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately preceding the first AD conversion period is equal to the number of second signal transfer operations between the first AD conversion period and the AD conversion period following the first AD conversion period.

2. The photoelectric conversion device according to claim 1, characterized in that the period from the end of the first signal transfer operation to the start of the first AD conversion period is the same as the period from the end of the second signal transfer operation to the start of the next AD conversion period.

3. the number of times of the first signal transfer operation and the number of times of the second signal transfer operation are each plural, The photoelectric conversion device according to claim 1, characterized in that the period from the end of multiple first signal transfer operations to the start of the first AD conversion period is the same as the period from the end of multiple second signal transfer operations to the start of the next AD conversion period.

4. a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; When transitioning from the second mode to the first mode, the second scanning circuit performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately preceding the first AD conversion period is the same for each scan in the first mode.

5. 5. The photoelectric conversion device according to claim 4, wherein the period from the end of the first signal transfer operation to the start of the first AD conversion period is the same for each scan in the first mode.

6. the first signal transfer operation is performed a plurality of times; 5. The photoelectric conversion device according to claim 4, wherein the period from the end of a plurality of first signal transfer operations to the start of the first AD conversion period is the same for each scan in the first mode.

7. a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; When transitioning from the second mode to the first mode, the second scanning circuit performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period next to the first AD conversion period is the same for each scan in the first mode.

8. 8. The photoelectric conversion device according to claim 7, wherein the period from the end of the first signal transfer operation to the start of the next AD conversion period is the same for each scan in the first mode.

9. the first signal transfer operation is performed a plurality of times; 8. The photoelectric conversion device according to claim 7, wherein the period from the end of a plurality of first signal transfer operations to the start of the next AD conversion period is the same for each scan in the first mode.

10. a plurality of pixels each having a first photoelectric conversion unit and a second photoelectric conversion unit that generate signal charges; a first scanning circuit that scans the plurality of pixels in a first mode in which an analog signal of a reset level and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel, and a second mode in which the analog signal of the reset level, an analog signal corresponding to the signal charges of the first photoelectric conversion unit, and an analog signal corresponding to the signal charges of both the first photoelectric conversion unit and the second photoelectric conversion unit are output from the pixel; an AD conversion unit that converts each of the plurality of analog signals into a digital signal during each of a plurality of AD conversion periods; a memory for storing the digital signal; a second scanning circuit that performs a signal transfer operation to output the digital signal from the memory during each of a plurality of transfer periods different from the plurality of AD conversion periods; the plurality of AD conversion periods includes a first AD conversion period for converting the analog signal at the reset level in the first mode into the digital signal; When transitioning from the second mode to the first mode, the second scanning circuit performs an additional signal transfer operation so that the number of first signal transfer operations between the first AD conversion period and the AD conversion period immediately preceding the first AD conversion period is the same for each scan in the first mode, and performs the additional signal transfer operation so that the number of second signal transfer operations between the first AD conversion period and the AD conversion period next to the first AD conversion period is the same for each scan in the first mode.

11. The photoelectric conversion device according to claim 10, characterized in that the period from the end of the first signal transfer operation to the start of the first AD conversion period is the same for each scan in the first mode, and the period from the end of the second signal transfer operation to the start of the next AD conversion period is the same for each scan in the first mode.

12. the number of times of the first signal transfer operation and the number of times of the second signal transfer operation are each plural, The photoelectric conversion device according to claim 10, characterized in that the period from the end of multiple first signal transfer operations to the start of the first AD conversion period is the same for each scan in the first mode, and the period from the end of multiple second signal transfer operations to the start of the next AD conversion period is the same for each scan in the first mode.

13. 11. The photoelectric conversion device according to claim 1, wherein the number of times the additional signal transfer operation is performed is one per scan.

14. 11. The photoelectric conversion device according to claim 1, wherein the number of times of the additional signal transfer operation is a plurality of times in one scan.

15. 11. The photoelectric conversion device according to claim 1, wherein the additional signal transfer operation is an operation of outputting a dummy signal different from the digital signal.

16. 11. The photoelectric conversion device according to claim 1, wherein the first scanning circuit intermittently scans in the second mode while scanning in the first mode.

17. 11. The photoelectric conversion device according to claim 1, wherein the first photoelectric conversion unit and the second photoelectric conversion unit are provided corresponding to one microlens.

18. The photoelectric conversion device according to any one of claims 1, 4, 7, and 10; an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

19. 20. The device of claim 18, wherein the processing device acquires distance information from the photoelectric conversion device to an object.

Images