Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

To provide a nitride semiconductor device capable of obtaining a high breakdown voltage, and to provide a method of manufacturing the nitride semiconductor device.SOLUTION: A nitride semiconductor device comprising: a first nitride semiconductor layer including a channel layer and a barrier layer overlapping each other along a first axis and having a first surface perpendicular to the first axis; a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer therebetween along a second axis perpendicular to the first axis, wherein, in a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer includes a first covering portion covering a part of the first surface, the third nitride semiconductor layer includes a second covering portion covering a portion of the first surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In order to reduce contact resistance and the like in nitride semiconductor devices, a structure has been proposed in which a nitride semiconductor layer containing a high concentration of impurities is regrown. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-329350 [Patent Document 2] Special Publication No. 2007-538402 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for further improvement in pressure resistance.

[0005] An object of the present disclosure is to provide a nitride semiconductor device that can obtain a high breakdown voltage and a method for manufacturing the nitride semiconductor device. [Means for solving the problem]

[0006] The nitride semiconductor device of the present disclosure comprises a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis and having a first surface perpendicular to the first axis, and a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis perpendicular to the first axis, wherein, in a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion covering a portion of the first surface, and the third nitride semiconductor layer has a second covering portion covering a portion of the first surface. [Effects of the Invention]

[0007] According to the present disclosure, a high breakdown voltage can be obtained. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a nitride semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a plan view showing the nitride semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) illustrating a first method for manufacturing a nitride semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) illustrating the first manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) illustrating the first manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) illustrating the first manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a fifth cross-sectional view showing the first manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) showing the first manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 7) illustrating the first manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 1) illustrating the second manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 2) illustrating the second manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 3) illustrating the second manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 4) illustrating the second manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 14]FIG. 14 is a cross-sectional view (part 5) showing the second manufacturing method of the nitride semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a phenomenon in the nitride semiconductor device according to the embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a phenomenon in a nitride semiconductor device according to a reference example. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A nitride semiconductor device according to one embodiment of the present disclosure includes: a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis, the first nitride semiconductor layer having a first surface perpendicular to the first axis; and a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis perpendicular to the first axis, wherein, in a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion covering a portion of the first surface, and the third nitride semiconductor layer has a second covering portion covering a portion of the first surface.

[0011] When the second nitride semiconductor layer and the third nitride semiconductor layer are formed by sputtering, recesses may be formed non-uniformly on the upper surfaces of the second nitride semiconductor layer and the third nitride semiconductor layer. Furthermore, polycrystalline layers are formed in unnecessary locations. Since the second nitride semiconductor layer has a first covering portion and the third nitride semiconductor layer has a second covering portion, recesses are generally formed in the first covering portion and the second covering portion. Therefore, even if low-crystalline portions of the second nitride semiconductor layer and the third nitride semiconductor layer near the recesses are slightly etched when the polycrystalline layer is removed, the barrier layer and the channel layer are not etched, and a high breakdown voltage can be obtained for the nitride semiconductor device.

[0012] [2] In [1], the first nitride semiconductor layer may have a second surface opposite to the first surface, the second nitride semiconductor layer may have a third surface that is farther from the second surface than a first distance between the first surface and the second surface, and the third nitride semiconductor layer may have a fourth surface that is farther from the second surface than the first distance. In this case, etching of the barrier layer and the channel layer is easily prevented.

[0013] [3] In [2], the distance between the first surface and the third surface may be 5 nm or more and 30 nm or less, and the distance between the first surface and the fourth surface may be 5 nm or more and 30 nm or less. When these distances are 5 nm or more, etching of the barrier layer and the channel layer is more easily prevented. When these distances are 30 nm or less, excessive steps are more easily prevented.

[0014] [4] In any one of [1] to [3], the first nitride semiconductor layer may have a cap layer having the first surface. In this case, it is possible to reduce gate leakage current and improve long-term reliability.

[0015] [5] In any of [1] to [4], the length of the first covering portion in the direction along the second axis may be 30 nm or more and 200 nm or less, and the length of the second covering portion in the direction along the second axis may be 30 nm or more and 200 nm or less. When these lengths are 30 nm or more, etching of the barrier layer and the channel layer is more easily prevented. When these lengths are 200 nm or less, short-circuiting between a gate electrode provided between the second nitride semiconductor layer and the third nitride semiconductor layer and the second nitride semiconductor layer and the third nitride semiconductor layer is more easily prevented.

[0016] [6] In any one of [1] to [5], the channel layer may have a channel region containing two-dimensional electron gas, and the electrical resistance of the second nitride semiconductor layer and the electrical resistance of the third nitride semiconductor layer may be lower than the electrical resistance of the channel region. In this case, the electrical resistance between the electrodes provided on the second nitride semiconductor layer and the third nitride semiconductor layer can be reduced.

[0017] [7] In any one of [1] to [6], the second nitride semiconductor layer and the third nitride semiconductor layer may contain n-type impurities, which makes it easier to obtain low electrical resistance in the second nitride semiconductor layer and the third nitride semiconductor layer.

[0018] [8] In [7], the concentration of the impurity is 1×10 20 cm -3 In this case, it is easy to obtain particularly low electrical resistance in the second nitride semiconductor layer and the third nitride semiconductor layer.

[0019] [9] In any of [1] to [8], a first recess and a second recess may be formed in the first nitride semiconductor layer along the second axis, sandwiching the channel layer and the barrier layer therebetween, the second nitride semiconductor layer being provided in the first recess, and the third nitride semiconductor layer being provided in the second recess. In this case, it is easy to form the second nitride semiconductor layer and the third nitride semiconductor layer.

[0020]

[10] In any one of [1] to [9], an insulating layer may be provided on the first surface and in contact with the first covering portion and the second covering portion. In this case, the insulating layer can protect the first nitride semiconductor layer.

[0021]

[11] A method for manufacturing a nitride semiconductor device according to another embodiment of the present disclosure includes the steps of: preparing a first nitride semiconductor layer having a first surface, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis; and forming, by a sputtering method, a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis perpendicular to the first axis, wherein, in a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion covering a part of the first surface, and the third nitride semiconductor layer has a second covering portion covering a part of the first surface.

[0022] As described above, even if the low-crystalline portions of the second nitride semiconductor layer and the third nitride semiconductor layer near the recess are slightly etched when the polycrystalline layer is removed, the barrier layer and the channel layer are not etched, and the nitride semiconductor device can achieve a high breakdown voltage.

[0023]

[12] In the method of

[11] , between the step of preparing the first nitride semiconductor layer and the step of forming the second nitride semiconductor layer and the third nitride semiconductor layer, a step of forming a first recess and a second recess in the first nitride semiconductor layer along the second axis, sandwiching the channel layer and the barrier layer therebetween, may be included, wherein the second nitride semiconductor layer is formed in the first recess and the third nitride semiconductor layer is formed in the second recess. In this case, it is easy to form the second nitride semiconductor layer and the third nitride semiconductor layer.

[0024]

[13] In the method of

[12] , between the step of forming the first nitride semiconductor layer and the step of forming the first recess and the second recess, the method may include the steps of forming an insulating layer on the first surface, forming a mask having a first opening and a second opening on the insulating layer, and etching the insulating layer through the first opening and the second opening to form a third opening connected to the first opening and larger than the first opening in a plan view, and a fourth opening connected to the second opening and larger than the second opening in a plan view, in the insulating layer, wherein the first recess and the second recess are formed by etching through the first opening and the second opening, and the method may include the step of removing the mask between the step of forming the first recess and the second recess and the step of forming the second nitride semiconductor layer and the third nitride semiconductor layer. In this case, the sizes of the first covering portion and the second covering portion can be adjusted during etching of the insulating layer.

[0025]

[14] In the method of

[12] , between the step of forming the first nitride semiconductor layer and the step of forming the first recess and the second recess, there may be a step of forming an insulating layer on the first surface, a step of forming a mask having a first opening and a second opening on the insulating layer, and a step of etching the insulating layer through the first opening and the second opening to form a fifth opening connected to the first opening and a sixth opening connected to the second opening in the insulating layer, wherein the first recess and the second recess are formed by etching through the first opening and the second opening, and between the step of forming the first recess and the second recess and the step of forming the second nitride semiconductor layer and the third nitride semiconductor layer, there may be a step of ashing the mask to widen the first opening and the second opening and expose a part of the insulating layer from the first opening and the second opening, a step of removing the part of the insulating layer exposed from the first opening and the second opening, and a step of removing the mask after the step of removing the part of the insulating layer exposed from the first opening and the second opening. In this case, the sizes of the first and second covering portions can be adjusted during ashing of the mask.

[0026] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the nitride semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the −Z direction may be referred to as downward, lower side, or bottom.

[0027] An embodiment of the present disclosure relates to a nitride semiconductor device including a high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing a nitride semiconductor device according to an embodiment. Fig. 2 is a plan view showing a nitride semiconductor device according to an embodiment. Fig. 1 corresponds to a cross-sectional view taken along line II in Fig. 2.

[0028] As shown in FIGS. 1 and 2, the nitride semiconductor device 100 according to the embodiment includes a substrate 110, a first nitride semiconductor layer 120, a second nitride semiconductor layer 142S, a third nitride semiconductor layer 142D, an insulating layer 130, a gate electrode 50, a source electrode 44S, and a drain electrode 44D.

[0029] The substrate 110 is, for example, a substrate for growing a gallium nitride (GaN)-based semiconductor layer, such as a semi-insulating silicon carbide (SiC) substrate. When the substrate 110 is a SiC substrate, the upper surface of the substrate 110 is a silicon (Si) polar plane. When the surface of the substrate 110 is a Si polar plane, the first nitride semiconductor layer 120 undergoes crystal growth with the gallium (Ga) polar plane as the growth plane.

[0030] The first nitride semiconductor layer 120 has a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128. The buffer layer 122, the channel layer 124, the barrier layer 126, and the cap layer 128 are stacked in this order along the Z axis. The first nitride semiconductor layer 120 has an upper surface 161 and a lower surface 162 that are perpendicular to the Z axis. The upper surface 161 is located on the cap layer 128. The Z axis is an example of a first axis. The upper surface 161 is an example of a first surface, and the lower surface 162 is an example of a second surface opposite the first surface.

[0031] The buffer layer 122 is on the substrate 110. The buffer layer 122 is, for example, an aluminum nitride (AlN) layer. The buffer layer 122 may include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer. The channel layer 124 is on the buffer layer 122. The channel layer 124 is, for example, an undoped gallium nitride (GaN) layer. The barrier layer 126 is on the channel layer 124. The barrier layer 126 is, for example, an n-type AlGaN layer. A channel region 155 including a two-dimensional electron gas (2DEG) is present near the top surface of the channel layer 124. The cap layer 128 is on the barrier layer 126. The cap layer 128 is, for example, an n-type GaN layer.

[0032] A first recess 140S for a source and a second recess 140D for a drain are formed in the cap layer 128, the barrier layer 126, and a part of the channel layer 124. The first recess 140S and the second recess 140D penetrate the cap layer 128 and the barrier layer 126 and extend into the channel layer 124. The channel layer 124 is exposed from the first recess 140S and the second recess 140D.

[0033] The insulating layer 130 is on the cap layer 128. The insulating layer 130 is, for example, a silicon nitride (SiN) film. The insulating layer 130 has a thickness of, for example, 1 nm or more and 10 nm or less. An opening 130S for a source and an opening 130D for a drain are formed in the insulating layer 130. The opening 130S is connected to the first recess 140S, and the opening 130D is connected to the second recess 140D. The opening 130D is on the +X side of the opening 130S. In a plan view, the opening 130S is larger than the first recess 140S, and the opening 130D is larger than the second recess 140D. In the X-axis direction, the +X side edge of the opening 130S is closer to the +X side edge of the first recess 140S, and the -X side edge of the opening 130D is closer to the -X side edge of the second recess 140D. The X-axis is an example of a second axis.

[0034] The second nitride semiconductor layer 142S is located on the cap layer 128 and the channel layer 124 within the first recess 140S and the opening 130S. In a ZX cross-sectional view including the Z axis and the X axis, the second nitride semiconductor layer 142S has a first covering portion 144S covering a portion of the upper surface 161. The second nitride semiconductor layer 142S has an upper surface 163. The distance of the upper surface 163 from the lower surface 162 of the first nitride semiconductor layer 120 may be greater than the first distance L0 between the upper surface 161 and the lower surface 162 of the first nitride semiconductor layer 120. The second nitride semiconductor layer 142S contacts the sidewall surface of the opening 130S and the sidewall surface of the opening 130S. The upper surface 163 is an example of a third surface.

[0035] The third nitride semiconductor layer 142D is located on the cap layer 128 and the channel layer 124 within the second recess 140D and the opening 130D. In a ZX cross-sectional view including the Z axis and the X axis, the third nitride semiconductor layer 142D has a second covering portion 144D covering a portion of the upper surface 161. The third nitride semiconductor layer 142D has an upper surface 164. The distance of the upper surface 164 from the lower surface 162 of the first nitride semiconductor layer 120 may be greater than the first distance L0 between the upper surface 161 and the lower surface 162 of the first nitride semiconductor layer 120. The third nitride semiconductor layer 142D contacts the sidewall surface of the opening 130D and the sidewall surface of the opening 130D. The upper surface 164 is an example of a fourth surface.

[0036] The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D sandwich the channel layer 124 and the barrier layer 126 along the X-axis. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are, for example, n-type GaN layers. The electrical resistances of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are lower than the electrical resistance of the channel region 155.

[0037] The source electrode 44S is on the second nitride semiconductor layer 142S, and the drain electrode 44D is on the third nitride semiconductor layer 142D. The source electrode 44S is in direct contact with the second nitride semiconductor layer 142S, and the drain electrode 44D is in direct contact with the third nitride semiconductor layer 142D. The source electrode 44S is in ohmic contact with the second nitride semiconductor layer 142S, and the drain electrode 44D is in ohmic contact with the third nitride semiconductor layer 142D.

[0038] An opening 130G for a gate is formed in the insulating layer 130. The opening 130G is located between the openings 130S and 130D. The gate electrode 50 is provided on the insulating layer 130 and is in Schottky contact with the first nitride semiconductor layer 120 through the opening 130G.

[0039] Next, a first method for manufacturing the nitride semiconductor device 100 according to the embodiment will be described. Figures 3 to 9 are cross-sectional views illustrating the first method for manufacturing the nitride semiconductor device 100 according to the embodiment.

[0040] In the first manufacturing method, first, as shown in FIG. 3, a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128 are formed on a substrate 110. The buffer layer 122, the channel layer 124, the barrier layer 126, and the cap layer 128 can be formed by, for example, a metal organic chemical vapor deposition (MOCVD) method. Next, an insulating layer 130 is formed on the cap layer 128. The insulating layer 130 can be formed by, for example, a CVD method. In this manner, a first nitride semiconductor layer 120 is obtained.

[0041] Next, as shown in FIG. 4, a mask 200 is formed on the insulating layer 130. The mask 200 has an opening 201 for the first recess 140S and an opening 202 for the second recess 140D. For example, the mask 200 is formed from photoresist. The opening 201 is an example of a first opening, and the opening 202 is an example of a second opening.

[0042] Next, as shown in FIG. 5 , the insulating layer 130 is etched through the openings 201 and 202 to form an opening 130S connected to the opening 201 and an opening 130D connected to the opening 202 in the insulating layer 130. The insulating layer 130 is etched under conditions that cause side etching. In plan view, the opening 130S is formed larger than the opening 201, and the opening 130D is formed larger than the opening 202. In the X-axis direction, the +X-side edge of the opening 130S is located closer to the +X-side edge of the opening 201, and the -X-side edge of the opening 130D is located closer to the -X-side edge of the opening 202. The openings 130S and 130D can be formed by reactive ion etching (RIE) using a reactive gas containing, for example, fluorine (F). In RIE, for example, the pressure in the chamber is set to 2 Pa or more and 10 Pa or less, and the bias power is set to 0 W or more and 2 W or less. Opening 130S is an example of a third opening, and opening 130D is an example of a fourth opening.

[0043] Next, as shown in FIG. 6 , the first nitride semiconductor layer 120 is etched through the openings 201 and 202 to form a first recess 140S connected to the opening 130S and a second recess 140D connected to the opening 130D in the first nitride semiconductor layer 120. The first recess 140S and the second recess 140D sandwich the channel layer 124 and the barrier layer 126 along the X-axis. The first recess 140S and the second recess 140D can be formed by RIE using a reactive gas containing chlorine (Cl), for example. In RIE, the pressure in the chamber is set to 0.2 Pa to 5 Pa, and the bias power is set to 1 W to 5 W, for example. For example, the angle formed by the sidewall surfaces of the first recess 140S and the second recess 140D and the top surface 161 of the first nitride semiconductor layer 120 is set to be close to 90 degrees.

[0044] 7, the mask 200 is removed. Next, a second nitride semiconductor layer 142S is formed in the first recess 140S and the opening 130S, and a third nitride semiconductor layer 142D is formed in the second recess 140D and the opening 130D. The second nitride semiconductor layer 142S is formed on the cap layer 128 and the channel layer 124 in the first recess 140S and the opening 130S. The third nitride semiconductor layer 142D is formed on the cap layer 128 and the channel layer 124 in the second recess 140D and the opening 130D. The edge of the cap layer 128 on the −X side is covered with the second nitride semiconductor layer 142S, and the edge on the +X side is covered with the third nitride semiconductor layer 142D. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D can be formed by, for example, a sputtering method. When the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are formed by sputtering, Ga and n-type impurities may be supplied intermittently while nitrogen radicals are continuously supplied. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are epitaxially grown as single crystals. Meanwhile, a polycrystalline layer 142X is also formed on the insulating layer 130.

[0045] Next, as shown in FIG. 8, the polycrystalline layer 142X is removed. The polycrystalline layer 142X can be removed using an alkaline etchant such as tetramethylammonium hydroxide (TMAH). At this time, the single-crystal second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are hardly removed. Therefore, the edges of the cap layer 128 remain covered by the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, and the etchant does not come into contact with the first nitride semiconductor layer 120, so the first nitride semiconductor layer 120 is not etched.

[0046] 9, a source electrode 44S is formed on the second nitride semiconductor layer 142S, and a drain electrode 44D is formed on the third nitride semiconductor layer 142D. The source electrode 44S and the drain electrode 44D can be formed by, for example, evaporation and lift-off.

[0047] Next, an opening 130G is formed in the insulating layer 130. The opening 130G can be formed by RIE using a reactive gas containing fluorine (F), for example. Next, a gate electrode 50 is formed on the insulating layer 130, making Schottky contact with the first nitride semiconductor layer 120 through the opening 130G (see FIG. 1).

[0048] In this manner, the nitride semiconductor device 100 according to the embodiment can be manufactured.

[0049] Next, a second method for manufacturing the nitride semiconductor device 100 according to the embodiment will be described. Figures 10 to 14 are cross-sectional views illustrating the second method for manufacturing the nitride semiconductor device 100 according to the embodiment.

[0050] In the second manufacturing method, first, similar to the first manufacturing method, processing up to the formation of mask 200 is performed (see FIG. 4). Next, as shown in FIG. 10, insulating layer 130 is etched through openings 201 and 202 to form openings 132S and 132D in insulating layer 130, which are connected to opening 201 and opening 202, respectively. Etching of insulating layer 130 is performed under conditions that make side etching unlikely. In plan view, openings 132S and 132D are formed to be the same size as openings 201 and 202, respectively. For example, in the X-axis direction, the +X-side edge of opening 132S coincides with the +X-side edge of opening 201, and the -X-side edge of opening 132D coincides with the -X-side edge of opening 202. However, these do not need to coincide perfectly, and manufacturing errors are acceptable. Openings 132S and 132D can be formed by RIE using a reactive gas containing fluorine (F), for example. In RIE, for example, the pressure in the chamber is set to 0.5 Pa or more and 2 Pa or less, and the bias power is set to 2 W or more and 5 W or less. Opening 132S is an example of a fifth opening, and opening 132D is an example of a sixth opening.

[0051] 11, first nitride semiconductor layer 120 is etched through openings 201 and 202 to form first recesses 140S connected to openings 132S and second recesses 140D connected to openings 132D in first nitride semiconductor layer 120. First recesses 140S and second recesses 140D can be formed under the same conditions as in the first manufacturing method.

[0052] 12 , the mask 200 is then ashed to widen the openings 201 and 202, thereby exposing portions of the insulating layer 130 through the openings 201 and 202. When ashing the mask 200, for example, oxygen plasma is used to remove the edges of the mask 200. At this time, the upper portion of the mask 200 is also removed, but by making the thickness of the mask 200 before ashing larger than the length by which the openings 201 and 202 are widened, the mask 200 can remain after ashing, and the functionality of the mask 200 can be maintained.

[0053] 13, the portions of insulating layer 130 exposed through opening 201 and opening 202 are removed. The portions of insulating layer 130 exposed through opening 201 and opening 202 can be removed by RIE using a reactive gas containing fluorine (F), for example. In RIE, the pressure in the chamber is set to 0.5 Pa or more and 2 Pa or less, and the bias power is set to 2 W or more and 5 W or less. As a result of this process, openings 130S and 130D are formed in insulating layer 130.

[0054] Next, as shown in Fig. 14, the mask 200 is removed. Thereafter, similarly to the first manufacturing method, the processes from the formation of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D onwards are carried out.

[0055] In this manner, the nitride semiconductor device 100 according to the embodiment can be manufactured.

[0056] When the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are formed by sputtering, as shown in FIG. 15 , depressions 165 may be formed near the insulating layer 130 on the upper surfaces of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. This is because part of the flow of raw material flying from the target is blocked by the already formed polycrystalline layer 142X. Furthermore, the shape and size of the depressions 165 in the ZX cross section are nonuniform along the Y-axis direction. In this embodiment, the second nitride semiconductor layer 142S has the first covering portion 144S, and the third nitride semiconductor layer 142D has the second covering portion 144D, and the depressions 165 are formed mainly in the first covering portion 144S and the second covering portion 144D. When removing the polycrystalline layer 142X, the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are hardly etched, but the portions with low crystallinity near the recess 165 may be slightly etched. However, since the portions with low crystallinity near the recess 165 are in the first covering portion 144S and the second covering portion 144D, even if the first covering portion 144S and the second covering portion 144D are slightly etched, the cap layer 128, the barrier layer 126, and the channel layer 124 are not etched. Therefore, a high breakdown voltage can be obtained in the nitride semiconductor device 100.

[0057] On the other hand, when the lower end of the opening 130S and the upper end of the first recess 140S overlap in plan view, as in the nitride semiconductor device according to the reference example shown in FIG. 16 , the low-crystallinity portion of the second nitride semiconductor layer 142S may be slightly etched during removal of the polycrystalline layer 142X. If the low-crystallinity portion of the second nitride semiconductor layer 142S is slightly etched, the cap layer 128 and the barrier layer 126 may be etched depending on the shape and size of the recess 165 in the ZX cross section. Similarly, if the low-crystallinity portion of the third nitride semiconductor layer 142D is slightly etched, the cap layer 128 and the barrier layer 126 may be etched depending on the shape and size of the recess 165 in the ZX cross section. Furthermore, the degree of etching of the barrier layer 126 becomes nonuniform along the Y-axis. This causes the 2DEG concentration to become nonuniform along the Y-axis, and current tends to concentrate in areas with high 2DEG concentration and low electrical resistance. This can result in a decrease in breakdown voltage.

[0058] The distance L3 of the upper surface 163 from the lower surface 162 is greater than the first distance L0 between the upper surface 161 and the lower surface 162 of the first nitride semiconductor layer 120, which makes it easier to prevent etching of the barrier layer 126 and the channel layer 124 in the vicinity of the second nitride semiconductor layer 142S. For example, a recess 165, which will be described later, is formed above the cap layer 128 in the Z-axis direction, and therefore etching of the recess 165 is less likely to affect the cap layer 128 and the barrier layer 126. The distance L4 of the upper surface 164 from the lower surface 162 is greater than the first distance L0 between the upper surface 161 and the lower surface 162 of the first nitride semiconductor layer 120, which makes it easier to prevent etching of the barrier layer 126 and the channel layer 124 in the vicinity of the third nitride semiconductor layer 142D. For example, if a recess similar to recess 165 in second nitride semiconductor layer 142S is formed in third nitride semiconductor layer 142D, etching of the recess will be less likely to affect cap layer 128 and barrier layer 126 near third nitride semiconductor layer 142D. Note that first distance L0 may not be constant within nitride semiconductor device 100 due to factors such as the formation of first recess 140S and second recess 140D. If first distance L0 is not constant, the values ​​of distances L3 and L4 can be compared with the maximum value of first distance L0. Furthermore, in forming second nitride semiconductor layer 142S and third nitride semiconductor layer 142D, distances L3 and L4 may not be constant within nitride semiconductor device 100. If at least one of distances L3 and L4 is not constant, the value of first distance L0 can be compared with the minimum value of distances L3 and L4.

[0059] The distance L1 between the upper surface 161 and the upper surface 163 is, for example, not less than 5 nm and not more than 30 nm. When the distance L1 is 5 nm or more, etching of the barrier layer 126 and the channel layer 124 near the second nitride semiconductor layer 142S is easily prevented. Furthermore, when the distance L1 is 30 nm or less, an excessive step due to the first covering portion 144S is easily prevented. The distance L1 may be not less than 7 nm and not more than 28 nm, or may be not less than 10 nm and not more than 25 nm.

[0060] The distance L2 between the upper surface 161 and the upper surface 164 is, for example, not less than 5 nm and not more than 30 nm. When the distance L2 is 5 nm or more, etching of the barrier layer 126 and the channel layer 124 near the third nitride semiconductor layer 142D is easily prevented. Furthermore, when the distance L2 is 30 nm or less, an excessive step due to the second covering portion 144D is easily prevented. The distance L2 may be not less than 7 nm and not more than 28 nm, or may be not less than 10 nm and not more than 25 nm.

[0061] The top surfaces of the first covering portion 144S and the second covering portion 144D do not need to be flat, and may be inclined to conform to the sidewall surfaces of the first recess 140S and the second recess 140D, respectively. Furthermore, the top surface 163 of the second nitride semiconductor layer 142S, including the first covering portion 144S, may be flat, and the top surface 164 of the third nitride semiconductor layer 142D, including the second covering portion 144D, may be flat.

[0062] First nitride semiconductor layer 120 has a cap layer with upper surface 161, which can reduce gate leakage current and improve long-term reliability.

[0063] The length W1 of the first covering portion 144S in the X-axis direction is, for example, 30 nm or more and 200 nm or less. When the length W1 is 30 nm or more, etching of the barrier layer 126 and the channel layer 124 near the second nitride semiconductor layer 142S is easily prevented. Furthermore, when the length W1 is 200 nm or less, a short circuit between the gate electrode 50 and the second nitride semiconductor layer 142S is easily prevented. The length W1 may be 40 nm or more and 150 nm or less, or may be 50 nm or more and 100 nm or less.

[0064] The length W2 of the second covering portion 144D in the X-axis direction is, for example, 30 nm or more and 200 nm or less. When the length W2 is 30 nm or more, etching of the barrier layer 126 and the channel layer 124 near the third nitride semiconductor layer 142D is easily prevented. When the length W2 is 200 nm or less, a short circuit between the gate electrode 50 and the third nitride semiconductor layer 142D is easily prevented. The length W2 may be 40 nm or more and 150 nm or less, or may be 50 nm or more and 150 nm or less. The lengths W1 and W2 may be equal to or different from each other.

[0065] The electrical resistance of the second nitride semiconductor layer 142S and the electrical resistance of the third nitride semiconductor layer 142D are lower than the electrical resistance of the channel region 155, thereby making it possible to reduce the electrical resistance between the source electrode 44S and the drain electrode 44D.

[0066] By including n-type impurities in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, low electrical resistance can be easily obtained in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. The n-type impurity is not limited to Ge, and may be silicon (Si). The concentration of the n-type impurity is, for example, 1×10 20 cm -3 The concentration of n-type impurities is 1×10 20 cm -3 When the concentration of n-type impurities is 5×10 or more, it is easy to obtain a particularly low electrical resistance in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. 20 cm -3 May be greater than 1 x 10 21 cm -3 The concentration of n-type impurities may be 1×10 or more. 20 cm -3 The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D can be formed by, for example, sputtering, but it is difficult to form them by MOCVD. The concentration of n-type impurities can be measured by secondary ion mass spectrometry.

[0067] When the second nitride semiconductor layer 142S is provided in the first recess 140S and the third nitride semiconductor layer 142D is provided in the second recess 140D, the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are easily formed.

[0068] The insulating layer 130 is provided on the upper surface 161 and is in contact with the first covering portion 144S and the second covering portion 144D, so that the first nitride semiconductor layer 120 can be protected by the insulating layer 130.

[0069] Furthermore, in the first manufacturing method, the sizes of the first covering portion 144S and the second covering portion 144D can be adjusted during etching of the insulating layer 130 (see FIG. 5). On the other hand, in the second manufacturing method, the sizes of the first covering portion 144S and the second covering portion 144D can be adjusted during ashing of the mask (see FIG. 12).

[0070] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0071] 44D: Drain electrode 44S: Source electrode 50: Gate electrode 100: Nitride semiconductor device 110: Substrate 120: First nitride semiconductor layer 122: Buffer layer 124: Channel layer 126: Barrier layer 128: Cap layer 130: Insulating layer 130D, 130G, 130S, 132D, 132S, 201, 202: Aperture 140D: Second recess 140S: First recess 142D: Third nitride semiconductor layer 142S: Second nitride semiconductor layer 142X: Polycrystalline layer 144D: Second coating part 144S: First coated part 155: Channel region 161, 163, 164: Top surface 162: Bottom surface 165: Depression 200: Mask L0: 1st distance L1: distance L2: distance L3: Distance L4: Distance

Claims

1. a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis and having a first surface perpendicular to the first axis; a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis perpendicular to the first axis; and In a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion that covers a part of the first surface, the third nitride semiconductor layer has a second covering portion that covers a part of the first surface.

2. the first nitride semiconductor layer has a second surface opposite to the first surface, the second nitride semiconductor layer has a third surface that is at a greater distance from the second surface than a first distance between the first surface and the second surface; The nitride semiconductor device according to claim 1 , wherein said third nitride semiconductor layer has a fourth surface that is at a distance from said second surface greater than said first distance.

3. the distance between the first surface and the third surface is 5 nm or more and 30 nm or less; The nitride semiconductor device according to claim 2 , wherein the distance between said first surface and said fourth surface is not less than 5 nm and not more than 30 nm.

4. The nitride semiconductor device according to claim 1 , wherein the first nitride semiconductor layer has a cap layer that is provided with the first surface.

5. a length of the first covering portion in a direction along the second axis is equal to or greater than 30 nm and equal to or less than 200 nm; The nitride semiconductor device according to claim 1 , wherein the second covering portion has a length in the direction along the second axis of not less than 30 nm and not more than 200 nm.

6. the channel layer has a channel region containing a two-dimensional electron gas; 4. The nitride semiconductor device according to claim 1, wherein the electric resistance of said second nitride semiconductor layer and the electric resistance of said third nitride semiconductor layer are lower than the electric resistance of said channel region.

7. The nitride semiconductor device according to claim 1 , wherein said second nitride semiconductor layer and said third nitride semiconductor layer contain n-type impurities.

8. The concentration of the impurity is 1×10 ２０ cm －３ The nitride semiconductor device according to claim 7 .

9. a first recess and a second recess are formed in the first nitride semiconductor layer along the second axis, with the channel layer and the barrier layer sandwiched therebetween; the second nitride semiconductor layer is provided in the first recess; The nitride semiconductor device according to claim 1 , wherein the third nitride semiconductor layer is provided in the second recess.

10. The nitride semiconductor device according to claim 1 , further comprising an insulating layer provided on said first surface and in contact with said first covering portion and said second covering portion.

11. providing a first nitride semiconductor layer having a first surface, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis; forming a second nitride semiconductor layer and a third nitride semiconductor layer by a sputtering method, the second nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis perpendicular to the first axis; and In a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion that covers a part of the first surface, the third nitride semiconductor layer has a second covering portion covering a part of the first surface.

12. a step of forming a first recess and a second recess in the first nitride semiconductor layer along the second axis, the first recess and the second recess sandwiching the channel layer and the barrier layer therebetween, between the step of preparing the first nitride semiconductor layer and the step of forming the second nitride semiconductor layer and the third nitride semiconductor layer; the second nitride semiconductor layer is formed in the first recess; The method for manufacturing a nitride semiconductor device according to claim 11 , wherein the third nitride semiconductor layer is formed in the second recess.

13. between the step of forming the first nitride semiconductor layer and the step of forming the first recess and the second recess, forming an insulating layer on the first surface; forming a mask on the insulating layer, the mask having a first opening and a second opening; etching the insulating layer through the first opening and the second opening to form a third opening in the insulating layer, the third opening being connected to the first opening and larger than the first opening in a plan view, and a fourth opening in the insulating layer, the fourth opening being connected to the second opening and larger than the second opening in a plan view; and the first recess and the second recess are formed by etching through the first opening and the second opening, 13. The method for manufacturing a nitride semiconductor device according to claim 12, further comprising the step of removing the mask between the step of forming the first recess and the second recess and the step of forming the second nitride semiconductor layer and the third nitride semiconductor layer.

14. between the step of forming the first nitride semiconductor layer and the step of forming the first recess and the second recess, forming an insulating layer on the first surface; forming a mask on the insulating layer, the mask having a first opening and a second opening; etching the insulating layer through the first opening and the second opening to form a fifth opening connected to the first opening and a sixth opening connected to the second opening in the insulating layer; and the first recess and the second recess are formed by etching through the first opening and the second opening, between the step of forming the first recess and the second recess and the step of forming the second nitride semiconductor layer and the third nitride semiconductor layer, ashing the mask to widen the first opening and the second opening and expose a portion of the insulating layer through the first opening and the second opening; removing a portion of the insulating layer exposed through the first opening and a portion of the insulating layer exposed through the second opening; removing the mask after removing the portion of the insulating layer exposed from the first opening and the portion of the insulating layer exposed from the second opening; The method for manufacturing a nitride semiconductor device according to claim 12 , comprising:

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