Semiconductor device

Abstract

An object is to provide a novel semiconductor device with sufficiently reduced standby power.SOLUTION: A semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor including an oxide semiconductor material, and an integrated circuit, in which the first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor, the other of the source terminal and the drain terminal of the switching transistor is electrically connected to one of terminals of the integrated circuit, and the other of the terminals of the integrated circuit is electrically connected to the second power supply terminal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical field of the disclosed invention relates to a semiconductor device using an oxide semiconductor. A semiconductor device is a general term for devices that function by utilizing the characteristics of semiconductors. Semiconductor elements such as transistors, diodes, and thyristors (including so-called power devices) (including image sensors, memories, converters, and other integrated circuits, integrated circuits containing these, liquid crystal displays, Display devices, such as liquid crystal display devices, are broadly included in the category of semiconductor devices. [Background technology]

[0002] CMOS circuits have low power consumption, are capable of high-speed operation, and can be highly integrated. These features make it an essential component for semiconductor integrated circuits. With the miniaturization of MOS transistors, leakage current (off-state current, subthreshold voltage) The power consumption during non-operation (standby power consumption, hereafter referred to as standby power consumption) caused by the increase in For example, the increase in the channel length of 0.1 μm or less is becoming a problem. In miniaturized silicon MOS transistors, the gate-source potential is set to a value less than the threshold voltage. Even if the drain current is reduced, it is not possible to make the drain current zero.

[0003] In order to suppress the increase in standby power consumption caused by the leakage current as described above, A technique using a transistor has been proposed (see, for example, Patent Document 1). This technology uses a switch between the power supply and the CMOS circuit, which has a smaller leakage current than the CMOS circuit. When the CMOS circuit is not in operation, the switching transistor is turned on. The aim is to reduce standby power consumption by turning off the starter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 5-210976 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology disclosed in Patent Document 1, standby power is the leakage current of a switching transistor. In other words, the leakage current of the switching transistor must be kept small enough. This makes it possible to sufficiently reduce standby power consumption.

[0006] On the other hand, to ensure proper operation of the CMOS circuit, sufficient Therefore, a switching transistor such as that disclosed in Patent Document 1 is required. When a transistor is provided, it is necessary to supply sufficient current to the CMOS circuit to ensure its operation. In order to achieve this, the channel width of the switching transistor is set to the same as that of the transistors that make up the CMOS circuit. Therefore, the width of the signal must be equal to or greater than the channel width of the master.

[0007] For the above reasons, the channel width of the switching transistor is set to the value of the width of the semiconductor device that constitutes the integrated circuit. The transistor channel width is made smaller to reduce the leakage current of the switching transistor itself. suppression is not a realistic approach.

[0008] In this way, the technology disclosed in Patent Document 1 makes the standby power consumption of the CMOS circuit substantially zero. For this reason, in an integrated circuit that is made up of a collection of many circuits, The small standby power consumption of each circuit that makes up an integrated circuit accumulates to a large amount of standby power. This can cause problems.

[0009] In view of the above problems, it is an object of the present invention to provide a new semiconductor device that sufficiently reduces standby power consumption. It shall be one. [Means for solving the problem]

[0010] In the disclosed invention, a semiconductor device (e.g., a transistor) is fabricated using a highly purified oxide semiconductor. A transistor made of a highly purified oxide semiconductor Since the transistor current is extremely small, it is possible to increase the on / off ratio sufficiently. Even if the current driving capability of the transistor is sufficiently ensured, it is not possible to suppress the leakage current to an extremely low level. It is possible to do this.

[0011] By using the oxide semiconductor as described above in the following configuration, the standby power of the semiconductor device can be reduced. It is possible to sufficiently suppress it.

[0012] For example, one embodiment of the disclosed invention is a semiconductor device including a first power supply terminal, a second power supply terminal, and an oxide semiconductor. a switching transistor using the material, and an integrated circuit, , one of the source terminal and the drain terminal of the switching transistor is electrically connected The other of the source terminal or the drain terminal of the switching transistor and the integrated One of the terminals of the circuit is electrically connected to the other terminal of the integrated circuit and the second power supply terminal are electrically connected semiconductor devices.

[0013] Another embodiment of the disclosed invention is a semiconductor device including a first power supply terminal, a second power supply terminal, and an oxide semiconductor. a switching transistor using a dielectric material and having a first control terminal and a second control terminal; an integrated circuit, the first power supply terminal and the source terminal of the switching transistor The source or drain terminal of the switching transistor is electrically connected to the The other of the terminals or the drain terminal is electrically connected to one of the terminals of the integrated circuit, and the integrated The other terminal of the circuit is electrically connected to the second power supply terminal of the semiconductor device.

[0014] The switching transistor includes an oxide semiconductor layer made of an oxide semiconductor material and a A gate electrode that applies an electric field to the conductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer. Also, it is preferable to have a gate electrode that controls the threshold voltage of the switching transistor. Here, the gate electrode is an electrode corresponding to the control terminal, and the source electrode is a The drain electrode is an electrode that corresponds to a drain terminal. As long as the circuit operation is not hindered, the various electrodes and the various terminals do not have to be the same. For example, if there is some element ( Wiring, switching elements, resistor elements, inductors, capacitors, and other various functions In some cases, other components (such as a resistor) may be connected.

[0015] The oxide semiconductor material may be an In-Ga-Zn-O based oxide semiconductor material. stomach.

[0016] In addition, the leakage current of the switching transistor is 1×10 -13 A or less can.

[0017] The integrated circuit can be formed using a semiconductor material other than an oxide semiconductor material. The semiconductor material other than the oxide semiconductor material may be silicon.

[0018] Integrated circuits also include CMOS circuits.

[0019] In this specification, the terms "above" and "below" refer to the positional relationship of a component, such as "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" is not limited to "directly under" the gate insulating layer. If the expression "electrode" is used, it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely expressions used for the convenience of explanation, and Unless otherwise specified, this also includes the reversed top and bottom.

[0020] In addition, the terms "electrode" and "wiring" used in this specification refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes." This also includes cases where the "wiring" is formed integrally.

[0021] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0022] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a wire. is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between the connection objects.

[0023] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0024] In the disclosed invention, a highly purified oxide semiconductor is used for a semiconductor device. It is necessary to remove hydrogen from the oxide semiconductor layer as much as possible, or It supplies oxygen that is lacking in the body and fills the energy gap caused by oxygen deficiency in oxide semiconductors. The concept includes at least one of reducing the defect level in the silicon substrate.

[0025] The above-mentioned purification is performed to make the oxide semiconductor layer intrinsic (i-type). Since nitride semiconductors are generally n-type, transistors made using them have a leakage current In one embodiment of the disclosed invention, in order to sufficiently reduce the leakage current, The compound semiconductor is highly purified to become i-type or close to it.

[0026] A semiconductor device is manufactured by using at least a part of the oxide semiconductor highly purified as described above. By configuring the above, a semiconductor device that sufficiently suppresses standby power consumption can be realized. It can be said that the effect of power reduction becomes greater as the circuit becomes more complex. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a circuit diagram of an example of a semiconductor device. [Figure 2] 1A and 1B are a cross-sectional view and a plan view of an example of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram of an example of a semiconductor device. [Figure 7] FIG. 1 is a cross-sectional view of an example of a semiconductor device. [Figure 8] FIG. 1 is a block diagram illustrating an example of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 11] 1A and 1B are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0028] The embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above and may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents described.

[0029] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily accurate to facilitate understanding. It may not represent the actual position, size, range, etc. Therefore, the disclosed invention The position, size, range, etc. are not necessarily limited to those disclosed in the drawings.

[0030] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid any unnecessary errors and are not intended to limit the number of errors.

[0031] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. 1 to 5. Note that in the circuit diagrams, To indicate that it is a transistor, the symbol OS may also be added.

[0032] <Circuit Configuration and Operation of Semiconductor Device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. FIG. 1(A) shows the simplest CMOS circuit. FIG. 1(B) shows an example of a semiconductor device using a CMOS inverter circuit. 1 is an example of a semiconductor device having a plurality of inverter circuits.

[0033] The semiconductor device shown in FIG. 1A includes a power supply terminal VH, a power supply terminal VL, and a gate electrode made of an oxide semiconductor material. The switching transistor S1 and the CMOS inverter circuit C1 are used. The switching transistor S1 is typically an n-channel transistor using an oxide semiconductor. A high potential is supplied to the power supply terminal VH, and a low potential is supplied to the power supply terminal VL. do.

[0034] Here, the power supply terminal VH and the solenoid of the p-channel transistor of the CMOS inverter circuit C1 The p-channel CMOS inverter circuit C1 is electrically connected to the source terminal. The drain terminal of the n-channel transistor of the CMOS inverter circuit C1 is The drain terminal of the CMOS inverter circuit C1 is electrically connected to the output terminal OU of the CMOS inverter circuit C2. In addition, the source of the n-channel transistor of the CMOS inverter circuit C1 is The drain terminal of the switching transistor S1 is electrically connected to the drain terminal of the switching transistor S1. The source terminal of the switching transistor S1 and the power supply terminal VL are electrically connected. The gate terminal of the p-channel transistor of the CMOS inverter circuit C1 is and the gate terminal of the n-channel transistor of the CMOS inverter circuit C1 are electrically and serves as the input terminal IN of the CMOS inverter circuit C1.

[0035] When the semiconductor device is in operation, a high potential is applied to the control terminal S_IN of the switching transistor S1. In this state, a high voltage is applied to the input terminal IN, and the switching transistor S1 is turned on. When either high or low potential is input, high or low potential is generated depending on the potential. For example, when the potential input to the input terminal IN is high, In this case, the p-channel transistor of the CMOS inverter circuit C1 is turned off, and the CMOS inverter Since the n-channel transistor of the inverter circuit C1 is turned on, The input terminal I outputs a low potential corresponding to the potential supplied to the power supply terminal VL. When the potential input to N is low, the p-channel transistor of the CMOS inverter circuit C1 The n-channel transistor of the CMOS inverter circuit C1 turns on and the n-channel transistor of the CMOS inverter circuit C2 turns off. Therefore, the CMOS inverter circuit C1 outputs a voltage corresponding to the potential supplied to the power supply terminal VH. It outputs a high voltage.

[0036] When the semiconductor device is not in operation, a low voltage is applied to the control terminal S_IN of the switching transistor S1. The switching transistor S1 is turned off. The current (leakage current) flows through the CMOS inverter circuit C1 and the switching transistor Since it is controlled by the combined resistance of S1, the resistance of the switching transistor S1 when it is off By sufficiently increasing the leakage current of the switching transistor S1, This allows the power consumption when not in operation (standby power consumption, hereinafter also referred to as standby power) to be sufficiently small. It is possible.

[0037] A transistor using an oxide semiconductor material is characterized by an extremely low off-state current. For example, in a fully intrinsic (i-type) oxide semiconductor, the carrier density is, for example, , 1×10 12 / cm 3 Less than 1.45 x 10 10 / cm 3 Less than For example, when the drain voltage Vd is +1 V or +10 V, the off-state current of the transistor is Therefore, when the gate voltage Vg is in the range of -5V to -20V, -13 It will be A or below. Therefore, by configuring the switching transistor S1 using an oxide semiconductor, It is possible to sufficiently reduce the leakage current of the device. When using a compound semiconductor, the leakage current at room temperature is 1×10 -20 A(10zA(Zepto Ampere) to 1 x 10 -19 A (100zA) can be reduced. That is, it is even possible to make the leakage current substantially zero. Even if the channel width of transistor S1 is relatively large, the magnitude of the leakage current remains the same. That is, a transistor using an oxide semiconductor material does not have sufficient current driving capability. This makes it possible to suppress leakage current while ensuring sufficient power, thereby reducing the power consumption of the semiconductor device.

[0038] The semiconductor device shown in FIG. 1B is a semiconductor device shown in FIG. 1A, in which a CMOS inverter is used. The inverter circuit C1 is replaced with multiple CMOS inverter circuits C1 to Cn. do.

[0039] That is, the semiconductor device shown in FIG. 1B includes a power supply terminal VH, a power supply terminal VL, and an oxide semiconductor. A switching transistor S1 made of a conductive material and CMOS inverter circuits C1 to Cn (also simply referred to as an integrated circuit). Each CMOS inverter circuit has , input terminals I1 to In, and output terminals O1 to On. The connection relationship of each element is as follows: The difference from FIG. 1(A) is that the plurality of CMOS inverter circuits C1 to Cn are connected in parallel, and each CMOS inverter circuit is connected to the power supply terminal VH and the switch The point where the switching transistor S1 is connected to the CMOS inverter circuit C If the circuit in which 1 to Cn are connected in parallel is considered as one integrated circuit, then the switching transistor S The drain terminal of the first transistor is electrically connected to one of the terminals of the integrated circuit, and the drain terminal of the first transistor is electrically connected to another of the terminals of the integrated circuit. It can also be said that the power supply terminal VH is electrically connected to the power supply terminal VH.

[0040] The operation of the above circuit is the same as that of Figure 1(A). However, each input terminal has At the point where a potential is input and a corresponding potential is output from the output terminal, ) is different from

[0041] As described above, the present invention uses an oxide semiconductor, particularly a highly purified oxide semiconductor, at least in part. By configuring the semiconductor device in this way, a semiconductor device in which standby power consumption is sufficiently reduced can be realized. Previous technology has been developed that can achieve substantially zero leakage current while ensuring proper operation of the semiconductor device. degree (e.g., 1×10 -13 It was difficult to reduce the level to A or below. In this respect, the disclosed invention is excellent. In particular, in a circuit that is complex and has many integrated circuits, Even if the standby power consumption of each circuit is small, the total amount becomes large. The effect of reducing standby power consumption to a level that can be called essentially zero is achieved by the circuit This phenomenon becomes more pronounced as the system becomes more integrated and complex.

[0042] Although an example of a semiconductor device using a CMOS inverter circuit has been described here, One aspect of the disclosed invention is not limited to this. It can be used for any circuit (integrated circuit) where power is an issue. .

[0043] The above explanation is for the case where an n-channel switching transistor S1 is used. However, a p-channel transistor is used for the switching transistor S1. In this case, for example, the switching transistor S1 may be It is preferable to electrically connect the transistor to the p-channel type transistor of the OS inverter circuit.

[0044] <Planar and cross-sectional configurations of semiconductor device> 2 shows an example of the configuration of the semiconductor device shown in FIG. 2(A) shows a cross section of the semiconductor device, and FIG. 2(B) shows a plan view of the semiconductor device. , corresponds to the cross section taken along A1-A2-A3 in FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 ( The CMOS inverter circuit C1 is made up of a transistor and an oxide semiconductor is used on the top. Transistor 162 (a transistor that functions as a switching transistor S1) The transistor 160 and the transistor 162 are both The explanation will be given assuming that the transistor is an n-channel type, but the CMOS inverter circuit has a p It goes without saying that a channel type transistor is also used. The technical idea of ​​the invention is to switch transistors using oxide semiconductors to reduce power consumption. Since the purpose is to use the semiconductor device as a switching transistor, the specific configuration of the semiconductor device will be shown here. There is no need to limit it to anything.

[0045] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 provided so as to sandwich the channel forming region 116. The pure region 120 (collectively referred to as the impurity region) and the channel forming region 11 6, and a gate electrode provided on the gate insulating layer 108. 110 and a source or drain electrode 130a electrically connected to the impurity region 114. , and a source electrode or a drain electrode 130b.

[0046] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, a high A high concentration impurity region 120 is provided, and a metal compound region 124 is provided on the high concentration impurity region 120. In addition, an element isolation insulating layer 106 is formed on the substrate 100 so as to surround the transistor 160. The transistor 160 is covered with an interlayer insulating layer 126 and an interlayer insulating film. A source or drain electrode 130a, a source or drain electrode 130b, a The drain electrode 130b is formed through an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or the drain electrode is electrically connected to the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are formed in the metal compound region 124. The semiconductor layer 112 is electrically connected to the high concentration impurity region 120 and the impurity region 114 via the junction.

[0047] The transistor 162 includes a gate electrode 136c provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136c, and a gate insulating layer 138 is provided on the gate insulating layer 138. an oxide semiconductor layer 140; and a metal oxide film provided on the oxide semiconductor layer 140. The source or drain electrode 142a is electrically connected to the source or drain electrode 142b. and an inner electrode 142b.

[0048] Here, the gate electrode 136c is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136c, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrodes 136b are formed in contact with the respective electrodes.

[0049] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150c and 150d are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150c and 150d, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer Electrode 150a contacts electrodes 136a and 136b through an opening in layer 146. , electrode 150b is formed.

[0050] Here, the oxide semiconductor layer 140 is formed from a material from which impurities such as hydrogen have been sufficiently removed or from which sufficient oxidation has been achieved. It is desirable that the raw material be highly purified by supplying it. The hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 atoms / cm 3 The following is desirable: 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The hydrogen concentration is sufficiently reduced to achieve high purity, and oxygen deficiency is prevented by supplying sufficient oxygen. In the oxide semiconductor layer 140 in which the defect levels in the energy gap due to the depletion are reduced, Carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Less than, Preferably 1.45 x 10 10 / cm3 For example, if the drain voltage Vd is +1 When the gate voltage Vg is in the range of -5V to -20V, the The current is 1×10 -13 A or less. The off-resistivity is 1×10 9 Ω·m or more, desired Or 1 x 10 10 In this way, the intrinsic (i-type) or substantially intrinsic By using a functionalized oxide semiconductor, a transistor with excellent off-state current characteristics was developed. The hydrogen concentration in the oxide semiconductor layer 140 can be determined by the secondary ion Secondary ion mass spectrometry (SIMS) py).

[0051] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, and 154c are provided so that the electrodes are embedded in the liquid. Electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150b and electrode 150c. Electrode 154c is in contact with electrode 150d.

[0052] That is, in the semiconductor device shown in FIG. 2, the source electrode or the drain electrode of the transistor 160 The source electrode 130b and the source or drain electrode 142a of the transistor 162 are Electrically connected via electrode 136b, electrode 150b, electrode 154b and electrode 150c It is being done.

[0053] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The method for fabricating the transistor 160 will be explained with reference to FIG. A method for manufacturing the capacitor 162 will be described with reference to FIGS.

[0054] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate in which silicon semiconductor is formed on an insulating surface. It refers to a substrate having a structure in which a conductor layer is provided, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. The concept also includes substrates having semiconductor layers made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is configured such that a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes:

[0055] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of the transistor, an impurity that gives n-type conductivity is added. The substrate 100 may be doped with an element or an impurity element that imparts p-type conductivity. In the case of a capacitor, impurities that give it n-type conductivity include, for example, phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Umium, gallium, etc. can be used.

[0056] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0057] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. There are several methods for removing the insulating layer, such as polishing processes like CMP and etching processes. Either of them may be used. After the semiconductor region 104 is formed or after the element isolation insulating layer After forming 106, the protective layer 102 is removed.

[0058] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0059] The insulating layer will later become the gate insulating layer and is obtained using a CVD method, sputtering method, etc. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, oxide It is preferable to use a single layer or multilayer structure of a film containing tantalum chloride or the like. The surface of the semiconductor region 104 is oxidized or nitrided by thermal oxidation or thermal oxidation. An insulating layer may be formed. The high density plasma treatment may be performed using, for example, He, Ar, Kr, Xe, etc. This is done using a mixture of rare gases such as oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. It can be below.

[0060] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material will be described. This shall be shown.

[0061] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 3(C)).

[0062] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 3(C)). Phosphorus (P) or arsenic (As) is added to the conductive region 104 to form a shallow junction with the substrate 100. In this case, an n-type transistor is formed. However, when forming a p-type transistor, Impurity elements such as boron (B) and aluminum (Al) may be added. By forming the gate insulating layer 108 in the semiconductor region 104, a channel forming region 114 is formed. A region 116 is formed (see FIG. 3(C)). Here, the concentration of the added impurity is appropriately set. However, when semiconductor elements are highly miniaturized, the concentration can be increased. In this case, the impurity region 114 is formed after the insulating layer 112 is formed. However, the process of forming the insulating layer 112 after forming the impurity region 114 is also adopted. You can do that.

[0063] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is advisable to expose the top surface of 14.

[0064] Next, a layer is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. An insulating layer is formed on the impurity region 114. Then, phosphorus ( By adding ions such as P and arsenic (As), a high concentration impurity region 120 is formed (see FIG. 3(E)). After that, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, A metal layer 122 is formed so as to cover the high concentration impurity region 120 and the like (see FIG. 3(E)). The metal layer 122 can be formed by using various film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed by reacting with the semiconductor material that constitutes the semiconductor region 104. It is desirable to form the layer using a metal material that reacts with the metal to form a low-resistance metal compound. Examples of metal materials include titanium, tantalum, tungsten, nickel, cobalt, and white. There is money etc.

[0065] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0066] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize heat treatment in a very short time. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0067] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the structure is a two-layer structure of the layer 126 and the interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is subjected to a CMP or etching process. It is desirable to flatten it.

[0068] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 3(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. can be formed by removing

[0069] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also maintains the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, it is possible to This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0070] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, An electrode in contact with the source electrode 110 can also be formed. The drain electrode 130a can be used as a source electrode or a drain electrode 130b. There is no particular limitation on the material, and various conductive materials can be used. Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium A conductive material such as aluminum can be used.

[0071] In this manner, the transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, insulating layers, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0072] <Method of manufacturing the upper transistor> Next, referring to FIGS. 4 and 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0073] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 132 is formed on the drain electrode 130b (see FIG. 4(A)). It can be formed by using a VD method, a CVD method, etc. Also, silicon oxide, silicon oxynitride, etc. Inorganic insulating materials such as silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The material may be formed using a material containing a metal.

[0074] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 are An opening is formed that reaches the drain electrode 130b. At this time, the gate electrode 136c is formed later. An opening is also formed in the region where the conductive layer is to be formed. The opening is formed by etching or the like using a mask (see FIG. 4(B)). The mask can be formed by a method such as exposure using a photomask. The etching method can be wet etching or dry etching. However, from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 134 can be formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 134 include molybdenum, titanium, Conductors such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium Examples of the conductive materials include conductive materials, alloys thereof, and compounds (for example, nitrides).

[0075] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as the native oxide film) on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode) is and reducing the contact resistance with the source or drain electrodes 130a, 130b, etc. In addition, the titanium nitride film formed afterwards suppresses the diffusion of the conductive material. It also has a barrier function that prevents the formation of a barrier film made of titanium or titanium nitride. Alternatively, a copper film may be formed by plating.

[0076] After the conductive layer 134 is formed, the conductive layer 134 is removed by etching or CMP. 34 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and gate An electrode 136c is formed (see FIG. 4C). When forming the electrodes 136a, 136b, and gate electrode 136c, the surface becomes flat. In this way, the insulating layer 132, the electrode 136a, and the electrode 136 b) By planarizing the surface of the gate electrode 136c, a good electrode can be obtained in the subsequent process. , it becomes possible to form wiring, insulating layers, semiconductor layers, etc.

[0077] Next, the insulating layer 132, the electrode 136a, the electrode 136b, and the gate electrode 136c are covered with The gate insulating layer 138 is formed (see FIG. 4(D)). The gate insulating layer 138 is formed by a CVD method or The gate insulating layer 138 can be formed by a sputtering method or the like. silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide It is preferable that the gate insulating layer 138 is formed to include the above. The thickness of the gate insulating layer 138 is not particularly limited, but For example, the thickness can be set to 10 nm or more and 500 nm or less. In the case of a laminated structure, for example, a first gate insulating layer having a thickness of 50 nm or more and 200 nm or less; It is preferable to form a second gate insulating layer having a thickness of 5 nm to 300 nm.

[0078] Note that an oxide semiconductor (high Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When using such an oxide semiconductor for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high High quality will be required.

[0079] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made into a good one.

[0080] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering or plasma CVD may be used. In addition, the film quality and the interface with the oxide semiconductor layer can be improved by heat treatment after the formation. In either case, the film quality is good and The gate insulating layer 138 may be formed so as to reduce the interface state with the oxide semiconductor layer.

[0081] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 4(E)).

[0082] The oxide semiconductor layer is preferably formed by a sputtering method. The In-Sn-Ga-Zn-O system, which is a binary metal oxide, and the In- Ga-Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Z nO system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, and binary metal oxides. In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn- Mg-O system, In-Mg-O system, and single-element metal oxides such as In-O system, Sn-O system, and Z The film can be formed using a metal oxide such as nO. For example, a target containing 2% by weight or more and 10% by weight or less of SiO2 may be used. A semiconductor layer may be formed.

[0083] Among these, by using In-Ga-Zn-O based metal oxides, the resistance in the absence of an electric field is sufficiently low. and a semiconductor device with sufficiently high and sufficiently small off-state current, and a semiconductor device with high field-effect mobility. Therefore, the In-Ga-Zn-O metal oxide is suitable for semiconductor devices. It is suitable as a semiconductor material to be used.

[0084] A typical example of an In-Ga-Zn-O metal oxide is InGaO3(ZnO). m (m >0). Also, M is used instead of Ga, and InMO3(ZnO) is used. m There are metal oxides that are written as (m>0), where M is gallium (Ga), Aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (C o) represents one or more metal elements selected from the following. For example, M is: Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. can be applied. Note that the above composition is derived from the crystal structure. It should be noted that this is merely an example.

[0085] In this embodiment, the oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor film forming tank. The film is formed by sputtering using a target.

[0086] The oxide semiconductor layer is formed by holding a substrate in a treatment chamber kept in a reduced pressure state, and adjusting the substrate temperature to Preferably, the temperature is 100°C or higher and 600°C or lower, more preferably 200°C or higher and 400°C or lower. Here, the oxide semiconductor layer is formed while the substrate is heated. The impurity concentration in the oxide semiconductor layer can be reduced, and damage to the oxide semiconductor layer due to sputtering can be prevented. can be alleviated.

[0087] Then, the remaining moisture in the processing chamber is removed and sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor layer is formed using a metal oxide as a target. The atmosphere may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically It is preferable to use a mixed atmosphere of hydrogen (or argon) and oxygen. The concentration of impurities such as water, hydroxyl groups, and hydrides is on the order of several ppm (preferably on the order of several ppb). It is preferable to use a high purity gas atmosphere in which even the minimum amount of oxygen has been removed.

[0088] Here, in order to remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump may be used. In addition, the exhaust means can be a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms, water ( Compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) such as HO are exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor layer formed in the deposition chamber can be reduced. .

[0089] The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0090] In addition, by using a pulsed direct current (DC) power supply in the deposition of the oxide semiconductor layer, the deposition It reduces the amount of powdery material (also called particles or dust) that sometimes occurs, and also ensures uniform film thickness distribution. It can be said that:

[0091] The sputtering conditions for the oxide semiconductor layer are, for example, the distance between the substrate and the target. The distance was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was oxygen ( The conditions that can be applied are an atmosphere with an oxygen flow rate of 100%.

[0092] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen atmosphere, helium atmosphere, oxygen atmosphere, etc. can be used instead of argon atmosphere. An atmosphere or the like may also be used.

[0093] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable etching, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The etching time, temperature, etc. may be set appropriately.

[0094] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride fluorine (CCl4, etc.) and gases containing fluorine (fluorine-based gases, for example, tetrafluorine Carbon fluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and helium (H e) or a gas to which a rare gas such as argon (Ar) is added may also be used.

[0095] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0096] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. That's fine.

[0097] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The oxide semiconductor layer can be dehydrated or dehydrogenated by the first heat treatment. The temperature is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and 700°C or lower. The substrate is placed in an electric furnace using a heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the air. Ensure that hydrogen (including water) is not re-mixed.

[0098] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may be a device that heats the object to be treated by thermal radiation. For example, a LRTA (Lamp Rapid Thermal Anneal (GRTA) equipment, RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0099] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is removed from the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Since this is a heat treatment, when using a substrate with low heat resistance such as a glass substrate, distortion of the substrate may occur. This makes it possible to apply the method even under temperature conditions exceeding the melting point.

[0100] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain hydrogen, water, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0101] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. In addition, the semiconductor layer may contain crystals. Depending on the material of the conductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. .

[0102] In addition, by providing a crystalline layer on the amorphous surface, the electrical characteristics of the oxide semiconductor layer can be changed. For example, it is possible to form a crystal layer in which crystal grains having electrical anisotropy are oriented. By this, the electrical properties of the oxide semiconductor layer can be changed. Because of their shape, they are sometimes called plate crystals.

[0103] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0104] Note that the first heat treatment has a dehydrogenation (dehydration) effect on the oxide semiconductor layer 140. Therefore, it can also be called dehydrogenation treatment (dehydration treatment). After the oxide semiconductor layer is formed, a source electrode or a drain electrode is laminated on the oxide semiconductor layer 140. After forming a protective insulating layer on the source electrode or drain electrode, This process can be performed multiple times. is also good.

[0105] In addition, it is possible to obtain an oxide semiconductor layer in which hydrogen is sufficiently reduced by controlling the deposition atmosphere or the like. In such cases, the first heat treatment may be omitted.

[0106] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. Depending on the material and etching conditions, , a part of the oxide semiconductor layer 140 is etched to form an oxide semiconductor layer having a groove (a recess). This can sometimes happen.

[0107] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the above elements Alloys containing manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, one or more materials selected from the group consisting of aluminum and thorium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a single element selected from the group consisting of aluminum and a combination of multiple elements may be used. It may have a single layer structure or a laminated structure of two or more layers. Single-layer aluminum film structure, two-layer aluminum film with titanium film laminated on top, titanium Examples of such a structure include a three-layer structure in which a film, an aluminum film, and a titanium film are laminated.

[0108] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0109] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the The distance between the source electrode or the drain electrode 142b and the lower end of the channel When exposure is performed with a length (L) of less than 25 nm, the wavelength is extremely low, ranging from several nm to several tens of nm. Extreme ultraviolet light with short wavelengths is used for etching. Exposure using extreme ultraviolet light provides high resolution and a large depth of focus. Therefore, the channel length (L) of the formed transistor is set to 10 nm or more and 1000 nm or less. This makes it possible to increase the operating speed of the circuit and reduce power consumption. do.

[0110] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adhered water and other substances are removed. In addition, gases containing oxygen, such as a mixture of oxygen and argon, In this case, oxygen is supplied to the oxide semiconductor layer, and plasma treatment using a gas is performed. It is possible to reduce defect levels in the energy gap caused by oxygen deficiency.

[0111] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 4(G)).

[0112] The protective insulating layer 144 is formed by mixing impurities such as hydrogen and water into the protective insulating layer 144 using a method such as sputtering. The thickness of the film is 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, Silicon oxynitride, etc. The structure may be a single layer structure or a multilayer structure. The substrate temperature when forming the protective insulating layer 144 is set to be equal to or higher than room temperature and equal to or lower than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. A mixed atmosphere of gas (typically argon) and oxygen is preferred.

[0113] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer 140 or may be dissolved in water. The oxygen in the oxide semiconductor layer 140 is extracted by the oxygen. The back channel side of the gate electrode becomes low in resistance, which may result in the formation of a parasitic channel. Therefore, in order to prevent the protective insulating layer 144 from containing as much hydrogen as possible, the method for forming the protective insulating layer 144 is It is preferable not to use it.

[0114] For example, when the protective insulating layer 144 is formed by sputtering, the sputtering gas is water. The concentration of impurities such as silicon, water, hydroxyl groups, and hydrides is on the order of several ppm (preferably on the order of several ppb). ) high-purity gases that have been removed to the point of being 100% pure must be used. Also, any residual moisture in the processing chamber must be removed. is desirable.

[0115] In this embodiment, an insulating layer containing silicon oxide is formed as the protective insulating layer 144 by a sputtering method. Therefore, it is formed.

[0116] Then, a second heat treatment (preferably 20 It is desirable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The second heat treatment can reduce the variation in the electrical characteristics of the transistor. Oxygen is supplied from the insulating layer containing oxygen to the oxide semiconductor layer, and energy due to oxygen deficiency is released. It is also possible to reduce the defect level in the gap. However, the atmosphere may be air. It is desirable to use an atmosphere that is free of hydrogen and water to prevent hydrogen from being mixed in. The heat treatment in step 2 is not an essential step and may be omitted.

[0117] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide After the interlayer insulating layer 146 is formed, the insulating layer 146 can be formed using a material containing an inorganic insulating material such as It is desirable to flatten the surface by a method such as CMP or etching. stomach.

[0118] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, source or drain electrode 142a, source or drain electrode An opening is formed that reaches the inner electrode 142b, and the conductive layer 148 is formed so as to fill the opening. (See FIG. 5(B)). The opening is formed by etching using a mask. The mask can be formed by a method such as exposure using a photomask. Etching can be either wet etching or dry etching. However, from the viewpoint of fine processing, it is preferable to use dry etching. The material used for the conductive layer 148 and the method for forming the conductive layer 148 are the same as those for the conductive layer 134. Therefore, the description of the conductive layer 134 can be referred to.

[0119] After the conductive layer 148 is formed, the conductive layer 148 is removed by a method such as etching or CMP. 150a, 150b, and 150c are removed to expose the interlayer insulating layer 146. 50c and an electrode 150d are formed (see FIG. 5(C)). When forming the electrodes 150a, 150b, 150c, and 150d by removing the layers, It is desirable to process the surface so that it is flat. By planarizing the surfaces of the electrodes 150a, 150b, 150c, and 150d, In subsequent processes, it becomes possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc. do.

[0120] Thereafter, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, an opening is formed that reaches the electrode 150d. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP to form an insulating layer. The edge layer 152 is exposed to form electrodes 154a, 154b, and 154c (FIG. 5). (See (D)). This process is the same as that for forming the electrodes 136a, 150a, etc. Therefore, details will be omitted.

[0121] When the transistor 162 is manufactured by the above method, the hydrogen concentration in the oxide semiconductor layer 140 is Degrees are 5 x 10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The following is true, and the transistor The off current of 162 is 1×10 -13 A or less, and the off-resistivity is 1×10 9 Ω m or more ( or 1×10 10 In this way, the hydrogen concentration is sufficiently reduced and the purity is high. oxide semiconductors in which defect levels in the energy gap caused by oxygen deficiency are reduced By using such a material, the transistor 162 can have excellent characteristics.

[0122] Note that in this embodiment, a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor are The semiconductor device having a stacked structure with a transistor using a semiconductor material has been described. The structure that can be clearly used is not limited to the laminated structure. A single layer structure may also be used. For example, an oxide semiconductor has a relatively high field-effect mobility. Therefore, semiconductor devices with a single layer structure or a stacked structure using only oxide semiconductors as semiconductor materials are In particular, when a crystalline oxide semiconductor is used, the field effect Mobility μ is μ>100cm 2 / V·s is possible, and the semiconductor is made only of oxide semiconductors. In this case, the device is a practical one. It is possible to form a device.

[0123] In addition, the arrangement and connection of electrodes (wiring), insulating layers, semiconductor layers, etc., wiring width, channel width, Various parameters such as channel length and other conditions are required for semiconductor integrated circuits. For example, when a semiconductor device is formed in a single layer structure, The configuration of electrodes and wiring in the case of a laminated structure is significantly different from that in the case of a laminated structure.

[0124] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0125] (Embodiment 2) In this embodiment, a semiconductor device having a different configuration from the semiconductor device shown in the previous embodiment is used. The arrangement will be described with reference to FIGS. 6 and 7. FIG.

[0126] <Circuit Configuration and Operation of Semiconductor Device> 6A and 6B show examples of circuit configurations of semiconductor devices according to this embodiment. This is an example of a semiconductor device using a CMOS inverter circuit, which is a simple CMOS circuit. B) is an example of a semiconductor device having a plurality of CMOS inverter circuits.

[0127] The difference between the semiconductor device shown in FIG. 6 and the semiconductor device shown in FIG. 1 is that the semiconductor device shown in FIG. The difference between the semiconductor device shown in FIG. In this device, the switching transistor S1 has a back gate, so that the back gate By controlling the potential of the gate, the threshold voltage of the switching transistor S1 is controlled. This reduces the leakage current when the device is off to a level that can be said to be virtually zero. It becomes easier to control.

[0128] In this embodiment, as described above, the switching transistor S1 has a back gate. Therefore, there are two control terminals, control terminal S_IN_1 and control terminal S_IN_2. As in the previous embodiment, a high potential or a low potential is input to the control terminal S_IN_1. The control terminal S_IN_ The potential input to 2 is set so that the threshold voltage of the switching transistor S1 becomes the desired value. There is no particular limitation as long as the potential is such that a constant potential or a fluctuating potential may be input. Alternatively, a potential such as a ground potential may be used.

[0129] Other configurations and operations are the same as those shown in the previous embodiment. Omitted.

[0130] <Planar and cross-sectional configurations of semiconductor device> FIG. 7 is a cross-sectional view showing an example of the configuration of the semiconductor device shown in FIG. 6(A). The device has a transistor 160 (CMOS inverter) made of a material other than an oxide semiconductor at the bottom. The transistors constituting the data circuit C1 are oxide semiconductor transistors on the top. The transistor 162 (which functions as the switching transistor S1) 2. The semiconductor device shown in FIG. 2 and the semiconductor device shown in FIG. The difference between the semiconductor devices is whether or not the semiconductor device has a gate electrode 145 in addition to the gate electrode 136c. It is.

[0131] The details of each component are the same as those of the semiconductor device shown in the previous embodiment. The gate electrode 145 provided on the insulating layer 144 in a region overlapping with the oxide semiconductor layer 140 is , has the function of generating an electric field for controlling the threshold voltage of the transistor 162. This reduces the leakage current when the transistor 162 is off to a level that can be said to be substantially zero. In this case, the gate electrode 136c is used to The gate electrode 145 controls the threshold voltage by switching the transistor 162 on and off. However, these roles can be reversed. 4 also functions as a gate insulating layer.

[0132] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0133] (Embodiment 3) In this embodiment, an integrated semiconductor device which is another embodiment of the disclosed invention will be described. The following description will be given with reference to FIG.

[0134] FIG. 8 shows an integrated semiconductor device which is a modification of the semiconductor device shown in the previous embodiment (for example, embodiment 1). 1 shows an integrated semiconductor device 170. A specific example of the integrated semiconductor device 170 is a CP Examples include U and MPU.

[0135] The semiconductor device 170 includes a plurality of circuit blocks such as a circuit block 171 to a circuit block 174. Each circuit block is composed of a switching element 181, a switch The current flows through an element that uses an oxide semiconductor at least in part, such as the switching element 182. are electrically connected.

[0136] The circuit blocks 171 to 174 include, for example, the above-mentioned CMOS inverter circuits. An integrated circuit including C1 to Cn can be applied. Each circuit block may be provided with an appropriate function according to the requirements. It is necessary to give them the ability.

[0137] The switching elements 181 and 182 are, for example, the above-mentioned switching transistors. The switching element 181, the switching element S1, etc. can be applied. The element 182 is made of an oxide semiconductor, particularly a highly purified oxide semiconductor, at least in part. It is preferable to form it as follows.

[0138] The semiconductor device 170 shown in FIG. 8 is merely an example in which the configuration is simplified. It has a wide variety of configurations depending on its application.

[0139] The semiconductor device 170 is made of at least one oxide semiconductor, particularly a highly purified oxide semiconductor. This results in a semiconductor device with sufficiently reduced standby power consumption. As explained in the embodiment, in an integrated and complicated semiconductor device, standby power consumption The effect of suppression is very large.

[0140] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0141] (Fourth embodiment) Next, as the switching transistor S1 in the previous embodiments (such as the first embodiment), Another example of a method for manufacturing a transistor including an oxide semiconductor that can be used in the present invention is described below. In this embodiment, a highly purified oxide semiconductor (particularly, a non-purified oxide semiconductor) is used. In the following, we will explain in detail the case where a top-gate type We will use a transistor as an example to explain this, but it is not necessary to limit the transistor structure to a top-gate type. There is no.

[0142] First, an insulating layer 202 is formed on a lower substrate 200. Then, an oxide film is formed on the insulating layer 202. A semiconductor layer 206 is formed (see FIG. 9(A)).

[0143] For example, the lower layer substrate 200 may be the interlayer insulating layer in the semiconductor device of the previous embodiment (FIG. 2, etc.). The structure below the edge layer 128 can be used. can be taken into consideration.

[0144] The insulating layer 202 functions as a base, and is the same as the gate insulating layer 1 in the previous embodiment. The insulating layer 38 and the protective insulating layer 144 can be formed in the same manner. Note that the insulating layer 202 should be formed so as to contain as little hydrogen and water as possible. It is desirable to form

[0145] The oxide semiconductor layer 206 is made of a quaternary metal oxide such as In—Sn—Ga—Zn—O, or a ternary metal oxide such as In—Sn—Ga—Zn—O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides It can be formed using an In-O system, an Sn-O system, a Zn-O system, or the like.

[0146] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0147] The oxide semiconductor layer is InMO3(ZnO) m (m>0 and m is not a natural number) The thin film described below can be used, where M is selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co. Also, InGa x Zn y O z Using a material expressed as Here, x, y, and z are arbitrary numbers. Also, x, y, and z are integers. It is not necessary for x to be 0, and it can be a non-integer. For example, this notation includes In-Zn-O where x is 0. The oxide semiconductor material represented by In-Ga-Zn-O in this specification is InGaO3 ( ZnO) m (m>0 and m is not a natural number), and the fact that m is not a natural number is due to ICP -This can be confirmed using MS analysis or RBS analysis. Also, the expression x=1, y=1 This includes cases where the composition is expressed as x=1 and y=0.5. It should be noted that this is merely an example, derived from the crystal structure.

[0148] In this embodiment, the amorphous oxide semiconductor layer 206 is formed by using an In—Ga—Zn—O-based oxide. The film is formed by sputtering using a target for forming a semiconductor compound film.

[0149] A target for forming an In-Ga-Zn-O oxide semiconductor layer 206 by sputtering. The compound is In:Ga:Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In:Ga:Zn=1:1:1[atom Ratio] (x = 1, y = 1), i.e., In2O3:Ga2O3:ZnO = 1:1:2 [m Alternatively, a target having a composition ratio of In:Ga:Zn=1 may be used. :1:0.5 [atom ratio] (x=1, y=0.5) A target having a composition ratio of n:Ga:Zn=1:1:2 [atom ratio] (x=1, y=2) and a composition ratio of In:Ga:Zn=1:0:1 [atomic ratio] (x=0, y=1). A target that does not change color can also be used.

[0150] The relative density of the metal oxide in the oxide semiconductor film formation target is 80% or more, preferably 95% or more. % or more, and more preferably 99.9% or more. By using a target, the oxide semiconductor layer 206 can be formed with a dense structure. is.

[0151] The oxide semiconductor layer 206 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, for example, the concentration of impurities such as hydrogen, water, hydroxyl groups, and hydrides is about several ppm. It is preferable to use a high-purity gas atmosphere in which the concentration is reduced to a few ppb. .

[0152] When the oxide semiconductor layer 206 is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. Then, the substrate is heated to remove the moisture in the processing chamber and hydrogen and water are removed. The oxide semiconductor layer 206 is formed using the target. The oxide semiconductor layer 206 is formed while the substrate is heated. In addition, impurities contained in the oxide semiconductor layer 206 can be reduced. To remove moisture from the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, or a titanium sublimator may be used. A cold trap can be added to the turbo pump. By using a cryopump to evacuate the processing chamber, hydrogen, water, etc. can be removed. Since the impurities are removed, the impurity concentration in the oxide semiconductor layer 206 can be reduced.

[0153] The oxide semiconductor layer 206 is formed under the conditions, for example, when the distance between the substrate and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen 10 0%) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon It is possible to apply conditions such as a mixed atmosphere. This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and improves film thickness. The thickness of the oxide semiconductor layer 206 is preferably 2 nm to 200 nm. However, the thickness of the oxide semiconductor material to be used is set to 100 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the material and application of the semiconductor device. The method may be selected depending on the purpose.

[0154] Before the oxide semiconductor layer 206 was formed by a sputtering method, argon gas was introduced. The deposition on the surface of the insulating layer 202 is removed by reverse sputtering, which generates plasma. Here, the reverse sputtering is a method of sputtering a sputter target in a normal sputtering. On the other hand, by bombarding the surface with ions, the surface is This refers to a method of modifying the surface. The method of bombarding the treated surface with ions is called argon bombardment. A method of applying a high frequency voltage to the surface to be treated in an atmosphere to generate plasma near the substrate. In addition, instead of the argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used. You can use it.

[0155] Next, the oxide semiconductor layer 206 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 206a is formed.

[0156] The oxide semiconductor layer 206 can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching temperature) are adjusted to suit the material so that the layer can be etched into the desired shape. The gas, etching solution, etching time, temperature, etc. are set appropriately. The oxide semiconductor layer 206 is etched in the same manner as in the previous embodiment. The etching can be performed in the same manner as in the etching of the oxide semiconductor layer in the embodiment. The above embodiment may be referred to.

[0157] After that, the oxide semiconductor layer 206a is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (water or hydroxyl groups) from the oxide semiconductor layer 206a. The structure of the oxide semiconductor layer is adjusted, and the energy The defect level in the gap can be reduced. The temperature of the first heat treatment is, for example, 300 °C or higher and 750 °C or lower, or 400 °C or higher and 700 °C or lower.

[0158] In the first heat treatment, for example, the lower substrate 200 is placed in an electric furnace using a resistance heating element, and nitrogen is heated. The treatment can be carried out under conditions of a nitrogen atmosphere at 450° C. for 1 hour. 6a should not be exposed to the atmosphere, and water or hydrogen should not be mixed in.

[0159] The heat treatment device is not limited to an electric furnace, and may be heat conduction from a medium such as a heated gas, or A device that heats the object to be treated by thermal radiation may be used. For example, a LRTA (Lamp Rapid Thermal Anneal (GRTA) equipment, RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0160] For example, in the first heat treatment, the substrate is placed in an inert gas atmosphere at 650°C to 700°C. After heating for several minutes, the substrate may be removed from the inert gas atmosphere and subjected to GRTA treatment. GRTA treatment allows high-temperature heat treatment in a short time. Therefore, it can be applied even under temperature conditions that exceed the heat resistance temperature of the substrate. During the heating, the inert gas may be replaced with a gas containing oxygen. By performing the heat treatment of 1, the defect level in the energy gap caused by oxygen vacancies is reduced. This is because it is possible to

[0161] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0162] In any case, the first heat treatment reduces impurities and makes the silicon nitride into an i-type or substantially i-type. By forming the oxide semiconductor layer 206a, a transistor with excellent characteristics can be realized. It is possible.

[0163] The first heat treatment is performed on the oxide semiconductor layer 206 before it is processed into the island-shaped oxide semiconductor layer 206a. In this case, the lower substrate 20 is removed from the heating device after the first heat treatment. 0 is extracted and the photolithography process is carried out.

[0164] The first heat treatment has the effect of removing hydrogen and water, so the first heat treatment is called dehydration treatment. The dehydration treatment or the dehydrogenation treatment may be called hydrogenation treatment or the like. After forming the oxide semiconductor layer 206a, a source electrode or a drain electrode is stacked on the oxide semiconductor layer 206a. It is also possible to carry out such dehydration treatment and dehydrogenation at the timing of The treatment may be carried out not only once but also multiple times.

[0165] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. The source or drain electrode 208a, the source or drain electrode The source electrode 208b is formed (see FIG. 9(B)). The process is similar to that for the electrode 142a or the drain electrode 142b. The form of implementation can be taken into consideration.

[0166] Next, a gate insulating layer 212 is formed in contact with a part of the oxide semiconductor layer 206a (FIG. 9( For details, please refer to the description of the gate insulating layer 138 in the previous embodiment. It is possible.

[0167] After the gate insulating layer 212 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the second heat treatment is preferably 200°C or higher and 450°C or lower. The temperature is 250°C or higher and 350°C or lower. For example, the second heating is performed in a nitrogen atmosphere at 250°C for 1 hour. By performing the second heat treatment, the electrical characteristics of the transistor are improved. In addition, when the gate insulating layer 212 contains oxygen, the oxide semiconductor Oxygen is supplied to the conductor layer 206a to compensate for oxygen vacancies in the oxide semiconductor layer 206a, thereby forming an i-type It is also possible to form an oxide semiconductor layer that is an intrinsic semiconductor or an oxide semiconductor layer that is as close to i-type as possible.

[0168] In this embodiment, the second heat treatment is performed after the gate insulating layer 212 is formed. The timing of the second heat treatment is not particularly limited to this.

[0169] Next, a gate electrode 21 is formed on the gate insulating layer 212 in a region overlapping with the oxide semiconductor layer 206a. 9(D) , the gate electrode 214 is formed by depositing a conductive layer on the gate insulating layer 212. After forming the conductive layer, the conductive layer can be selectively patterned. For details, see the description of the gate electrode 136c and the gate electrode 145 in the previous embodiment. The following description may be taken into consideration.

[0170] Next, an interlayer insulating layer 216 and an interlayer insulating film 218 are formed on the gate insulating layer 212 and the gate electrode 214. The insulating interlayer 216 and the insulating interlayer 218 are formed (see FIG. 9(E)). The film can be formed by using a PVD method, a CVD method, or the like. Inorganic insulators such as silicon, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The interlayer insulating layer can be formed using a material containing an insulating material. However, one embodiment of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of two or more layers.

[0171] It is desirable that the interlayer insulating layer 218 be formed so that its surface is flat. By forming the interlayer insulating layer 218 so that the surface is flat, it is possible to form an electrode on the interlayer insulating layer 218. This is because electrodes, wiring, etc. can be formed in a suitable manner.

[0172] Through the above steps, the transistor 250 including the highly purified oxide semiconductor layer 206a is completed. do.

[0173] The transistor 250 shown in FIG. 9(E) is provided on the lower substrate 200 via the insulating layer 202. The oxide semiconductor layer 206a is electrically connected to the source electrode 206b. a source or drain electrode 208a, a source or drain electrode 208b, and an oxide semiconductor layer 206a, source or drain electrode 208a, source or drain electrode A gate insulating layer 212 covering 208b, a gate electrode 214 on the gate insulating layer 212, and a gate electrode 214 on the gate insulating layer 212. An interlayer insulating layer 216 on the gate insulating layer 212 and the gate electrode 214, and a and an interlayer insulating layer 218.

[0174] In the transistor 250 described in this embodiment, the oxide semiconductor layer 206a is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5 x10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Below The carrier density of the oxide semiconductor layer 206a is lower than that of a general silicon wafer. carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., , 1×10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) This results in a sufficiently small off-state current. When the thickness of the oxide semiconductor layer is 30 nm, the drain voltage is 1 V to 10 V. When the gate-source voltage is in the range of about 0V, the off-state current (the drain current when the gate-source voltage is 0V or less) current) is 1×10 -13 A or less. Or, the off-current density at room temperature (off-current divided by the transistor channel width) is 100aA (1aA (attoampere) is 10 -18 A (ampere)) / μm or less (preferably, 10 aA / μm or less, more preferably or 1 aA / μm or less).

[0175] In addition to the off-state current and off-state current density, the characteristics of the above-mentioned transistors include the off-state resistance (transistor Resistivity (resistance when the transistor is off) and off resistivity (resistivity when the transistor is off) Here, the off-resistance R can be expressed using the off-current and drain voltage as The off-resistivity ρ is a value calculated from Ohm's law. This value can be calculated from ρ=RA / L using the area A and the channel length L. In the above case, the off-resistivity is 1×10 9 Ω·m or more (or 1×10 10 Ω·m or more) The cross-sectional area A is expressed as A=dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. will be done.

[0176] By using the oxide semiconductor layer 206a that has been highly purified and made intrinsic, Therefore, the off-state current of the transistor can be sufficiently reduced.

[0177] In this embodiment, a transistor Although the case where the stan 250 is used has been described, it is not necessary to interpret the disclosed invention as being limited to this case. For example, by sufficiently improving the electrical properties of oxide semiconductors, It is also possible to use an oxide semiconductor for all transistors including the transistor. In such a case, it is not necessary to have a laminated structure as shown in the previous embodiment. To achieve good circuit operation, the field-effect mobility μ is μ>100cm 2 In this case, it is desirable that the temperature is / V·s. A semiconductor device can be formed using such a substrate.

[0178] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0179] (Embodiment 5) Next, as the switching transistor S1 in the previous embodiments (such as the first embodiment), Another example of a method for manufacturing a transistor including an oxide semiconductor is described below. 10. In this embodiment, a crystalline region is formed as an oxide semiconductor layer. a first oxide semiconductor layer having a crystal region and a second oxide semiconductor layer formed by crystal growth from a crystalline region of the first oxide semiconductor layer; The case where the oxide semiconductor layer of the top gate electrode 2 is used will be described in detail. The explanation will be given using a top-gate transistor as an example, but if the transistor configuration is changed to a top-gate type, There's no need to limit it.

[0180] First, an insulating layer 302 is formed on a lower substrate 300. Then, a first insulating layer 302 is formed on the insulating layer 302. An oxide semiconductor layer is formed, and a first heat treatment is performed to form a first oxide semiconductor layer on at least the surface of the first oxide semiconductor layer. The region containing the oxide semiconductor layer is crystallized to form the first oxide semiconductor layer 304 (see FIG. 10A). ).

[0181] For example, the lower layer substrate 300 may be the interlayer insulating layer in the semiconductor device of the previous embodiment (FIG. 2, etc.). The structure below the edge layer 128 can be used. can be taken into consideration.

[0182] The insulating layer 302 functions as a base, and is the same as the gate insulating layer 1 in the previous embodiment. The insulating layer 38 and the protective insulating layer 144 can be formed in the same manner. Note that the insulating layer 302 should be formed so as to contain as little hydrogen and water as possible. It is desirable to form

[0183] The first oxide semiconductor layer 304 is formed in the same manner as the oxide semiconductor layer 206 in the previous embodiment. The first oxide semiconductor layer 304 and a method for forming the same can be described in detail below. However, in this embodiment, the first heat treatment is performed to In order to intentionally crystallize the first oxide semiconductor layer 304, an oxide that is easily crystallized is used. It is desirable to form the first oxide semiconductor layer 304 using a semiconductor film formation target. The thickness of the first oxide semiconductor layer 304 is preferably greater than or equal to 3 nm and less than or equal to 15 nm. In this embodiment, the thickness is set to 5 nm as an example. The appropriate thickness varies depending on the material and the application of the semiconductor device. The selection may be made depending on the application.

[0184] The temperature of the first heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. The heat treatment time should be between 1 minute and 24 hours. The atmosphere for the first heat treatment is preferably an atmosphere that does not contain hydrogen, water, etc. , water-free, nitrogen atmosphere, oxygen atmosphere, rare gas (helium, neon, argon) It can be an atmosphere such as a lounge.

[0185] Heat treatment equipment includes electric furnaces, as well as equipment that uses heat conduction from a medium such as heated gas or heat radiation. For example, a device for heating the object to be treated can be used. Rapid Thermal Anneal (GRTA) equipment, Gas Rapid Th RTA (Rapid Thermal Anneal) equipment l) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. Inert gases that do not react with the material to be treated by heat treatment, such as rare gases such as fluorine or nitrogen. is used.

[0186] By the above-described first heat treatment, a region including at least the surface of the first oxide semiconductor layer 304 The crystalline region is formed by crystallizing the first oxide semiconductor layer 304 from the surface of the first oxide semiconductor layer 304. This is a region formed by the progress of crystal growth toward the inside of the semiconductor layer 304 . The crystalline region may contain plate-like crystals with an average thickness of 2 nm to 10 nm. The crystalline region is a crystal whose c-axis is oriented in a direction perpendicular to the surface of the oxide semiconductor layer. May include:

[0187] Furthermore, the first heat treatment forms a crystalline region and also forms a thin film in the first oxide semiconductor layer 304. It is desirable to remove hydrogen (including water and hydroxyl groups) from the The purity of nitrogen is 6N (99.9999%) or more (i.e., the concentration of impurities is 1 ppm or less). In nitrogen atmosphere, oxygen atmosphere, rare gas (helium, neon, argon, etc.) atmosphere, etc. It is preferable to carry out the heat treatment of 1. It is more preferable to use a material with a purity of 7N (99.99999%) or higher (i.e. The atmosphere is one in which the concentration of impurities is 0.1 ppm or less. Also, the concentration of H2O is 20 ppm or less. The first heat treatment is carried out in ultra-dry air, preferably in ultra-dry air with an H2O content of 1 ppm or less. You can go.

[0188] Furthermore, the first heat treatment is performed to form a crystalline region and to add an oxide to the first oxide semiconductor layer 304. For example, it is desirable to change the atmosphere of the heat treatment to an oxygen atmosphere. Thus, oxygen can be supplied to the first oxide semiconductor layer 304.

[0189] In this embodiment, the first heat treatment is performed at 700° C. for 1 hour in a nitrogen atmosphere. After removing hydrogen and the like from the oxide semiconductor layer, the atmosphere was changed to an oxygen atmosphere. In this case, oxygen is supplied to the inside of the first oxide semiconductor layer 304. The goal is to form crystalline regions, so the removal of hydrogen and other substances and the supply of oxygen are separate processes. For example, heat treatment to remove hydrogen and the like, or treatment to supply oxygen can be performed. After the heating, a heat treatment for crystallization can be carried out.

[0190] By such a first heat treatment, a crystalline region is formed and hydrogen (including water and hydroxyl groups) is removed. The oxygen-supplied first oxide semiconductor layer 304 is obtained.

[0191] Next, a first oxide semiconductor layer 304 having a crystalline region at least in a region including a surface thereof is formed with a A second oxide semiconductor layer 306 is formed (see FIG. 10B).

[0192] The second oxide semiconductor layer 306 is formed in the same manner as the oxide semiconductor layer 206 in the above embodiment. The second oxide semiconductor layer 306 and a method for forming the second oxide semiconductor layer 306 can be formed as follows. The above embodiment may be referred to for the second oxide semiconductor layer 306. It is desirable to form the first oxide semiconductor layer 304 thicker than the first oxide semiconductor layer 305. the sum of the thicknesses of the oxide semiconductor layer 304 and the second oxide semiconductor layer 306 is 3 nm to 50 nm. It is desirable to form the second oxide semiconductor layer 306. The appropriate thickness varies depending on the material used and the application of the semiconductor device. The selection may be made depending on the application.

[0193] The second oxide semiconductor layer 306 is made of a material having the same main component as that of the first oxide semiconductor layer 304, e.g., For example, use materials with close lattice constants after crystallization (lattice constant mismatch of 1% or less). When materials having the same main component are used, the second oxide semiconductor layer 306 is preferably formed of the same material. In the crystallization, crystal growth using the crystalline region of the first oxide semiconductor layer 304 as a seed is likely to proceed. Furthermore, when the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are made of the same main component material, The physical properties and electrical properties of the interface with the second oxide semiconductor layer 306 are also improved.

[0194] If the desired film quality can be obtained by crystallization, a second film may be formed using a material with a different main component. The oxide semiconductor layer 306 may be formed as follows.

[0195] Next, the second oxide semiconductor layer 306 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 The crystalline region is used as a seed for crystal growth to form the second oxide semiconductor layer 306a (FIG. 1 0(C)).

[0196] The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The heating time for the second heat treatment is 1 minute or more and 100 hours or less, preferably 5 hours or more. The heat treatment time is set to 20 hours or less, typically 10 hours. It is desirable that the atmosphere used for the process does not contain hydrogen, water, etc.

[0197] The details of the atmosphere and the effects of the heat treatment are the same as those of the first heat treatment. The heat treatment apparatus that can perform this is the same as that for the first heat treatment. The inside of the furnace is sometimes in a nitrogen atmosphere, and when cooling, the inside of the furnace is in an oxygen atmosphere. Hydrogen and the like can be removed in the atmosphere, and oxygen can be supplied in the oxygen atmosphere.

[0198] By performing the second heat treatment as described above, the oxide semiconductor layer 304 formed in the first oxide semiconductor layer 304 Crystal growth is promoted from the crystalline region to the entire second oxide semiconductor layer 306, and the second oxide semiconductor The conductor layer 306a can be formed. In addition, hydrogen (including water and hydroxyl groups) is removed. In this way, the second oxide semiconductor layer 306a to which oxygen is supplied can be formed. The heat treatment in step 2 can improve the orientation of the crystalline region of the first oxide semiconductor layer 304. It is Noh.

[0199] For example, an In—Ga—Zn—O-based oxide semiconductor material is used for the second oxide semiconductor layer 306a. If used, the second oxide semiconductor layer 306a is InGaO3(ZnO) m (m>0, and and In2Ga2ZnO7 (In:Ga:Zn:O Such crystals may contain crystals represented by the following formula: (Ratio of crystals) = 2:2:1:7. Therefore, the c-axis of the second oxide semiconductor layer 306b is perpendicular to the surface of the second oxide semiconductor layer 306b. The orientation is such that

[0200] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be understood as a stacked structure of layers parallel to the a-axis and b-axis. In general, the crystals described above are composed of layers containing In and layers not containing In (Ga or The oxide semiconductor has a structure in which layers containing Zn or Zn are stacked in the c-axis direction. The membrane layer includes a crystalline region, and the crystalline region has an ab plane that is approximately adjacent to the membrane surface. The oxide semiconductor is composed of crystals whose c-axes are approximately parallel to the film surface and whose c-axes are approximately perpendicular to the film surface. The crystalline region contained in the layer is c-axis oriented. Since the oxide semiconductor layer includes a region having crystallinity, the oxide semiconductor layer is ligated Crystalline Oxide Semiconductor) That is, the oxide semiconductor layer including the crystalline region is non-single-crystal, and The entire film does not become amorphous.

[0201] In the In-Ga-Zn-O oxide semiconductor crystal, the a-axis and The conductivity in the direction parallel to the b-axis is good. In semiconductor crystals, electrical conduction is mainly controlled by In, and The 5s orbital of In overlaps with the 5s orbital of the adjacent In, forming a carrier path. It depends on what is achieved.

[0202] In addition, the first oxide semiconductor layer 304 may have an amorphous region at the interface with the insulating layer 302. In the case of the structure, the second heat treatment is performed to form a thin film on the surface of the first oxide semiconductor layer 304. Crystal growth proceeds from the crystalline region toward the bottom of the first oxide semiconductor layer 304. In some cases, the amorphous region may be crystallized. Depending on the conditions of the heat treatment, the amorphous region may remain.

[0203] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are made of oxide semiconductors having the same main component. When a dielectric material is used, as shown in FIG. 10C, a first oxide semiconductor layer 304 and a second oxide semiconductor layer 305 are formed. In some cases, the oxide semiconductor layer 306a and the oxide semiconductor layer 306b have the same crystal structure. In (C), the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are shown by the dotted line. a becomes indistinguishable, and the boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 30 In some cases, 6a can be considered the same layer.

[0204] Next, the first oxide semiconductor layer 304 and the The second oxide semiconductor layer 306a is processed to form the island-shaped first oxide semiconductor layer 304a and A second oxide semiconductor layer 306b is formed (see FIG. 10D).

[0205] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a are etched using a dopant. Either dry etching or wet etching may be used. In order to etch the oxide semiconductor layer into a desired shape, Etching conditions (etching gas, etching solution, etching time, temperature) are adjusted to suit the material. The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a are set appropriately. The etching may be performed in the same manner as the etching of the oxide semiconductor layer in the above embodiment. For details, please refer to the above embodiment.

[0206] Note that a region of the oxide semiconductor layer that serves as a channel formation region has a flat surface. For example, it is desirable that the height difference of the surface of the second oxide semiconductor layer 306b is In the region overlapping with the above (channel forming region), the thickness is 1 nm or less (preferably 0.2 nm or less) ) is preferable.

[0207] Next, a conductive layer is formed in contact with the second oxide semiconductor layer 306b. The conductive layer is selectively etched to form the source or drain electrode 308a, the source or drain electrode 308b, The source or drain electrode 308b is formed (see FIG. 10(D)). The electrode 308a and the source or drain electrode 308b are the same as those in the previous embodiment. The source or drain electrode 142a has a shape similar to that of the source or drain electrode 142b. For details, please refer to the above embodiment.

[0208] In the step shown in FIG. 10D, the first oxide semiconductor layer 304a and the second oxide semiconductor layer On the side of the conductor layer 306b, a source or drain electrode 308a, a source or drain electrode Alternatively, the crystalline layer in contact with the drain electrode 308b may become amorphous. The entire region of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306b is crystalline. It doesn't necessarily have to be a structure.

[0209] Next, the gate insulating layer 312 is formed in contact with part of the second oxide semiconductor layer 306b. The gate insulating layer 312 can be formed by using a CVD method, a sputtering method, or the like. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are formed on the gate insulating layer 312. A gate electrode 314 is formed in a region overlapping with the gate insulating layer 312 and the gate insulating layer 313. An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed on the gate electrode 314 (FIG. 10). (See (E)). A gate insulating layer 312, a gate electrode 314, an interlayer insulating layer 316, and an interlayer insulating film 318 are formed. The edge layer 318 is the same as the gate insulating layer 138, the gate electrode 136c, and the gate electrode 136d in the previous embodiment. The insulating layer 216 and the insulating layer 218 can be formed in the same manner as the insulating layer 145 and the insulating layer 216. For details, please refer to the previous embodiment.

[0210] After the gate insulating layer 312 is formed, a third heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the third heat treatment is preferably 200°C or higher and 450°C or lower. The temperature is 250°C or higher and 350°C or lower. For example, By performing the third heat treatment, the electrical characteristics of the transistor are improved. In addition, when the gate insulating layer 312 is an insulating layer containing oxygen, In this case, oxygen is supplied to the second oxide semiconductor layer 306b, and the oxygen in the second oxide semiconductor layer 306b is Compensating for the electron deficiency to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible You can also do this.

[0211] In this embodiment, the third heat treatment is performed after the gate insulating layer 312 is formed. The timing of the third heat treatment is not limited to this. In addition, the timing of the third heat treatment may be set to other treatments such as the second heat treatment. Therefore, when oxygen is supplied to the second oxide semiconductor layer, the third heat treatment can be omitted. good.

[0212] As a result of the above, the first oxide semiconductor layer 304a and the A transistor 350 including a second oxide semiconductor layer 306b grown from a crystalline region is completed.

[0213] The transistor 350 shown in FIG. 10(E) is provided on the lower substrate 300 via the insulating layer 302. The first oxide semiconductor layer 304a is formed on the first oxide semiconductor layer 304a. The second oxide semiconductor layer 306b is electrically connected to the second oxide semiconductor layer 306b. A source or drain electrode 308a, a source or drain electrode 308b, and a the second oxide semiconductor layer 306b, the source or drain electrode 308a, The gate insulating layer 312 covers the drain electrode 308b, and the gate electrode 308b is formed on the gate insulating layer 312. an interlayer insulating layer 316 on the gate electrode 314; An interlayer insulating layer 318 is provided on the insulating layer 316 .

[0214] In the transistor 350 described in this embodiment, the first oxide semiconductor layer 304a and Since the second oxide semiconductor layer 306b is highly purified, the hydrogen concentration in the second oxide semiconductor layer 306b is 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 The oxide semiconductor layer 206a has the following structure. The carrier density is the carrier density in a typical silicon wafer (1 × 10 14 / cm 3 A sufficiently small value (e.g., 1×10 12 / cm 3Less than, more preferably is 1.45 x 10 10 / cm 3 This allows the off-state current to be sufficiently low. For example, when the channel length is 10 μm and the oxide semiconductor layer is 30 nm thick, In this case, when the drain voltage is in the range of about 1V to 10V, the off-current (gate- The drain current when the voltage between the source and drain is 0V or less is 1×10 -13 A or below Alternatively, the off-state current density at room temperature (off-state current divided by the channel width of the transistor) is 100aA (1aA (attoampere) is 10 -18 A (ampere) / μm or less ( Preferably, it is 10 aA / μm or less, and more preferably, it is 1 aA / μm or less.

[0215] In addition to the off-state current and off-state current density, the characteristics of the above-mentioned transistors include the off-state resistance (transistor Resistivity (resistance when the transistor is off) and off resistivity (resistivity when the transistor is off) Here, the off-resistance R can be expressed using the off-current and drain voltage as The off-resistivity ρ is a value calculated from Ohm's law. This value can be calculated from ρ=RA / L using the area A and the channel length L. In the above case, the off-resistivity is 1×10 9 Ω·m or more (or 1×10 10 Ω·m or more) The cross-sectional area A is expressed as A=dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. will be done.

[0216] The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are thus highly purified and made intrinsic. By using the compound semiconductor layer 306b, the off-state current of the transistor can be sufficiently reduced. Cut.

[0217] Furthermore, in this embodiment, the oxide semiconductor layer is a first oxide semiconductor having a crystalline region. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are grown as crystals from the crystalline region of the first oxide semiconductor layer 304a. The use of the oxide semiconductor layer 306b improves the field effect mobility and provides good electrical characteristics. It is possible to realize a transistor having the above structure.

[0218] In this embodiment, a transistor Although the case where the stator 350 is used has been described, it is not necessary to interpret the disclosed invention as being limited to this case. For example, the transistor 350 described in this embodiment has a first oxide film having a crystalline region. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are grown from the crystalline region of the first oxide semiconductor layer 304a. The second oxide semiconductor layer 306b has a good field-effect mobility, and therefore, integration It is possible to use oxide semiconductors for all transistors, including those that constitute circuits. In such a case, the laminated structure shown in the previous embodiment can be used. However, to achieve good circuit operation, the field-effect mobility of the oxide semiconductor must be high. μ is μ>100cm 2 / V·s. In this case, the glass substrate A semiconductor device can be formed using a substrate such as a silicon dioxide film.

[0219] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0220] (Sixth embodiment) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 11. In this embodiment, telephones, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) digital cameras, digital video cameras, electronic paper, television equipment (television The semiconductor device described above is applied to electronic devices such as a television receiver. This section explains the case where

[0221] FIG. 11A shows a notebook personal computer, which includes a housing 401, a housing 402, The display unit 403 and the keyboard 404 are included. The semiconductor device described in the above embodiment is provided inside the semiconductor device. This realizes a notebook-type personal computer with reduced size.

[0222] FIG. 11B shows a personal digital assistant (PDA), and a main body 411 includes a display unit 413 and an external An external interface 415 and operation buttons 414 are provided. The main body 411 is provided with a stylus 412 for operating the terminal. Therefore, a portable information terminal with sufficiently reduced power consumption can be provided. It will be realized.

[0223] FIG. 11C shows an electronic book 420 equipped with electronic paper, which is made up of a housing 421 and a housing 422. The housing 421 and the housing 423 are connected by a shaft 437. The shaft 437 serves as an axis for opening and closing operations. The case 421 also includes a power supply 431, an operation key, and a At least one of the housings 421 and 423 is provided with a speaker 433 and a speaker 435. The semiconductor device described in the above embodiment is provided in the This allows for a reduced electronic book size.

[0224] FIG. 11D shows a mobile phone that is composed of two housings, a housing 440 and a housing 441. Furthermore, the housing 440 and the housing 441 slide and unfold as shown in FIG. 11(D). The two can be folded into an overlapping state, making them compact and suitable for portability. The housing 441 also includes a display panel 442, a speaker 443, a microphone 444, a pointing device, and a The camera is equipped with a viewing device 446, a camera lens 447, an external connection terminal 448, etc. The display panel 442 has a touch panel function, and the image display shown in FIG. The multiple operation keys 445 shown are indicated by dotted lines. The device is equipped with a solar cell 449 for charging the device, an external memory slot 450, etc. The antenna is built into the housing 441. At least one of the housings 440 and 441 Therefore, the standby power consumption can be sufficiently reduced. This will result in a mobile phone with reduced power consumption.

[0225] FIG. 11(E) shows a digital camera, which includes a main body 461, a display unit 467, an eyepiece 463, an operation unit, and a camera body 466. It is composed of an operation switch 464, a display unit 465, a battery 466, etc. The semiconductor device described in the above embodiment is provided in the semiconductor device 461. This realizes a digital camera in which the above-mentioned noise is sufficiently reduced.

[0226] FIG. 11F shows a television device 470, which includes a housing 471, a display unit 473, a stand, and the like. The television device 470 is operated by a switch provided in the housing 471. This can be done by a switch or a remote control operation device 480. The semiconductor device described in the above embodiment is mounted on the device 480. A television device with significantly reduced forces is realized.

[0227] As described above, the electronic device shown in this embodiment mode includes the integrated circuit according to the above embodiment. This has enabled the realization of electronic devices that consume less power by sufficiently suppressing standby power consumption. can be. [Explanation of symbols]

[0228] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective Insulation Layer 145 gate electrode 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 160 transistors 162 transistors 170 Semiconductor devices 171 Circuit Blocks 172 Circuit Blocks 173 Circuit Blocks 174 Circuit Blocks 181 Switching element 182 Switching element 200 Lower layer board 202 Insulating layer 206 Oxide semiconductor layer 206a Oxide semiconductor layer 208a Source electrode or drain electrode 208b Source electrode or drain electrode 212 Gate insulating layer 214 gate electrode 216 Interlayer insulating layer 218 Interlayer Insulation Layer 250 transistors 300 Lower layer board 302 Insulation layer 304 First oxide semiconductor layer 304a First oxide semiconductor layer 306 Second oxide semiconductor layer 306a Second oxide semiconductor layer 306b Second oxide semiconductor layer 308a Source electrode or drain electrode 308b Source electrode or drain electrode 312 Gate insulating layer 314 Gate electrode 316 Interlayer insulation layer 318 Interlayer Insulation Layer 350 transistors 401 Case 402 Case 403 Display section 404 Keyboard 411 Main Unit 412 Stylus 413 Display section 414 Operation Button 415 external interface 420 e-books 421 Case 423 Case 431 Power supply 433 Operation Key 435 Speaker 437 Shaft 440 chassis 441 Case 442 Display Panel 443 Speaker 444 Microphone 445 Operation Key 446 Pointing Device 447 Camera Lenses 448 External connection terminal 449 Solar Cells 450 external memory slot 461 Main Unit 463 Eyepiece 464 Operation Switch 465 Display section 466 Battery 467 Display section 470 Television Equipment 471 Case 473 Display section 475 Stand 480 Remote Controlled Machine

Claims

1. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, The second conductive layer is always electrically connected to one of the source and drain of the second transistor.

2. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor.

3. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; The first conductive layer does not have a region overlapping with a channel formation region of the second transistor.

4. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor, The first conductive layer does not have a region overlapping with a channel formation region of the second transistor.

5. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

6. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor, In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

7. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the first conductive layer does not have a region overlapping with a channel formation region of the second transistor, In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

8. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the oxide semiconductor layer contains In, Ga, and Zn, the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor, the first conductive layer does not have a region overlapping with a channel formation region of the second transistor, In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

9. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; The second conductive layer is always electrically connected to one of the source and drain of the second transistor.

10. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor.

11. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; The first conductive layer does not have a region overlapping with a channel formation region of the second transistor.

12. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor, The first conductive layer does not have a region overlapping with a channel formation region of the second transistor.

13. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

14. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor, In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

15. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the first conductive layer does not have a region overlapping with a channel formation region of the second transistor, In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

16. a first transistor, a second transistor, and a third transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is always electrically connected to a first wiring; a gate of the first transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; a semiconductor device, wherein the third transistor is turned on when a power supply line is in a conductive state with the other of the source and the drain of the second transistor through at least a channel formation region of the third transistor; a first insulating layer having a region located above a channel formation region of the second transistor; a first conductive layer having a region located above the first insulating layer and functioning as a first gate electrode of the third transistor; a second insulating layer having a region located above the first conductive layer and functioning as a first gate insulating layer of the third transistor; an oxide semiconductor layer having a region located above the second insulating layer and functioning as a channel formation region of the third transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the third transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the third transistor; a third insulating layer having a region located above the oxide semiconductor layer and functioning as a second gate insulating layer of the third transistor; a fourth conductive layer having a region located above the third insulating layer and functioning as a second gate electrode of the third transistor; a fourth insulating layer having a region located above the fourth conductive layer; a channel formation region of the second transistor includes silicon; the second conductive layer is always electrically connected to one of the source and the drain of the second transistor; the oxide semiconductor layer does not have a region overlapping with a channel formation region of the second transistor, the first conductive layer does not have a region overlapping with a channel formation region of the second transistor, In a plan view, the first transistor has a channel length direction along a first direction, In a plan view, the second transistor has a channel length direction aligned with the first direction, In a plan view, the third transistor has a channel length direction aligned with the first direction, A semiconductor device having a region in which the longitudinal direction of the second conductive layer extends along the first direction in a plan view.

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