Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing variation in dielectric breakdown position of an insulating film when a writing operation is performed on an anti-fuse element.SOLUTION: A semiconductor memory device (DEV1) includes a semiconductor memory substrate (SUB), an insulating film (IF), and an anti-fuse device (AFE) having a first contact plug (CP4). The substrate has a top F1. The semiconductor substrate has an impurity diffusion layer (IDL) formed in the upper surface of the semiconductor substrate. The insulating film is formed on the impurity diffusion layer. The first contact plug is formed on the insulating film so as to be in contact with the insulating film.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2018-98445 (Patent Document 1) discloses a semiconductor device. The semiconductor device described in Patent Document 1 has a semiconductor substrate and an insulating film. The semiconductor substrate has a first impurity diffusion layer and a second impurity diffusion layer. The first impurity diffusion layer and the second impurity diffusion layer are formed on the upper surface of the semiconductor substrate within the semiconductor substrate. An insulating film is formed between the first impurity diffusion layer and the second impurity diffusion layer. The first impurity diffusion layer, the second impurity diffusion layer, and the insulating film function as an anti-fuse element.

[0003] When a voltage is applied between the first impurity diffusion layer and the second impurity diffusion layer, the insulating film is broken down and the electrical resistance between the first impurity diffusion layer and the second impurity diffusion layer changes, thereby performing a write operation on the anti-fuse element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-98445 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device described in Patent Document 1, the position of breakdown of the insulating film varies when a write operation is performed on the anti-fuse element. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes an anti-fuse element having a semiconductor substrate, an insulating film, and a first contact plug. The semiconductor substrate has an upper surface. The semiconductor substrate has an impurity diffusion layer on the upper surface within the semiconductor substrate. The insulating film is formed on the impurity diffusion layer. The first contact plug is formed on the insulating film. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, it is possible to suppress variations in the position of dielectric breakdown in the insulating film when a write operation is performed on the anti-fuse element. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a schematic circuit diagram of the semiconductor device DEV1. [Figure 2] FIG. 2 is a first cross-sectional view of the semiconductor device DEV1. [Figure 3] FIG. 2 is a second cross-sectional view of the semiconductor device DEV1. [Figure 4] FIG. 10 is a plan view of a semiconductor device DEV1 according to a modified example. [Figure 5] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 6] FIG. 10 is a cross-sectional view illustrating an element isolation film forming step S2. [Figure 7] FIG. 10 is a cross-sectional view illustrating an ion implantation step S3. [Figure 8] FIG. 10 is a cross-sectional view illustrating a gate insulating film forming step S4. [Figure 9] FIG. 10 is a cross-sectional view illustrating a gate electrode forming step S5. [Figure 10] FIG. 10 is a cross-sectional view illustrating an ion implantation step S6. [Figure 11] FIG. 10 is a cross-sectional view illustrating a sidewall spacer forming step S7. [Figure 12] FIG. 10 is a first cross-sectional view illustrating an ion implantation step S8. [Figure 13] FIG. 10 is a second cross-sectional view illustrating the ion implantation step S8. [Figure 14]FIG. 10 is a cross-sectional view illustrating an insulating film forming step S9. [Figure 15] FIG. 10 is a first cross-sectional view illustrating a silicide step S10. [Figure 16] FIG. 10 is a second cross-sectional view illustrating the silicide step S10. [Figure 17] FIG. 10 is a first cross-sectional view illustrating a protective film forming step S11. [Figure 18] FIG. 10 is a second cross-sectional view illustrating the protective film forming step S11. [Figure 19] FIG. 10 is a first cross-sectional view illustrating an interlayer insulating film forming step S12. [Figure 20] FIG. 10 is a second cross-sectional view illustrating the interlayer insulating film forming step S12. [Figure 21] FIG. 10 is a first cross-sectional view illustrating a contact plug forming step S13. [Figure 22] FIG. 10 is a second cross-sectional view illustrating a contact plug forming step S13. [Figure 23] FIG. 10 is a first cross-sectional view illustrating a wiring formation step S14. [Figure 24] FIG. 10 is a second cross-sectional view illustrating the wiring formation step S14. [Figure 25] FIG. 10 is a first cross-sectional view of the semiconductor device DEV2. [Figure 26] FIG. 2 is a second cross-sectional view of the semiconductor device DEV2. [Figure 27A] FIG. 10 is a plan view of a semiconductor device DEV2 according to a first modification. [Figure 27B] FIG. 10 is a cross-sectional view of a semiconductor device DEV2 according to a second modification. [Figure 27C] FIG. 11 is a cross-sectional view of a semiconductor device DEV2 according to a third modification. [Figure 28] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV2. [Figure 29] FIG. 10 is a first cross-sectional view illustrating a wiring formation step S16. [Figure 30] FIG. 10 is a second cross-sectional view illustrating the wiring formation step S16. [Figure 31] FIG. 10 is a first cross-sectional view illustrating an interlayer insulating film forming step S17. [Figure 32]FIG. 10 is a second cross-sectional view illustrating the interlayer insulating film forming step S17. [Figure 33] FIG. 10 is a first cross-sectional view illustrating a via hole forming step S18. [Figure 34] FIG. 10 is a second cross-sectional view illustrating a via hole forming step S18. [Figure 35] FIG. 10 is a first cross-sectional view illustrating an insulating film forming step S19. [Figure 36] FIG. 10 is a second cross-sectional view illustrating the insulating film forming step S19. [Figure 37] FIG. 10 is a first cross-sectional view of the semiconductor device DEV3. [Figure 38] FIG. 2 is a second cross-sectional view of the semiconductor device DEV3. [Figure 39] FIG. 10 is a plan view of a semiconductor device DEV3 according to a modified example. [Figure 40] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV3. [Figure 41] FIG. 10 is a first cross-sectional view illustrating an insulating film forming step S21. [Figure 42] FIG. 10 is a second cross-sectional view illustrating the insulating film forming step S21. [Figure 43] FIG. 10 is a first cross-sectional view illustrating a cap insulating film forming step S22. [Figure 44] FIG. 10 is a second cross-sectional view illustrating the cap insulating film forming step S22. DETAILED DESCRIPTION OF THE INVENTION

[0009] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0010] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0011] <Configuration of semiconductor device DEV1> The semiconductor device DEV1 has a plurality of memory cells MC. Only one memory cell MC is shown in FIG. 1. The memory cell MC has a bit line BIT, a select transistor SEL, an anti-fuse element AFE, and a word line WOR. The bit line BIT, select transistor SEL, and anti-fuse element AFE are connected in series in this order. The word line WOR is connected to the gate electrode of the select transistor SEL. A sense circuit SEN is connected to the bit line BIT. Although not shown, a voltage application circuit is connected to the bit line BIT.

[0012] As shown in FIGS. 2 and 3, the semiconductor device DEV1 has a semiconductor substrate SUB. The semiconductor substrate SUB is formed of, for example, single crystal silicon. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 located opposite the upper surface F1. The semiconductor substrate SUB has a source layer SL, a drain layer DL, and a well layer WEL. The conductivity type of the source layer SL and the conductivity type of the drain layer DL are first conductivity types. The conductivity type of the well layer WEL is a second conductivity type. The second conductivity type is opposite to the first conductivity type. The first conductivity type is, for example, n-type, and the second conductivity type is, for example, p-type.

[0013] The source layer SL is formed on the upper surface F1 in the semiconductor substrate SUB. The drain layer DL is formed on the upper surface F1 in the semiconductor substrate SUB. The drain layer DL is spaced apart from the source layer SL. The source layer SL has a first portion SLa and a second portion SLb. The first portion SLa is located between the second portion SLb and the drain layer DL. The dopant concentration in the first portion SLa is lower than the dopant concentration in the second portion SLb. In other words, the source layer SL has an LDD (Lightly Doped Diffusion) structure. The drain layer DL has a first portion DLa and a second portion DLb. The first portion DLa is located between the second portion DLb and the source layer SL. The dopant concentration in the first portion DLa is lower than the dopant concentration in the second portion DLb. In other words, the drain layer DL has an LDD structure. The well layer WEL is formed on the upper surface F1 so as to surround the source layer SL and the drain layer DL.

[0014] The semiconductor device DEV1 further includes a gate insulating film GI, a gate electrode GE, and sidewall spacers SWS. The gate insulating film GI is made of, for example, silicon oxide. The gate electrode GE is made of, for example, polycrystalline silicon containing a dopant. The sidewall spacers SWS are made of, for example, silicon oxide.

[0015] The gate insulating film GI is formed on the upper surface F1 so as to be located between the source layer SL and the drain layer DL in a plan view. The gate electrode GE is formed on the gate insulating film GI. The source layer SL, the drain layer DL, the well layer WEL, the gate insulating film GI, and the gate electrode GE form a transistor. This transistor is, for example, a select transistor SEL. The sidewall spacers SWS are formed on the upper surface F1 so as to be in contact with the gate electrode GE and the gate insulating film GI. More specifically, the sidewall spacers SWS are formed on the first portion SLa and the first portion DLa.

[0016] The second portion SLb has a silicide layer SILa formed on the upper surface F1. The second portion DLb has a silicide layer SILb formed on the upper surface F1. The gate electrode GE has a silicide layer SILc formed on the upper surface of the gate electrode GE. The silicide layer SILa, the silicide layer SILb, and the silicide layer SILc are formed of, for example, an intermetallic compound of silicon and titanium, cobalt, or the like.

[0017] The semiconductor device DEV1 further has an isolation film ISL. The isolation film ISL is made of, for example, silicon oxide. A trench TR1 is formed in the upper surface F1. The trench TR1 extends toward the lower surface F2. The isolation film ISL is formed in the trench TR1. The isolation film ISL (trench TR1) surrounds the well layer WEL in plan view. This allows one of the transistors to be insulated and isolated from the other transistors.

[0018] The semiconductor substrate SUB further has an impurity diffusion layer IDL. The conductivity type of the impurity diffusion layer IDL is, for example, the second conductivity type (p-type). The dopant concentration in the impurity diffusion layer IDL is, for example, higher than the dopant concentration in the semiconductor substrate SUB. The impurity diffusion layer IDL is formed on an upper surface F1 in the semiconductor substrate SUb. The semiconductor device DEV1 further has an insulating film IF. The insulating film IF is made of, for example, silicon oxide. The insulating film IF is formed on the upper surface F1. More specifically, the insulating film IF is formed on the impurity diffusion layer IDL. An opening OP is formed in the insulating film IF. The opening OP penetrates the insulating film IF. The impurity diffusion layer IDL has a silicide layer SILd. The silicide layer SILd is formed on the upper surface F1 at a position overlapping with the opening OP in a plan view. The silicide layer SILd is formed of, for example, an intermetallic compound of silicon and titanium, cobalt, or the like.

[0019] The semiconductor device DEV1 further includes a protective film PF and an interlayer insulating film ILD1. The protective film PF is made of, for example, silicon nitride. The interlayer insulating film ILD1 is made of, for example, silicon oxide. The protective film PF is formed on the upper surface F1 so as to cover the sidewall spacers SWS, the gate electrode GE, the element isolation film ISL, and the insulating film IF. The interlayer insulating film ILD1 is formed on the protective film PF.

[0020] Contact holes CH1, CH2, CH3, CH4, and CH5 are formed in the protective film PF and the interlayer insulating film ILD1. The contact holes CH1, CH2, CH3, CH4, and CH5 penetrate the protective film PF and the interlayer insulating film ILD1.

[0021] The semiconductor device DEV1 further includes contact plugs CP1, CP2, and CP3. The contact plugs CP1, CP2, and CP3 are formed of, for example, tungsten. The contact plug CP1 is formed in a contact hole CH1, the contact plug CP2 is formed in a contact hole CH2, and the contact plug CP3 is formed in a contact hole CH3.

[0022] The semiconductor device DEV1 further includes wiring WL1a, wiring WL1b, and wiring WL1c. The wiring WL1a, wiring WL1b, and wiring WL1c are formed in the same layer. The wiring WL1a, wiring WL1b, and wiring WL1c are formed of, for example, aluminum or an aluminum alloy. The contact plug CP1 electrically connects the wiring WL1a to the source layer SL (silicide layer SILa). The contact plug CP2 electrically connects the wiring WL1b to the drain layer DL (silicide layer SILb). The contact plug CP3 electrically connects the wiring WL1c to the gate electrode GE (silicide layer SILc).

[0023] The semiconductor device DEV1 further has contact plugs CP4 and CP5. The contact plugs CP4 and CP5 are made of, for example, tungsten. The contact plug CP4 is formed in a contact hole CH4, and the contact plug CP5 is formed in the contact hole CH5. The semiconductor device DEV1 further has wirings WL1d and WL1e. The wirings WL1d and WL1e are formed in the same layer as the wirings WL1a, WL1b, and WL1c. The contact plug CP4 is electrically connected to the wiring WL1d. The contact plug CP4 is electrically insulated from the impurity diffusion layer IDL. The lower end of the contact plug CP4 is in contact with the insulating film IF. The contact plug CP5 electrically connects the impurity diffusion layer IDL (silicide layer SILd) and the wiring WL1e.

[0024] The contact plug CP4, insulating film IF, and impurity diffusion layer IDL form an anti-fuse element AFE. That is, when a write operation is performed, a voltage is applied to the word line WOR, turning on the select transistor SEL, and a voltage is applied from the voltage application circuit between the contact plug CP4 and the impurity diffusion layer IDL via the bit line BIT and the contact plug CP4. This causes dielectric breakdown in the insulating film IF interposed between the contact plug CP4 and the impurity diffusion layer IDL, reducing the electrical resistance between the contact plug CP4 and the impurity diffusion layer IDL. The voltage detected by the sense circuit SEN changes before and after the write operation, and the anti-fuse element AFE functions as an OTP (One Time Programmable memory).

[0025] <Modification> 4, the width of the lower end of the contact plug CP4 may decrease toward the insulating film IF, that is, the lower end of the contact plug CP4 may have a tapered shape.

[0026] <Method of Manufacturing Semiconductor Device DEV1> As shown in FIG. 5, the manufacturing method of the semiconductor device DEV1 includes a preparation step S1, an element isolation film formation step S2, an ion implantation step S3, a gate insulating film formation step S4, a gate electrode formation step S5, an ion implantation step S6, a sidewall spacer formation step S7, an ion implantation step S8, an insulating film formation step S9, and a silicide step S10.

[0027] In a preparation step S1, a semiconductor substrate SUB is prepared. As shown in FIG. 6, in an element isolation film formation step S2, an element isolation film ISL is formed on the upper surface F1. In the element isolation film formation step S2, first, a hard mask having an opening is formed on the upper surface F1. Second, a trench TR1 is formed on the upper surface F1 by dry etching through the opening in the hard mask. Third, a constituent material of the element isolation film ISL is filled in the trench TR1 and formed on the upper surface F1 by, for example, a CVD (Chemical Vapor Deposition) method. Fourth, the constituent material of the element isolation film ISL formed outside the trench TR1 is removed by, for example, CMP (Chemical Mechanical Polishing), etch-back, or the like. In this manner, the element isolation film ISL is formed. After the element isolation film ISL is formed, the hard mask is removed.

[0028] As shown in Fig. 7, in the ion implantation step S3, ions are implanted to form a well layer WEL. As shown in Fig. 8, in the gate insulating film formation step S4, for example, the upper surface F1 is thermally oxidized to form a gate insulating film GI.

[0029] As shown in FIG. 9, in the gate electrode formation step S5, a gate electrode GE is formed on a gate insulating film GI. In the gate electrode formation step S5, first, a constituent material of the gate electrode GE is deposited on the gate insulating film GI by, for example, a CVD method. Second, a resist pattern having openings is formed on the deposited constituent material of the gate electrode GE. The constituent material of the gate electrode GE is dry-etched through the openings in the resist pattern, thereby patterning the constituent material of the gate electrode GE. In this way, the gate electrode GE is formed. Note that during the dry etching, the gate insulating film GI located other than under the gate electrode GE is also removed.

[0030] As shown in Figure 10, in the ion implantation step S6, ion implantation is performed to form a first portion SLa of the source layer SL and a first portion DLa of the drain layer DL. As shown in Figure 11, in the sidewall spacer formation step S7, sidewall spacers SWS are formed on the first portions SLa and DLa. In the sidewall spacer formation step S7, first, a film made of a material for the sidewall spacer SWS is formed by, for example, a CVD method so as to cover the gate electrode GE, the gate insulating film GI, and the element isolation film ISL. Second, the material for the sidewall spacer SWS is etched back. In this manner, the sidewall spacer SWS is formed.

[0031] As shown in FIG. 12, in the ion implantation step S8, ion implantation is performed to form the second portion SLb of the source layer SL and the second portion DLb of the drain layer DL. As shown in FIG. 13, at this time, the impurity diffusion layer IDL is also formed by ion implantation. As shown in FIG. 14, in the insulating film formation step S9, an insulating film IF is formed on the impurity diffusion layer IDL. In the insulating film formation step S9, first, a constituent material of the insulating film IF is deposited by, for example, a CVD method so as to cover the sidewall spacer SWS, the gate electrode GE, and the element isolation film ISL. Second, a resist pattern having openings is formed on the constituent material of the insulating film IF. Third, the constituent material of the insulating film IF is dry-etched through the openings of the resist pattern. In this manner, the insulating film IF is formed. Note that in the insulating film formation step S9, the thickness of the insulating film IF may be reduced by dry etching the insulating film IF. This reduces the voltage required to cause dielectric breakdown of the insulating film IF.

[0032] As shown in FIGS. 15 and 16 , in the silicide step S10, silicide layers SILa, SILb, SILb, and SILd are formed. In the silicide step S10, a metal material such as titanium or cobalt is formed on the upper surface F1 so as to cover the gate electrode GE, the sidewall spacer SWS, and the element isolation film ISL. Second, heating is performed, causing the metal material to react with silicon in the semiconductor substrate SUB and the gate electrode GE. Third, etching is performed, removing the metal material that has not reacted with silicon. As a result, the silicide layers SILa, SILb, SILb, and SILd are formed. Note that the silicide layer SILd is not formed in the impurity diffusion layer IDL located below the insulating film IF. That is, the insulating film IF functions as a silicide block film.

[0033] As shown in FIG. 5, the manufacturing method of the semiconductor device DEV1 further includes a protective film forming step S11, an interlayer insulating film forming step S12, a contact plug forming step S13, a wiring forming step S14, and an interlayer insulating film forming step S15.

[0034] 17 and 18, in the protective film formation step S11, a protective film PF is formed by, for example, a CVD method so as to cover the sidewall spacers SWS, the gate electrodes GE, and the element isolation films ISL. As shown in FIGS. 19 and 20, in the interlayer insulating film formation step S12, an interlayer insulating film ILD1 is formed on the protective film PF. In the interlayer insulating film formation step S12, first, a constituent material of the interlayer insulating film ILD1 is deposited on the protective film PF. Second, the upper surface of the constituent material of the interlayer insulating film ILD1 is planarized by, for example, a CMP method. In this manner, the interlayer insulating film ILD1 is formed.

[0035] 21 and 22, in the contact plug formation process S13, contact plugs CP1, CP2, CP3, CP4, and CP5 are formed in the interlayer insulating film ILD1 and the protective film PF. In the contact plug formation process S13, first, a resist pattern having openings is formed on the interlayer insulating film ILD1. Second, dry etching is performed on the interlayer insulating film ILD1 and the protective film PF through the openings in the resist pattern. As a result, contact holes CH1, CH2, CH3, CH4, and CH5 are formed in the interlayer insulating film ILD1 and the protective film PF.

[0036] Third, by, for example, a CVD method, constituent materials of the contact plug CP1 and the like are buried in the contact holes CH1, CH2, CH3, CH4, and CH5, and are also formed on the interlayer insulating film ILD1. Fourth, constituent materials of the contact plug CP1 and the like formed outside the contact holes CH1, CH2, CH3, CH4, and CH5 are removed by, for example, a CMP method.

[0037] 23 and 24, in the interconnect formation step S14, interconnects WL1a, WL1b, WL1c, WL1d, and WL1e are formed on the interlayer insulating film ILD1. In the interconnect formation step S14, first, the constituent materials of the interconnects WL1a, WL1b, WL1c, WL1d, and WL1e are deposited on the interlayer insulating film ILD1 by, for example, sputtering. Second, a resist pattern having openings is formed on the constituent materials of the interconnects WL1a, WL1b, WL1c, WL1d, and WL1e. Third, the constituent materials of the interconnects WL1a, WL1b, WL1c, WL1d, and WL1e are patterned by, for example, dry etching the constituent materials of the interconnects WL1a, WL1b, WL1c, WL1d, and WL1e through the openings in the resist pattern. In this way, the wiring WL1a, wiring WL1b, wiring WL1c, wiring WL1d, and wiring WL1e are formed.

[0038] In the interlayer insulating film forming step S15, an interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 so as to cover the wirings WL1a, WL1b, WL1c, WL1d, and WL1e. In the interlayer insulating film forming step S15, first, a constituent material of the interlayer insulating film ILD2 is deposited on the interlayer insulating film ILD1 by, for example, CVD so as to cover the wirings WL1a, WL1b, WL1c, WL1d, and WL1e. Second, the upper surface of the constituent material of the interlayer insulating film ILD2 is planarized by, for example, CMP. In this way, the interlayer insulating film ILD2 is formed, and the structure of the semiconductor device DEV1 shown in FIGS. 2 and 3 is completed.

[0039] <Effects of semiconductor device DEV1> In the semiconductor device DEV1, during a write operation, breakdown of the insulating film IF occurs between the contact plug CP4 and the impurity diffusion layer IDL, so the location of breakdown in the insulating film IF is less likely to vary. As a result, variation in the electrical resistance value of the anti-fuse element AFE after a write operation is suppressed. If the location of breakdown occurring in the insulating film used for OTP varies, it becomes necessary to form a peripheral structure to correct the variation in the electrical resistance value caused by the variation, which increases the chip area. In the semiconductor device DEV1, variation in the electrical resistance value of the anti-fuse element AFE after a write operation is suppressed, so there is no need to form a peripheral structure to suppress variation in the electrical resistance value of the anti-fuse element AFE. In this way, the semiconductor device DEV1 can reduce the chip area.

[0040] Furthermore, when the width of the lower end of the contact plug CP4 becomes smaller toward the insulating film IF, the position of the dielectric breakdown that occurs in the insulating film IF is less likely to vary, thereby further suppressing the variation in the electrical resistance value of the anti-fuse element AFE after the write operation.

[0041] (Second embodiment) A semiconductor device DEV2 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0042] <Configuration of semiconductor device DEV2> As shown in FIGS. 25 and 26, the semiconductor device DEV2 has wirings WL2a, WL2b, and WL2c instead of wirings WL1a, WL1b, WL1c, WL1d, and WL1e. The wirings WL2a, WL2b, and WL2c are formed in the same layer. In a plan view, the wirings WL2a and WL2b are arranged along the first direction DR1 with a gap between them. In the semiconductor device DEV2, grooves TR2a and TR2b are formed in the upper surface of the interlayer insulating film ILD2. The grooves TR2a and TR2b, for example, penetrate the interlayer insulating film ILD2. The wiring WL2a is formed in the groove TR2a, and the wiring WL2b is formed in the groove TR2b.

[0043] In the semiconductor device DEV2, a trench TR2c is further formed in the upper surface of the interlayer insulating film ILD2. The trench TR2c, for example, penetrates the interlayer insulating film ILD2. The wiring WL2c is formed in the trench TR2c. The wiring WL2a, the wiring WL2b, and the wiring WL2c are made of, for example, copper or a copper alloy.

[0044] The semiconductor device DEV2 further includes an interlayer insulating film ILD3. The interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2. The interlayer insulating film ILD3 is formed of, for example, silicon oxide. Note that in the semiconductor device DEV2, the interlayer insulating films ILD2 and ILD3 may be collectively referred to as the interlayer insulating film ILD. The wiring WL2a, wiring WL2b, and wiring WL2c are covered with the interlayer insulating film ILD.

[0045] A trench TR3a and a via hole VHa are formed in the interlayer insulating film ILD (interlayer insulating film ILD2, interlayer insulating film ILD3). The trench TR3a is formed on the upper surface of the interlayer insulating film ILD3. The via hole VHa is formed on the bottom surface of the trench TR3a so as to penetrate the interlayer insulating film ILD3. The via hole VHa is located between the wiring WL2a and the wiring WL2b in the first direction DR1. The lower end of the via hole VHa is located lower than the upper surfaces of the wiring WL2a and WL2b. That is, the lower end of the via hole VHa reaches the interlayer insulating film ILD2. In the semiconductor device DEV2, an insulating film IF is formed on the inner wall surface of the trench TR3a, on the bottom surface of the trench TR3a, and on the inner wall surface of the via hole VHa. In the semiconductor device DEV2, the insulating film IF is formed of, for example, silicon oxide or silicon nitride.

[0046] The semiconductor device DEV2 further has via plugs VPa, VPb, wiring WL3a, and wiring WL3b. The via plug VPa is formed in the via hole VHa. As described above, the lower end of the via hole VHa is located lower than the upper surfaces of the wiring WL2a and wiring WL2b, and therefore the lower end of the via plug VPa is located lower than the upper surfaces of the wiring WL2a and wiring WL2b. The wiring WL3a is formed in the trench TR3a. The via plug VPa and wiring WL3a are integrally formed of, for example, copper or a copper alloy. The insulating film IF and the interlayer insulating film ILD (interlayer insulating film ILD2) electrically insulate the via plug VPa from the wiring WL2a and from the via plug VPa from the wiring WL2b. However, it is sufficient that the insulating film IF at least electrically insulates the via plug VPa from the wiring WL2a and from the via plug VPa from the wiring WL2b.

[0047] When a voltage is applied to the wiring WL2a (wiring WL2b) from the voltage application circuit, the insulating film IF and the interlayer insulating film ILD between the via plug VPa and the wiring WL2a (wiring WL2b) undergo dielectric breakdown, and the electrical resistance value between the via plug VPa and the wiring WL2a (wiring WL2b) changes. Therefore, the wiring WL2a (wiring WL2b), the via plug VPa, the insulating film IF, and the interlayer insulating film ILD form an anti-fuse element AFE.

[0048] A trench TR3b and a via hole VHb are further formed in the interlayer insulating film ILD (interlayer insulating films ILD2 and ILD3). The trench TR3b is formed on the upper surface of the interlayer insulating film ILD3. The via hole VHb is formed on the bottom surface of the trench TR3b so as to penetrate the interlayer insulating film ILD3. The via hole VHb is located on the wiring WL2c. In the semiconductor device DEV2, an insulating film IF is also formed on the inner wall surface of the trench TR3b, the bottom surface of the trench TR3b, and the inner wall surface of the via hole VHb.

[0049] The via plug VPb is formed in the via hole VHb. The wiring WL3b is formed in the trench TR3b. The via plug VPb and the wiring WL3b are integrally formed of, for example, copper or a copper alloy. The via plug VPb electrically connects the wiring WL3b and the wiring WL2c. That is, the wiring WL2c and the wiring WL3b function as normal circuit wiring.

[0050] <Variation 1> As shown in FIG. 27A, the semiconductor device DEV2 may further include a wiring WL2d and a wiring WL2e. The wirings WL2a, WL2b, WL2d, and WL2e are formed in the same layer. The wirings WL2a and WL2d face each other in a second direction DR2 perpendicular to the first direction DR1, with a gap between them. The wirings WL2d and WL2e face each other in the first direction DR1, with a gap between them. The wirings WL2b and WL2e face each other in the second direction DR2, with a gap between them. Note that a trench TR2d and a trench TR2e are further formed on the upper surface of the interlayer insulating film ILD2. The wiring WL2d is formed in the trench TR2d, and the wiring WL2e is formed in the trench TR2e.

[0051] In plan view, the via hole VHa is located between the wiring WL2a and the wiring WL2e, and also between the wiring WL2b and the wiring WL2d. When a voltage from a voltage application circuit is applied to the wiring WL2a, dielectric breakdown occurs in the insulating film IF and the interlayer insulating film ILD2 located between the corner of the wiring WL2a in plan view and the corner of the via plug VPa in plan view. Similarly, when a voltage from the voltage application circuit is applied to any one of the wiring WL2b, the wiring WL2d, and the wiring WL2e, dielectric breakdown occurs in the insulating film IF and the interlayer insulating film ILD2 located between the corner of that one in plan view and the corner of the via plug VPa in plan view.

[0052] <Variation 2> 27B, in the semiconductor device DEV2, the wiring WL2a and the wiring WL2b may be exposed from the inner wall surface of the via hole VHa at the lower end thereof. In this case, the side surfaces of the wiring WL2a and the wiring WL2b are inclined so that the width of the lower end of the via hole VHa decreases toward the lower end thereof. From another perspective, the upper surfaces of the wiring WL2a and the wiring WL2b are not exposed from the inner wall surface of the via hole VHa. In this case, the insulating film IF electrically insulates the via plug VPa from the wiring WL2a (wiring WL2b).

[0053] <Variation 3> In the above description, the wirings WL2a, WL2b, WL2c, WL3a, and WL3b are formed of copper or a copper alloy. However, in the semiconductor device DEV2, as shown in FIG. 27C, the wirings WL2a, WL2b, WL2c, WL3a, and WL3b may be formed of aluminum or an aluminum alloy. In this case, the wirings WL2a, WL2b, and WL2c are formed on an interlayer insulating film ILD1, an interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 so as to cover the wirings WL2a, WL2b, and WL2c, the wirings WL3a and WL3b are formed on the interlayer insulating film ILD2, and an interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 so as to cover the wirings WL3a and WL3b. In this case, the via plugs VPa and VPb are formed of, for example, tungsten and are not integral with the wirings WL3a and WL3b.

[0054] <Method of manufacturing semiconductor device DEV2> 28, the method for manufacturing the semiconductor device DEV2 includes a wiring formation step S16, an interlayer insulating film formation step S17, a via hole formation step S18, an insulating film formation step S19, and a via plug formation step S20. The steps before the wiring formation step S16 are the same as those in the method for manufacturing the semiconductor device DEV1, and therefore will not be described here. However, the wiring formation step S14 is not performed in the method for manufacturing the semiconductor device DEV2.

[0055] As shown in FIGS. 29 and 30 , in the interconnect formation step S16, interconnects WL2a, WL2b, and WL2c are formed. In the interconnect formation step S16, first, a resist pattern having openings is formed on the interlayer insulating film ILD2. Second, the interlayer insulating film ILD2 is dry-etched through the openings in the resist pattern to form trenches TR2a, TR2b, and TR2c. Third, a barrier metal and a seed metal are formed on the inner wall surfaces of the trenches TR2a, TR2b, and TR2c, on the bottom surfaces of the trenches TR2a, TR2b, and TR2c, and on the interlayer insulating film ILD2. Fourth, plating is performed on the seed metal, thereby filling the trenches TR2a, TR2b, and TR2c with the constituent materials for the interconnects WL2a, WL2b, and WL2c, and forming the constituent materials for the interconnects WL2a, WL2b, and WL2c on the interlayer insulating film ILD2. Fourth, the constituent materials of the wirings WL2a, WL2b, and WL2c formed outside the trenches TR2a, TR2b, and TR2c are removed by, for example, the CMP method. As described above, the wirings WL2a, WL2b, and WL2c are formed by the single damascene method.

[0056] 31 and 32, in the interlayer insulating film forming step S17, an interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 by, for example, a CVD method. As shown in FIGS. 33 and 34, in the via hole forming step S18, via holes VHa and VHb are formed. In the via hole forming step S18, trenches TR3a and TR3b are also formed. In the via hole forming step S18, first, a first resist pattern having an opening is formed on the interlayer insulating film ILD3.

[0057] Second, the interlayer insulating film ILD3 is dry-etched through the openings in the first resist pattern, thereby forming via holes VHa and VHb. At this time, the etching is stopped on the wiring WL2c by the wiring WL2c, but is not stopped between the wiring WL2a and the wiring WL2b, so the via hole VHa is deeper than the via hole VHb. Third, a second resist pattern having openings is formed on the interlayer insulating film ILD3. Fourth, the interlayer insulating film ILD3 is dry-etched again through the openings in the second resist pattern, thereby forming grooves TR3a and TR3b.

[0058] 35 and 36, in the insulating film forming step S19, an insulating film IF is formed on the inner wall surfaces of the via holes VHa, VHb, VHb, TR3a, TR3b, TR3b's bottom surface, and TR3b's inner wall surfaces. In the insulating film forming step S19, first, by CVD, for example, an insulating film IF is formed on the inner wall surfaces of the via holes VHa, VHb, VHb's bottom surface, TR3a, TR3b's inner wall surfaces, TR3a's bottom surface, TR3b's inner wall surfaces, TR3b's bottom surface. Second, by dry etching, the insulating film IF is removed from the bottom surfaces of the via holes VHa and VHb's bottom surfaces. Thus, the insulating film IF is formed.

[0059] In the via plug forming process S20, a via plug VPa is formed in the via hole VHa, a via plug VPb is formed in the via hole VHb, and wirings WL3a and WL3b are formed in the trenches TR3a and TR3b. In the via plug forming process S20, first, a barrier metal and a seed metal are formed on the insulating film IF, on the bottom surface of the via hole VHa, and on the inner wall surface of the via hole VHb. Second, plating is performed on the seed metal, so that the constituent materials of the via plugs VPa, VPb, wirings WL3a, and wirings WL3b are embedded in the via holes VHa, VHb, and trenches TR3a and TR3b, and are also formed on the interlayer insulating film ILD3. Third, the constituent materials of the wirings WL3a and WL3b formed outside the trenches TR3a and TR3b are removed by, for example, CMP. As described above, the via plugs VPa, VPb, the wiring WL3a and the wiring WL3b are formed by the dual damascene method, and the structure of the semiconductor device DEV2 shown in FIGS. 25 and 26 is completed.

[0060] 27B, the dry etching conditions in the via hole formation step S19 are adjusted so that the etching rate for the wirings WL2a and WL2b is larger than that in the case of forming the structure shown in FIGS. 25 and 26. That is, the dry etching conditions in the via hole formation step S19 are adjusted so that the selectivity for the wirings WL2a and WL2b is smaller. This makes it easier to remove the corners of the wirings WL2a and WL2b exposed from the inner wall surface of the via hole VHa at the bottom end of the via hole VHa by dry etching, and the shape of the side surfaces of the wirings WL2a and WL2b shown in FIG. 27B, i.e., the shape of the inner wall surface of the via hole VHa at the bottom end of the via hole VHa, is formed. In this case, when dry etching is performed to remove the insulating film IF formed on the bottom surface of the via hole VHa and the bottom surface of the via hole VHb in the insulating film formation process S19, the insulating film IF formed on the side surface of the wiring WL2a and the side surface of the wiring WL2b is difficult to remove, and the insulating film IF can more reliably electrically insulate the wiring WL2a and the wiring WL2b from the via plug VPa.

[0061] 27C, in the interconnect formation step S16, interconnects WL2a, WL2b, and WL2c are formed by the same method as in the interconnect formation step S14, and in the interlayer insulating film formation step S17, the interlayer insulating film ILD2 is formed by the same method as in the interlayer insulating film formation step S15. Also, in the via hole formation step S18, only the via holes VHa and VHb are formed, and the trenches TR3a and TR3b are not formed.

[0062] When forming the structure of the semiconductor device DEV2 shown in FIG. 27C, in the via plug forming step S20, first, the constituent materials of the via plug VPa and the via plug VPb are embedded in the via hole VHa and the via hole VHb, and are formed on the interlayer insulating film ILD2. Second, the constituent materials of the via plug VPa and the via plug VPb formed outside the via hole VHa and outside the via hole VHb are removed, for example, by the CMP method. When forming the structure of the semiconductor device DEV2 shown in FIG. 27C, after the via plugs VPa and VPB are formed, wirings WL3a and WL3b are formed on the interlayer insulating film ILD2 by the same method as in the wiring forming step S16. After the wirings WL3a and WL3b are formed, an interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 so as to cover the wirings WL3a and WL3b by the same method as in the interlayer insulating film forming step S15.

[0063] <Effect of the semiconductor device DEV2> In the semiconductor device DEV2, in the write operation, since dielectric breakdown of the insulating film IF occurs between the via plug VPa and the wiring WL2a (wiring WL2b), the position of the dielectric breakdown occurring in the insulating film IF is less likely to vary. As a result, variation in the electrical resistance value of the anti-fuse element AFE after the write operation is suppressed.

[0064] Therefore, the semiconductor device DEV2 eliminates the need to form a peripheral structure for suppressing variations in the electrical resistance value of the anti-fuse element AFE, thereby avoiding an increase in chip area associated with the formation of the anti-fuse element AFE. Furthermore, the proportion of the area of ​​the wiring layer located above the semiconductor substrate SUB in which wiring and via plugs are formed in a planar view is smaller than the proportion of the area of ​​the semiconductor substrate SUB in which transistors and their peripheral structures are formed in a planar view. In other words, the wiring layer located above the semiconductor substrate SUB has a relatively large area margin for forming new structures. In the semiconductor device DEV2, this area margin can be utilized to form the anti-fuse element AFE in the wiring layer located above the semiconductor substrate SUB, thereby further suppressing an increase in chip area associated with the formation of the anti-fuse element AFE. Furthermore, in the semiconductor device DEV2, one anti-fuse element AFE has multiple breakdown points. More specifically, the semiconductor device DEV2 has two breakdown points in the examples shown in FIGS. 25 and 26 and four breakdown points in the example shown in FIG. 27. This allows the anti-fuse element to be multi-bit. In the example shown in FIG. 27, the wiring and the via hole VHa are not adjacent to each other in the first direction DR1 and the second direction DR2, and therefore the overlay margin when forming the via hole VHa is improved.

[0065] 25 and 26, if the formation position of the via hole VHa is shifted in the first direction DR1, the wiring WL2a or the wiring WL2b may be exposed from the inner wall surface of the via hole VHa. However, since the insulating film IF is formed on the inner wall surface of the via hole VHa, even if such a shift occurs in the formation position of the via hole VHa, a short circuit between the via plug VPa and the wiring WL2a or the wiring WL2b is suppressed.

[0066] (Third embodiment) A semiconductor device DEV3 according to the third embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV2, and overlapping descriptions will not be repeated.

[0067] As shown in Figures 37 and 38, in the semiconductor device DEV3, the insulating film IF is formed on the interlayer insulating film ILD2 so as not to overlap with the trenches TR2a, TR2b, and TR2c. In the semiconductor device DEV3, the insulating film IF is made of, for example, aluminum oxide or aluminum oxynitride. The semiconductor device DEV3 further has a cap insulating film CAP. The cap insulating film CAP is formed on the interlayer insulating film ILD2 so as to cover the insulating film IF, and an interlayer insulating film ILD3 is formed on the cap insulating film CAP. The cap insulating film CAP is made of, for example, silicon nitride, silicon carbonitride, or the like. In the semiconductor device DEV3, the interlayer insulating film ILD2, the interlayer insulating film ILD3, and the cap insulating film CAP may be collectively referred to as the interlayer insulating film ILD.

[0068] In the semiconductor device DEV3, a via hole VHa is formed in the interlayer insulating film ILD3 and the cap insulating film CAP on the insulating film IF. Therefore, the insulating film IF electrically insulates the via plug VPa from the wiring WL2a and the via plug VPa from the wiring WL2b. When a voltage is applied to the wiring WL2a (wiring WL2b) from the voltage application circuit, the insulating film IF undergoes dielectric breakdown between the via plug VPa and the wiring WL2a (wiring WL2b), and the electrical resistance value between the via plug VPa and the wiring WL2a (wiring WL2b) changes. Therefore, the wiring WL2a (wiring WL2b), the via plug VPa, and the insulating film IF form an anti-fuse element AFE.

[0069] <Modification> As shown in FIG. 39, the semiconductor device DEV3 may further include wiring WL2d and wiring WL2e. The wirings WL2a, WL2b, WL2d, and WL2e are formed in the same layer. In a plan view, the wirings WL2a and WL2d face each other in a second direction DR2 perpendicular to the first direction DR1, with a gap between the wiring WL2a and the wiring WL2d. In a plan view, the wirings WL2d and WL2e face each other in the first direction DR1, with a gap between the wiring WL2d and the wiring WL2e. In a plan view, the wirings WL2b and WL2e face each other in the second direction DR2, with a gap between the wiring WL2b and the wiring WL2e. In a plan view, the via hole VHa is located between the wirings WL2a and WL2e and between the wirings WL2b and WL2d.

[0070] <Method of manufacturing semiconductor device DEV3> As shown in FIG. 40, the manufacturing method of the semiconductor device DEV3 includes an insulating film forming step S21 instead of the insulating film forming step S19. The manufacturing method of the semiconductor device DEV3 also includes a cap insulating film forming step S22. The insulating film forming step S21 is performed after the interconnect forming step S16, the cap insulating film forming step S22 is performed after the insulating film forming step S21, and the interlayer insulating film forming step S17 is performed after the cap insulating film forming step S22. As shown in FIGS. 41 and 42, in the insulating film forming step S21, the insulating film IF is formed in a self-aligned manner on the upper surface of the interlayer insulating film ILD2 by, for example, the SAM (Self-Assembled Monolayer) method so as not to overlap with the trenches TR2a (interconnects WL2a), TR2b (interconnects WL2b), and TR2c (interconnects WL2c). As shown in FIGS. 43 and 44, in the cap insulating film forming step S22, a cap insulating film CAP is formed on the interlayer insulating film ILD2 by, for example, the CVD method so as to cover the insulating film IF.

[0071] <Effects of semiconductor device DEV3> In the semiconductor device DEV3, during a write operation, breakdown of the insulating film IF occurs between the via plug VPa and the wiring WL2a (wiring WL2b), so the location of breakdown in the insulating film IF is less likely to vary.As a result, variation in the electrical resistance value of the anti-fuse element AFE after a write operation is suppressed.In the semiconductor device DEV3, the corners of the via plug VPa in a planar view are areas where electric fields concentrate and breakdown is more likely to occur at these areas, so the voltage applied during a write operation can be reduced.

[0072] Therefore, the semiconductor device DEV3 eliminates the need to form a peripheral structure that suppresses variations in the electrical resistance value of the antifuse element AFE, thereby avoiding an increase in chip area associated with the formation of the antifuse element AFE. Furthermore, the proportion of the area of ​​the wiring layer located above the semiconductor substrate SUB in which wiring and via plugs are formed in a planar view is smaller than the proportion of the area of ​​the semiconductor substrate SUB in which transistors and their peripheral structures are formed in a planar view. In other words, the wiring layer located above the semiconductor substrate SUB has a relatively large area margin for forming new structures. The semiconductor device DEV3 can utilize this area margin to form the antifuse element AFE in the wiring layer located above the semiconductor substrate SUB, thereby further suppressing an increase in chip area associated with the formation of the antifuse element AFE. Furthermore, in the semiconductor device DEV3, one antifuse element AFE has multiple breakdown points. More specifically, the semiconductor device DEV3 has two breakdown points in the examples shown in FIGS. 37 and 38 and four breakdown points in the example shown in FIG. 39. This allows the antifuse element to have multiple bits. In the example shown in FIG. 39, the wiring and the via hole VHa are not adjacent to each other in the first direction DR1 and the second direction DR2, and therefore the overlay margin when forming the via hole VHa is improved.

[0073] In the semiconductor device DEV3, the steps from the interlayer insulating film formation step S17 onwards are the same as the normal steps, so no additional mask is required to form the anti-fuse element AFE. Also, the insulating film IF functions as an etch stopper against the etching for forming the via hole VHa, so the process for forming the via hole VHa can be easily controlled.

[0074] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0075] AFE anti-fuse element, CAP cap insulating film, CH1, CH2, CH3, CH4, CH5 contact holes, CP1, CP2, CP3, CP4, CP5 contact plugs, DEV1, DEV2, DEV3 semiconductor device, DL drain layer, DLa first portion, DLb second portion, DR1 first direction, DR2 second direction, F1 upper surface, F2 lower surface, GE gate electrode, GI gate insulating film, IDL impurity diffusion layer, IF insulating film, ILD, ILD1, ILD2, ILD3 interlayer insulating film, ISL element isolation film, MC memory cell, OP opening, PF protective film, S1 preparation step, S2 element isolation film formation step, S3 ion implantation step, S4 gate insulating film formation step, S5 gate electrode formation step, S6 ion implantation step, S7 sidewall spacer formation step, S8 ion implantation step, S9 insulating film formation step, S10 silicide step, S11 Protective film forming step, S12 interlayer insulating film forming step, S13 contact plug forming step, S14 wiring forming step, S15 interlayer insulating film forming step, S16 wiring forming step, S17 interlayer insulating film forming step, S18 via hole forming step, S19 insulating film forming step, S20 via plug forming step, S21 insulating film forming step, S22 cap insulating film forming step, SEL select transistor, SEN sense circuit, SILa, SILb, SILc, SILd silicide layer, SL source layer, SLa first portion, SLb second portion, SUB semiconductor substrate, SWS sidewall spacer, TR1, TR2a, TR2b, TR2d, TR2c, TR3b, TR3a trench, VHa, VHb via hole, VPa, VPb via plug, WEL Well layer, WL1d, WL1e, WL1a, WL1c, WL1b, WL2c, WL2a, WL2d, WL2e, WL2b, WL3a, WL3b wiring, WOR word line.

Claims

1. an anti-fuse element having a semiconductor substrate, an insulating film, and a first contact plug; the semiconductor substrate has an upper surface; the semiconductor substrate has an impurity diffusion layer formed in the semiconductor substrate and on the upper surface thereof; the insulating film is formed on the impurity diffusion layer, The first contact plug is formed on the insulating film so as to be in contact with the insulating film.

2. the first contact plug has a bottom end; 2. The semiconductor device according to claim 1, wherein the width of said lower end portion decreases toward said insulating film.

3. a protective film formed on the insulating film; an interlayer insulating film formed on the protective film, a first contact hole penetrating the protective film and the interlayer insulating film is formed in the protective film and the interlayer insulating film; 2. The semiconductor device according to claim 1, wherein said first contact plug is formed in said first contact hole.

4. 4. The semiconductor device according to claim 3, wherein said protective film is made of silicon nitride.

5. an opening penetrating the insulating film is formed in the insulating film; the impurity diffusion layer has a silicide layer formed on the upper surface thereof, the silicide layer overlaps the opening in a plan view, 2. The semiconductor device according to claim 1, wherein said anti-fuse element further comprises a second contact plug formed on said silicide layer.

6. 2. The semiconductor device according to claim 1, wherein said insulating film is a silicide blocking film.

7. 2. The semiconductor device according to claim 1, wherein said insulating film is made of silicon oxide.

8. a protective film formed on the insulating film and the silicide layer; an interlayer insulating film formed on the protective film, a first contact hole and a second contact hole are formed in the protective film and the interlayer insulating film; the first contact hole and the second contact hole penetrate the protective film and the interlayer insulating film; the first contact plug is formed in the first contact hole; The semiconductor device according to claim 5 , wherein said second contact plug is formed in said second contact hole.

9. an anti-fuse element having a first wiring, a via plug, and an insulating film; The insulating film electrically insulates the via plug from the first wiring.

10. the anti-fuse element further includes an interlayer insulating film covering the first wiring, a via hole is formed in the interlayer insulating film; the via plug is formed in the via hole such that a lower end of the via plug is located below a first upper surface of the first wiring; 10. The semiconductor device according to claim 9, wherein said insulating film is formed on an inner wall surface of said via hole.

11. the anti-fuse element further includes a second wiring formed in the same layer as the first wiring, the first wiring and the second wiring are arranged in a first direction with a gap between the first wiring and the second wiring, The semiconductor device according to claim 10 , wherein the via hole is located between the first wiring and the second wiring in a plan view.

12. the anti-fuse element further includes a second wiring, a third wiring, and a fourth wiring, the second wiring, the third wiring, and the fourth wiring are formed in the same layer as the first wiring, the first wiring faces the second wiring with a gap therebetween in a first direction, and faces the third wiring with a gap therebetween in a second direction perpendicular to the first direction, in a plan view; the fourth wiring faces the third wiring with a gap therebetween in the first direction, and faces the second wiring with a gap therebetween in the second direction, in a plan view; 11. The semiconductor device according to claim 10, wherein the via hole is located between the first wiring and the fourth wiring, and between the second wiring and the third wiring, in a plan view.

13. the anti-fuse element further includes an interlayer insulating film, a groove is formed in the second upper surface of the interlayer insulating film; the first wiring is formed in the trench, the insulating film is formed on the second upper surface so as not to overlap the groove in a plan view; 10. The semiconductor device according to claim 9, wherein said via plug is formed on said insulating film so as to be located adjacent to said first wiring in a plan view.

14. the anti-fuse element further includes an interlayer insulating film, a first groove and a second groove are formed in a second upper surface of the interlayer insulating film; the anti-fuse element further includes a second wiring; the first wiring is formed in the first trench, the second wiring is formed in the second trench, the first wiring and the second wiring are arranged in a first direction with a gap between the first wiring and the second wiring, the insulating film is formed on the second upper surface so as not to overlap with the first groove and the second groove in a plan view; 10. The semiconductor device according to claim 9, wherein said via plug is formed on said insulating film so as to be located between said first wiring and said second wiring in a plan view.

15. the anti-fuse element further includes an interlayer insulating film, a first groove, a second groove, a third groove, and a fourth groove are formed in a second upper surface of the interlayer insulating film; the anti-fuse element further includes a second wiring, a third wiring, and a fourth wiring, the first wiring is formed in the first trench, the second wiring is formed in the second trench, the third wiring is formed in the third trench, the fourth wiring is formed in the fourth trench, the first wiring faces the second wiring at an interval in a first direction, and faces the third wiring at an interval along a second direction perpendicular to the first direction, in a plan view; the fourth wiring faces the third wiring with a gap therebetween in the first direction, and faces the second wiring with a gap therebetween in the second direction, in a plan view; the insulating film is formed on the second upper surface so as not to overlap with the first groove, the second groove, the third groove, and the fourth groove in a plan view; 10. The semiconductor device according to claim 9, wherein the via plug is formed on the insulating film so as to be located between the first wiring and the fourth wiring and between the second wiring and the third wiring in a plan view.

Images