Host device

Abstract

To speed up a communication interface.SOLUTION: A host device is provided having a connector, a transmitter, a receiver, a first AC coupling capacitor, and a second AC coupling capacitor. The connector includes a first group of connector contacts and a second group of connector contacts. The first connector contact group is connectable to the first terminal group. The second connector contact group is connectable to the second terminal group. The first connector contact group includes a terminal to which a differential clock signal compliant with the PCIe standard is assigned, a terminal to which a single-ended signal is assigned, and a terminal to which a first power supply voltage is assigned. The second connector contact group includes two terminals to which a first differential data signal is assigned, two terminals to which a second differential data signal is assigned, and a plurality of terminals to which ground is assigned.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiments generally relate to host devices. [Background technology]

[0002] As memory cards have increased storage capacity, the amount of data transferred has also increased. To prevent this increase in data transfer time, there is a demand for faster communication interfaces installed in memory cards. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-29556 Summary of the Invention [Means for solving the problem]

[0004] According to one embodiment, there is provided a host device having a connector, a transmitter, a receiver, a first AC coupling capacitor, and a second AC coupling capacitor. The connector is connectable to a memory card. The memory card has a first surface, a second surface, a first terminal group, and a second terminal group. The first surface includes a first row and a second row. The second surface faces the opposite side from the first surface. The first terminal group is arranged in the first row. The second terminal group is arranged in the second row. The transmitter transmits a first differential data signal to the connector via a first transmission path. The first differential data signal complies with the PCIe standard. The receiver receives a second differential data signal from the connector via a second transmission path. The second differential data signal complies with the PCIe standard. The first AC coupling capacitor is provided in the first transmission path. The second AC coupling capacitor is provided in the second transmission path. The connector includes a first connector contact group and a second connector contact group. The first connector contact group is connectable to a first terminal group. The second connector contact group is connectable to a second terminal group. The first connector contact group includes terminals to which a differential clock signal conforming to the PCIe standard is assigned, a terminal to which a single-ended signal is assigned, and a terminal to which a first power supply voltage is assigned. The second connector contact group includes two terminals to which a first differential data signal is assigned, two terminals to which a second differential data signal is assigned, and a plurality of terminals to which ground is assigned. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of a memory card according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing a schematic configuration of a memory card according to the second embodiment. [Figure 3] FIG. 3 is a plan view showing another schematic configuration of the memory card according to the second embodiment. [Figure 4A] FIG. 4A is a plan view showing a schematic configuration of a memory card according to a third embodiment. [Figure 4B] FIG. 4B is a plan view showing a schematic configuration of a memory card according to the fifth embodiment. [Figure 4C] FIG. 4C is a plan view showing a schematic configuration of a memory card according to the fourth embodiment. [Figure 5] FIG. 5 is a block diagram showing a schematic configuration of a memory card according to the sixth embodiment. [Figure 6] FIG. 6 is a block diagram showing a schematic configuration of a host device in which a memory card according to the seventh embodiment is installed. [Figure 7] FIG. 7 is a block diagram showing a schematic configuration of an interface card to which a memory card according to the eighth embodiment is attached. [Figure 8] FIG. 8 is a flowchart showing the operation of the host device when setting the bus mode of the memory card according to the ninth embodiment. [Figure 9] FIG. 9 is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the tenth embodiment. [Figure 10A] FIG. 10A is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to an eleventh embodiment. [Figure 10B] FIG. 10B is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the twelfth embodiment. [Figure 11A] FIG. 11A is a perspective view showing an example of a schematic configuration of a connector used in a memory card according to a thirteenth embodiment. [Figure 11B] FIG. 11B is a cross-sectional view showing an example of a schematic configuration of a connector used in a memory card according to the thirteenth embodiment. [Figure 12A] FIG. 12A is a cross-sectional view showing an example of a schematic configuration of a connector according to a fourteenth embodiment before a memory card is inserted. [Figure 12B] FIG. 12B is a plan view showing an example of a schematic configuration of a connector according to the fourteenth embodiment before a memory card is inserted. [Figure 12C] FIG. 12C is a cross-sectional view showing an example of a schematic configuration of the connector after the memory card according to the fourteenth embodiment is mounted. [Figure 12D] FIG. 12D is a plan view showing an example of a schematic configuration of the connector after the memory card according to the fourteenth embodiment is inserted. [Figure 13A] FIG. 13A is a cross-sectional view showing an example of a schematic configuration of an adapter before a memory card is inserted according to the fifteenth embodiment. [Figure 13B] FIG. 13B is a plan view showing an example of a schematic configuration of the adapter before a memory card is inserted according to the fifteenth embodiment. [Figure 13C] FIG. 13C is a cross-sectional view showing an example of a schematic configuration of the adapter after a memory card has been inserted according to the fifteenth embodiment. [Figure 13D] FIG. 13D is a plan view showing an example of a schematic configuration of the adapter after a memory card is inserted according to the fifteenth embodiment. [Figure 14A] FIG. 14A is a cross-sectional view showing an example of a schematic configuration of an adapter before a memory card is inserted according to the sixteenth embodiment. [Figure 14B] FIG. 14B is a plan view showing an example of a schematic configuration of the adapter before a memory card is inserted according to the sixteenth embodiment. [Figure 14C] FIG. 14C is a cross-sectional view showing an example of a schematic configuration of the adapter after a memory card according to the sixteenth embodiment is inserted. [Figure 14D] FIG. 14D is a plan view showing an example of a schematic configuration of the adapter after a memory card according to the sixteenth embodiment is inserted. [Figure 15A] FIG. 15A is a cross-sectional view showing an example of a schematic configuration of an adapter before a memory card is inserted according to the seventeenth embodiment. [Figure 15B] FIG. 15B is a plan view showing an example of a schematic configuration of the adapter according to the seventeenth embodiment before a memory card is inserted. [Figure 15C] FIG. 15C is a cross-sectional view showing an example of a schematic configuration of the adapter after a memory card according to the seventeenth embodiment is inserted. [Figure 15D]FIG. 15D is a plan view showing an example of a schematic configuration of the adapter after a memory card according to the seventeenth embodiment is inserted. [Figure 16A] FIG. 16A is a perspective view showing a schematic configuration of a memory card according to the eighteenth embodiment. [Figure 16B] FIG. 16B is a cross-sectional view showing an example of a schematic configuration of the adapter before a memory card is inserted according to the nineteenth embodiment. [Figure 16C] FIG. 16C is a perspective view showing a schematic configuration of a memory card according to the twentieth embodiment. [Figure 16D] FIG. 16D is a cross-sectional view showing the state of the adapter after the memory card of FIG. 16C has been inserted. [Figure 17] FIG. 17 is a plan view showing an example of a schematic configuration of an adapter after a memory card according to the twenty-first embodiment is inserted. [Figure 18] FIG. 18 is a plan view showing a schematic configuration of a memory card according to the twenty-second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] A memory card, a host device, a memory card connector, and a memory card adapter according to embodiments will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. In the following embodiments, an SD card is used as an example of a memory card, but other cards such as a multimedia card may also be used.

[0007] (First embodiment) FIG. 1 is a plan view showing a schematic configuration of a memory card according to the first embodiment. In FIG. 1, rows R1 and R2 are provided on the card surface of memory card SD1. Terminal groups PA1 and PA2 are provided in rows R1 and R2, respectively. Row R1 can specify an area where the terminals of terminal group PA1 are arranged horizontally. Row R2 can specify an area where the terminals of terminal group PA2 are arranged horizontally.

[0008] The terminals of the terminal groups PA1 and PA2 may have different dimensions, and the spacing between the terminals of the terminal groups PA1 and PA2 may also be different. In row R1, the positions of the terminals of the terminal group PA1 may be shifted vertically. In row R2, the positions of the terminals of the terminal group PA2 may be shifted vertically.

[0009] The form factor of this memory card SD1 can be made compatible with microSD cards, with the vertical dimension A1 of the memory card SD1 being set to 15 mm, the horizontal dimension B1 being set to 11 mm, and the thickness being set to 1.0 mm.

[0010] Each of the rows R1 and R2 is assigned a signal used for communication conforming to a single interface standard. At this time, it is possible to prevent signals used for communication conforming to multiple interface standards from being assigned to a single row. However, signals used for communication conforming to a single interface standard may be assigned to multiple rows.

[0011] Signals used for communication in a first mode conforming to the SD standard are assigned to row R1. Single-ended signals can be used for communication in the first mode conforming to the SD standard. That is, single-ended signals conform to the SD standard. In the first mode conforming to the SD standard, a power supply VDD, a ground potential VSS, a command CMD, a clock CLK, and data DAT[3:0] are assigned to terminal group PA1.

[0012] The first mode, which complies with the SD standard, allows communication in accordance with DS (Default Speed), HS (High Speed), or UHS (Ultra High Speed)-I. The maximum transfer speed for DS is 12.5 MB / s, for HS it is 25 MB / s, and for UHS-I it is 104 MB / s.

[0013] Row R2 is assigned signals used for communication in a second mode compliant with the PCIe (Peripheral Component Interconnect express) standard. In the second mode compliant with the PCIe standard, differential signals can be used for data communication. In the second mode compliant with the PCIe standard, transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N are assigned to terminal group PA2. Bidirectional communication can be performed using the transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N. In this case, in row R2, GND terminals at ground potential are assigned to sandwich the terminals assigned to the differential signals.

[0014] Furthermore, in row R2, one terminal of the terminal group PA2 is assigned to the power supply terminal VDD2 or the power supply terminal VDD3, and another terminal of the terminal group PA2 is assigned to the power supply terminal VDD2. Furthermore, yet another terminal of the terminal group PA2 is assigned to SWIO. SWIO can be used for NFC (Near Field Communication).

[0015] In the first mode, which complies with the SD standard, the clock CLK and the data DAT[3:0] are assigned to separate terminals, and therefore the clock CLK and the data DAT[3:0] are transmitted via separate transmission paths.

[0016] In the second mode, which complies with the PCIe standard, data is transmitted serially, but the data is coded in units to prevent the same voltage level from continuing for long periods so that the receiving circuit can generate a clock. Methods such as 8B10B or 128b / 130b are used for coding. The receiving side generates a clock from the point where the data changes, allowing it to receive data even if the voltage level fluctuates slightly. Even when there are multiple lanes (pairs of uplink and downlink differential data signals), lane-to-lane skew can be canceled by configuring independent receiving circuits for each lane and aligning the start position of the received data.

[0017] For example, in the second mode compatible with the PCIe 3.0 standard, the maximum transfer speed is 2 GB / s per lane (upstream and downstream combined). In the second mode compatible with the PCIe standard, one lane can be configured with a pair of transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N. One pair of transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N can be placed in one row of the memory card SD1.

[0018] Therefore, by increasing the number of rows of the memory card SD1, the number of lanes in the second mode compatible with the PCIe standard can be increased, and the transfer speed in the second mode compatible with the PCIe standard can be improved. In the second mode compatible with the PCIe standard, a multi-lane configuration is recognized during initialization, and one piece of data can be transferred over multiple lanes.

[0019] When communication is performed in the second mode conforming to the PCIe standard, control signals used to control communication in the second mode conforming to the PCIe standard are assigned to row R1. These control signals may include the reference differential clock signal REFCLKp / n, the reset signal PERST, and the power management control signal CLKREQ. Furthermore, these control signals may also include the wake-up signal PEWAKE. These control signals are assigned instead of the command CMD and data DAT[3:0] of row R1.

[0020] Two reference differential clock signals REFCLKp / n form a differential clock, and by sending the clock from the host device, memory card SD1 can easily synchronize with the host device in which it is installed. However, the reference differential clock signal REFCLKp / n is assigned to row R1, while the transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N are assigned to row R2 and later. For this reason, the reference differential clock signal REFCLKp / n is transmitted over a transmission path separate from that of the transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N.

[0021] The host device may be, for example, an information processing device such as a personal computer, a mobile phone, a digital camera, an imaging device, a mobile terminal such as a tablet computer or a smartphone, a game device, or an in-vehicle terminal such as a car navigation system.

[0022] The memory card SD1 generates a bit clock by multiplying the received reference differential clock. Data is output from the transmit differential signals TX0P, TX0N in synchronization with the bit clock, and the data read from the receive differential signals RX0P, RX0N is synchronized with the bit clock and aligned. Even in the case of multiple lanes, data can be synchronized with the bit clock and aligned as a single piece of data.

[0023] The reset signal PERST can be used by the host device to reset the bus used for communication in the second mode conforming to the PCIe standard, and can be used by the host device to reinitialize the card when an error occurs, for example.

[0024] The power management control signal CLKREQ can be used as a clock to return from power saving mode, which can reduce power consumption by stopping the high-frequency bit clock used for data transfer.

[0025] If the wake-up signal PEWAKE is implemented in the memory card SD1, the memory card SD1 can use the wake-up signal PEWAKE to notify the host device of various events in power-saving mode. When the host device receives the wake-up signal PEWAKE from the memory card SD1, it can cancel power-saving mode and process the event. Some memory cards also implement I / O functions, and can also be used as a means of notifying I / O interrupts.

[0026] In row R2, one terminal of terminal group PA2 is assigned to power supply terminal VDD2 or power supply terminal VDD3. The host device can supply power supply voltage VDD1 to the power supply VDD of row R1. The power supply voltage VDD1 can be set to 3.3V. The power supply terminal VDD2 of row R2 can be supplied with power supply voltage VDD2. The power supply voltage VDD2 can be set to 1.8V. Alternatively, the power supply terminal VDD3 of row R2 can be supplied with power supply voltage VDD3. The power supply voltage VDD3 can be set to 1.2V. The power supply voltage notation indicates the median value, and a certain voltage fluctuation range is allowed. For example, the allowable range for 3.3V is 2.7V to 3.6V, for 1.8V is 1.70 to 1.95V, and for 1.2V is 1.1V to 1.3V.

[0027] The following explanation assumes the presence of the power supply terminal VDD3, but if the memory card SD1 that supports the power supply voltage VDD3 does not have the power supply terminal VDD3, the power supply voltage VDD2 or VDD3 can be supplied using the power supply terminal VDD2 in row R2. Specifically, the power supply voltage VDD2 is applied at 1.8V or 1.2V. In other words, there are cases where the memory card SD1 does not have the power supply terminal VDD3, but the explanation is the same; simply change the supply destination of the power supply voltage VDD3 to the power supply terminal VDD2. In the above description, the signals used for communication in the second mode conforming to the PCIe standard are assigned to Row R2, but signals used for communication in UHS-II may also be assigned to Row R2. The maximum transfer speed of UHS-II is 312 MB / s.

[0028] Here, the power supply voltage VDD2 or the power supply voltage VDD3 can be used to determine whether the memory card SD1 communicates in the second mode compliant with the UHS-II standard or the second mode compliant with the PCIe standard. When a power supply voltage is applied to the power supply terminal VDD2 or the power supply terminal VDD3 of the terminal group PA2, the memory card SD1 can communicate in the PCIe bus mode if it supports the PCIe standard.

[0029] Alternatively, there is a method of switching by detecting the change point of the power supply voltage VDD2 or VDD3. When VDD2 or VDD3 changes from off to on, the device enters PCIe bus mode, and when it changes from on to off, the device exits PCIe bus mode. This allows operation in SD mode whether VDD2 or VDD3 is on or off.

[0030] Host devices that use the UHS-II standard apply the power supply voltage VDD2 to the power supply terminal VDD2, while host devices that use the PCIe standard apply either the power supply voltage VDD2 to the power supply terminal VDD2 or the power supply voltage VDD3 to the power supply terminal VDD3. The memory card SD1 can easily determine the bus mode expected by the host device based on the combination of the presence or absence of the VDD2 / VDD3 voltages. Therefore, the memory card SD1 does not need to determine the bus mode based on the symbols sent in the data.

[0031] To enable a host device to determine whether memory card SD1 supports the PCIe standard or the UHS-II standard, a PCIe-compatible host device can transmit a predetermined PCIe symbol to terminal group PA2 in row R2 to determine that the memory card supports the PCIe standard. If memory card SD1 responds to the symbol, the host device can determine that the memory card supports the PCIe standard. A UHS-II-compatible host device can transmit a UHS-II initialization symbol to terminal group PA2 in row R2. If memory card SD1 responds to the symbol, the host device can determine that the memory card supports UHS-II.

[0032] Here, by assigning the signals used for communication in the second mode compliant with the PCIe standard to row R2 and enabling memory card SD1 to support communication in accordance with the PCIe standard, the data transfer speed can be increased. As the storage capacity of memory card SD1 increases, the time required to access the entire memory area increases, but this time can be reduced by further increasing the bus speed using methods such as a multi-lane configuration.

[0033] Furthermore, because the memory card SD1 supports PCIe-compliant communications, it can use the standard PCIe physical layer (PHY), which simplifies the design and reduces development costs for increasing the data transfer speed of the memory card SD1.

[0034] Furthermore, the SD1 memory card's support for PCIe communication means that NVMe (Non Volatile Memory Express) can be used for the PCIe data link layer, reducing data transfer overhead and improving data transfer efficiency.

[0035] (Second embodiment) FIG. 2 is a plan view showing a schematic configuration of a memory card according to the second embodiment.

[0036] In Fig. 2, rows R1 to R4 are provided on the card surface of memory card SD2. Rows R1 and R2 are provided with terminal groups PA1 and PA2, respectively. Rows R1 and R2 can be used in the same way as memory card SD1 in Fig. 1. For example, row R2 can support UHS-II, and rows R3 and R4 can support the PCIe standard.

[0037] Rows R3 and R4 are provided with terminal groups PA3 and PA4, respectively. Row R3 can specify an area where the terminals of terminal group PA3 are arranged horizontally. Row R4 can specify an area where the terminals of terminal group PA4 are arranged horizontally. The form factor of this memory card SD2 can be compatible with microSD cards. Note that if memory card SD2 has rows R3 and R4, row R2 can be optional (not required).

[0038] In Figure 2, rows R3 and R4 are configured in two rows, but each row indicates a group of terminals required to configure one lane, and does not limit the terminal arrangement on the memory card. For example, the pads in the two rows may be arranged in a zigzag pattern, or rows R3 and R4 may be arranged in a single row in a U-shape.

[0039] The area of ​​each terminal of terminal groups PA3 and PA4 can be smaller than the area of ​​each terminal of terminal groups PA1 and PA2. Depending on the connector contact method, the shapes of each terminal of terminal groups PA3 and PA4 can be made equal to each other. Here, by reducing the area of ​​each terminal of terminal groups PA3 and PA4, it is possible to reduce parasitic capacitance and also reduce stubs when contacting the terminals, thereby improving frequency characteristics. Note that the stub here refers to the portion of the terminal that does not come into contact with the connector pin when contacting the terminal of memory card SD2. Furthermore, by making the shapes of each terminal of terminal groups PA3 and PA4 equal to each other, it is possible to improve the symmetry of the electrical characteristics of the differential signals that make up the lanes.

[0040] Signals used for communication in accordance with the PCIe standard are assigned to each of rows R3 and R4. Transmit differential signals TX0P, TX0N and receive differential signals RX0P, RX0N are assigned to the terminal group PA3 of row R3. Transmit differential signals TX1P, TX1N and receive differential signals RX1P, RX1N are assigned to the terminal group PA4 of row R4.

[0041] Here, one row can constitute one lane of the PCIe standard. Therefore, by allocating signals used for communication according to the PCIe standard to rows R3 and R4, two lanes of the PCIe standard can be configured, which doubles the data transfer speed compared to a method in which signals used for communication according to the PCIe standard are allocated to one row.

[0042] Even when communication is performed using the two rows R3 and R4 in accordance with the PCIe standard, the control signals used to control communication in accordance with the PCIe standard are assigned to row R1. In this case, the control signals assigned to row R1 can be shared by the two rows R3 and R4.

[0043] In row R3, a power supply terminal VDD3 is assigned to one terminal of terminal group PA3. A power supply voltage VDD3 can be supplied to the power supply terminal VDD3 of row R3. The power supply terminal VDD3 of terminal group PA3 can be shared by rows R3 and R4. The power supply voltage VDD3 can be used to determine whether memory card SD2 communicates in a first mode compliant with the SD standard or in a second mode compliant with the PCIe standard.

[0044] In addition, in each of rows R3 and R4, GND terminals at ground potential are assigned so that the terminals to which differential signals are assigned are sandwiched between them. For example, in row R3, receive differential signals RX0N, RX0P, TX0N, and TX0P are assigned to the second, third, sixth, and seventh terminals from the right. At this time, ground potential GND is assigned to the first, fourth, fifth, and eighth terminals from the right of row R3.

[0045] However, the memory card may have the configuration shown in Fig. 3, in which a power supply terminal is arranged in place of one of the two GND terminals surrounding the differential signal terminals, as compared to the configuration shown in Fig. 2. The power supply terminal may be a power supply terminal compatible with a stable power supply. Fig. 3 is a plan view showing another schematic configuration of the memory card according to the second embodiment.

[0046] Here, by assigning the ground potential GND to the terminals sandwiching the terminal to which the differential signal is assigned, a return path can be secured for each differential signal, and mutual interference between the differential signals can be reduced.

[0047] 2 and 3, a method has been described in which the ground potential GND is independently assigned to each differential signal. However, if there is a sufficient noise margin against mutual interference between differential signals, adjacent terminals to which the ground potential GND is assigned may be shared. For example, in row R3, either of the fourth and fifth terminals from the right to which the ground potential GND is assigned may be omitted. This reduces the number of terminals provided in each row R3 and R4, and easily accommodates any limitations on the number of terminals that can be arranged in one row of the memory card SD2.

[0048] Furthermore, in the example of FIG. 2 or FIG. 3, a method of providing rows R3 and R4 in the memory card SD2 has been described, but row R4 may be omitted.

[0049] 2 and 3, two rows R3 and R4 are provided in addition to rows R1 and R2. However, three or more rows may be provided in addition to rows R1 and R2. For example, rows R5 and R6 may be added. Since memory card SD2 supports PCIe communication, the number of rows can be increased, thereby increasing the number of lanes, making it easy to accommodate increased data transfer speeds.

[0050] That is, N rows (N is an integer equal to or greater than 2) can be provided on the card surface of a memory card. The first row performs data communication in a first mode conforming to the SD standard, while the second through Nth rows perform data communication according to the PCIe standard. The second row may be assigned as a PCIe lane, but since the pad shape is different from that of the third and subsequent rows, it need not be used. If the number of PCIe lanes is X, the PCIe standard allows data communication using X lanes. For example, the PCIe 3.0 standard can achieve a maximum transfer speed of X x 2 GB / s (bidirectional).

[0051] (Third embodiment) FIG. 4A is a plan view showing a schematic configuration of a memory card according to a third embodiment.

[0052] The microSD form factor has three possible combinations: with or without row R2, and with or without rows R3 and R4.

[0053] (1) Row R2 is present, but rows R3 and R4 are absent (case in Figure 1) Row R2 is assigned one lane of UHS-II differential signaling or PCIe standard differential signaling. Which is supported is identified during initialization (both may be supported). Furthermore, Row R2 may or may not have a power supply terminal VDD3; if the power supply terminal VDD3 is present, 1.2V is applied. If the power supply terminal VDD3 is not present, the power supply terminal VDD2 is used, and 1.8V or 1.2V is applied to the power supply terminal VDD2.

[0054] (2) Without row R2, with rows R3 and R4 (case in Figure 4A) Rows R3 and R4 are assigned two lanes of differential signaling according to the PCIe standard. The power supply voltage VDD3 is in row R3. UHS-II is not supported.

[0055] (3) Row R2 and rows R3 and R4 are present (case in Figure 2) Row R2 is assigned UHS-II differential signals, while Rows R3 and R4 are assigned two PCIe standard differential signal lanes. Furthermore, Row R2 may or may not have a power supply pin VDD3; if it does, 1.2V is applied. If the power supply pin VDD3 is not present, the power supply pin VDD2 is used, or the power supply pin VDD3 on Row R3 may be used. If the power supply pin VDD2 is used, 1.8V or 1.2V is applied. Furthermore, in the second mode compatible with the PCIe standard, Row R2 can be used as an interface for a different purpose.

[0056] The rows R1, R3, and R4 of the memory card SD3 can be used in the same way as the rows R1, R3, and R4 of the memory card SD2 in FIG.

[0057] Here, by removing row R2 of memory card SD2, the free space on the card surface of memory card SD3 can be increased, which can be used as a contact area for heat dissipation, for example.

[0058] (Fourth embodiment) FIG. 4C is a plan view showing a schematic configuration of a memory card according to the fourth embodiment.

[0059] In Figure 4C, rows R1, R3, and R4 are provided on the card surface of memory card SD5. Row R1 is provided with a terminal group PC1. Row R1 is assigned signals used for communication in the first mode compliant with the SD standard. At this time, in row R1, power supply VDD is assigned to terminal 4, ground potential VSS is assigned to terminals 3 and 6, command CMD is assigned to terminal 2, clock CLK is assigned to terminal 5, and data DAT[3:0] is assigned to terminals 1, 9, 8, and 7.

[0060] Rows R3 and R4 are provided with terminal groups PC3 and PC4, respectively, allowing for a two-lane configuration. The form factor of this memory card SD5 can be made compatible with standard-sized SD cards. In this case, the vertical dimension A2 of the memory card SD5 can be set to 32 mm, the horizontal dimension B2 to 24 mm, and the thickness to 2.1 mm.

[0061] Rows R1, R3, and R4 of the SD5 memory card can be used in the same way as rows R1, R3, and R4 of the SD2 memory card. This allows the SD5 memory card to support communication in the second mode that complies with the PCIe standard, even if the form factor of the SD5 memory card is compatible with standard-sized SD cards, thereby increasing data transfer speeds.

[0062] (Fifth embodiment) FIG. 4B is a plan view showing a schematic configuration of a memory card according to the fifth embodiment.

[0063] In Figure 4B, the memory card SD4 has rows R1, R3, and R4 on its card surface. Row R1 has terminal group PB1. Row R1 is assigned signals used for communication in the first mode conforming to the SD standard. While the terminal group PB1 in Figure 4B has the same shape as the terminal group PA1 in Figure 4A, the shape of terminal group PB1 may be the same as or similar to the shape of the terminals in rows R3 and R4, or a small pad shape. By using an adapter, compatibility can be maintained by converting to the form factor shown in Figure 4C.

[0064] Rows R3 and R4 are provided with terminal groups PB3 and PB4, respectively. The form factor of this memory card SD4 can volumetrically encompass the form factor corresponding to a microSD card and can also volumetrically encompass the form factor corresponding to a standard-sized SD card. In this case, the vertical dimension A3 of the memory card SD4 can be set in the range of 16 mm to 20 mm, the horizontal dimension B3 in the range of 12 mm to 16 mm, and the thickness in the range of 1.4 mm to 1.6 mm.

[0065] Here, the form factor of the memory card SD4 voluntarily encompasses the form factor corresponding to the microSD card, so that even if the chip size of the NAND flash memory increases, the NAND flash memory can be accommodated in the memory card SD4, and it can accommodate increases in the storage capacity of the NAND flash memory.

[0066] Furthermore, the form factor of the SD4 memory card is volumetrically contained within the form factor corresponding to a standard-sized SD card, which helps prevent the memory card SD4 from increasing in size. This ensures the compactness of the SD4 memory card, making it suitable for use in mobile devices such as smartphones and digital cameras.

[0067] Rows R1, R3, and R4 on the SD4 memory card can be used in the same way as rows R1, R3, and R4 on the SD5 memory card and rows R1, R3, and R4 on the SD3 memory card. This means that even if the form factor of the SD4 memory card differs from that of a microSD card and a standard-sized SD card, it can support communication using the PCIe standard and access memory areas regardless of the form factor.

[0068] The memory cards SD2 to SD5 can have the same dimensions, shape, and spacing of the terminals arranged in rows R3 and R4, which allows the connectors that make contact with the terminals arranged in rows R3 and R4 to be standardized among the memory cards SD2 to SD5.

[0069] (Sixth embodiment) Fig. 5 is a block diagram showing a schematic configuration of a memory card according to a sixth embodiment. The configuration in Fig. 5 can be used for any of the memory cards SD1 to SD5 in Figs. 1, 2, and 4A to 4C. In the following explanation, the configuration in Fig. 5 is applied to the memory card SD2 in Fig. 2 as an example.

[0070] 5, the memory card SD2 includes regulators 11 and 12, a comparator 13, a card controller 14, a memory interface circuit 15, and a memory 16. A NAND flash memory can be used for the memory 16. The card controller 14 can control read / write operations to the memory 16 and communication with the outside world. This communication control can include protocol control for a first mode compliant with the SD standard and protocol control for the PCIe standard. The card controller 14 includes an I / O cell 17, a physical layer interface 18, and a card interface circuit 19.

[0071] The IO cell 17 can accommodate a single-ended signal. The IO cell 17 can accommodate a signal assigned to row R1. The IO cell 17 is provided with input buffers V1 and V3 and an output buffer V2. A clock CLK can be input to the input buffer V1. A command CMD and data DAT[3:0] can be input to the input buffer V3. The output buffer V2 can output a response to the command CMD and data DAT[3:0]. An input buffer V3 and an output buffer V2 can be provided for each command CMD and data DAT[3:0].

[0072] The physical layer interface 18 can support differential signals. The physical layer interface 18 can support signals assigned to rows R2, R3, and R4. The physical layer interface 18 includes a receiver RE and a transmitter TR. The receiver RE can receive differential signals RX0P and RX0N from rows R2 and R3 and receive differential signals RX1P and RX1N from row R4. The transmitter TR can output differential transmit signals TX0P and TX0N from rows R2 and R3 and transmit differential signals TX1P and TX1N from row R4. A receiver RE and a transmitter TR can be provided for each of rows R2, R3, and R4. In row R2, the physical layer interface 18 can have the same configuration whether it is in the second mode compliant with the UHS-II standard or the second mode compliant with the PCIe standard.

[0073] The IO cell 17 and physical layer interface 18 are connected to a card interface circuit 19. The card controller 14 is connected to the memory 16 via a memory interface circuit 15. To enable the memory card SD2 to support the PCIe standard, the card controller 14 can be provided with a PCIe-compliant physical layer interface 18 as well as a PCIe-compliant data link layer and transaction layer. The physical layer interface 18 can perform serial-to-parallel conversion, parallel-to-serial conversion, and data symbolization. This symbolization is a process that limits the number of consecutive occurrences of the same value when data contains consecutive 0s or 1s to a predetermined value or less. This symbolization can reduce bias in voltage levels during data transmission. Furthermore, using symbols that do not increase harmonics of a specific frequency can also reduce EMI (electromagnetic interference).

[0074] The transaction layer of the PCIe standard can packetize data and add commands to the packet header. The data link layer of the PCIe standard can add sequence numbers and CRC (Cyclic Redundancy Check) codes to packets received from the transaction layer. The sequence number can be used to confirm packet delivery, etc.

[0075] The power supply voltage VDD1 is supplied to the regulator 11, the card controller 14, the memory interface circuit 15, and the memory 16. The power supply voltage VDD1 supplied to the regulator 11 is converted to the power supply voltage VDDL and supplied to the card controller 14 and the memory interface circuit 15. The power supply voltage VDDL is determined according to the technology of the card controller. The memory interface circuit 15 is a level shifter circuit when the interface voltage of the card controller 14 and the interface voltage of the memory 16 are different.

[0076] In the first mode (DS, HS, or UHS-I) compatible with the SD standard, the device is configured to operate with only the power supply voltage VDD1. In UHS-7 mode, the card controller 14 and memory interface circuit 15 can use a power supply voltage VDDL of 1.8V. In this case, the IO cell 17 can switch the output signal voltage and input threshold according to the power supply voltages VDD1 and VDDL. The voltage VDD2 can be supplied as an option.

[0077] The power supply voltage VDD3 is supplied to the regulator 12 and the comparator 13. The power supply voltage VDD3 supplied to the regulator 12 is converted into a power supply voltage VDDPHY required to operate the physical layer interface 18, and is supplied to the physical layer interface 18.

[0078] The power supply voltage VDD3 supplied to the comparator 13 is compared with a reference voltage. Based on the comparison result, the application of the power supply voltage VDD3 is detected, and a detection signal VDD3SP is output to the card controller 14. Although not shown in the figure, when the power supply voltage VDD2 is used, the power supply voltage VDD2 is similarly supplied to the regulator 12 and the comparator 13, converted into the power supply voltage VDDPHY required to operate the physical layer interface 18, supplied to the physical layer interface 18, and the detection signal VDD3SP is output to the card controller 14.

[0079] If the comparator 13 does not detect the application of the power supply voltage VDD3, the memory card SD2 communicates in the first mode conforming to the SD standard. At this time, the clock CLK transmitted from the host device to the memory card SD2 is sent to the card interface circuit 19 via the input buffer V1. The command CMD and data DAT[3:0] transmitted from the host device to the memory card SD2 are sent to the card interface circuit 19 via the input buffer V3. The response to the command CMD transmitted from the card interface circuit 19 and the data DAT[3:0] are sent to the host device via the output buffer V2.

[0080] When comparator 13 detects the application of power supply voltage VDD2 or VDD3, memory card SD2 communicates in the second mode compliant with the PCIe standard. At this time, memory card SD2 can communicate data via rows R3 and R4 and control signals via row R1. The control signals are the reference differential clock signal REFCLKp / n, the reset signal PERST, the power management control signal CLKREQ, and the wake-up signal PEWAKE, which are assigned in place of the command CMD and data DAT[3:0] of row R1. However, implementing the wake-up signal PEWAKE is not mandatory.

[0081] When serial receive differential signals RX0P, RX0N, RX1P, and RX1N are transmitted from the host device to the memory card SD2, they are converted into parallel data receive signals Rx by the receiver RE and transmitted to the card interface circuit 19. When parallel data transmit signals Tx are transmitted from the card interface circuit 19 to the transmitter TR, the transmit signals Tx are converted into serial transmit differential signals TX0P, TX0N, TX1P, and TX1N and transmitted to the host device.

[0082] Seventh embodiment FIG. 6 is a block diagram showing a schematic configuration of a host device in which a memory card according to the seventh embodiment is installed.

[0083] 6, the host device includes a system controller 21 and a system memory 27. The system controller 21 includes a route complex 22, an SD host controller 23, a first row switch 24, a connector 25, and a memory controller 26. The memory controller 26 is connected to the system memory 27.

[0084] The root complex 22 can control access to system memory by arbitrating multiple PCIe lanes. It can also arbitrate data transfer between devices connected to the PCIe lanes and the system memory. If the root complex 22 has multiple PCIe lanes, it can be connected to multiple PCIe devices (including memory cards) in a star-star configuration. Multiple lanes can also be assigned to a single device. The SD host controller 23 can be used to control the memory card SD2 in a first mode compliant with the SD standard. The first row switch 24 can switch between using row R1 for communication in the first mode compliant with the SD standard and for communication in the second mode compliant with the PCIe standard based on the selection signal R1SEL.

[0085] The connector 25 can make contact with the memory card SD2. In this case, the form factor of the connector 25 can be made compatible with a microSD card. The connector 25 can be provided with a group of connector contact terminals corresponding to the card terminals of the memory card SD2 in order to make contact with the memory card SD2. The card terminals of the memory card SD2 are terminals PA1 to PA4 in FIG. 2. The connector 25 also has a group of connector terminals for connecting to a host controller. In the following description, to distinguish between the terminals provided on the memory card and the terminals provided on the connector, the terminals provided on the memory card will sometimes be referred to as the card terminals, and the terminals provided on the connector will sometimes be referred to as the connector terminals.

[0086] A power supply voltage VDD3 is applied to the connector 25, and when the power supply voltage VDD3 is not applied, the power supply voltage VDD2 is applied to the connector 25. The memory controller 26 can control the operation of the system memory 27.

[0087] The root complex 22 is provided with physical layer interfaces 22A, 22C, and 22E and IO cells 22B, 22D, and 22F. Each of the physical layer interfaces 22A, 22C, and 22E is a differential signal interface conforming to the PCIe standard, and each of the IO cells 22B, 22D, and 22F is an interface conforming to the PCIe standard for single-ended signals and differential reference clocks.

[0088] The physical layer interface 22A and the IO cell 22B are connected to the SD host controller 23. At this time, the root complex 22 can communicate with the SD host controller 23 using a differential signal DS1 and a control signal CS1. The physical layer interface 22C is connected to a connector 25. The IO cell 22D is connected to a first row switch 24. The physical layer interface 22E and the IO cell 22F are connected to an M.2 slot. The M.2 supports the SATA (Serial Advanced Technology Attachment) and PCIe standards and can connect various PCIe devices. The SD host controller 23 is connected to the connector 25 via the first row switch 24.

[0089] When communication in the first mode conforming to the SD standard is selected by the selection signal R1SEL, the first row switch 24 switches row R1 of the memory card SD2 to the SD host controller 23 side. Then, the SD bus signal BS output from the SD host controller 23 is assigned to row R1, and communication between the SD host controller 23 and the memory card SD2 is performed in the first mode conforming to the SD standard. The SD bus signal BS can include a command CMD, a clock CLK, and data DAT[3:0].

[0090] When the selection signal R1SEL selects communication in the second mode conforming to the PCIe standard, the first row switch 24 switches row R1 of the memory card SD2 to the IO cell 22D side. Then, a control signal CS2 is assigned to row R1. This control signal CS2 may include a reference differential clock signal REFCLKp / n, a reset signal PERST, and a power management control signal CLKREQ. Furthermore, this control signal CS2 may further include a wake-up signal PEWAKE.

[0091] Additionally, differential signals DS2 are transmitted and received between the physical layer interface 22C and rows R3 and R4 of the memory card SD2. These differential signals DS2 may include receive differential signals RX0P, RX0N, RX1P, and RX1N and transmit differential signals TX0P, TX0N, TX1P, and TX1N. This allows communication between the root complex 22 and the memory card SD2 in a second mode that complies with the PCIe standard.

[0092] The selection signal R1SEL can be set based on whether the power supply voltage VDD2 or VDD3 is applied. The state during initialization can be controlled by detecting the change point of the power supply voltage VDD2 or VDD3 (off to on, on to off). Alternatively, a register may be provided in the system controller 21 or the like, and the selection signal R1SEL may be set based on the value stored in this register. By setting the selection signal R1SEL based on the value stored in the register, it is possible to switch between communication in a first mode conforming to the SD standard and communication in a second mode conforming to the PCIe standard, regardless of whether the power supply voltage VDD3 is used.

[0093] In the embodiment of FIG. 6, a configuration is shown in which a connector 25 into which memory card SD2 can be attached is mounted on the host device, but connectors into which memory cards SD1, SD3 to SD5 can be attached may also be mounted on the host device. The form factor of the connector into which memory cards SD1 and SD3 can be attached can be compatible with microSD cards. The form factor of the connector into which memory card SD4 can be attached can include form factors compatible with microSD cards and can be included in form factors compatible with standard-sized SD cards. The form factor of the connector into which memory card SD5 can be attached can be compatible with standard-sized SD cards and can include form factors compatible with microSD cards and the form factor of card SD4.

[0094] (Eighth embodiment) FIG. 7 is a block diagram showing a schematic configuration of an interface card to which a memory card according to the eighth embodiment is attached.

[0095] In FIG. 7, an interface card 31 is provided with a bridge 32, an SD host controller 33, a first row switch 34, and a connector 35.

[0096] By inserting interface card 31 into the PCIe slot or M.2 slot, bridge 32 can transition to communication in the second mode that complies with the PCIe standard. SD host controller 33, first row switch 34, and connector 35 can be configured in the same way as SD host controller 23, first row switch 24, and connector 25 in FIG. 6.

[0097] The bridge 32 is provided with physical layer interfaces 32A and 32C and IO cells 32B and 32D. Each physical layer interface 32A and 32C can interface a differential signal of the PCIe standard. The IO cells 32B and 32D can interface a single-ended signal of the PCIe standard and a differential reference clock.

[0098] The physical layer interface 32A and the IO cell 32B are connected to the SD host controller 33. At this time, the bridge 32 can communicate with the SD host controller 33 using the differential signal DS1 and the control signal CS1. The physical layer interface 32C is connected to the connector 35. The IO cell 32D is connected to the first row switch 34.

[0099] When communication in the first mode conforming to the SD standard is selected by the selection signal R1SEL, the first row switch 34 switches row R1 of the memory card SD2 to the SD host controller 33 side. Then, the SD bus signal BS output from the SD host controller 33 is assigned to row R1, and communication between the SD host controller 33 and the memory card SD2 is carried out in the first mode conforming to the SD standard.

[0100] When the selection signal R1SEL selects communication in the second mode conforming to the PCIe standard, the first row switch 34 switches row R1 of the memory card SD2 to the I / O cell 32D side. Then, a control signal CS2 is assigned to row R1. Furthermore, a differential signal DS2 is transmitted and received between the physical layer interface 32C and rows R3 and R4 of the memory card SD2. Then, communication in the second mode conforming to the PCIe standard is performed between the bridge 32 and the memory card SD2.

[0101] (Ninth embodiment) 8 is a flowchart showing the operation of the host device when setting the bus mode of the memory card according to the ninth embodiment. This method of setting the bus mode of the memory card can be used for any of the memory cards SD1 to SD5 shown in FIGS. 1, 2, and 4A to 4C.

[0102] In FIG. 8, the host device supplies power supply voltages VDD1 and VDD3 to the memory card (S1). The power supply voltage VDD1 can be supplied to the power supply terminal VDD of row R1 of the memory card. As shown in FIG. 1, if the memory card has only rows R1 and R2, the power supply voltage VDD3 can be supplied to the power supply terminal VDD3 of row R2 of the memory card, or to the power supply terminal VDD2 if the power supply terminal VDD3 is not present. As shown in FIG. 2 or FIGS. 4A to 4C, if the memory card has row R3, the power supply voltage VDD3 can be supplied to the power supply terminal VDD3 of row R3 of the memory card.

[0103] Although not shown, if the power supply voltage VDD3 is not supported, the power supply voltage VDD2 is supplied to the power supply terminal VDD2 instead.

[0104] At this time, the host device can detect whether a card is inserted by monitoring the rise time of the voltage at the terminals of rows R3 and R4, which are assigned the transmit differential signals TX0P, TX0N, TX1P, and TX1N. The host device and card are connected via an AC coupling capacitor, and charging current flows to the capacitor only when a card is inserted. Therefore, when a memory card is inserted in the host device, the rise time is longer than when a memory card is not inserted. Therefore, based on this rise time, it is possible to determine whether a memory card is inserted in the host device. In a system consisting of multiple lanes, it is also possible to determine which lanes are available for communication. If a memory card is inserted in the host device, the host device can begin communication with the memory card.

[0105] Next, the host device selects row R1 as the third bus mode (S2). The third bus mode is communication in the second mode conforming to the PCIe standard.

[0106] Next, the host device transmits a symbol to row R2, R3, or R4 that identifies whether the memory card supports the PCIe standard (S3).

[0107] If a response to the symbol in S3 is sent from the memory card within the specified time (Yes in S4), the host device executes a training sequence (S5). This training sequence allows the host device and the memory card to determine the maximum operating frequency that they can both support.

[0108] Next, the host device sets the communication method with the memory card to the third bus mode (S6).

[0109] On the other hand, if a response to the symbol in S3 is not sent from the memory card within the specified time (No in S4), the host device stops supplying the power supply voltage VDD3 (S7) and supplies the power supply voltage VDD2 to the memory card (S8). The power supply voltage VDD2 can be supplied to the power supply terminal VDD2 of row R2 of the memory card.

[0110] Next, the host device selects row R1 as the control terminal for the UHS-II mode (S9). Specifically, a differential reference clock is assigned to the two terminals.

[0111] Next, the host device transmits a symbol to row R2 that identifies whether the memory card supports UHS-II (S10).

[0112] If a response to the symbol in S10 is sent from the memory card within the specified time (Yes in S11), the host device performs initialization in UHS-II mode (S12). This initialization in UHS-II mode allows the maximum operating frequency supported by both the memory card and the host device to be determined.

[0113] Next, the host device sets the communication method with the memory card to the second bus mode (S13), which is communication according to UHS-II.

[0114] On the other hand, if a response to the symbol in S10 is not sent from the memory card within the specified time (No in S11), the host device stops the supply of power supply voltage VDD2 (S14). Note that whether or not to stop the supply of power supply voltage VDD2 is optional.

[0115] Next, the host device selects row R1 as a signal terminal for the first mode that complies with the SD standard (S15).

[0116] Next, the host device transmits a command to row R1 to execute initialization in the first mode that complies with the SD standard (S16).

[0117] If a response to the command in S16 is sent from the memory card within the specified time (Yes in S17), the host device executes initialization in the first mode that complies with the SD standard (S18). This initialization in the first mode that complies with the SD standard can determine the SD bus mode and operating frequency that provide the maximum performance supported by both the memory card and the host device.

[0118] Next, the host device sets the communication method with the memory card to the first bus mode (S19), which is a first mode of communication compliant with the SD standard.

[0119] On the other hand, if a response to the command in S16 is not received from the memory card within the specified time (No in S17), the host device determines that there is an error and stops initialization in the first mode that complies with the SD standard (S20). S20 also includes the case where a card other than an SD card is connected.

[0120] For example, assume that the process of Figure 8 is applied to the memory card SD1 of Figure 1. At this time, a power supply voltage VDD3 is supplied to the power supply terminal VDD3 of row R2 of memory card SD1 (S1). If memory card SD1 supports the PCIe standard, when a symbol is sent to row R2 of memory card SD1 (S3), a response is received from memory card SD1 (Yes in S4). Therefore, the host device sets the communication method with memory card SD1 to the second mode compatible with the PCIe standard (S6).

[0121] On the other hand, if memory card SD1 supports UHS-II, when a symbol is transmitted to row R2 of memory card SD1 (S3), there is no response from memory card SD1 (No in S4). As a result, the power supply voltage VDD3 at the power supply terminal VDD3 of row R2 of memory card SD1 is stopped (S7), and power supply voltage VDD2 is supplied to the power supply terminal VDD2 of row R2 of memory card SD1 (S8). Then, when a symbol is transmitted to row R2 of memory card SD1 (S10), there is a response from memory card SD1 (Yes in S11). As a result, the host device sets the communication method with memory card SD1 to UHS-II (S13).

[0122] On the other hand, if the memory card SD1 does not support UHS-II either, when a symbol is sent to row R2 of the memory card SD1 (S10), there is no response from the memory card SD1 (No in S11). Then, when a command is sent to row R1 of the memory card SD1 (S16), if there is a response from the memory card SD1, the host device sets the communication method with the memory card SD1 to the first mode compatible with the SD standard (S19).

[0123] As another example, assume that the process of Figure 8 is applied to memory card SD3 in Figure 4A. At this time, power supply voltage VDD3 is supplied to power supply terminal VDD3 in row R3 of memory card SD3 (S1). Because memory card SD3 supports the PCIe standard, when a symbol is sent to row R3 of memory card SD3 (S3), a response is received from memory card SD3 (Yes in S4). Therefore, the host device sets the communication method with memory card SD1 to a second mode that complies with the PCIe standard (S6).

[0124] On the other hand, when memory card SD3 is operated in the first mode compliant with the SD standard, power supply voltage VDD3 is not supplied to the power supply terminal VDD3 of row R3 of memory card SD3 in S1. At this time, when a symbol is transmitted to row R3 of memory card SD3 (S3), there is no response from memory card SD3 (No in S4). Furthermore, because memory card SD3 does not have row R2, there is no response from memory card SD3 when a symbol is transmitted to row R2 of memory card SD3 (S10) (No in S11). Because memory card SD3 supports the SD standard, there is a response from memory card SD3 when a command is transmitted to row R1 of memory card SD3 (S16) (Yes in S17). Therefore, the host device sets the communication method with memory card SD3 to the first mode compliant with the SD standard (S19).

[0125] (Tenth embodiment) FIG. 9 is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the tenth embodiment.

[0126] 9, the host device is provided with a system board 81 and a system controller 83. The system board 81 is provided with a connector 82 and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1. The receiver RE1 can input transmit differential signals TX0P and TX0N transmitted from row R2 of the memory card SD1. The transmitter TR1 can output receive differential signals RX0P and RX0N received at row R2 of the memory card SD1.

[0127] The transmitter TR1 and the connector 82 are connected via a differential transmission line TP1. At this time, the differential transmission line TP1 can connect the transmitter TR1 and the connector 82 via AC coupling capacitors C1 and C2. A switch WT is connected to the AC coupling capacitors C1 and C2. The switch WT can short-circuit the AC coupling capacitors C1 and C2. Implementation of the switch WT is optional.

[0128] The receiver RE1 and the connector 82 are connected via a differential transmission line TP2. At this time, the differential transmission line TP2 can connect the receiver RE1 and the connector 82 via AC coupling capacitors C3 and C4. A switch WR is connected to the AC coupling capacitors C3 and C4. The switch WR can short-circuit the AC coupling capacitors C3 and C4. Implementation of the switch WR is optional.

[0129] The memory card SD1 is provided with a physical layer interface 85. The physical layer interface 85 can support either the UHS-II standard or the PCIe standard. The physical layer interface 85 is provided with a receiver RE2 and a transmitter TR2. The receiver RE2 can input reception differential signals RX0P and RX0N received at row R2 of the memory card SD1. The transmitter TR2 can output transmission differential signals TX0P and TX0N transmitted from row R2 of the memory card SD1.

[0130] The receiver RE2 is connected to the differential transmission line TP3. The transmitter TR2 is connected to the differential transmission line TP4. By inserting the memory card SD1 into the connector 82, the differential transmission lines TP1 and TP3 can be connected to each other, and the differential transmission lines TP2 and TP4 can also be connected to each other.

[0131] If the memory card SD1 supports the UHS-II standard, the system controller 83 can turn on the switches WT and WR to short-circuit the AC coupling capacitors C1 to C4.

[0132] On the other hand, if the memory card SD1 supports the PCIe standard, the system controller 83 can turn off the switches WT and WR to separate the physical layer interfaces 84 and 85 in terms of DC current.

[0133] This allows the memory card SD1 to be compatible with both the case where it supports the UHS-II standard and the case where it supports the PCIe standard without having to replace the system board 81 depending on whether the memory card SD1 supports the UHS-II standard or the PCIe standard.

[0134] In the second mode that complies with the PCIe standard, connecting the physical layer interfaces 84 and 85 via AC coupling capacitors C1 to C4 enables DC isolation between the transmitting and receiving sides of the differential signal, and the common voltage levels of the physical layer interfaces 84 and 85 can be designed independently for the transmitting and receiving sides (they are not affected by each other). On the other hand, when DC coupling is used without AC coupling capacitors, fluctuations in the ground level affect the signal voltages of both sides, so a design that suppresses fluctuations in the ground level is required.

[0135] Furthermore, the AC coupling capacitor requires a capacitance of about 200 nF, and its size makes it difficult to mount it within the microSD form factor. Therefore, by providing AC coupling capacitors C1 to C4 on system board 81, it becomes unnecessary to provide AC coupling capacitors C3 and C4 on memory card SD1, making it possible to easily manufacture the thin memory card SD1.

[0136] (Eleventh embodiment) FIG. 10A is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to an eleventh embodiment.

[0137] 10A, the host device is provided with a system board 81'. The system board 81' is provided with a connector 82 and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1.

[0138] The transmitter TR1 and the differential transmission line TP1 from the connector 82 are connected via AC coupling capacitors C1 and C2.

[0139] The receiver RE1 and the connector 82 are connected via a differential transmission line TP2. In this case, the differential transmission line TP2 can directly connect the receiver RE1 and the connector 82.

[0140] The memory card SD5 is provided with a physical layer interface 85'. The physical layer interface 85' can support the PCIe standard. The physical layer interface 85' is provided with a receiver RE2' and a transmitter TR2'. The receiver RE2' can input reception differential signals RX0P and RX0N received at row R3 of the memory card SD5. The transmitter TR2' can output transmission differential signals TX0P and TX0N transmitted from row R3 of the memory card SD5.

[0141] The receiver RE2' is connected to the differential transmission line TP3. The transmitter TR2' and differential transmission line TP4 are connected via AC coupling capacitors C3 and C4. This is a common mounting method for PCIe devices.

[0142] However, the capacitance range of AC coupling capacitors is limited, and they are too large to be implemented in the microSD form factor, meaning that the configuration shown in Figure 10A is not suitable for application to small removable cards with a thin form factor.

[0143] (Twelfth embodiment) FIG. 10B is a block diagram showing a method for mounting an AC coupling capacitor in a differential transmission line connected to a memory card according to the twelfth embodiment.

[0144] In FIG. 10B, the host device is provided with a system board 81". The system board 81" is provided with a connector 82' and a physical layer interface 84. The physical layer interface 84 is provided with a receiver RE1 and a transmitter TR1. The connector 82' is provided with AC coupling capacitors C3 and C4. The AC coupling capacitors C3 and C4 can be electrically inserted between a connector terminal of the connector 82' to which the memory card SD1 side can be connected and a connection terminal connected to the physical layer interface 84 of the host device.

[0145] The transmitter TR1 and the differential transmission path TP1 from the connector 82' are connected via AC coupling capacitors C1 and C2. The AC coupling capacitors C1 and C2 may be placed inside the connector 82', which eliminates the need to secure an area on the PCB for placing C1 and C2.

[0146] The receiver RE1 and the connector 82' are connected via a differential transmission line TP2. At this time, the differential transmission line TP2 can directly connect the receiver RE1 and the connector 82'. The differential transmission line TP2 on the host device side and the differential transmission line TP4 on the card side are connected via AC coupling capacitors C3 and C4 within the connector 82'.

[0147] 10B shows a case where AC coupling capacitors C3 and C4 are arranged inside the connector, but instead of arranging them inside the connector, AC coupling capacitors C3 and C4 may be inserted between the receiver RE1 and the differential transmission path TP2 from the connector 82'. In this case, it is necessary to secure an area on the PCB (Printed Circuit Board) for arranging AC coupling capacitors C3 and C4.

[0148] By attaching the memory card SD1 to the connector 82', the differential transmission path (differential transmission path on the transmitting side of the host device) TP1 and the differential transmission path (differential transmission path on the receiving side of the memory card SD1) TP3 are connected to each other, and the differential transmission path (differential transmission path on the receiving side of the host device) TP2 and the differential transmission path (differential transmission path on the transmitting side of the memory card SD1) TP4 can be connected to each other via AC coupling capacitors C3 and C4.

[0149] Here, by providing AC coupling capacitors C3 and C4 in connector 82', it is no longer necessary to provide AC coupling capacitors C3 and C4 in memory card SD1, and it becomes possible to support small removable cards with thin form factors such as microSD memory cards. Naturally, it can also be applied to larger form factors.

[0150] (Thirteenth embodiment) Fig. 11A is a perspective view showing an example of a schematic configuration of a connector used in a memory card according to a thirteenth embodiment, and Fig. 11B is a cross-sectional view showing an example of a schematic configuration of a connector used in a memory card according to the thirteenth embodiment. Note that Fig. 11B shows two pogo pins as shown in Fig. 11A.

[0151] 11A, this connector can be used to make contact with terminal groups PA3-PC3 and PA4-PC4 of rows R3 and R4 of memory cards SD2-SD5. This connector is provided with pogo pins 40. The pogo pins 40 can be arranged in accordance with the arrangement of terminals in rows R3 and R4.

[0152] 11B, the pogo pin 40 is provided with a pin 44. The pin 44 is housed in a cylinder 43. Inside the cylinder 43, a spring 45 is provided at the bottom of the pin 44, and the pin 44 is supported via the spring 45 in a state where it can move up and down. The pogo pin 40 is supported in an upright state by a housing 42. The housing 42 can be installed on a base 41.

[0153] For example, when making contact with row R3 of memory card SD2, each terminal of terminal group PA3 of memory card SD2 is pressed against the tip of pin 44. At this time, as pin 44 is pressed down, spring 45 pushes pin 44 upward. This allows pin 44 to be firmly crimped onto the terminal, improving impact resistance. As a result, even when memory card SD2 is used in an environment where it is subject to severe vibrations and impacts, such as in a car or drone, it is possible to prevent the operation of memory card SD2 from becoming unstable.

[0154] (Fourteenth embodiment) Figure 12A is a cross-sectional view showing an example of the schematic configuration of a connector before a memory card in the 14th embodiment is inserted, Figure 12B is a plan view showing an example of the schematic configuration of a connector before a memory card in the 14th embodiment is inserted, Figure 12C is a cross-sectional view showing an example of the schematic configuration of a connector after a memory card in the 14th embodiment is inserted, and Figure 12D is a plan view showing an example of the schematic configuration of a connector after a memory card in the 14th embodiment is inserted.

[0155] 12B and 12D show the state when the cover of the connector is removed. In addition, in this embodiment, the connector that makes contact with the memory card SD4 in FIG. 4B is taken as an example.

[0156] 12A and 12B, connector CN1 is provided with a base 51 and a cover 52. An end of base 51 and an end of cover 52 are connected via pin 53. In this case, cover 52 can be opened and closed by rotating cover 52 around pin 53 as a rotation axis.

[0157] A recess 54 is provided in the center of the base 51 so as to extend laterally across the base 51. A heat dissipation sheet 55 is provided in the recess 54. The heat dissipation sheet 55 can be made of a flexible material with high thermal conductivity. For example, an acrylic resin can be used as the material for the heat dissipation sheet 55. In this case, the dimensions of the heat dissipation sheet 55 can be set so that it is pulled out laterally from the base 51. The heat dissipation sheet 55 pulled out laterally from the base 51 can be brought into contact with the installation surface of the connector CN1. The installation surface of the connector CN1 is, for example, the housing of the host device.

[0158] The base 51 has a connector row R1 terminal group 58 and a connector row R3 / R4 terminal group 59 that connect to the host side, a connector row R1 contact group and a connector row R3 / R4 contact group that connect to the card side while protruding above the surface of the base 51, and lead pins 56 and pogo pins 57 embedded therein. The lead pins 56 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD4. The pogo pins 57 can be arranged to correspond to the terminal arrangement of rows R3 and R4 of the memory card SD4. The connector row R1 contact group of the lead pins 56 is wired to the connector row R1 terminal group 58 and can be connected to a host device. The connector row R3 / R4 contact group of the pogo pins 57 is wired to the connector row R3 / R4 terminal group 59 and can be connected to a host device.

[0159] When the memory card SD4 is inserted into the connector CN1, the memory card SD4 is placed on the base 51 with the cover 52 open. Then, by closing the cover 52, the memory card SD4 can be fixed to the connector CN1.

[0160] 12C and 12D, the terminal group PB1 of row R1 of memory card SD4 can be crimped onto lead pins 56, and the terminal groups PB3 and PB4 of rows R3 and R4 of memory card SD4 can be crimped onto pogo pins 57. In addition, the empty space between row R1 and rows R3 and R4 on the card surface of memory card SD4 can be crimped onto heat dissipation sheet 55.

[0161] Here, by using pogo pins 57 to make contact with terminal groups PB3 and PB4 of rows R3 and R4 of memory card SD4, it is possible to reduce lateral displacement when terminal groups PB3 and PB4 make contact with pogo pins 57. This allows for reliable contact between terminal groups PB3 and PB4 and pogo pins 57 while also accommodating the miniaturization of each terminal of terminal groups PB3 and PB4.

[0162] Furthermore, by providing a heat dissipation sheet 55 on the connector CN1, heat generated in the memory card SD4 can be efficiently dissipated to the host device via the heat dissipation sheet 55, thereby improving the heat dissipation performance of the memory card SD4.

[0163] In the above embodiment, a method of installing the heat dissipation sheet 55 in the recess 54 of the base 51 has been described, but a Peltier element may be installed in the recess 54 of the base 51 instead of the heat dissipation sheet 55. By using a Peltier element, it becomes possible to forcibly cool the memory card SD4.

[0164] (Fifteenth embodiment) Figure 13A is a cross-sectional view showing an example of the general configuration of an adapter before a memory card in the 15th embodiment is inserted, Figure 13B is a plan view showing an example of the general configuration of an adapter before a memory card in the 15th embodiment is inserted, Figure 13C is a cross-sectional view showing an example of the general configuration of an adapter after a memory card in the 15th embodiment is inserted, and Figure 13D is a plan view showing an example of the general configuration of an adapter after a memory card in the 15th embodiment is inserted.

[0165] In this embodiment, an adapter that converts the form factor of the memory card SD1 in FIG. 1 into the form factor of the memory card SD4 in FIG. 4B is shown.

[0166] 13A and 13B, the adapter AP1 is provided with an insertion portion IE1 into which a memory card SD1 is inserted. An entrance to the insertion portion IE1 can be provided at the rear end of the adapter AP1.

[0167] The surface of the adapter AP1 is provided with a terminal group DA1, which is a group of adapter row R1 terminals that connect to the connector, and terminal groups DA3 and DA4, which are a group of adapter row R3 / R4 terminals. The terminals of terminal groups DA1, DA3, and DA4 can be arranged to correspond to the terminal arrangement of rows R1, R3, and R4 of the memory card SD4, respectively.

[0168] The inner surface of the insertion portion IE1 of the adapter AP1 is provided with lead pins IA1, which are part of the adapter row R1 contact group that connects to the memory card, and lead pins IA2, which are part of the adapter row R2 contact group. The lead pins IA1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD1. The lead pins IA2 can be arranged to correspond to the terminal positions of the terminals assigned to the transmit differential signals TX0P, TX0N, the receive differential signals RX0P, RX0N, and the power supply VDD of row R2 of the memory card SD1.

[0169] The adapter row R1 contact group of lead pin IA1 is wired to the adapter row R1 terminal group of terminal group DA1, allowing connection to a connector. The adapter row R2 contact group of lead pin IA2 is wired to the connector row R4 terminal group of terminal group DA4 (or the connector row R3 terminal group of terminal group DA3), allowing connection to a connector. Figure 5 shows an example of connection to row R4. The wiring between the power supply terminal VDD3 and the data line is shown with dashed lines, but the wiring to the GND terminal has been omitted for clarity.

[0170] The terminal groups DA1, DA3, and DA4 can be used as adapter terminal groups of the adapter AP1. The lead pins IA1 and IA2 can be used as adapter contact groups of the adapter AP1. The adapter terminal groups can come into contact with the connector contact groups when the adapter AP1 is attached to a connector. The adapter contact groups can come into contact with the card terminal groups when the memory card SD1 is inserted into the adapter AP1.

[0171] Lead pin IA1 is connected one-to-one to each terminal in terminal group DA1 via wiring HA1. Lead pin IA2 is connected one-to-one to each terminal in terminal group DA4 (or DA3) via wiring HA2. The host device can determine whether the card is connected to terminal group DA3 or terminal group DA4 during the initialization sequence, so it does not matter which one you connect to. Connecting to terminal group DA4 shortens the wiring, so this example is shown in the figure.

[0172] When the memory card SD1 is attached to the adapter AP1, the memory card SD1 is inserted into the insertion portion IE1 from the rear end of the adapter AP1.

[0173] 13C and 13D, each terminal of the terminal group PA1 in row R1 of memory card SD1 can be brought into contact with the lead pin IA1, and each terminal of the terminal group PA2 in row R2 of memory card SD1 can be brought into contact with the lead pin IA2, thereby converting the form factor of memory card SD1 to the form factor of memory card SD4.

[0174] (16th embodiment) Figure 14A is a cross-sectional view showing an example of the general configuration of an adapter before a memory card in accordance with the 16th embodiment is inserted, Figure 14B is a plan view showing an example of the general configuration of an adapter before a memory card in accordance with the 16th embodiment is inserted, Figure 14C is a cross-sectional view showing an example of the general configuration of an adapter after a memory card in accordance with the 16th embodiment is inserted, and Figure 14D is a plan view showing an example of the general configuration of an adapter after a memory card in accordance with the 16th embodiment is inserted.

[0175] In this embodiment, an adapter that converts the form factor of the memory card SD3 in FIG. 4A into the form factor of the memory card SD4 in FIG. 4B is shown.

[0176] 14A and 14B, the adapter AP3 has an insertion portion IE2 into which a memory card SD3 is inserted. An entrance to the insertion portion IE2 can be provided at the rear end of the adapter AP3. The insertion portion IE2 has a notch IK2 that exposes the terminal groups PA3 and PA4 of rows R3 and R4 of the memory card SD3 on the surface of the adapter AP3 when the memory card SD3 is inserted into the insertion portion IE2.

[0177] The position of the insertion section IE2 can be set so that when the memory card SD3 is inserted into the insertion section IE2, the positions of the terminals of the terminal groups PA3 and PA4 of rows R3 and R4 of the memory card SD3 correspond to the positions of the terminals of the terminal groups PB3 and PB4 of rows R3 and R4 of the memory card SD4.

[0178] A terminal group DA1 is provided on the surface of the adapter AP3. The terminals of the terminal group DA1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD4.

[0179] Lead pins IA1 are provided on the inner surface of the insertion portion IE2 of the adapter AP3. The lead pins IA1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD3. The lead pins IA1 are connected one-to-one to each terminal of the terminal group DA1 via wiring HA1.

[0180] When the memory card SD3 is attached to the adapter AP3, the memory card SD3 is inserted into the insertion section IE2 from the rear end of the adapter AP3.

[0181] 14C and 14D, each terminal of terminal group PA1 in row R1 of memory card SD3 can be brought into contact with lead pin IA1. Furthermore, when each terminal of terminal group PA1 in row R1 of memory card SD3 is brought into contact with lead pin IA1, the relative positions of terminal group DA1 of adapter AP3 and terminal groups PA3 and PA4 of memory card SD3 can be made to match the relative positions of terminal groups PB1, PB3, and PB4 of memory card SD4. This allows the form factor of memory card SD3 to be converted to the form factor of memory card SD4.

[0182] Here, when the memory card SD3 is inserted into the adapter AP3, the terminals PA3 and PA4 of the memory card SD3 are exposed on the surface of the adapter AP3, so that they can be in contact with the terminals PA3 and PA4 of the memory card SD3 without the need for the terminals of the adapter AP3. Therefore, even if the form factor of the memory card SD3 is converted to the form factor of the memory card SD4, there is no need to bring the terminals PA3 and PA4 of the memory card SD3 into contact with the terminals of the adapter AP3. As a result, when the memory card SD3 is inserted into the adapter AP3, deterioration of the electrical characteristics of the terminals PA3 and PA4 of the memory card SD3 can be prevented.

[0183] (17th embodiment) Figure 15A is a cross-sectional view showing an example of the general configuration of an adapter before a memory card in accordance with the 17th embodiment is inserted, Figure 15B is a plan view showing an example of the general configuration of an adapter before a memory card in accordance with the 17th embodiment is inserted, Figure 15C is a cross-sectional view showing an example of the general configuration of an adapter after a memory card in accordance with the 17th embodiment is inserted, and Figure 15D is a plan view showing an example of the general configuration of an adapter after a memory card in accordance with the 17th embodiment is inserted.

[0184] In this embodiment, an adapter that converts the form factor of the memory card SD4 in FIG. 4B into the form factor of the memory card SD5 in FIG. 4C is shown.

[0185] 15A and 15B, the adapter AP4 is provided with an insertion portion IE3 into which a memory card SD4 is inserted. An entrance to the insertion portion IE3 can be provided on the surface of the adapter AP4. The entrance to the insertion portion IE3 can expose terminal groups PB3 and PB4 of rows R3 and R4 of the memory card SD4 on the surface of the adapter AP4 when the memory card SD4 is inserted into the insertion portion IE3.

[0186] The position of the insertion section IE3 can be set so that when the memory card SD4 is inserted into the insertion section IE3, the positions of the terminals of the terminal groups PB3 and PB4 of rows R3 and R4 of the memory card SD4 correspond to the positions of the terminals of the terminal groups PC3 and PC4 of rows R3 and R4 of the memory card SD5.

[0187] A terminal group DB1 is provided on the surface of the adapter AP4, and the terminals of the terminal group DB1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD5.

[0188] Lead pins IB1 are provided on the inner surface of the insertion portion IE3 of the adapter AP4. The lead pins IB1 can be arranged to correspond to the terminal arrangement of row R1 of the memory card SD4. The lead pins IB1 are connected one-to-one to each terminal of the terminal group DB1 via wiring HB1.

[0189] When the memory card SD4 is attached to the adapter AP4, the memory card SD4 is inserted into the insertion section IE3 from the surface of the adapter AP4.

[0190] 15C and 15D, each terminal of terminal group PB1 in row R1 of memory card SD4 can be brought into contact with lead pin IB1. Furthermore, when each terminal of terminal group PB1 in row R1 of memory card SD4 is brought into contact with lead pin IB1, the relative positions of terminal group DB1 of adapter AP4 and terminal groups PB3 and PB4 of memory card SD4 can be made to match the relative positions of terminal groups PC1, PC3, and PC4 of memory card SD5. This allows the form factor of memory card SD4 to be converted to the form factor of memory card SD5.

[0191] Here, when the memory card SD4 is inserted into the adapter AP4, the terminals PB3 and PB4 of the memory card SD4 are exposed on the surface of the adapter AP4, allowing contact with the terminals PB3 and PB4 of the memory card SD4 without the need for the terminals of the adapter AP4. Therefore, even if the form factor of the memory card SD4 is converted to the form factor of the memory card SD5, there is no need to contact the terminals PB3 and PB4 of the memory card SD4 with the terminals of the adapter AP4. As a result, when the memory card SD4 is inserted into the adapter AP4, deterioration of the electrical characteristics of the terminals PB3 and PB4 of the memory card SD4 can be prevented.

[0192] (18th embodiment) Fig. 16A is a perspective view showing a schematic configuration of a memory card according to an eighteenth embodiment, which is a modified example of the memory card SD4 in Fig. 4B.

[0193] 16A, this memory card SD4' has a terminal group PB1' instead of the terminal group PB1 of the memory card SD4. The terminals of the terminal group PB1' are arranged from the front surface to the front end face of the memory card SD4'. This allows contact to be made from the tip of the memory card SD4' with the terminals of row R1 of the memory card SD4'.

[0194] (19th embodiment) Fig. 16B is a cross-sectional view showing an example of a schematic configuration of an adapter before a memory card is inserted according to the 19th embodiment. Fig. 16B shows a modified example of the adapter AP4 of Figs. 15A to 15D.

[0195] 16B, adapter AP4' has an insertion section IE3', pogo pins 62, and wires HB2 instead of the insertion section IE3, lead pin IB1, and wires HB1 of adapter AP4. The pogo pins 62 are embedded in the side surface of the tip of the insertion section IE3'. The pogo pins 62 are connected one-to-one to each terminal of the terminal group DB1 via the wires HB2.

[0196] When the memory card SD4' is inserted into the adapter AP4', the memory card SD4' is inserted into the insertion section IE3' from the front side of the adapter AP4'. At this time, the tips of the terminals of the terminal group PB1' of row R1 of the memory card SD4' are crimped onto the pogo pins 62, thereby ensuring stable contact.

[0197] 15C, when memory card SD4 is inserted into adapter AP4, a step occurs between terminal group DB1 of adapter AP4 and terminal groups PB3 and PB4 of memory card SD4. When making contact with these terminal groups DB1, PB3, and PB4, the step must be absorbed by the connector.

[0198] On the other hand, when the memory card SD4' is attached to the adapter AP4', the difference in level between the terminal group DB1 of the adapter AP4' and the terminal groups PB3 and PB4 of the memory card SD4' can be almost completely eliminated. This eliminates the need to absorb the difference in level with a connector that makes contact with the terminal groups DB1, PB3, and PB4, preventing the connector structure from becoming complicated.

[0199] (Twentyth embodiment) Fig. 16C is a perspective view showing a schematic configuration of a memory card according to the twentieth embodiment, and Fig. 16D is a cross-sectional view showing the state of the adapter after the memory card of Fig. 16C is inserted. Fig. 16C shows a modified example of the memory card SD4 of Fig. 4B.

[0200] In FIG. 16C, a step 61 is provided at the tip of the memory card SD4''. In this case, the terminal group PB1 can be disposed at a position lower by the height of the step 61.

[0201] When the memory card SD4" is attached to the adapter AP4, the memory card SD4" is inserted into the insertion section IE3 from the front side of the adapter AP4. At this time, each terminal of the terminal group PB1 of row R1 of the memory card SD4" can be brought into contact with the lead pin IB1.

[0202] Here, as shown in FIG. 15C, when the memory card SD4 is inserted into the adapter AP4, a step occurs between the terminal group DB1 of the adapter AP4 and the terminal group PB3, PB4 of the memory card SD4.

[0203] On the other hand, when memory card SD4" is attached to adapter AP4, the difference in level between terminal group DB1 of adapter AP4 and terminal groups PB3 and PB4 of memory card SD4" can be almost completely eliminated. This eliminates the need to absorb the difference in level with a connector that makes contact with terminal groups DB1, PB3, and PB4, preventing the connector structure from becoming complicated.

[0204] (21st embodiment) Fig. 17 is a plan view showing an example of a schematic configuration of an adapter according to the 21st embodiment after a memory card is inserted. Fig. 17 shows a modified example of the adapter AP1 shown in Figs. 13A to 13D.

[0205] 17, adapter AP1' is provided with a semiconductor chip 71. The semiconductor chip 71 may be mounted in any position other than the location shown in the figure, and the semiconductor chip 71 may be embedded in any empty space in adapter AP1'. The semiconductor chip 71 is connected to lead pin IA2 in FIGS. 13A and 13B.

[0206] The semiconductor chip 71 can be provided with functions such as a wireless module, a proximity wireless module, a secure module, and a sensor for smells, illuminance, etc.

[0207] Wireless modules can be compatible with standards such as 11a, 11b, 11g, 11n, 11ad, and WiGig. Proximity wireless modules can be compatible with standards such as NFC, Zwave, ZigBee, and Transfer Jet. Secure modules can be compatible with standards such as TEE (Trusted Execution Environment), TCG (Trusted Computing Group), and OPAL.

[0208] When the memory card SD2 is attached to the adapter AP1', the host device is connected to the memory card SD2 via rows R3 and R4, and the semiconductor chip 71 can be connected to the memory card using the terminal group of row R2 of the memory card SD2. As a result, by attaching the adapter AP1' with the memory card SD2 attached to the host device, the host device can be equipped with functions such as a wireless module, a secure module, or a sensor.

[0209] (Twenty-second embodiment) Fig. 18 is a plan view showing a schematic configuration of a memory card according to a 22nd embodiment, which shows a modification of the memory card SD4 in Fig. 4B.

[0210] In FIG. 18, in memory card SD6, terminal group PB1 of row R1 of memory card SD4 has been removed. Rows R3 and R4 have been added in the position of row R1 of memory card SD4. In rows R3 and R4 of memory card SD6, terminal groups PB3' and PB4' have been added to differential signal terminal groups PB3 and PB4 of memory card SD4, respectively, as replacements for the control signal terminals that used row R1. Although terminal groups PB3' and PB4' may differ in shape or number, compatibility can be maintained by inheriting the functions of row R1. In other words, memory card SD6 can be converted to memory card SD5 using an adapter.

[0211] The memory card SD6 can be provided with a second-mode communication function compatible with the PCIe standard. In this case, control signals used to control communication in the second mode compatible with the PCIe standard are assigned to the terminal groups PB3' and PB4'. These control signals can include the reference differential clock signal REFCLKp / n, the reset signal PERST, and the power management control signal CLKREQ. Furthermore, the wake-up signal PEWAKE can also be used as this control signal.

[0212] Here, by removing the terminal group PB1 from row R1 of memory card SD4 and providing terminal groups PB3, PB3', PB4, and PB4' in rows R3 and R4 of memory card SD6, it is possible to provide memory card SD6 with a second mode communication function that complies with the PCIe standard while increasing the free space on the card surface of memory card SD6. This makes it easy to increase the number of rows of memory card SD6, and therefore the number of lanes of the PCIe standard, and therefore the data transfer speed of memory card SD6.

[0213] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0214] SD1 to SD5 memory cards, PA1 to PA4 terminal group, R1 to R4 rows, 11, 12 regulator, 13 comparator, 14 card controller, 15 memory interface circuit, 16 memory, 17 IO cell, 18 physical layer, 19 card interface circuit

Claims

1. a connector connectable to a memory card having a first surface including a first row and a second row, a second surface facing the opposite side to the first surface, a first group of terminals arranged in the first row, and a second group of terminals arranged in the second row; a transmitter that transmits a first differential data signal conforming to the PCIe standard to the connector via a first transmission line; a receiver that receives a second differential data signal conforming to the PCIe standard from the connector via a second transmission line; a first AC coupling capacitor provided in the first transmission line; a second AC coupling capacitor provided in the second transmission line; Equipped with The connector comprises: a connector first contact group connectable to the first terminal group; a second connector contact group connectable to the second terminal group; Including, The first connector contact group includes: a terminal to which a differential clock signal conforming to the PCIe standard is assigned; A terminal to which a single-ended signal is assigned, a terminal to which a first power supply voltage is assigned; Including, The second connector contact group includes: two terminals to which the first differential data signals are assigned; two terminals to which the second differential data signals are assigned; A plurality of terminals to which ground is assigned; Contains Host device.

2. the two terminals to which the first differential data signals are assigned are arranged adjacent to each other; the two terminals to which the second differential data signals are assigned are arranged adjacent to each other; two terminals to which the first differential data signals are assigned are disposed between two terminals of the plurality of terminals to which the ground is assigned; The two terminals to which the second differential data signals are assigned are disposed between two terminals of the plurality of terminals to which the ground is assigned. The host device of claim 1 .

3. When communicating with the memory card in a first mode, a data signal conforming to the SD standard is transmitted using a plurality of first terminals included in the connector first contact group, and a clock signal conforming to the SD standard is transmitted using a second terminal included in the first terminal group; When communicating with the memory card in a second mode, a differential clock signal conforming to the PCIe standard is transmitted using the plurality of first terminals included in the connector first contact group, and a differential data signal conforming to the PCIe standard is transmitted using two terminals included in the connector second contact group to which the first differential data signal is assigned. The host device of claim 1 .

4. When communicating with the memory card in the second mode, a differential data signal conforming to the PCIe standard is received using two terminals included in the second connector contact group and to which the second differential data signal is assigned. The host device according to claim 3 .

5. the second connector contact group includes terminals to which a second power supply voltage is assigned, When communicating with the memory card in the second mode, a first voltage is applied to the terminal to which the first power supply voltage is assigned, and a second voltage lower than the first voltage is applied to the terminal to which the second power supply voltage is assigned. The host device according to claim 4 .

6. The first voltage is 3.3V and the second voltage is 1.8V. The host device according to claim 5 .

7. The memory card is a microSD card. The host device of claim 1 .

8. a first switch that shorts both ends of the first AC coupling capacitor; a second switch that shorts both ends of the second AC coupling capacitor; Further equipped The host device of claim 1 .

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