Clock signal generation circuit and clock signal generation method thereof

Abstract

To provide a clock signal generation device and a clock signal generation method thereof.SOLUTION: When the analog clock-signal generator circuit is not providing the output-clock signal CLK3, the control circuit controls the multiplexer circuit 108 to selectively output the oscillator signal CLK2 to the analog clock-signal generator circuit, and controls the clock-path circuit to stop transmitting the input-clock signal CLK1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a clock signal generating device, and more particularly to a multiphase clock signal generating circuit and a clock signal generating method thereof. [Background technology]

[0002] Generally speaking, to achieve high-speed read / write operations, memory devices often use multi-phase clock signals provided by a multi-phase clock circuit to serialize or deserialize data signals. The multi-phase clock circuit may be, for example, a four-phase analog clock generator circuit used to generate a four-phase clock signal. Even when the four-phase analog clock generator circuit does not need to output a clock signal and is in a power-off mode, it must continue to provide a clock signal to the four-phase clock generator circuit via a clock path circuit, allowing the four-phase clock generator circuit to return to normal mode and operate normally. However, the clock path circuit usually includes circuit components such as buffers that consume relatively high power, and configuring the clock path circuit to provide a clock signal to the four-phase clock generator in this state would consume a considerable amount of power. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a clock signal generating circuit and a clock signal generating method that can effectively and significantly reduce the power consumption of the clock signal generating circuit. [Means for solving the problem]

[0004] The clock signal generation circuit of the present invention includes a receiver circuit, a clock path circuit, an oscillator circuit, a multiplexer circuit, an analog clock signal generator circuit, and a control circuit. The receiver circuit receives an input clock signal. The clock path circuit is coupled to the receiver circuit and transmits the input clock signal. The oscillator circuit provides an oscillator signal having the same frequency as the input clock signal. The input end of the multiplexer circuit is coupled to the clock path circuit and the oscillator circuit. The analog clock signal generator circuit is coupled to the oscillator circuit and provides an output clock signal. The control circuit is coupled to the clock path circuit and the multiplexer circuit. When the analog clock signal generator circuit is not providing an output clock signal, the multiplexer circuit is controlled to selectively output the oscillator signal to the analog clock signal generator circuit, and the clock path circuit is controlled to stop transmitting the input clock signal.

[0005] In one embodiment of the present invention, an input of an oscillator circuit is coupled to an input of a clock path circuit or an output of an analog clock signal generator circuit to generate an oscillator signal based on an input clock signal or an output clock signal.

[0006] In one embodiment of the present invention, the oscillator circuit comprises a ring oscillator circuit or an injection-locked oscillator circuit.

[0007] In one embodiment of the present invention, the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit.

[0008] In one embodiment of the present invention, when the analog clock signal generator circuit enters an idle mode or a power-off mode, the control circuit determines that the analog clock signal generator circuit is not providing an output clock signal.

[0009] The present invention also provides a clock signal generation method for a clock signal generation circuit. The clock signal generation circuit includes a clock path circuit, an oscillator circuit, a multiplexer circuit, and an analog clock signal generator circuit. The clock path circuit and the oscillator circuit are coupled to an input terminal of the multiplexer circuit. The output terminal of the oscillator circuit is coupled to the analog clock signal generator circuit. The clock path circuit is configured to transmit an input clock signal. The clock signal generation method for the clock signal generation circuit includes the following steps: determining whether the analog clock signal generator circuit is providing an output clock signal; controlling the multiplexer circuit to selectively output the input clock signal to the analog clock signal generator circuit in response to the analog clock signal generator circuit providing the output clock signal; and controlling the multiplexer circuit to selectively output the oscillator signal to the analog clock signal generator circuit and controlling the clock path circuit to stop transmitting the input clock signal in response to the analog clock signal generator circuit not providing the output clock signal.

[0010] In one embodiment of the present invention, an input of an oscillator circuit receives an input clock signal or an output clock signal to generate an oscillator signal based on the input clock signal or the output clock signal.

[0011] In one embodiment of the present invention, the oscillator circuit comprises a ring oscillator circuit or an injection-locked oscillator circuit.

[0012] In one embodiment of the present invention, the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit.

[0013] In one embodiment of the present invention, when the analog clock signal generator circuit enters an idle mode or a power-off mode, it is determined that the analog clock signal generator circuit is not providing an output clock signal. [Effects of the Invention]

[0014] Based on the above, the control circuit of an embodiment of the present invention can control the multiplexer circuit to selectively output the oscillator signal provided by the oscillator circuit to the analog clock signal generator circuit when the analog clock signal generator circuit does not provide an output clock signal, and control the clock path circuit to stop transmitting the input clock signal. In this way, when the analog clock signal generator circuit does not provide an output clock signal, the oscillator circuit is used instead of the clock path circuit to provide an oscillator signal with the same frequency as the input clock signal to the analog clock signal generator circuit, thereby effectively reducing the power consumption of the clock signal generation circuit.

[0015] In order to make the above-mentioned features and advantages of the present invention clearer and easier to understand, the following embodiments will be described in detail with reference to the accompanying drawings. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic diagram of a clock signal generation circuit according to an embodiment of the present invention; [Figure 2] 1 is a schematic diagram of a clock signal generation circuit according to an embodiment of the present invention; [Figure 3] 1 is a schematic diagram of a clock signal generation circuit according to an embodiment of the present invention; [Figure 4] FIG. 2 is a flow diagram of a clock signal generation method of the clock signal generation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] FIG. 1 is a schematic diagram of a clock signal generation circuit according to one embodiment of the present invention. Referring to FIG. 1, the clock signal generation circuit may include a receiver circuit 102, a clock path circuit 104, a control circuit 106, a multiplexer circuit 108, an oscillator circuit 110, and an analog clock signal generator circuit 112. The clock path circuit 104 is coupled to the receiver circuit 102, the control circuit 106, and an input terminal of the multiplexer circuit 108. The oscillator circuit 110 is coupled to another input terminal of the multiplexer circuit 108. The control terminal of the oscillator circuit 110 is coupled to the control circuit 106. The output terminal of the multiplexer circuit 108 is coupled to the analog clock signal generator circuit 112. The analog clock signal generator circuit 112 may be, for example, a four-phase analog clock signal generator circuit, although the present invention is not limited thereto. In other embodiments, the analog clock signal generator circuit 112 may be an analog clock signal generator with a different number of phases. The receiver circuit 102, the clock path circuit 104, the control circuit 106, the multiplexer circuit 108, the oscillator circuit 110, and the analog clock signal generator circuit 112 may be applied to, for example, a memory device and may be implemented as an integrated circuit, a system on a chip (SoC), a chipset, or a chip assembly.

[0018] The receiver circuit 102 can receive an input clock signal CLK1 for transmission to an input end of the multiplexer circuit 108 via the clock path circuit 104. The oscillator circuit 110 is configured to receive the input clock signal CLK0 and provide an oscillator signal CLK2 having the same frequency as the input clock signal CLK1. The oscillator circuit 110 can be, for example, an injection locked oscillator (ILO) circuit or a ring oscillator circuit, but the present invention is not limited thereto. For example, as shown in FIG. 2, the oscillator circuit 110 can be coupled to the output end of the analog clock signal generator circuit 112 to receive the output clock signal CLK3 provided by the analog clock signal generator circuit 112 as the input clock signal CLK0 and provide the oscillator signal CLK2 based on the output clock signal CLK3 output by the analog clock signal generator circuit 112. Alternatively, as shown in FIG. 3, the oscillator circuit 110 can be coupled to the input end of the clock path circuit 104 to provide the oscillator signal CLK2 based on the input clock signal CLK1. In other embodiments, the input clock signal CLK0 received by the oscillator circuit 110 may be from other circuits, without being limited to the embodiments of FIGS.

[0019] The control circuit 106 may determine whether the analog clock signal generator circuit 112 is providing the output clock signal CLK3, for example, by determining whether the analog clock signal generator circuit 112 has entered an idle mode or a power-off mode. When the analog clock signal generator circuit 112 has entered an idle mode or a power-off mode, it is determined that the analog clock signal generator circuit 112 is not providing an output clock signal. Otherwise, it is determined that the analog clock signal generator circuit 112 is providing an output clock signal. When the control circuit 106 determines that the analog clock signal generator circuit 112 is not providing an output clock signal, the control circuit 106 can control the multiplexer circuit 108 to selectively output the oscillator signal CLK2 to the analog clock signal generator circuit 112 and control the clock path circuit 104 to stop transmitting the input clock signal CLK1. In this way, when analog clock signal generator circuit 112 does not need to provide an output clock signal, oscillator circuit 110 is used in place of clock path circuit 104 to provide oscillator signal CLK2, which has the same frequency as input clock signal CLK1, to analog clock signal generator circuit 112, and clock path circuit 104 is configured to stop transmitting input clock signal CLK1, thereby effectively reducing the power consumption of the clock signal generation circuit without affecting the normal operation of the clock signal generation circuit.

[0020] FIG. 4 is a flow diagram of a clock signal generation method of a clock signal generation circuit according to one embodiment of the present invention. The clock signal generation circuit includes a clock path circuit, an oscillator circuit, a multiplexer circuit, and an analog clock signal generator circuit. The clock path circuit and the oscillator circuit are coupled to an input terminal of the multiplexer circuit. The output terminal of the multiplexer circuit is coupled to the analog clock signal generator circuit. The oscillator circuit may be implemented as a ring oscillator circuit or an injection-locked oscillator circuit, but the present invention is not limited thereto. The clock path circuit is configured to transmit an input clock signal. From the above embodiment, it can be seen that the clock signal generation method of the clock signal generation circuit may include at least the following steps: First, determine whether the analog clock signal generator circuit provides an output clock signal (step S402). For example, it can be determined whether the analog clock signal generator circuit has entered idle mode or power-off mode. When the analog clock signal generator circuit has entered idle mode or power-off mode, it is determined that the analog clock signal generator circuit is not providing an output clock signal. The analog clock signal generator circuit may be, for example, a four-phase analog clock signal generator circuit, but the present invention is not limited thereto. If the analog clock signal generator circuit is providing an output clock signal, the multiplexer circuit is controlled to selectively output the input clock signal to the analog clock signal generator circuit. If it is determined that the analog clock signal generator circuit is providing an output clock signal, the multiplexer circuit is controlled to selectively output the input clock signal provided by the clock path circuit to the analog clock signal generator circuit (step S404). If it is determined that the analog clock signal generator circuit is not providing an output clock signal, the multiplexer circuit is controlled to selectively output an oscillator signal to the analog clock signal generator circuit (step S406), and the clock path circuit is controlled to stop transmitting the input clock signal (step S408). The oscillator circuit can receive the input clock signal or the output clock signal output from the analog clock signal generator circuit to generate an oscillator signal based on the input clock signal or the output clock signal.

[0021] In summary, the control circuit of an embodiment of the present invention can control the multiplexer circuit to selectively output the oscillator signal provided by the oscillator circuit to the analog clock signal generator circuit when the analog clock signal generator circuit is not providing an output clock signal, and control the clock path circuit to stop transmitting the input clock signal. In this way, when the analog clock signal generator circuit is not providing an output clock signal, the oscillator circuit is used instead of the clock path circuit to provide an oscillator signal having the same frequency as the input clock signal to the analog clock signal generator circuit, thereby effectively reducing the power consumption of the clock signal generation circuit. [Industrial Applicability]

[0022] The clock signal generating circuit and the clock signal generating method thereof can be applied in the field of memory devices. [Explanation of symbols]

[0023] 102: Receiver circuit 104: Clock path circuit 106: Control circuit 108: Multiplexer circuit 110: Oscillator circuit 112: Analog clock signal generator circuit CLK1~CLK3: Clock signals S402 to S408: Steps of the clock signal generating method of the clock signal generating circuit

Claims

1. a receiver circuit configured to receive an input clock signal; a clock path circuit coupled to the receiver circuit for transmitting the input clock signal; an oscillator circuit configured to provide an oscillator signal at the same frequency as the input clock signal; a multiplexer circuit having inputs coupled to the clock path circuit and the oscillator circuit; an analog clock signal generator circuit coupled to the oscillator circuit for providing an output clock signal; a control circuit coupled to the clock path circuit and the multiplexer circuit, configured to control the multiplexer circuit to selectively output the oscillator signal to the analog clock signal generator circuit and to control the clock path circuit to stop transmitting the input clock signal when the analog clock signal generator circuit is not providing the output clock signal; Including, Clock signal generation circuit.

2. an input of the oscillator circuit coupled to an input of the clock path circuit or an output of the analog clock signal generator circuit to generate the oscillator signal based on the input clock signal or the output clock signal; 2. The clock signal generating circuit according to claim 1.

3. the oscillator circuit comprises a ring oscillator circuit or an injection-locked oscillator circuit; 2. The clock signal generating circuit according to claim 1.

4. the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit; 2. The clock signal generating circuit according to claim 1.

5. When the analog clock signal generator circuit enters an idle mode or a power-off mode, the control circuit determines that the analog clock signal generator circuit is not providing the output clock signal.

2. The clock signal generating circuit according to claim 1.

6. A clock signal generation method for a clock signal generation circuit, comprising: the clock signal generation circuit includes a clock path circuit, an oscillator circuit, a multiplexer circuit, and an analog clock signal generator circuit, the clock path circuit and the oscillator circuit are coupled to an input of the multiplexer circuit, an output of the multiplexer circuit is coupled to the analog clock signal generator circuit, and the clock path circuit is configured to transmit an input clock signal; The clock signal generating method of the clock signal generating circuit includes: determining whether the analog clock signal generator circuit is providing an output clock signal; controlling the multiplexer circuit to selectively output the input clock signal to the analog clock signal generator circuit in response to the analog clock signal generator circuit providing the output clock signal; controlling the multiplexer circuit to selectively output an oscillator signal to the analog clock signal generator circuit and controlling the clock path circuit to stop transmitting the input clock signal in response to the analog clock signal generator circuit not providing the output clock signal; Including, A clock signal generating method for a clock signal generating circuit.

7. an input end of the oscillator circuit receives the input clock signal or the output clock signal to generate the oscillator signal based on the input clock signal or the output clock signal; 7. A clock signal generating method for the clock signal generating circuit according to claim 6.

8. the oscillator circuit comprises a ring oscillator circuit or an injection-locked oscillator circuit; 7. A clock signal generating method for the clock signal generating circuit according to claim 6.

9. the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit; 7. A clock signal generating method for the clock signal generating circuit according to claim 6.

10. determining that the analog clock signal generator circuit is not providing an output clock signal when the analog clock signal generator circuit enters an idle mode or a power-off mode; 7. A clock signal generating method for the clock signal generating circuit according to claim 6.

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