High electron mobility transistor

Abstract

To provide a gallium nitride (GaN) high electron mobility transistor with improved component current and output power.SOLUTION: The high electron mobility transistor 100 includes a substrate 1, a barrier layer 2, a semiconductor layer 3, an insertion layer 4, a passivation layer 5, a drain electrode 61, a source electrode 62, and a gate electrode 63. The barrier layer 2 is disposed on the substrate 1 and includes aluminum gallium indium nitride. The semiconductor layer 3 is disposed between the substrate 1 and the barrier layer 2. The insertion layer 4 is disposed between the semiconductor layer 3 and the barrier layer 2 and contains aluminum gallium nitride. The thickness of the barrier layer may range from 3nm to 40nm. The passivation layer 5 is arranged on the barrier layer 2 and comprises silicon nitride. The drain electrode 61 and the source electrode 62 are disposed on the barrier layer 2, and the gate electrode 63 is disposed on the passivation layer 5.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of Taiwan Patent Application No. 113127442, filed July 23, 2024, the subject matter of which is incorporated herein by reference.

[0002] The present invention relates to high electron mobility transistors, and more particularly to gallium nitride (GaN) high electron mobility transistors. [Background technology]

[0003] High electron mobility transistors (HEMTs) have been attracting increasing attention from various fields in recent years. HEMTs have the advantages of high switching speed, high electron mobility, high breakdown field, good thermal stability, and wide energy gap, and can be used in high-voltage or high-frequency electronic components.

[0004] Current high electron mobility transistors use GaN as the channel layer, and a tertiary or quaternary barrier layer is formed on the channel layer. However, due to issues such as lattice mismatch between the barrier layer and the channel layer and differences in growth temperature, epitaxial quality often deteriorates, leading to increased leakage current and thus affecting transistor performance.

[0005] Therefore, to address future radio frequency power component applications, it is desirable to propose an improved high electron mobility transistor that further improves component current and output power, thereby eliminating or mitigating the above problems. Summary of the Invention

[0006] The present invention provides a high electron mobility transistor (HEM) having an insertion layer between a barrier layer and a channel layer of semiconductor layers, the insertion layer comprising aluminum gallium nitride (AlGaN). The insertion layer acts as an intermediary, thereby improving lattice matching or barrier layer quality, resulting in a smooth interface and enhanced structural integrity. Furthermore, the insertion layer significantly improves surface roughness, electron mobility, and two-dimensional electron gas (2DEG) polarization, reducing leakage current and thereby significantly enhancing the performance of the HEM.

[0007] In this respect, according to one aspect of the present invention, there is provided a high electron mobility transistor comprising a substrate, a barrier layer, a semiconductor layer, and an insertion layer. The barrier layer is deposited on the substrate, and the barrier layer comprises aluminum gallium nitride (InAlGaN). The semiconductor layer is disposed between the substrate and the barrier layer. The insertion layer is disposed between the semiconductor layer and the barrier layer, and comprises aluminum gallium nitride (AlGaN).

[0008] In the present invention, the substrate can be a quartz substrate, a glass substrate, a silicon substrate, a sapphire substrate, a silicon carbide substrate, a GaN substrate, or a combination thereof. For example, the substrate is a silicon substrate.

[0009] In the present invention, aluminum gallium indium nitride (InAlGaN) is In 1-x-y Al x Ga y N, where x is 0.1 to 0.8, and y is 0.8 to 0.1.

[0010] In the present invention, the thickness of the barrier layer may range from 3 nm to 40 nm, for example, 3 nm to 35 nm, 3 nm to 30 nm, 3 nm to 25 nm, 3 nm to 20 nm, 3 nm to 15 nm, 3 nm to 10 nm, 5 nm to 40 nm, 5 nm to 35 nm, 5 nm to 30 nm, 5 nm to 20 nm, 5 nm to 15 nm, or about 6 nm.

[0011] In the present invention, the semiconductor layer may include a nucleation layer, a buffer layer, and a GaN layer. The GaN layer may be disposed on the nucleation layer, and the buffer layer may be disposed between the nucleation layer and the GaN layer. The nucleation layer may include aluminum nitride (AlN), and the buffer layer may include aluminum gallium nitride (AlGaN) and gallium nitride (GaN). Furthermore, the thickness of the nucleation layer may be in the range of 50 nm to 300 nm, e.g., 50 nm to 250 nm, 50 nm to 200 nm, 50 nm to 150 nm, or approximately 100 nm. The thickness of the buffer layer may be in the range of 50 nm to 5000 nm, e.g., 50 nm to 4000 nm, 50 nm to 3000 nm, 50 nm to 2000 nm, approximately 200 nm, or approximately 2500 nm.

[0012] In the present invention, the thickness of the insertion layer ranges from 1 nm to 15 nm, for example, 1 nm to 12 nm, 1 nm to 10 nm, 1 nm to 8 nm, 1 nm to 5 nm, 1 nm to 3 nm, and can be about 1 nm or about 2 nm.

[0013] In the present invention, AlGaN is Al Z Ga 1-Z N, and z can be 0.1 to 0.8. For example, z can be 0.1 to 0.7, 0.1 to 0.6, 0.1 to 0.5, 0.1 to 0.4, 0.1 to 0.3, 0.2 to 0.7, 0.2 to 0.6, 0.2 to 0.5, 0.2 to 0.4, about 0.15, or about 0.22.

[0014] In the present invention, the high electron mobility transistor may further comprise a passivation layer disposed on the barrier layer, and the passivation layer may include silicon nitride.

[0015] In the present invention, the high electron mobility transistor may further comprise a drain electrode, a source electrode and a gate electrode, where the drain electrode and the source electrode may be disposed on the barrier layer and the gate electrode may be disposed on the passivation layer.

[0016] In the present invention, the materials of the drain electrode, source electrode, and gate electrode can be copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, copper alloy, aluminum alloy, molybdenum alloy, tungsten alloy, gold alloy, chromium alloy, nickel alloy, platinum alloy, titanium alloy, other suitable metal, or combination thereof. Furthermore, the drain electrode, source electrode, and gate electrode can comprise a single or multiple metal layers.

[0017] Other objects, advantages, and novel features of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a schematic diagram showing a high electron mobility transistor of the present invention. [Figure 2] FIG. 2 is an AFM photograph of the first embodiment. [Figure 3] FIG. 3 is an AFM photograph of Comparative Example 2. [Figure 4] FIG. 4 is an energy band diagram of the first embodiment of the present invention, the first comparative embodiment, and the second comparative embodiment. [Figure 5] FIG. 5 is an ID-VG plot of the first embodiment of the present invention, the first comparative embodiment, and the second comparative embodiment. [Figure 6] FIG. 6 is an ID-VD plot of the first embodiment of the present invention, the first comparative embodiment, and the second comparative embodiment. [Figure 7] FIG. 7 is a CV plot of Inventive Example 1 and Comparative Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0019] Various embodiments of the present invention are provided in the following description. These embodiments are intended to illustrate the technical concept of the present invention and do not limit the scope of the present invention. Features described in one embodiment can be applied to other embodiments by appropriate modification, substitution, combination, or separation.

[0020] In this specification, when it is stated that a component has a certain element, unless otherwise specified, it means that the component may have one or more elements, and does not mean that the component has only one of those elements.

[0021] Furthermore, in this specification, terms such as "top," "bottom," "left," "right," "front," "back," or "center," and terms such as "above," "upper," "lower," "below," or "between," are used to describe relative positions between multiple elements, and the described relative positions can be interpreted to include translation, rotation, or reflection thereof.

[0022] Furthermore, when an element is described herein as being disposed "on" another element, this does not necessarily mean that the element is in contact with the other element unless otherwise specified. Such an interpretation also applies to other cases similar to "on."

[0023] Furthermore, in this specification, unless otherwise specified, a value may be interpreted as encompassing a range of ±10% of that value, particularly a range of ±5% of that value. A range may be interpreted as consisting of multiple subranges defined by a lower endpoint, a lower quartile, a median, an upper quartile, and a higher endpoint.

[0024] Embodiment 1 FIG. 1 is a schematic diagram showing a high electron mobility transistor according to a first embodiment of the present invention.

[0025] As shown in FIG. 1 , the high electron mobility transistor 100 of this embodiment includes a substrate 1, a barrier layer 2, a semiconductor layer 3, an insertion layer 4, a passivation layer 5, a drain electrode 61, a source electrode 62, and a gate electrode 63. The barrier layer 2 is disposed on the substrate 1 and includes aluminum gallium indium nitride (InAlGaN). The semiconductor layer 3 is disposed between the substrate 1 and the barrier layer 2 and includes a nucleation layer 31, a buffer layer 32, and a GaN layer 33. The GaN layer 33 is disposed on the nucleation layer 31, and the buffer layer 32 is disposed between the nucleation layer 31 and the GaN layer 33. The nucleation layer 31 includes aluminum nitride (AlN). The insertion layer 4 is disposed between the semiconductor layer 3 and the barrier layer 2 and includes aluminum gallium nitride (AlGaN). Furthermore, the passivation layer 5 is disposed on the barrier layer 2 and includes silicon nitride. The drain electrode 61 and the source electrode 62 are disposed on the barrier layer 2, and the gate electrode 63 is disposed on the passivation layer 5.

[0026] The method for fabricating the high electron mobility transistor 100 of this embodiment comprises the following steps: A silicon substrate 1 is provided, and a nucleation layer 31 containing 100 nm of AlN, a 200 nm of Al 0.15 Ga 0.85 A buffer layer 32 containing N and 2.5 μm of carbon-doped GaN and a GaN layer 33 containing 500 nm of GaN are sequentially grown on the silicon substrate 1 by metalorganic chemical vapor deposition (MOCVD) to form the semiconductor layer 3. Next, a 2 nm Al 0.15 Ga 0.85 N-containing insertion layers of 4 and 6 nm In 0.04 Al 0.66 Ga 0.3A barrier layer 2 containing N is sequentially formed on the semiconductor layer 3. Using an electron gun, a metal layer of 200 Å Ti / 1200 Å Al / 250 Å Ni / 1000 Å Au is deposited on the barrier layer 2 as the drain electrode 61 and the source electrode 62. After removing the remaining portions and annealing at 820°C in a nitrogen ambient, a passivation layer 5 containing 25 nm SiN is deposited using atomic layer deposition (ALD) and rapid thermal annealing (RTA) at 300°C. Next, an electron gun is used to form a metal layer of 500 Å Ni / 3000 Å Au as the gate electrode 63. Finally, etching is performed using chlorine inductively coupled plasma (ICP) to obtain the high electron mobility transistor 100. The gate length L of the gate electrode is g is 2 μm, and the distance between the gate electrode and the source electrode L gs is 3 μm, and the distance between the gate electrode and the drain electrode L gd is 5 μm.

[0027] Embodiment 2 The HEMT of this embodiment has an insertion layer 4 of 4 nm. 0.15 Ga 0.85 It is the same as that of embodiment 1 except that N is included.

[0028] Embodiment 3 The HEMT of this embodiment has an insertion layer 4 of 6 nm. 0.15 Ga 0.85 It is the same as that of embodiment 1 except that N is included.

[0029] Embodiment 4 The HEMT of this embodiment has a barrier layer 2 of 4 nm In 0.04 Al 0.66 Ga 0.3 It is the same as that of embodiment 3 except that N is included.

[0030] Embodiment 5 The HEMT of this embodiment has a barrier layer 2 of 7 nm In0.04 Al 0.66 Ga 0.3 It is the same as that of embodiment 1 except that N is included.

[0031] Embodiment 6 The HEMT of this embodiment has an insertion layer 4 of 2 nm. 0.22 Ga 0.78 It is the same as that of embodiment 1 except that N is included.

[0032] Comparative embodiment 1 The HEMT of Comparative Example 1 is similar to that of Example 1, except that the insertion layer 4 of Comparative Example 1 includes 1 nm of AlN.

[0033] Comparative embodiment 2 The HEMT of Comparative Example 2 is similar to that of Example 1, except that the HEMT of Comparative Example 2 does not include the insertion layer 4.

[0034] Comparative Embodiment 3 The HEMT of Comparative Example 3 is similar to that of Example 1, except that the insertion layer 4 of Comparative Example 3 includes 2 nm of AlN.

[0035] Comparative Embodiment 4 The HEMT of Comparative Example 4 has a barrier layer 2 of 23 nm Al 0.2 Ga 0.8 It is the same as that of Comparative Example 3 except that it contains N.

[0036] Experimental results FIG. 2 is an AFM photograph of the first embodiment.

[0037] FIG. 3 is an AFM photograph of Comparative Example 2.

[0038] 1 to 3, in the high electron mobility transistor 100 of embodiment 1, the insertion layer 4 is an intermediary between the GaN layer 33 and the barrier layer 2, and its lattice constant is very close to that of the GaN layer 33 and the barrier layer 2. Therefore, the epitaxial quality and surface morphology can be significantly improved. Furthermore, the interface between the insertion layer 4 and the GaN layer 33 is smoother, which can reduce the binding energy of indium atoms and improve the growth of the barrier layer 2.

[0039] Furthermore, the surface roughness (RMS) of the barrier layer 2 of the high electron mobility transistor 100 of Example 1 is 0.471 nm, the surface roughness of the barrier layer 2 of the high electron mobility transistor 100 of Example 2 is 0.383 nm, and the surface roughness of the barrier layer 2 of the high electron mobility transistor 100 of Example 3 is 0.357 nm. As the thickness of the insertion layer 4 increases, the epitaxial quality can be improved due to the longer transfer length and growth time. On the other hand, the roughness of the barrier layer 2 of Comparative Example 2 is 0.521 nm, and the barrier layer 2 has more irregularities, which leads to interface and quality problems. Therefore, compared to Comparative Example 2, the high electron mobility transistors 100 of Examples 1, 2, and 3 have lower interface scattering due to improved epitaxial quality and alloy scattering, which helps achieve better electron mobility.

[0040] FIG. 4 is an energy band diagram of the first embodiment of the present invention, the first comparative embodiment, and the second comparative embodiment.

[0041] FIG. 5 shows the I of the first embodiment of the present invention, the first comparative embodiment, and the second comparative embodiment. D -V G It's a plot.

[0042] 1, 4, and 5. The leakage mechanism will be discussed through energy band diagrams. The insertion layer 4 of the high electron mobility transistor 100 of Embodiment 1 forms an additional quantum well with the heterostructure of the barrier layer 2 and the GaN layer 33, efficiently trapping electrons in the off-state. This plays an important role in reducing gate electrode leakage current. Furthermore, the insertion layer 4 of the high electron mobility transistor 100 of Embodiment 1 exhibits a flatter conduction band slope compared to the results of Comparative Embodiments 1 and 2, which prevents electrons from passing through the barrier and dielectric interfaces. Furthermore, the additional quantum well formed at the interface between the barrier layer 2 and the insertion layer 4 introduces an extra barrier height, thereby hindering electron migration and promoting electron trapping. Therefore, the off-state leakage current of the high electron mobility transistor 100 of Embodiment 1 is low (as shown in FIG. 5).

[0043] FIG. 6 shows the I of the first embodiment of the present invention, the first comparative embodiment, and the second comparative embodiment. D -V D It's a plot.

[0044] FIG. 7 is a CV plot of Inventive Example 1 and Comparative Example 2.

[0045] As shown in FIGS. 1 and 6, by optimizing the epitaxy and introducing the additional quantum well, the leakage current of the high electron mobility transistor 100 of Embodiment 1 is significantly reduced by two orders of magnitude compared to Comparative Embodiment 1. Furthermore, the breakdown voltage of the high electron mobility transistor 100 of Embodiment 1 reaches 450 V, an increase of 120 V compared to Comparative Embodiment 1. Furthermore, as shown in FIGS. 1 and 7, the insertion layer 4 of the high electron mobility transistor 100 of Embodiment 1 introduces additional capacitance, resulting in an overall decrease in total capacitance due to the correlation associated with summing the individual capacitances. Furthermore, at a gate electrode voltage of −18 V, a further slope in the capacitance curve appears. This phenomenon is due to the release of electrons previously trapped at the heterojunction between the barrier layer 2 and the insertion layer 4 during the formation of the additional quantum well. In the gate electrode voltage range of −20 to −15 V, the presence of trapped electrons affects the capacitance slope. As a higher positive gate electrode voltage is applied, the capacitance curve shows another slope related to channel behavior, similar to the trend observed for Comparative Embodiment 2.

[0046] The results of sheet resistance, electron mobility, carrier density, and maximum drain electrode current for Example 1, Example 2, Example 5, Example 6, and Comparative Example 4 are shown in Table 1 below. [Table 1]

[0047] 1, the high electron mobility transistors 100 of Embodiments 1, 2, 5, and 6 have better sheet resistance. As the thickness of the insertion layer 4 increases, a larger piezoelectric polarization is generated, resulting in more electrons and better epitaxial quality, which promotes a reduction in sheet resistance and maintains high electron mobility and high carrier density. This results in a high drain electrode current and helps to enhance the performance of the high electron mobility transistor 100.

[0048] In summary, the high electron mobility transistor of the present invention can improve epitaxial quality and enhance electronic performance or reliability. Furthermore, the high electron mobility transistor of the present invention can also improve the polarization of the two-dimensional electron gas or reduce leakage current, and the leakage current problem can be alleviated by forming an additional quantum well in the heterostructure of the barrier layer and the insertion layer. Meanwhile, the high electron mobility transistor of the present invention can reduce interface scattering, thereby improving the overall epitaxial quality.

[0049] Although the present disclosure has been described with reference to embodiments thereof, it should be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the disclosure as hereinafter claimed.

Claims

1. A high electron mobility transistor, A substrate; a barrier layer disposed on the substrate and comprising aluminum gallium indium nitride; a semiconductor layer disposed between the substrate and the barrier layer; an insertion layer disposed between the semiconductor layer and the barrier layer and including aluminum gallium nitride; A high electron mobility transistor comprising:

2. 2. The high electron mobility transistor of claim 1, wherein the barrier layer has a thickness in the range of 3 nm to 40 nm.

3. 2. The high electron mobility transistor of claim 1, wherein the semiconductor layer comprises a nucleation layer, a buffer layer, and a gallium nitride layer, the gallium nitride layer being disposed on the nucleation layer and the buffer layer being disposed between the nucleation layer and the gallium nitride layer.

4. The high electron mobility transistor of claim 3 , wherein the nucleation layer comprises aluminum nitride.

5. 2. The high electron mobility transistor of claim 1, wherein the insertion layer has a thickness in the range of 1 nm to 15 nm.

6. The aluminum gallium nitride is Al Ｚ Ga １－Ｚ 2. The high electron mobility transistor of claim 1, wherein N is N and z is 0.1 to 0.

8.

7. 7. The high electron mobility transistor of claim 6, wherein z is 0.1 to 0.

3.

8. The high electron mobility transistor of claim 1 further comprising a passivation layer disposed on the barrier layer.

9. The high electron mobility transistor of claim 8 , wherein the passivation layer comprises silicon nitride.

10. 9. The high electron mobility transistor of claim 8, further comprising a drain electrode, a source electrode, and a gate electrode, wherein the drain electrode and the source electrode are disposed on the barrier layer, and the gate electrode is disposed on the passivation layer.

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