Semiconductor device

Abstract

An object of the present disclosure is, in a semiconductor device having a double-sided gate structure, to suppress carrier injection in a termination region even when a failure occurs in a back side gate operation.SOLUTION: The semiconductor device 101 having the double-sided gate structure includes the buffer layer 7 of the first conductivity type provided on the back surface side of the drift layer 6, and the collector layer 8 of the second conductivity type provided between the buffer layer 7 and the collector electrode 13 in the element region 31. The collector layer 8 of the second conductivity type is not provided between the collector electrode 13 and the buffer layer 7 in the terminal region 32, or is provided between the collector electrode 13 and the buffer layer 7 in the terminal region 32 so that the total amount of impurities of the second conductivity type per unit area of the collector layer 8 of the second conductivity type in the terminal region 32 is smaller than the total amount of impurities of the second conductivity type per unit area of the collector layer 8 of the second conductivity type in the element region 31.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device having a double-sided gate structure and capable of allowing current to flow in both directions. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device with a double-sided gate structure that has gate electrodes on the front and back sides of a semiconductor layer. The semiconductor device described in Patent Document 1 performs a back-side gate operation that turns on the transistor on the back side during a turn-off operation, thereby suppressing the injection of holes into the drift region of the element region and reducing turn-off loss. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7407757 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device described in Patent Document 1 has a problem in that when a malfunction occurs in the back gate operation, carrier injection from the termination region to the element region cannot be suppressed, and breakdown resistance decreases.

[0005] The present disclosure is intended to solve the above problem, and aims to suppress carrier injection into the termination region even if a malfunction occurs in the back gate operation in a semiconductor device having a double-sided gate structure. [Means for solving the problem]

[0006] a first conductivity type collector layer provided between the buffer layer and the collector electrode in the termination region; a first conductivity type collector layer provided between the collector electrode and the buffer layer in the termination region; a second conductivity type collector layer provided between the collector electrode and the buffer layer in the termination region; a first conductivity type collector layer provided between the collector electrode and the buffer layer in the termination region; a first conductivity type collector layer provided between the collector electrode and the buffer layer in the termination region; a second conductivity type collector layer provided between the collector electrode and the buffer layer in the termination region; [Effects of the Invention]

[0007] According to one semiconductor device of the present disclosure, hole injection from the back side of the termination region can be suppressed without providing a back gate structure in the termination region, and therefore carrier injection in the termination region can be suppressed even if a malfunction occurs in the back gate operation. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a top view of a semiconductor device. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 5] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 7] Cross-sectional view of the semiconductor device according to Embodiment 6. [Figure 8] Cross-sectional view of the semiconductor device according to Embodiment 7.

Embodiments for Carrying Out the Invention

[0009] <A. Embodiment 1> <A-1. Configuration> FIG. 1 is a top view of a semiconductor device 101 according to Embodiment 1. The semiconductor device 101 is an IGBT (Insulated Gate Bipolar Transistor). As shown in FIG. 1, the semiconductor device 101 is divided into an element region 31 and a termination region 32 in a plan view. The element region 31 is a region where semiconductor elements are formed and the main current flows. The termination region 32 surrounds the element region 31 and includes an emitter-side gate pad region 33 and a collector-side gate pad region 34. Note that the top views of the semiconductor devices according to other embodiments in this specification are also as shown in FIG. 1.

[0010] FIG. 2 is a cross-sectional view of the semiconductor device 101 taken along the line A-A' in FIG. 1. As shown in FIG. 2, the semiconductor device 101 includes a semiconductor substrate 60. The semiconductor substrate 60 has a first main surface S1 which is the front main surface and a second main surface S2 which is the back main surface. The second main surface S2 is the main surface on the opposite side to the first main surface S1. The first main surface S1 is also referred to as the surface of the semiconductor substrate 60, and the second main surface S2 is also referred to as the back surface of the semiconductor substrate 60.

[0011] First, the configuration of the element region 31 will be described. The semiconductor device 101 includes, in the element region 31, a semiconductor substrate 60, an emitter electrode 12, an emitter-side interlayer film 14, a collector-side interlayer film 15, and a collector electrode 13. In the element region 31, the semiconductor substrate 60 includes an n-type drift layer 6, an n-type buffer layer 7, an emitter-side MOS channel portion 51, and a collector-side MOS channel portion 52. The n-type drift layer 6 functions as a breakdown voltage maintaining portion. The emitter-side MOS channel portion 51 is provided on the first main surface S1 side of the n-type drift layer 6. An emitter electrode 12, which is a main electrode portion, is provided on the first main surface S1.

[0012] The emitter-side MOS channel portion 51 includes an n-type source layer 1, a p-type base layer 2, an emitter-side oxide film 3, and an emitter-side gate electrode 4. The p-type base layer 2 is formed on the first main surface S1 side of the n-type drift layer 6. The n-type source layer 1 and the p-type contact layer 5 are formed on the first main surface S1 side of the p-type base layer 2. The upper surfaces of the n-type source layer 1 and the p-type contact layer 5 form the first main surface S1.

[0013] A trench T1 is formed from the first main surface S1, penetrating the n-type source layer 1 and the p-type base layer 2 to reach the n-type drift layer 6. An emitter-side gate electrode 4 is buried in the trench T1 via an emitter-side oxide film 3. An emitter-side interlayer film 14 is provided between the emitter-side gate electrode 4 and the emitter electrode 12 to insulate them from each other.

[0014] An n-type buffer layer 7 is provided on the second main surface S2 side of the n-type drift layer 6. A collector-side MOS channel portion 52 is provided on the second main surface S2 side of the n-type buffer layer 7. A collector electrode 13, which is a main electrode portion, is provided on the second main surface S2.

[0015] The collector-side MOS channel portion 52 includes a p-type collector layer 8, an n-type collector layer 9, a collector-side oxide film 10, and a collector-side gate electrode 11. The p-type collector layer 8 is formed on the second main surface S2 side of the n-type buffer layer 7. The lower surface of the p-type collector layer 8 forms the second main surface S2. The n-type collector layer 9 is provided in part of the surface layer of the p-type collector layer 8 on the second main surface S2 side.

[0016] A trench T2 is formed from the second main surface S2, penetrating the n-type collector layer 9 and the p-type collector layer 8 to reach the n-type buffer layer 7. A collector-side gate electrode 11 is buried in the trench T2 via a collector-side oxide film 10. A collector-side interlayer film 15 is provided between the collector-side gate electrode 11 and the collector electrode 13 to insulate them from each other.

[0017] The emitter-side n-type layer 22 is formed shallower than the bottom of the emitter-side gate electrode 4, and between the p-type base layer 2 and the n-type drift layer 6, which is a breakdown voltage maintaining portion. The repeating interval (emitter-side gate pitch) of the emitter-side gate electrodes 4 and the repeating interval (collector-side gate pitch) of the collector-side gate electrodes 11 do not have to be the same.

[0018] Next, the configuration of termination region 32 will be described. Semiconductor device 101 includes n-type drift layer 6, which is a breakdown voltage maintaining portion, in termination region 32. A plurality of p-type well layers 16 and n-type channel stopper layers 17 are provided in a portion of the surface layer of n-type drift layer 6 on the first main surface S1 side. N-type channel stopper layer 17 is provided at the outer peripheral edge of semiconductor device 101.

[0019] An emitter-side interlayer film 14, a field plate 19, and an emitter-side gate liner 20 are provided on the first main surface S1. An opening is formed in the emitter-side interlayer film 14 on the p-type well layers 16, excluding the p-type well layer 16 closest to the element region 31, and on the n-type channel stopper layer 17. The field plate 19 contacts the p-type well layer 16 or the n-type channel stopper layer 17 through the opening in the emitter-side interlayer film 14. Note that an opening in the emitter-side interlayer film 14 may also be formed on the p-type well layer 16 closest to the element region 31, and the field plate 19 may contact the p-type well layer 16 through this opening. The emitter-side gate liner 20 and the p-type well layer 16 are insulated from each other by the emitter-side interlayer film 14. A passivation film 18 is provided on the emitter-side interlayer film 14 , the field plate 19 and the emitter-side gate liner 20 .

[0020] A collector electrode 13 and a collector-side gate liner 21 are provided on the second main surface S2. The collector electrode 13 and the collector-side gate liner 21 are insulated from each other by a collector-side interlayer film 15. Although the termination region 32 having an FLR (Field Limiting Ring) structure has been described above, the termination region 32 may also have a RESURF (Reduced Surface Electric Field) structure or a VLD (Variation of lateral doping) structure.

[0021] In the device region 31, a p-type collector layer 8 is provided between the collector electrode 13 and the n-type buffer layer 7. However, in the termination region 32, no p-type collector layer 8 is provided between the collector electrode 13 and the n-type buffer layer 7. Alternatively, in the termination region 32, a p-type collector layer 8 is provided between the collector electrode 13 and the n-type buffer layer 7, but the p-type collector layer 8 in the termination region 32 has a smaller amount of acceptors per unit area in plan view than the p-type collector layer 8 in the device region 31. A smaller amount of acceptors per unit area means that the p-type collector layer 8 is thin or has a low acceptor concentration. This configuration suppresses carrier injection in the termination region. In other words, the structure on the back side of the termination region 32 functions as a carrier injection suppressor that suppresses carrier injection in the termination region.

[0022] The peak concentration of the n-type source layer 1 is 10 18 cm -3 Over 10 21 cm -3 The peak concentration of the p-type base layer 2 is about 10 17 cm -3 The peak concentration of the emitter-side n-type layer 22 is about 10 15 cm -3 Over 10 17 cm -3 The peak concentration of the n-type buffer layer is about 10 15 cm -3 Over 10 18 cm -3 The peak concentration in the p-type collector layer is about 10 17 cm -3 Over 10 19 cm -3 The peak concentration in the collector-side n-type layer is about 10 18 cm -3 Over 10 21 cm -3 It is about the following.

[0023] The concentration of n-type drift layer 6 is 10 12 cm -3 Over 10 14 cm -3It is at the following level. The peak concentration of the p-type well layer 16 is 10 16 cm -3 or more and 10 18 cm -3 or less. The peak concentration of the n-type channel stopper layer 17 is 10 18 cm -3 or more and 10 21 cm -3 or less.

[0024] <A-2. Operation> When a positive voltage is applied to the emitter-side gate electrode 4, the n-type source layer 1 and the breakdown voltage holding portion are connected by the emitter-side MOS channel, and the IGBT is turned on. When the application of the positive voltage to the emitter-side gate electrode 4 is stopped, the IGBT is turned off. At the time of turn-off, when a positive voltage is applied to the collector-side gate electrode 11, the n-type collector layer 9 and the n-type buffer layer 7 are connected by the collector-side MOS channel. This is also referred to as the back gate operation. As a result, the hole injection efficiency of the p-type collector layer 8 decreases, so that the current can be cut off at high speed. However, if a problem occurs in the back gate operation at the time of turn-off, the hole injection efficiency of the p-type collector layer 8 does not decrease, so that the carriers in the element region 31 and the termination region 32 increase. And when there are many carriers in the termination region 32, the breakdown voltage decreases.

[0025] In the semiconductor device 101 of the present embodiment, either the p-type collector layer 8 is not provided in the termination region 32, or the acceptor amount per unit area of the p-type collector layer 8 in the termination region 32 is smaller than the acceptor amount per unit area of the p-type collector layer 8 in the element region 31. The p-type collector layer 8 is a generation source of hole injection. Therefore, in the semiconductor device 101, when the IGBT is in the on state, the hole injection efficiency from the back side of the termination region 32 decreases, and the carriers in the termination region 32 can be reduced.

[0026] As described above, according to the semiconductor device 101 of the present embodiment, the carriers in the termination region 32 can be reduced without providing the back gate structure in the termination region 32. Therefore, even if a problem occurs in the back gate operation, a decrease in the breakdown voltage can be avoided.

[0027] Also, the terminal region 32 can also be used as a diode. Since the impurity concentration of the n-type buffer layer 7 is low and the carrier injection efficiency during diode operation is low, the breakdown voltage does not decrease even if the terminal region 32 is used as a diode.

[0028] <B. Embodiment 2> <B-1. Configuration> FIG. 3 is a cross-sectional view of the semiconductor device 102 according to Embodiment 2 taken along the line A-A' of FIG. 1. The semiconductor device 102 has a configuration different from that of the semiconductor device 101 according to Embodiment 1 in the element region end portion 31A, which is a portion of the element region 31 located near the terminal region 32. That is, in the semiconductor device 102, in the element region end portion 31A, the p-type collector layer 8 is not formed between the collector electrode 13 and the n-type buffer layer 7, or even if the p-type collector layer 8 is formed, the acceptor amount per unit area in the plan view is smaller than that of the p-type collector layer 8 in other portions of the element region 31. The configuration of the semiconductor device 102 other than the element region end portion 31A is the same as that of the semiconductor device 101.

[0029] <B-2. Operation> The semiconductor device 102 according to Embodiment 2 has the following effects in addition to the effects of the semiconductor device 101 according to Embodiment 1.

[0030] In the semiconductor device 102, in the terminal region 32 and the element region end portion 31A, the p-type collector layer 8 is not provided, or the acceptor amount per unit area of the p-type collector layer 8 in the terminal region 32 is smaller than the acceptor amount per unit area of the p-type collector layer 8 in the element region 31. The p-type collector layer 8 is a source of hole injection. Therefore, in the semiconductor device 102, in the terminal region 32 and the element region end portion 31A, holes are not injected or the influence is small when the IGBT is on, so the hole injection efficiency in the terminal region 32 and the element region end portion 31A decreases, and the carriers in the terminal region 32 can be reduced.

[0031] Thus, according to the semiconductor device 102 of the present embodiment, carriers in the termination region 32 can be reduced without providing a back gate structure in the termination region 32 and the element region end 31A. Therefore, even if a problem occurs in the back gate operation, a decrease in the breakdown voltage can be avoided.

[0032] <C. Embodiment 3> <C-1. Configuration> FIG. 4 is a cross-sectional view of a semiconductor device 103 according to Embodiment 3 taken along the line A-A' of FIG. 1. The semiconductor device 103 is different from the semiconductor device 101 according to Embodiment 1 only in that an n-type collector layer 9 is provided between the collector electrode 13 and the n-type buffer layer 7 in the element region end 31A, which is a portion of the element region 31 located near the termination region 32.

[0033] <C-2. Operation> The semiconductor device 103 according to Embodiment 3 has the following effects in addition to the effects of the semiconductor device 101 according to Embodiment 1.

[0034] The n-type collector layer 9 provided in the element region end 31A can reduce the injection of holes from the p-type collector layer 8 in the vicinity of the n-type collector layer 9 because electrons can easily flow and the electrons entering the p-type collector layer 8 can be reduced. As a result, the hole injection efficiency in the vicinity of the element region end 31A decreases, so that carriers in the termination region 32 can be reduced.

[0035] <D. Embodiment 4> <D-1. Configuration><B FIG. 5 is a cross-sectional view of a semiconductor device 104 according to Embodiment 4 taken along the line A-A' of FIG. The semiconductor device 104 is different from the semiconductor device 101 according to Embodiment 1 only in that a p-type collector layer 8 is provided on the second main surface S2 side of the n-type buffer layer 7 in the termination region 32, and a collector-side interlayer film 15 is provided between the p-type collector layer 8 and the collector electrode 13.

[0036] <D-2. Operation> The p-type collector layer 8 in the terminal region 32 is insulated from the collector electrode 13 by the collector-side interlayer film 15. Therefore, when the IGBT is on, hole injection from the p-type collector layer 8 in the terminal region 32 is suppressed. As a result, since the hole injection efficiency in the terminal region 32 decreases, the carriers in the terminal region 32 can be reduced.

[0037] Thus, according to the semiconductor device in this embodiment, the carriers in the terminal region 32 can be reduced without providing a back gate structure in the terminal region 32. Therefore, even if a problem occurs in the back gate operation, a decrease in the breakdown voltage can be avoided.

[0038] <E. Embodiment 5> <E-1. Structure> FIG. 6 is a cross-sectional view of a semiconductor device 105 according to Embodiment 5 taken along the line A-A' of FIG. 1. The semiconductor device 105 is different from the semiconductor device 104 according to Embodiment 4 only in that a collector-side interlayer film 15 is provided between the p-type collector layer 8 and the collector electrode 13 in the terminal region 32 and the element region end portion 31A.

[0039] <E-2. Operation> The p-type collector layers 8 in the terminal region 32 and the element region end portion 31A are insulated from the collector electrode 13 by the collector-side interlayer film 15. Therefore, when the IGBT is on, hole injection from the p-type collector layers 8 in the terminal region 32 and the element region end portion 31A is suppressed. As a result, since the hole injection efficiency in the terminal region 32 decreases, the carriers in the terminal region 32 can be reduced.

[0040] Thus, according to the semiconductor device in this embodiment, the carriers in the terminal region 32 can be reduced without providing a back gate structure in the terminal region 32 and the element region end portion 31A. Therefore, even if a problem occurs in the back gate operation, a decrease in the breakdown voltage can be avoided.

[0041] <F. Embodiment 6> <F-1. Structure> FIG. 7 is a cross-sectional view of a semiconductor device 106 according to Embodiment 6 taken along line A-A' of FIG. 1. The semiconductor device 106 differs from the semiconductor device 104 according to Embodiment 4 only in that an n-type collector layer 9 is provided between the p-type collector layer 8 and the collector electrode 13 in the terminal region 32 instead of the collector-side interlayer film 15.

[0042] <F - 2. Operation> In the terminal region 32, since the n-type collector layer 9 is provided between the p-type collector layer 8 and the collector electrode 13, the p-type collector layer 8 is not in contact with the collector electrode 13. Therefore, when the IGBT is on, hole injection from the p-type collector layer 8 in the terminal region 32 is suppressed. Thus, since the hole injection efficiency in the terminal region 32 decreases, the carriers in the terminal region 32 can be reduced.

[0043] As described above, according to the semiconductor device in this embodiment, the carriers in the terminal region 32 can be reduced without a back gate. Therefore, even if a problem occurs in the back gate operation, a decrease in the breakdown voltage can be avoided.

[0044] <G. Embodiment 7> <G - 1. Configuration> FIG. 8 is a cross-sectional view of a semiconductor device 107 according to Embodiment 7 taken along line A-A' of FIG. 1. The semiconductor device 107 differs from the semiconductor device 106 according to Embodiment 6 only in that an n-type collector layer 9 is provided between the p-type collector layer 8 and the collector electrode 13 in the terminal region 32 and the element region end portion 31A.

[0045] <G - 2. Operation> In the terminal region 32 and the element region end portion 31A, since the n-type collector layer 9 is provided between the p-type collector layer 8 and the collector electrode 13, the p-type collector layer 8 is not in contact with the collector electrode 13. Therefore, when the IGBT is on, hole injection from the p-type collector layer 8 in the terminal region 32 and the element region end portion 31A is suppressed. Thus, since the hole injection efficiency in the terminal region 32 decreases, the carriers in the terminal region 32 can be reduced.

[0046] In this way, the semiconductor device of this embodiment can reduce carriers in termination region 32 without a back gate, and therefore can avoid a decrease in breakdown resistance even if a problem occurs in the back gate operation.

[0047] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims. [Explanation of symbols]

[0048] 1 n-type source layer, 2 p-type base layer, 3 emitter-side oxide film, 4 emitter-side gate electrode, 5 p-type contact layer, 6 n-type drift layer, 7 n-type buffer layer, 8 p-type collector layer, 9 n-type collector layer, 10 collector-side oxide film, 11 collector-side gate electrode, 12 emitter electrode, 13 collector electrode, 14 emitter-side interlayer film, 15 collector-side interlayer film, 16 p-type well layer, 17 n-type channel stopper layer, 18 passivation film, 19 field plate, 20 emitter-side gate liner, 21 collector-side gate liner, 22 emitter-side n-type layer, 31 element region, 31A element region edge, 32 termination region, 33 emitter-side gate pad region, 34 collector-side gate pad region, 51 emitter-side MOS channel portion, 52 collector-side MOS channel portion, 60 semiconductor substrate, 101-107 Semiconductor device, S1 first main surface, S2 second main surface, T1, T2 trenches.

Claims

1. In plan view, the semiconductor device is divided into an element region through which a main current flows and a termination region surrounding the element region, a semiconductor substrate having a drift layer of a first conductivity type; an emitter electrode provided on the front surface side of the semiconductor substrate; a collector electrode provided on the back surface side of the semiconductor substrate; a surface gate electrode provided in the element region on the surface side of the semiconductor substrate; a back surface gate electrode provided in the element region on the back surface side of the semiconductor substrate; a buffer layer of a first conductivity type provided on a rear surface side of the drift layer; a collector layer of a second conductivity type provided between the buffer layer and the collector electrode in the element region, the second conductivity type collector layer is not provided between the collector electrode and the buffer layer in the termination region, or is provided between the collector electrode and the buffer layer in the termination region such that a total amount of second conductivity type impurities per unit area of ​​the second conductivity type collector layer in the termination region is smaller than a total amount of second conductivity type impurities per unit area of ​​the second conductivity type collector layer in the element region. Semiconductor device.

2. the second conductivity type collector layer is not provided between the collector electrode and the buffer layer at an end of the element region located in the vicinity of the termination region of the element region, or is provided between the collector electrode and the buffer layer at the end of the element region so that a total amount of second conductivity type impurities per unit area of ​​the second conductivity type collector layer at the end of the element region is smaller than a total amount of second conductivity type impurities per unit area of ​​the second conductivity type collector layer in other parts of the element region. The semiconductor device according to claim 1 .

3. the second conductivity type collector layer is not provided at the edge of the element region, a collector layer of a first conductivity type is provided between the collector electrode and the buffer layer at an end of the element region; The semiconductor device according to claim 2 .

4. In plan view, the semiconductor device is divided into an element region through which a main current flows and a termination region surrounding the element region, a semiconductor substrate having a drift layer of a first conductivity type; an emitter electrode provided on the front surface side of the semiconductor substrate; a collector electrode provided on the back surface side of the semiconductor substrate; a surface gate electrode provided in the element region on the surface side of the semiconductor substrate; a back surface gate electrode provided in the element region on the back surface side of the semiconductor substrate; a buffer layer of a first conductivity type provided on a back surface side of the semiconductor substrate; a collector layer of a second conductivity type provided between the buffer layer and the collector electrode in the element region and the termination region; a collector-side interlayer film provided between the collector layer of the second conductivity type and the collector electrode in the termination region; Semiconductor device.

5. the collector-side interlayer film is provided between the collector layer of the second conductivity type and the collector electrode in the termination region and in an end portion of the element region located near the termination region, The semiconductor device according to claim 4 .

6. In plan view, the semiconductor device is divided into an element region through which a main current flows and a termination region surrounding the element region, a semiconductor substrate having a drift layer of a first conductivity type; an emitter electrode provided on the front surface side of the semiconductor substrate; a collector electrode provided on the back surface side of the semiconductor substrate; a surface gate electrode provided in the element region on the surface side of the semiconductor substrate; a back surface gate electrode provided in the element region on the back surface side of the semiconductor substrate; a buffer layer of a first conductivity type provided on a back surface side of the semiconductor substrate; a collector layer of a second conductivity type provided between the buffer layer and the collector electrode in the element region and the termination region; a collector layer of a first conductivity type provided between the collector layer of the second conductivity type and the collector electrode in the termination region; Semiconductor device.

7. the collector layer of the first conductivity type is provided between the collector layer of the second conductivity type and the collector electrode in the termination region and in an end portion of the element region that is located near the termination region; The semiconductor device according to claim 6.

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