Oscillator

Abstract

To stabilize the characteristics of an oscillator and to reduce the cost.SOLUTION: An oscillator (2000B) includes a reference current generation circuit (2200) that generates a reference current (Iref), a current setting circuit (2600) that generates a specific voltage (V1) corresponding to the reference current using a first resistor (2601) and generates a specific current (I2) corresponding to the specific voltage using an operational amplifier (2603) and a second resistor (2602), and an oscillation circuit (2300) that causes a plurality of stages of signal delay circuits connected in a loop shape to perform an oscillation operation. The oscillation circuit generates an output rectangular wave signal having a frequency corresponding to a change speed of a voltage (Vc) between both terminals of the capacitor when the capacitor (2311) is charged with a charging constant current (Icc) corresponding to the specific current. At least one of the first resistor and the second resistor is formed of a variable resistor.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present disclosure relates to oscillators. [Background technology]

[0002] A rectangular wave signal can be obtained by an oscillation operation using a so-called ring oscillator structure (see Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-88885

[0004] [overview] It is important to stabilize the characteristics of the square wave signal obtained by the oscillation operation or to reduce the cost of the oscillator.

[0005] According to one embodiment of the present disclosure, there is provided an oscillator comprising: a reference current generating circuit configured to generate a reference current; a current setting circuit having a first resistor, a second resistor, and an operational amplifier, configured to generate a specific voltage corresponding to the reference current using the first resistor and to generate a specific current corresponding to the specific voltage using the operational amplifier and the second resistor; and an oscillation circuit having multiple signal delay circuits connected in a loop, configured to generate an output rectangular wave signal by causing the multiple signal delay circuits to oscillate. The oscillation circuit has a capacitor that is charged with a constant charging current corresponding to the specific current, and generates the output rectangular wave signal having a frequency corresponding to the rate of change of the voltage between both terminals of the capacitor when the capacitor is charged. At least one of the first resistor and the second resistor is formed by a variable resistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2]FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a schematic configuration diagram of an oscillator circuit according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a schematic waveform diagram of input and output signals of an oscillator circuit according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a circuit diagram of an oscillator according to a first reference example. [Figure 13] FIG. 13 is a circuit diagram of an oscillator according to the second embodiment. [Figure 14] FIG. 14 is a circuit diagram of an oscillator according to a first example of an embodiment of the present disclosure. [Figure 15] FIG. 15 is a waveform diagram of an output signal of an oscillation circuit and an output signal of an oscillator according to a first example of an embodiment of the present disclosure. [Figure 16] FIG. 16 is a timing chart relating to charging of a capacitor in an oscillation circuit according to a first example of an embodiment of the present disclosure. [Figure 17] FIG. 17 is a timing chart of an oscillator circuit according to a first example of an embodiment of the present disclosure. [Figure 18]FIG. 18 is a configuration diagram of an electronic device according to a fourth example of an embodiment of the present disclosure.

[0007] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0008] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0009] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0010] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0011] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0012] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0013] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0014] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0015] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0016] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0017] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0018] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0019] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0020] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0021] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0022] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0023] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0024] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0025] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0026] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0027] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0028] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0029] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0030] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0031] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0032] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0033] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0034] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0035] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0036] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0037] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0038] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0039] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0040] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0041] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0042] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0043] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0044] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0045] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0046] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0047] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0048] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0049] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0050] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0051] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0052] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0053] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0054] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0055] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0056] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0057] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0058] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0059] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0060] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0061] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0062] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0063] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0064] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0065] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0066] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0067] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0068] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0069] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0070] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0071] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0072] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0073] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0074] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0075] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0076] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0077] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0078] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0079] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0080] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0081] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0082] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0083] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0084] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0085] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0086] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0087] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0088] Referring to FIG. 7, it is preferable that the distance D1 between the low potential terminal 11 and the high potential terminal 12 exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation breakdown voltage to be achieved.

[0089] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0090] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration with respect to the high potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high potential coil 23.

[0091] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0092] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0093] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0094] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0095] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0096] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0097] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0098] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0099] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0100] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0101] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0102] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0103] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0104] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0105] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0106] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0107] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0108] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0109] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0110] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0111] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0112] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0113] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0114] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0115] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0116] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0117] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0118] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0119] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0120] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0121] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0122] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0123] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0124] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0125] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0126] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0127] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0128] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0129] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0130] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0131] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0132] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0133] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0134] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0135] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0136] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0137] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0138] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0139] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0140] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0141] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0142] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0143] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0144] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0145] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminal of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0146] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0147] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0148] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0149] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0150] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0151] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0152] <Oscillator> Next, the configuration of the oscillator according to this embodiment will be described. In describing the oscillator, some terminology will be explained. Ground refers to a reference conductor having an electric potential of 0V (zero volts) as a reference, or refers to the 0V potential itself. The reference conductor may be formed using a conductor such as metal. The 0V potential is sometimes referred to as ground potential. In the following description, voltages indicated without a particular reference represent potentials seen from ground.

[0153] A level refers to a level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal of interest, when the signal is at a high level, the inverted signal of that signal is at a low level, and when the signal is at a low level, the inverted signal of that signal is at a high level. For any signal or voltage of interest, a transition from a low level to a high level is sometimes referred to as a rising edge, and a transition from a high level to a low level is sometimes referred to as a falling edge.

[0154] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Additionally, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0155] The electrical characteristics of a MOSFET include the gate threshold voltage. For any transistor that is an N-channel enhancement MOSFET, when the gate potential of the transistor is higher than the source potential of the transistor and the magnitude of the gate-source voltage of the transistor (the gate potential as seen from the source potential) is equal to or greater than the gate threshold voltage of the transistor, the transistor is in an on state; otherwise, the transistor is in an off state. The same is true for P-channel MOSFETs. For any FET, the gate threshold voltage is defined as the gate-source voltage required to pass a predetermined amount of drain current when a predetermined voltage is applied between the drain and source of the FET under a predetermined ambient temperature environment.

[0156] Hereinafter, the on and off states of any transistor may be simply referred to as on and off. For any transistor, switching from the off state to the on state is referred to as turning on, and switching from the on state to the off state is referred to as turning off. Furthermore, for any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period.

[0157] For any signal that takes a high or low signal level, the period during which the signal level is high is called a high level period, and the period during which the signal level is low is called a low level period.

[0158] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified. In this specification, for the sake of simplicity of description, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element or component, etc., the name of the information, signal, physical quantity, functional part, circuit, element or component, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, the output signal referred to by "Sout" described later (see FIG. 10) may be denoted as the output signal Sout or may be abbreviated as the signal Sout, but they all refer to the same thing.

[0159] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0160] FIG. 10 shows the basic configuration of an oscillation circuit 1000 provided in an oscillator. A power supply voltage VACC is input to the oscillation circuit 1000 with respect to the ground as a reference. The power supply voltage VACC has a predetermined positive DC voltage value. The oscillation circuit 1000 is driven based on the power supply voltage VACC with the ground potential as a reference.

[0161] The oscillation circuit 1000 has a so-called ring oscillator structure and has a plurality of stages of signal delay circuits D[1] to D[N] connected in a loop. N is an arbitrary integer of 3 or more. The input signal to the oscillation circuit 1000 is represented by the symbol "Sin", and the output signal from the oscillation circuit 1000 is represented by the symbol "Sout". The input signal Sin and the output signal Sout are rectangular wave signals and have signal levels of high level or low level. In each of the input signal Sin and the output signal Sout, the high level has a potential substantially equal to the power supply voltage VACC, and the low level has a potential substantially equal to the ground potential. The output signal Sout corresponds to the output rectangular wave signal to be derived by the oscillation circuit 1000.

[0162] Each of the signal delay circuits D[1] to D[N] generates an output signal according to the input signal to it. The signal output from the signal delay circuit D[i] is represented by the symbol "S[i]", where i represents an arbitrary integer. The signal delay circuit D[i+1] is arranged after the signal delay circuit D[i], and the output signal S[i] of the signal delay circuit D[i] is input to the signal delay circuit D[i+1] (where i is an integer satisfying "1≦i≦N-1"). Therefore, the signal S[i] is the input signal to the signal delay circuit D[i+1], and the signal delay circuit D[i+1] generates and outputs the output signal S[i+1] according to the input signal S[i] to it.

[0163] Of the signal delay circuits D[1] to D[N], signal delay circuit D[1] is the first-stage signal delay circuit, and signal delay circuit D[N] is the final-stage signal delay circuit. The input signal Sin to the oscillation circuit 1000 is input to the signal delay circuit D[1] as the input signal S[0]. The signal delay circuit D[N] outputs the output signal S[N] as the output signal Sout of the oscillation circuit 1000. The output signal Sout of the oscillation circuit 1000 is fed back and input to the signal delay circuit D[1] as the input signal Sin to the oscillation circuit 1000 (and therefore as the input signal S[0] to the signal delay circuit D[1]).

[0164] When an input signal Sin is supplied to the signal delay circuit D[1], an output signal Sout corresponding to the input signal Sin is output from the signal delay circuit D[N] after a delay time according to the response characteristics of the oscillation circuit 1000. Here, the output signal Sout is a logical negation signal of the input signal Sin. Therefore, since the oscillation circuit 1000 has a negative gain overall, an oscillation operation is performed in the oscillation circuit 1000 (in the signal delay circuits D[1] to D[N]), and as a result, a rectangular wave signal is output as the output signal Sout.

[0165] Figure 11 shows the waveforms of the input signal Sin and the output signal Sout. As time progresses, times T1, T2, T3, and T4 occur in this order. Suppose a rising edge occurs in the input signal Sin at time T1. When a rising edge occurs in the input signal Sin at time T1, a falling edge occurs in the output signal Sout at time T2, a delay time td1 after time T1. The falling edge of the output signal Sout at time T2 triggers a falling edge in the input signal Sin at time T3. Note that the difference between times T2 and T3 is the delay time until the output signal Sout is fed back as the input signal Sin, and is extremely small. When a falling edge occurs in the input signal Sin at time T3, a rising edge occurs in the output signal Sout at time T4, a delay time td2 after time T3.

[0166] In this way, when the input signal Sin is at a high level, the output signal Sout becomes a low-level signal, which is the logical inversion signal of the input signal Sin. However, when the input signal Sin switches from a low level to a high level, the output signal Sout switches from a high level to a low level after a delay time td1 has elapsed. Conversely, when the input signal Sin is at a low level, the output signal Sout becomes a high-level signal, which is the logical inversion signal of the input signal Sin. However, when the input signal Sin switches from a high level to a low level, the output signal Sout switches from a low level to a high level after a delay time td2 has elapsed.

[0167] The delay times td1 and td2 are determined depending on the internal configuration of the oscillator circuit 1000. Although the delay times td1 and td2 are shown in Fig. 11 as if they were approximately equal in length, the delay times td1 and td2 may actually be different in length.

[0168] The signal delay circuits D[1] to D[N] may each be an inverter circuit (in other words, a NOT circuit), where N is any odd number equal to or greater than 3.

[0169] <<First reference example>> FIG. 12 shows a circuit diagram of an oscillator 9000 according to a first reference example. The oscillator 9000 has multiple inverter circuits connected in a loop, and uses resistors and capacitors to set a delay time and obtain a rectangular wave signal of a desired frequency. While a detailed description of the internal configuration of the oscillator 9000 is omitted, in the circuit configuration of FIG. 12, the delay time generated within the oscillator 9000 varies with fluctuations in the power supply voltage and also with temperature. This means that the frequency of the output rectangular wave signal obtained by the oscillator 9000 varies with fluctuations in the power supply voltage or temperature. Furthermore, variations in the characteristics of elements that occur during manufacturing can cause the obtained frequency to deviate from the desired frequency.

[0170] <<Second reference example>> 13 shows a circuit diagram of an oscillator 2000A according to a second reference example. The oscillator 2000A includes a start-up circuit 2100, a reference current generating circuit 2200, an oscillation circuit 2300, a waveform shaping circuit 2400, an enable circuit 2500, and a current setting circuit 2600ref.

[0171] The reference current generating circuit 2200 generates a reference current Iref using a reference resistor 2205. The current setting circuit 2600ref is provided with resistors 2681 and 2682 formed as variable resistors, a transistor 2683 which is a PNP bipolar transistor, and a transistor 2684 which is an NPN bipolar transistor. In the oscillator 2000A, a current Ia proportional to the reference current Iref is converted into a voltage Va using the resistor 2681 and the transistor 2683. The voltage Va is further converted into a current Ib using the resistor 2682 and the transistor 2684. A capacitor 2311 is provided in the first-stage signal delay circuit in the oscillation circuit 2300, and is configured to be able to charge the capacitor 2311 with a constant charging current proportional to the current Ib. In oscillator 2000A, output signal Sout has a frequency according to the rate of change of the voltage between both terminals of capacitor 2311 when capacitor 2311 is charged with a constant charging current (hence, has a frequency proportional to current Ib).

[0172] In this way, by adopting a configuration in which capacitor 2311 is charged using a constant current, the rate of change in the voltage across capacitor 2311 is less susceptible to fluctuations in power supply voltage VACC. Therefore, the frequency of output signal Sout is less susceptible to fluctuations in power supply voltage VACC. On the other hand, there is concern about changes in the characteristics of capacitor 2311 due to temperature changes. However, because reference current Iref is generated according to reference resistor 2205, it is possible to offset the changes in the characteristics of capacitor 2311 due to temperature changes and the changes in the characteristics of reference resistor 2205 due to temperature changes. Alternatively, the changes in the characteristics of capacitor 2311 due to temperature changes can be offset by the changes in the characteristics of resistors 2681 and 2682 due to temperature changes. In other words, it is possible to offset the effects of changes in the characteristics of capacitor 2311 on the frequency of output signal Sout and the effects of changes in the characteristics of resistors (2205, 2681, and 2682) on the frequency of output signal Sout. This makes it possible to suppress the effects of temperature changes on the frequency of output signal Sout. In addition, the influence of variations in the characteristics of the elements can be reduced by adjusting the values ​​of resistors 2681 and 2682.

[0173] However, because the oscillator 2000A includes a bipolar transistor, a dedicated process for forming the bipolar transistor is required in the manufacture of a semiconductor device including the oscillator 2000A, which increases the manufacturing costs of the oscillator and the semiconductor device including the oscillator.

[0174] <<First Example>> An oscillator 2000B according to a first embodiment that takes these circumstances into consideration will be described below. Fig. 14 is a circuit diagram of the oscillator 2000B according to the first embodiment. The oscillator 2000B includes a start-up circuit 2100, a reference current generating circuit 2200, an oscillation circuit 2300, a waveform shaping circuit 2400, an enable circuit 2500, and a current setting circuit 2600.

[0175] The start-up circuit 2100 includes transistors 2101 to 2103. The reference current generating circuit 2200 includes transistors 2201 to 2204 and a reference resistor 2205. The oscillation circuit 2300 includes a capacitor 2311 and transistors 2312, 2313, 2321, 2322, 2331, and 2332. The waveform shaping circuit 2400 includes a flip-flop 2401 and an inverter circuit 2402. The enable circuit 2500 includes an AND circuit 2501. The current setting circuit 2600 includes resistors 2601 and 2602, an operational amplifier 2603, and transistors 2604, 2605, and 2606. The transistors 2101, 2201, 2202, 2313, 2321, 2331, 2605, and 2606 are P-channel MOSFETs. The transistors 2102, 2103, 2203, 2204, 2312, 2322, 2332, and 2604 are N-channel MOSFETs. The operational amplifier 2603 is formed with a plurality of transistors, and all the transistors in the operational amplifier 2603 are configured with MOSFETs.

[0176] The oscillator circuit 2300 is an example of the oscillator circuit 1000 in FIG. 10 , and in the oscillator circuit 2300, “N=3.” The oscillator circuit 2300 has a signal delay circuit 2310 as the signal delay circuit D[1], a signal delay circuit 2320 as the signal delay circuit D[2], and a signal delay circuit 2330 as the signal delay circuit D[3]. The signal delay circuit 2310 is configured with a capacitor 2311 and transistors 2312 and 2313. The signal delay circuit 2320 is configured with transistors 2321 and 2322. The signal delay circuit 2330 is configured with transistors 2331 and 2332.

[0177] First, the connections of the elements in oscillator 2000 will be described. The above-mentioned power supply voltage VACC is applied to power supply wiring WR1. The sources of transistors 2101, 2201, 2202, 2313, 2321, 2331, 2605, and 2606 are connected to power supply wiring WR1 and receive the power supply voltage VACC. The sources of transistors 2102, 2204, 2312, 2322, and 2332 are connected to ground and therefore have ground potential. The gate of transistor 2101 is connected to ground. The drain of transistor 2101, the drain and gate of transistor 2102, and the gate of transistor 2103 are connected to each other. The gate and drain of transistor 2201 are connected to the gates of transistors 2202 and 2605, and the drains of transistors 2201, 2103, and 2203 are connected to each other. The source of the transistor 2103, the source of the transistor 2203, the gate of the transistor 2204, and a first terminal of the reference resistor 2205 are connected to each other. The second terminal of the reference resistor 2205 is connected to ground. The gate of the transistor 2203 is connected to the drains of the transistors 2202 and 2204.

[0178] The source of transistor 2605 is connected to the non-inverting input terminal of operational amplifier 2603 and the first terminal of resistor 2601 at node 2607. The second terminal of resistor 2601 is connected to ground. The voltage at node 2607 is referred to as voltage V1. The inverting input terminal of operational amplifier 2603 is connected to the source of transistor 2604 and the first terminal of resistor 2602 at node 2608. The second terminal of resistor 2602 is connected to ground. The output terminal of operational amplifier 2603 is connected to the gate of transistor 2604. The drain of transistor 2604, the drain and gate of transistor 2606, and the gates of transistors 2313 and 2321 are connected to each other.

[0179] The first end of capacitor 2311, the drain of transistor 2312, the drain of transistor 2313, and the gate of transistor 2322 are commonly connected at node 2314. The signal at node 2314 is represented by the symbol "Smid1". The second end of capacitor 2311 is connected to ground. Therefore, capacitor 2311 and transistor 2312 are connected in parallel. The drains of transistors 2321 and 2322 are commonly connected at node 2323. The signal at node 2323 is represented by the symbol "Smid2". The gates of transistors 2331 and 2332 are also connected to node 2323. The drains of transistors 2331 and 2332 are commonly connected at node 2333. The signal at node 2333 is the output signal Sout of oscillator circuit 2300. In the first embodiment, signal Sout refers to the signal at node 2333.

[0180] The flip-flop 2401 is a D-type flip-flop, and will be hereinafter referred to as DFF2401. DFF2401 has a D input terminal, a Q output terminal, a clock input terminal, and an R input terminal. The clock input terminal of DFF2401 is connected to the node 2333 and therefore receives the output signal Sout from the oscillator circuit 2300. The output signal of DFF2401 is output from the Q output terminal of DFF2401. The output signal of DFF2401 is the output signal of the waveform shaping circuit 2400. The output signal of the waveform shaping circuit 2400 is represented by the symbol "OSC_OUT". The Q output terminal of DFF2401 is connected to the terminal TM2 and therefore the signal OSC_OUT is applied to the terminal TM2. The signal OSC_OUT corresponds to the output signal of the oscillator 2000. The input terminal of the inverter circuit 2402 is connected to the Q output terminal of DFF2401. The output terminal of the inverter circuit 2402 is connected to the D input terminal of DFF2401.

[0181] An enable signal Sen is supplied to terminal TM1 from a circuit (not shown) provided outside the oscillator 2000. The R input terminal of DFF2401 serves as the reset input terminal of DFF2401, which operates on negative logic. The R input terminal of DFF2401 is connected to terminal TM1 and receives the enable signal Sen.

[0182] The AND circuit 2501 is a two-input logical product circuit and has first and second input terminals and an output terminal. The first input terminal of the AND circuit 2501 is connected to the terminal TM1 and receives the enable signal Sen. The second input terminal of the AND circuit 2501 is connected to the node 2333 and receives the signal Sout. An output signal of the AND circuit 2501 is output from the output terminal of the AND circuit 2501. The output signal of the AND circuit 2501 is the output signal of the enable circuit 2500 and is the logical product signal of the signals Sen and Sout. The output signal of the AND circuit 2501 is fed back to the signal delay circuit 2310 as the input signal Sin to the oscillation circuit 2300. More specifically, the output terminal of the AND circuit 2501 is connected to the gate of the transistor 2312, and therefore, in the first embodiment, the input signal Sin is applied to the gate of the transistor 2312.

[0183] Next, the operation of the startup circuit 2100 will be described. A state in which the driving power to the oscillator 2000 is cut off is called a power-off state. In the power-off state, the voltage of the power supply wiring WR1 is 0V, and each circuit in the oscillator 2000 is stopped operating. Starting from the power-off state, when the supply of driving power to the oscillator 2000 starts, the voltage value of the power supply wiring WR1 increases from 0V to a predetermined voltage value V DDuring this rising process, a drain current starts to flow in the transistor 2101, and the drain current of the transistor 2101 flows through the channel of the transistor 2102. The transistors 2102 and 2103 form a current mirror circuit. This current mirror circuit acts so that a current proportional to the drain current of the transistor 2102 flows from the drain to the source of the transistor 2103, so that the gate potentials of the transistors 2201 and 2202 become lower than the potential of the power supply wiring WR1. As a result, a drain current starts to flow in the transistors 2201 and 2202. After the drain current starts to flow in the transistors 2201 and 2202, when the voltage value of the power supply wiring WR1 reaches a predetermined voltage value V D When the reference current generating circuit 2200 has a predetermined voltage value V D is the positive voltage value that the power supply voltage VACC should ultimately have when the oscillator 2000 is in an operating state after the power supply is shut off.

[0184] In the following, unless otherwise specified, the power supply voltage VACC is the voltage value V D and the reference current generating circuit 2200 is in a balanced state. D is a DC voltage value, which may vary from the target voltage value due to manufacturing variations or temperature changes.

[0185] The operation of the reference current generating circuit 2200 will now be described. The drain current of the transistor 2201 when the reference current generating circuit 2200 is in an equilibrium state is referred to as the reference current Iref. The reference current Iref is a constant current having a constant value independent of the value of the power supply voltage VACC. In the configuration of the start-up circuit 2100 shown in FIG. 14, a current flows through the channel of the transistor 2103 not only when the oscillator 2000 is started but also after the reference current generating circuit 2200 has reached an equilibrium state. However, the drain current of the transistor 2103 is determined by the characteristics of the transistor 2101 functioning as a resistor and the current ratio of the current mirror circuit consisting of the transistors 2102 and 2103. When the reference current generating circuit 2200 is in an equilibrium state, the reference current Iref is sufficiently larger than the drain current of the transistor 2103. Therefore, when the reference current generating circuit 2200 is in an equilibrium state, the reference current Iref can be considered to flow entirely between the drain and source of the transistor 2203.

[0186] The resistance value of the reference resistor 2205 is represented by the symbol "R," and the gate threshold voltage of the transistor 2204 is represented by the symbol "Vth1." Then, the following equation (A1) is established. Iref=Vth1 / R (A1)

[0187] The reason why equation (A1) holds will now be explained. The voltage drop occurring across the reference resistor 2205 is applied between the gate and source of the transistor 2204. When the reference current generating circuit 2200 is in a balanced state, the voltage drop occurring across the reference resistor 2205 matches the gate threshold voltage Vth1.

[0188] When the reference current Iref becomes higher than the current (Vth1 / R), the voltage drop across the reference resistor 2205 becomes higher than the gate threshold voltage Vth1 of the transistor 2204, and the gate-source voltage of the transistor 2203 decreases through a decrease in the on-resistance of the transistor 2204 and an increase in the source potential of the transistor 2203, thereby decreasing the drain current of the transistor 2203 (thus decreasing the reference current Iref).

[0189] Conversely, when the reference current Iref becomes lower than the current (Vth1 / R), the voltage drop across the reference resistor 2205 becomes lower than the gate threshold voltage Vth1 of the transistor 2204, and the drain current of the transistor 2203 increases through an increase in the gate potential of the transistor 2203 (thus increasing the reference current Iref).

[0190] In this way, balance is achieved in an equilibrium state where the voltage drop occurring across the reference resistor 2205 coincides with the gate threshold voltage Vth1 of the transistor 2204. The voltage drop occurring across the reference resistor 2205 is a voltage (Iref × R), and in an equilibrium state, the voltage (Iref × R) coincides with the gate threshold voltage Vth1, so equation (A1) holds. Note that, because a current mirror circuit is formed by the transistors 2201 and 2202, a current proportional to the reference current Iref flows between the drain and source of the transistor 2202.

[0191] Current I2, which depends on the operation of oscillator circuit 2300, is generated by current setting circuit 2600. However, the operation of oscillator circuit 2300 will be explained before explaining the operation of current setting circuit 2600. The current mirror circuit formed by transistors 2606 and 2313 operates to generate a current proportional to current I2 as the drain current of transistor 2313. The drain current of transistor 2313 is referred to by the symbol "Icc." Because the drain current Icc of transistor 2313 is a constant current, it may also be referred to as the constant current Icc. The constant current Icc is a constant charging current used to charge capacitor 2311. Transistor 2313, in cooperation with transistor 2206, constitutes a charging current source that supplies constant current Icc to the parallel circuit of capacitor 2311 and transistor 2312.

[0192] The voltage across capacitor 2311 is represented by the symbol "Vc" and will be referred to as voltage Vc where appropriate. Signal Smid1 has voltage Vc. Voltage Vc is applied to node 2314 and the gate of transistor 2322. Voltage Vc is equal to the gate-source voltage of transistor 2322. During the on-period of transistor 2312, node 2314 is shorted to ground through the channel of transistor 2312, so voltage Vc is substantially equal to 0 V (hereinafter considered to be 0 V). During the off-period of transistor 2312, capacitor 2311 is charged by constant current Icc, so voltage Vc rises monotonically over time.

[0193] The current mirror circuit formed by transistors 2206 and 2321 operates to generate a current proportional to current I2 as the drain current of transistor 2321. Transistor 2321 cooperates with transistor 2206 to supply a constant current (i.e., the drain current of transistor 2321) from power supply line WR1 to node 2323. However, when the potential of node 2323 rises to the potential of power supply line WR1, the drain current of transistor 2321 becomes zero.

[0194] The transistor 2322 receives the voltage Vc between its gate and source, and forms a common-source amplifier together with a load connected to the drain of the transistor 2322. The load here is an active load, and is a current source formed by the transistor 2321. However, the load connected to the drain of the transistor 2322 may be a load formed by a passive element (resistor) connected between the power supply line WR1 and the drain of the transistor 2322.

[0195] The gate threshold voltage of transistor 2322 is represented by the symbol "Vth2." When voltage Vc is lower than gate threshold voltage Vth2 of transistor 2322, transistor 2322 is in an off state. When transistor 2322 is in an off state, the voltage of node 2323 is substantially equal to power supply voltage VACC (hereinafter, considered to be equal to power supply voltage VACC) if the transient response period is ignored. When the voltage of node 2323 is equal to power supply voltage VACC, transistor 2331 is in an off state and transistor 2332 is in an on state, so that the voltage of node 2333 is substantially equal to 0 V (hereinafter, considered to be equal to 0 V) ​​if the transient response period is ignored.

[0196] When the voltage Vc is equal to or higher than the gate threshold voltage Vth2 of the transistor 2322, the transistor 2322 is in an on state. When the transistor 2322 is in an on state, the voltage of the node 2323 is substantially equal to 0 V (hereinafter, considered to be 0 V) ​​if the transient response period is ignored. When the voltage of the node 2323 is equal to 0 V, the transistor 2331 is in an on state and the transistor 2332 is in an off state, so that the voltage of the node 2333 is substantially equal to the power supply voltage VACC (hereinafter, considered to be equal to the power supply voltage VACC) if the transient response period is ignored.

[0197] The operation of the waveform shaping circuit 2400 will now be described. The power supply voltage VACC is also supplied to DFF2401, the inverter circuit 2402, and the AND circuit 2501, and they are driven based on the power supply voltage VACC. The signal Sout at the node 2333 has a low or high signal level. The input signal and output signal of DFF2401 also have a high or low level. As with the signal Sout, the high level of the input signal and output signal of DFF2401 has substantially the potential of the power supply voltage VACC, and the low level has substantially the ground potential. The same applies to the inverter circuit 2402 and the AND circuit 2501.

[0198] The input signal to the R input terminal (reset input terminal) of DFF2401 is the enable signal Sen. The enable signal Sen is a binary signal that has a high or low signal level. Assuming that the enable signal Sen is high, DFF2401 captures and holds the level of the signal input to its D input terminal in synchronization with the rising edge of the signal Sout. Assuming that the enable signal Sen is high, DFF2401 outputs a signal having the held level from its Q output terminal. When the enable signal Sen is low, DFF2401 fixes the output signal from its Q output terminal at a low level. The output signal from the Q output terminal of DFF2401 is the signal OSC_OUT. The inverter circuit 2402 outputs an inverted signal of the output signal from the Q output terminal of DFF2401. Therefore, if the output signal from the Q output terminal of DFF2401 is at a high level, a low-level signal is output from the inverter circuit 2402, and if the output signal from the Q output terminal of DFF2401 is at a low level, a high-level signal is output from the inverter circuit 2402. The output signal of the inverter circuit 2402 is input to the D input terminal of DFF2401.

[0199] For this reason, assuming that the enable signal Sen is at a high level, the waveform shaping circuit 2400 inverts the level of the signal OSC_OUT between a high level and a low level each time a rising edge occurs in the signal Sout, as shown in FIG. 15 . As will be understood from the following explanation, the duty of the signal Sout is much smaller than 50%. The waveform shaping circuit 2400 shapes the waveform of the signal Sout and outputs the shaped signal OSC_OUT. The duty of the signal OSC_OUT is 50%. Furthermore, the frequency of the signal OSC_OUT is half the frequency of the signal Sout. Therefore, the waveform shaping circuit 2400 also functions as a frequency divider, and the waveform shaping in the waveform shaping circuit 2400 also has a frequency division effect. Note that, for any binary signal that takes a high or low signal level, the duty refers to the ratio of the high level period to the sum of the low level period and the high level period.

[0200] During a high-level period of the enable signal Sen, the AND circuit 2501 outputs the signal Sout at the node 2333 as the signal Sin to the gate of the transistor 2312. During a low-level period of the enable signal Sen, the AND circuit 2501 fixes the level of the signal Sin at a low level. The low level of the signal Sin has ground potential, and the transistor 2312 is off during the low-level period of the signal Sin. The high level of the signal Sin has the potential of the power supply voltage VACC, and the transistor 2312 is on during the high-level period of the signal Sin.

[0201] During the low-level period of the enable signal Sen, the transistor 2312 is fixed in the off state, and therefore the transistor 2322 is on except during the transient response period, resulting in the signal Sout being fixed at a high level. Furthermore, during the low-level period of the enable signal Sen, the signal OSC_OUT is fixed at a low level. Only during the high-level period of the enable signal Sen, the signal Sin switches between a low level and a high level, and in conjunction with this, the signals Sout and OSC_OUT also switch between a low level and a high level. A high-level enable signal Sen functions as a signal instructing the oscillator circuit 2300 to perform an oscillation operation, and a low-level enable signal Sen functions as a signal instructing the oscillation operation to stop. In the following, unless otherwise specified, it is assumed that the enable signal Sen is fixed at a high level.

[0202] In the first embodiment, the signal Sout at the node 2333 is an output square wave signal output from the oscillation circuit 2300. Then, a transistor 2312 serving as a switching element is turned on and off in synchronization with an input square wave signal (Sin) based on the output square wave signal (Sout).

[0203] Here, as shown in FIG. 16, at time t DELAY Define the time T A1At time T A1 The capacitor 2311 starts to be charged from time T A1 The voltage Vc starts to rise from 0V. Then, at time T A2 At time T A1 and T A2 The time difference between DELAY That is, the time required for the voltage Vc to reach the gate threshold voltage Vth2 after the transistor 2312 is turned off is the time t DELAY is.

[0204] The capacitance value of the capacitor 2311 is represented by the symbol "C." Then, the voltage Vc after a time Δt has elapsed since the transistor 2312 turned off is represented by "Icc×Δt / C." "Δt=t DELAY The voltage Vc at time t DELAY satisfies the following formula (A2). t DELAY = C × Vth2 / Icc (A2)

[0205] 17 shows a timing chart of the oscillator circuit 2300. The falling edge occurs in the signal Sin at time T B1 The operation of the oscillator circuit 2300 will be described starting from time T Bi+1 is time T Bi It is later than

[0206] Time T B1 At time T, a falling edge occurs in the signal Sin, turning off the transistor 2312 and causing the voltage Vc to start rising from 0V. B1 to delay time t DELAY Time T has passed B2 At time TB3 The falling edge of the signal Smid2 causes the transistor 2331 to turn on and the transistor 2332 to turn off at time T B4 A rising edge occurs in the signal Sout at time T B4 At the rising edge of the signal Sout at time T B5 A rising edge also occurs in the signal Sin.

[0207] Time T B5 At time T, a rising edge occurs in signal Sin, turning on transistor 2312, causing voltage Vc to drop sharply to 0 V. As voltage Vc drops to 0 V, transistor 2322 turns off, resulting in a drop at time T B6 The rising edge of the signal Smid2 causes the transistor 2331 to turn off and the transistor 2332 to turn on, at time T B7 A falling edge occurs in the signal Sout at time T B7 The falling edge of the signal Sout at time T B8 A fall edge also occurs in the signal Sin at . Thereafter, the above-described operation triggered by the fall edge of the signal Sin is repeated.

[0208] Each of the signal delay circuits 2310 to 2330 functions as an inverter circuit that outputs an inverted signal of the signal input to the circuit.

[0209] The input and output signals of the signal delay circuit 2310 will be described. The input signal of the signal delay circuit 2310 is the signal Sin, and the output signal of the signal delay circuit 2310 is the signal Smid1. The signal delay circuit 2310 outputs an inverted signal of the input signal Sin to itself. Therefore, when a falling edge occurs in the input signal Sin, the signal delay circuit 2310 raises the potential of its output signal Smid1 from the low level, which is the ground potential. However, in the signal delay circuit 2310, the rate of change in the potential of the output signal Smid1 triggered by the falling edge of the input signal Sin is extremely small compared to other signal delay circuits, and the output signal Smid1 is delayed by a delay time tDELAY The gate threshold voltage Vth2 is increased by applying this.

[0210] When a rising edge occurs in the input signal Sin to the signal delay circuit 2310, the signal delay circuit 2310 sharply reduces the potential of its output signal Smid1 from the current potential to a low level. The signal delay circuit 2310 has the ability to raise the potential of the output signal Smid1 to the level of the power supply voltage VACC as long as the input signal Sin to the signal delay circuit 2310 is maintained at a low level. However, at the time when a rising edge occurs in the input signal Sin (time T B5 Even if the output signal Smid1 has not reached the level of the power supply voltage VACC immediately before the rising edge of the input signal Sin, when a rising edge occurs in the input signal Sin, the potential of the output signal Smid1 is lowered to ground potential in order to output an inverted signal of the input signal Sin. The rate at which the potential of the output signal Smid1 drops when the rising edge of the input signal Sin occurs is sufficiently fast. In FIG. 17, the time from the rising edge of the input signal Sin until the potential of the output signal Vmid1 drops to ground potential is shown as if it were zero.

[0211] The input and output signals of the signal delay circuit 2320 will be described. The input signal to the signal delay circuit 2320 is the signal Smid1, and the output signal of the signal delay circuit 2320 is the signal Smid2. The signal delay circuit 2320 outputs an inverted signal of the input signal Smid1 to itself. In the input signal Smid1 to the signal delay circuit 2320, a potential equal to or greater than the gate threshold voltage Vth2 belongs to the high level, and a potential lower than the gate threshold voltage Vth2 belongs to the low level.

[0212] Therefore, when the signal delay circuit 2320 receives the input signal Smid1 having a potential equal to or higher than the gate threshold voltage Vth2 (i.e., the high-level input signal Smid1), it outputs the low-level signal Smid2, which is the inverted signal of the input signal Smid1. B2 and T B3The time difference between these is the delay time from when a high-level input signal Smid1 is applied to the signal delay circuit 2320 until the output signal Smid2 of the signal delay circuit 2320 switches to a low level. When the signal delay circuit 2320 receives an input signal Smid1 having a potential lower than the gate threshold voltage Vth2 (i.e., a low-level input signal Smid1), it outputs a high-level signal Smid2, which is an inverted signal of the input signal Smid1. At time T B5 and T B6 The time difference between these is the delay time from when the low-level input signal Smid1 is applied to the signal delay circuit 2320 until the output signal Smid2 of the signal delay circuit 2320 switches to high level.

[0213] The input and output signals of the signal delay circuit 2330 will be described. The input signal to the signal delay circuit 2330 is the signal Smid2, and the output signal from the signal delay circuit 2330 is the signal Sout. The signal delay circuit 2330 outputs an inverted signal of the input signal Smid2 to itself. Therefore, when the signal delay circuit 2330 receives a low-level input signal Smid2, it outputs a high-level output signal Sout, and when it receives a high-level input signal Smid2, it outputs a low-level output signal Sout. At time T B3 and T B4 The time difference between time T B6 and T B7 The time difference between these is the delay time from when the high-level input signal Smid2 is applied to the signal delay circuit 2330 until the output signal Sout of the signal delay circuit 2330 switches to low level.

[0214] In FIG. 17, for convenience of illustration, time T B2 and T B8 The length of the delay time t DELAY Although it is drawn at a fraction of the time T B2 and T B8 The length of the delay is t DELAYTherefore, the frequency of the signal Sout is substantially the same as the delay time t DELAY Here, the frequency of the signal Sout is assumed to be several tens of MHz, but the frequency of the signal Sout is arbitrary.

[0215] Next, the operation of the current setting circuit 2600 will be described (see FIG. 14). In the current setting circuit 2600, resistors 2601 and 2602 are variable resistors each having an adjustable resistance value. The resistance value of resistor 2601 is represented by the symbol "R1," and the resistance value of resistor 2602 is represented by the symbol "R2." Because a current mirror circuit is formed by transistors 2201 and 2605, a current I1 proportional to the reference current Iref flows between the drain and source of transistor 2605. In other words, the current I1 is generated by the current mirror circuit (2201, 2605) that uses the reference current Iref as the input current. Because the current I1 is supplied to resistor 2601, the voltage V1 at node 2607 is the voltage drop generated across resistor 2601 when current I1 flows through resistor 2601, and is expressed as "V1 = I1 × R1."

[0216] The current flowing between the drain and source of transistor 2606 (i.e., the drain current of transistor 2606) is represented by the symbol "I2." Current I2 flows through the drain and source of transistor 2604 and resistor 2602. Therefore, voltage V2 at node 2608 is the voltage drop that occurs across resistor 2602 when current I2 flows through resistor 2602, and is expressed as "V2=I2×R2."

[0217] Voltages V1 and V2 are input to an operational amplifier 2603. The operational amplifier 2603 adjusts the current I2 by controlling the gate potential of the transistor 2604 so that the voltage V1 at the node 2607 and the voltage V2 at the node 2608 become equal to each other (in other words, so that the difference between the voltages V1 and V2 is reduced to zero). Therefore, the following equation (B1) holds. Equation (B2) can be obtained by modifying equation (B1). Here, k Arepresents the ratio between the reference current Iref and the current I1, and can be adjusted by the size ratio between the transistors 2201 and 2605. I1×R1=I2×R2=k A ×Iref×R1 (B1) I2=k A ×Iref×R1 / R2 (B2)

[0218] Since a current mirror circuit is formed by transistors 2606 and 2313, the constant current Icc becomes a current proportional to the current I2. That is, the current mirror circuit (2606, 2313) that uses the current I2 as the input current generates the drain current Icc of transistor 2313 as a current proportional to the current I2. Because the reference current Iref is a constant current, the currents I1 and I2 are also constant currents, and as a result, the drain current Icc of transistor 2313 is also a constant current. Note that since a current mirror circuit is also formed by transistors 2606 and 2321, another current proportional to the current I2 flows as the drain current of transistor 2321 (however, when the voltage at node 2323 reaches the power supply voltage VACC, the drain current of transistor 2321 becomes zero).

[0219] The constant current Icc satisfies the following equation (B3) (see also the above equations (A1) and (B2)): where k B represents the ratio between the currents I2 and Icc, which can be adjusted by the size ratio between the transistors 2206 and 2613. Icc=k B ×I2 =k A ×k B ×Iref×R1 / R2 =k A ×k B ×(Vth1 / R)×(R1 / R2) ···(B3)

[0220] The current setting circuit 2600 can be said to be a circuit that sets a current value corresponding to the value of the reference current Iref and the values ​​(R1, R2) of the resistors 2601 and 2602 to the constant current Icc. The current setting circuit 2600 generates a voltage V1 corresponding to the reference current Iref using the resistor 2601 (converts the current I1 proportional to the reference current Iref into the voltage V1), and generates a current I2 corresponding to the voltage V1 using the operational amplifier 2603 and the resistor 2602. The current setting circuit 2600 then causes a current proportional to the current I2 to be generated as the constant current Icc in a charging current source (2313). The transistor 2313, in cooperation with the transistor 2206, constitutes a charging current source that supplies the constant current Icc to the parallel circuit of the capacitor 2311 and the transistor 2312.

[0221] By substituting equation (B3) into equation (A2), the following equation (B4) is obtained. A ×k B = 1" and "Vth2 / Vth1 = 1", then equation (B4) is equivalent to equation (B5). t DELAY =C×Vth2 / Icc =C / (k A ×k B )×(Vth2 / Vth1)×R×R2 / R1 ···(B4) t DELAY =C×R×R2 / R1 (B5)

[0222] The frequency of the signal Sout is DELAY It depends on the time t DELAY depends on the rate of change of voltage Vc when capacitor 2311 is charged (in other words, the rate of change of voltage Vc during the off period of transistor 2312), so signal Sout has a frequency according to this rate of change.

[0223] 14 employs a configuration in which the capacitor 2311 is charged using a constant current Icc, so that the rate of change in the voltage across the capacitor 2311 is less susceptible to fluctuations in the power supply voltage VACC. Therefore, the oscillation frequency of the oscillator 2000B is less susceptible to fluctuations in the power supply voltage VACC. The oscillation frequency corresponds to the frequency of the signal Sout or the frequency of the signal OSC_OUT.

[0224] On the other hand, there is a concern about changes in the characteristics of the capacitor 2311 due to temperature changes. However, because the reference current Iref is generated according to the reference resistor 2205, it is possible to cancel out changes in the characteristics of the capacitor 2311 due to temperature changes and changes in the characteristics of the reference resistor 2205 due to temperature changes. This makes it possible to suppress the effect of temperature changes on the oscillation frequency. Specifically, the capacitor 2311 may be given a positive temperature characteristic, while the reference resistor 2205 may be given a negative temperature characteristic. Alternatively, the capacitor 2311 may be given a negative temperature characteristic, while the reference resistor 2205 may be given a positive temperature characteristic.

[0225] Alternatively, the change in the characteristics of capacitor 2311 due to temperature change can be offset by the change in the characteristics of resistor 2601 or 2602 due to temperature change. That is, it is possible to offset the effect on the oscillation frequency of the change in the characteristics of capacitor 2311 due to temperature change and the effect on the oscillation frequency of the change in the characteristics of resistor 2601 or 2602 due to temperature change. This also makes it possible to suppress the effect of temperature change on the oscillation frequency.

[0226] In summary, in oscillator 2000B, the change in the characteristics of capacitor 2311 due to temperature change can be offset by the change in the characteristics of the target resistor due to temperature change, thereby suppressing the effect of temperature change on the oscillation frequency. The target resistor here refers to any one or two of resistors 2205, 2601, and 2602, or the combination of resistors 2205, 2601, and 2602. The temperature characteristics of capacitor 2311 and the temperature characteristics of the target resistor can be designed in advance so that the effect on the oscillation frequency of the change in the characteristics of capacitor 2311 due to temperature change and the effect on the oscillation frequency of the change in the characteristics of the target resistor due to temperature change are offset.

[0227] The electrical characteristics of each element constituting the oscillator 2000B vary due to manufacturing variations, and these variations are a factor in the deviation of the oscillation frequency from the desired target frequency. By adjusting the resistance value R1 or R2 in the adjustment process, the deviation between the oscillation frequency and the target frequency can be reduced. The adjustment process is carried out during the manufacturing stage of the oscillator 2000B or the inspection stage before shipping, and after the resistance values ​​R1 and R2 are adjusted in the adjustment process, the resistance values ​​R1 and R2 are fixed at the adjusted resistance values. As can be seen from equation (B5), for example, an adjustment to decrease the resistance value R1 takes place over a period of time t DELAY The increase in R2 leads to a decrease in the oscillation frequency, and the adjustment to decrease the resistance R2 is performed over time t DELAY This results in an increase in the oscillation frequency through a decrease in the resistance of resistors 2601 and 2602. Therefore, by adjusting the resistance values ​​R1 and R2, the difference between the oscillation frequency and the target frequency can be reduced, and the influence of manufacturing variations on the oscillation frequency can be mitigated. In this way, in oscillator 2000B, the influence of variations in the characteristics of the elements can be mitigated by adjusting the values ​​of resistors 2601 and 2602.

[0228] In addition, unlike the oscillator 2000A of Fig. 13, the oscillator 2000B of Fig. 14 does not include a bipolar transistor. Therefore, a dedicated process for forming a bipolar transistor is not required in the manufacture of a semiconductor device including the oscillator 2000B. As a result, it is possible to keep the manufacturing costs of the oscillator 2000B and the semiconductor device including the oscillator 2000B low.

[0229] <<Second Example>> A second embodiment will now be described. As described above, the deviation between the oscillation frequency and the target frequency can be reduced by adjusting the resistance value R1 or R2 during the adjustment process. Due to manufacturing constraints on the oscillator 2000B, the adjustment process often only allows the resistance values ​​R1 and R2 to be adjusted downward from a certain initial resistance value. However, as can be seen from equation (B5), the direction of change in the oscillation frequency caused by a decrease in resistance value R1 is opposite to the direction of change in the oscillation frequency caused by a decrease in resistance value R2. For this reason, in the oscillator 2000B of FIG. 14, both resistors 2601 and 2602 are variable resistors. The same applies when the adjustment process only allows the resistance values ​​R1 and R2 to be adjusted upward from a certain initial resistance value.

[0230] However, it is also possible to configure resistor 2601 so that resistance value R1 can be adjusted in either an increasing or decreasing direction in the adjustment process, and in this case, resistor 2601 may be a variable resistor, and a fixed resistor having a fixed resistance value may be used as resistor 2602. Conversely, it is also possible to configure resistor 2602 so that resistance value R2 can be adjusted in either an increasing or decreasing direction in the adjustment process, and in this case, resistor 2602 may be a variable resistor, and a fixed resistor having a fixed resistance value may be used as resistor 2601.

[0231] <<Third Example>> A third embodiment will now be described. In the first and second embodiments, a signal delay circuit 2310 including a capacitor 2311 is provided as a first-stage signal delay circuit. That is, in the first and second embodiments, the signal delay circuit 2310 is provided as a signal delay circuit D[1] (see FIG. 10). However, the signal delay circuit 2310 may also be used as any of the signal delay circuits D[2] to D[N-1]. In this case, a signal delay circuit 2320 is provided in the next stage of the signal delay circuit 2310. That is, if the signal delay circuit 2310 is a signal delay circuit D[i], then the signal delay circuit D[i+1] is the signal delay circuit 2320 (where i is a natural number equal to or less than (N-1)). The signal delay circuits 2310 and 2320 may be referred to as a first specified delay circuit and a second specified delay circuit, respectively.

[0232] For example, when "N=5", the oscillator circuit 2300 may be provided with signal delay circuits 2310, 2320, and 2330 as signal delay circuits D[3], D[4], and D[5], respectively, and signal delay circuits D[1] and D[2] may be added. In this case, the logical product signal of signals Sen and Sout is supplied from the enable circuit 2500 to the signal delay circuit D[1] as an input signal S[0] to the added signal delay circuit D[1], and the output signal S[2] of the added signal delay circuit D[2] is input to the gate of the transistor 2312 as an input square wave signal based on the output signal Sout.

[0233] In addition, any number of signal delay circuits may be provided in the preceding stage of the signal delay circuit 2310, and any number of signal delay circuits may be provided in the subsequent stage of the signal delay circuit 2310.

[0234] <<Fourth Example>> A fourth embodiment will now be described. Fig. 18 shows the configuration of an electronic device 4000 according to the fourth embodiment. The electronic device 4000 may be an electrical device mounted on a vehicle such as an automobile, a computer device, a home appliance device, or an industrial device. The electronic device 4000 has an upper device 4100, a gate driver 4200, and a power transistor 4300. In Fig. 18, the power transistor 4300 is an IGBT (insulated gate bipolar transistor), but the power transistor 4300 may also be a MOSFET.

[0235] The upper device 4100 supplies a control signal CNT to the gate driver 4200. The gate driver 4200 drives the power transistor 4300 by supplying a gate drive signal DRV corresponding to the control signal CNT to the gate of the power transistor 4300 while ensuring insulation between the upper device 4100 and the power transistor 4300. The above-mentioned signal transmission device 200 (see FIG. 1) is mounted on the gate driver 4200. The control signal CNT functions as an input pulse signal IN for the signal transmission device 200, and an output pulse signal OUT from the signal transmission device 200 functions as the gate drive signal DRV.

[0236] The gate driver 4200 controls the power transistor 4300 to be on by outputting a high-level gate drive signal DRV during a high-level period of the control signal CNT, and controls the power transistor 4300 to be off by outputting a low-level gate drive signal DRV during a low-level period of the control signal CNT. A load (e.g., a motor coil) (not shown) is connected in series to the power transistor 4300. A drive power supply voltage is supplied to the series circuit of the power transistor 4300 and the load, and the current supplied to the load is controlled by turning the power transistor 4300 on and off.

[0237] The electronic device 4000 may be provided with two pairs of gate drivers 4200 and power transistors 4300, and the first pair of power transistors 4300 and the second pair of power transistors 4300 may be connected in series to form a half-bridge circuit.

[0238] The electronic device 4000 may be provided with six pairs of gate drivers 4200 and power transistors 4300 to drive a three-phase motor. In this case, the first and second pairs of power transistors 4300 are used as the upper and lower arms of the U phase, the third and fourth pairs of power transistors 4300 are used as the upper and lower arms of the V phase, and the fifth and sixth pairs of power transistors 4300 are used as the upper and lower arms of the W phase. Then, by controlling the on / off of the six pairs of power transistors 4300, the currents supplied to the U-, V-, and W-phase coils of the three-phase motor can be controlled.

[0239] An oscillator 2000B can be provided within the gate driver 4200. In the gate driver 4200, the signal OSC_OUT from the oscillator 2000B can be used as a clock signal for various purposes. For example, the gate driver 4200 is equipped with a nonvolatile memory and a logic circuit that drives the nonvolatile memory, and the signal OSC_OUT can be used as a clock signal for a synchronous circuit included in the logic circuit. Also, for example, the signal OSC_OUT can be used to measure any time that needs to be measured within the gate driver 4200.

[0240] <<Fifth Example>> A fifth embodiment will be described. Modifications or supplementary matters to the above-mentioned matters relating to the oscillator will be described.

[0241] The channel types of the FETs (field effect transistors) described in each embodiment are merely examples. The channel type of any FET can be changed between P-channel and N-channel types without departing from the spirit of the above.

[0242] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first conduction electrode, a second conduction electrode, and a control electrode. In an FET, one of the first and second conduction electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second conduction electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second conduction electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0243] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0244] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0245] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0246] An oscillator (2000B; see FIG. 14) according to one aspect of the present disclosure includes a reference current generating circuit (2200) configured to generate a reference current (Iref), a current setting circuit (2600) having a first resistor (2601), a second resistor (2602), and an operational amplifier (2603), configured to generate a specific voltage (V1) according to the reference current using the first resistor, and to generate a specific current (I2) according to the specific voltage using the operational amplifier and the second resistor, and a plurality of signal delay circuits connected in a loop, and an oscillator circuit (2300) configured to generate an output rectangular wave signal (Sout) by causing several stages of signal delay circuits to perform an oscillating operation, the oscillator circuit having a capacitor (2311) that is charged using a constant charging current (Icc) corresponding to the specific current, generating the output rectangular wave signal having a frequency corresponding to the rate of change of the voltage (Vc) between both terminals of the capacitor when the capacitor is charged, and a configuration (first configuration) in which at least one of the first resistor and the second resistor is formed by a variable resistor.

[0247] The output rectangular wave signal has a frequency that corresponds to the rate of change of the voltage between the terminals of the capacitor. In this case, if a constant current is used to charge the capacitor, the rate of change of the voltage between the terminals of the capacitor is less affected by fluctuations in the power supply voltage. Therefore, the frequency of the output rectangular wave signal is less affected by fluctuations in the power supply voltage. While temperature-induced changes in the capacitor's characteristics are a concern, it is possible to offset the temperature-induced changes in the capacitor's characteristics with the temperature-induced changes in the target resistor (the target resistor is the first resistor, the second resistor, or a resistor for generating the reference current). That is, it is possible to offset the effect of changes in the capacitor's characteristics on the frequency of the output rectangular wave signal with the effect of changes in the target resistor's characteristics on the frequency of the output rectangular wave signal. Therefore, the effect of temperature changes on the frequency of the output rectangular wave signal can be suppressed. Furthermore, by forming at least one of the first and second resistors as a variable resistor, the effect of variations in the device characteristics can be mitigated by adjusting the variable resistor. Furthermore, since the current setting circuit can be formed without using bipolar transistors, cost reduction is expected compared to oscillators that require bipolar transistors.

[0248] In the oscillator according to the first configuration, the current setting circuit may be configured (second configuration) to supply a current (I1) proportional to the reference current to the first resistor, thereby inputting the specific voltage (V1) generated across the first resistor to the operational amplifier, and to generate the specific current according to the specific voltage and the second resistor using the operational amplifier.

[0249] In the oscillator according to the first configuration, the current setting circuit may generate a first voltage (V1) across the first resistor by supplying a first current (I1) proportional to the reference current to the first resistor, generate a second voltage (V2) across the second resistor by supplying a second current (I2) to the second resistor, input the first voltage and the second voltage to the operational amplifier, and adjust the second current by the operational amplifier so that the first voltage and the second voltage are equal, and the first voltage may be the specific voltage and the second current may be the specific current (third configuration).

[0250] In the oscillator according to the third configuration, the first current may be generated by a first current mirror circuit (2201, 2605) that uses the reference current as an input current, and the charging constant current may be generated by a second current mirror circuit (2606, 2313) that uses the second current as an input current (fourth configuration).

[0251] In the oscillator according to any of the first to fourth configurations, the multi-stage signal delay circuit may have two signal delay circuits, a first specified delay circuit (2310) and a second specified delay circuit (2320) provided in the next stage of the first specified delay circuit, and the first specified delay circuit may have a switching element (2312) configured to be turned on and off in synchronization with an input square wave signal (Sin in FIG. 14) based on the output square wave signal, the capacitor (2311) connected in parallel to the switching element, and a charging current source (2313) configured to supply the charging constant current to a parallel circuit of the switching element and the capacitor, and the voltage across the capacitor may be input to the second specified delay circuit (fifth configuration).

[0252] In the oscillator according to the fifth configuration, the second specified delay circuit may have an N-channel field effect transistor (2322) that receives the voltage across the capacitor between its gate and source, and a load (2321) connected to the drain of the field effect transistor, and the field effect transistor and the load form a source-grounded amplifier, and output the signal at the drain of the field effect transistor to the next-stage signal delay circuit (sixth configuration).

[0253] In an oscillator according to any one of the first to sixth configurations, the output rectangular wave signal may be a logical negation signal of an input signal to the oscillation circuit, and the oscillation circuit may be configured (seventh configuration) in which the output rectangular wave signal is output from the final-stage signal delay circuit among the multiple-stage signal delay circuits, and the output rectangular wave signal is input to the first-stage signal delay circuit as an input signal to the oscillation circuit, thereby performing the oscillation operation.

[0254] The oscillator according to any one of the first to seventh configurations may be configured (eighth configuration) further comprising a waveform shaping circuit (2400) configured to perform waveform shaping of the output rectangular wave signal. [Explanation of symbols]

[0255] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias 1000 Oscillator Circuit D[1]~D[N] signal delay circuit Sin input signal Sout output signal S[1]~S[N] signals VACC power supply voltage 2000A, 2000B, 9000 Oscillators 2100 Starter Circuit 2200 Reference current generation circuit 2300 2310, 2320, 2330 signal delay circuit 2400 waveform shaping circuit 2500 Enable Circuit 2600, 2600ref current setting circuit Iref reference current Icc constant current I1, I2 current Vth1, Vth2 gate threshold voltage WR1 power wiring 2311 capacitor 2205 Reference Resistor 2101-2103, 2201-2204, 2312, 2313, 2321, 2322, 2331, 2332, 2604-2606 transistors 2401 flip-flop 2402 Inverter circuit 2501 AND circuit 2601, 2602 Resistor 2603 operational amplifier 4000 electronic equipment 4100 Upper-level device 4200 Gate Driver 4300 Power Transistor CNT control signal DRV Gate drive signal

Claims

1. a reference current generating circuit configured to generate a reference current; a current setting circuit having a first resistor, a second resistor, and an operational amplifier, configured to generate a specific voltage according to the reference current using the first resistor, and to generate a specific current according to the specific voltage using the operational amplifier and the second resistor; an oscillation circuit having a plurality of stages of signal delay circuits connected in a loop, the oscillation circuit being configured to generate an output rectangular wave signal by causing the plurality of stages of signal delay circuits to perform an oscillation operation; the oscillator circuit has a capacitor that is charged using a constant current for charging that corresponds to the specific current, and generates the output square wave signal having a frequency that corresponds to a rate of change in voltage between both terminals of the capacitor when the capacitor is being charged; At least one of the first resistor and the second resistor is formed of a variable resistor. , oscillator.

2. The current setting circuit supplies a current proportional to the reference current to the first resistor, thereby inputting the specific voltage generated across the first resistor to the operational amplifier, and generates the specific current according to the specific voltage and the second resistor using the operational amplifier.

10. The oscillator of claim 1 .

3. the current setting circuit generates a first voltage across the first resistor by supplying a first current proportional to the reference current to the first resistor, generates a second voltage across the second resistor by supplying a second current to the second resistor, inputs the first voltage and the second voltage to the operational amplifier, and adjusts the second current by the operational amplifier so that the first voltage and the second voltage are equal; The first voltage is the specific voltage, and the second current is the specific current.

10. The oscillator of claim 1 .

4. The first current is generated by a first current mirror circuit that uses the reference current as a current on its input side, and the charging constant current is generated by a second current mirror circuit that uses the second current as a current on its input side.

4. The oscillator according to claim 3 .

5. the plurality of signal delay circuits includes two signal delay circuits, a first specified delay circuit and a second specified delay circuit provided in a stage subsequent to the first specified delay circuit; the first specified delay circuit includes a switching element configured to be turned on and off in synchronization with an input square wave signal based on the output square wave signal; the capacitor connected in parallel to the switching element; a charging current source configured to supply the constant charging current to a parallel circuit of the switching element and the capacitor, The voltage across the capacitor is input to the second specified delay circuit.

5. The oscillator according to claim 1 .

6. The second specified delay circuit has an N-channel field effect transistor that receives the voltage across the capacitor between its gate and source, and a load connected to the drain of the field effect transistor, and the field effect transistor and the load form a source-grounded amplifier, and outputs a signal at the drain of the field effect transistor to a signal delay circuit in the next stage.

6. The oscillator according to claim 5 .

7. the output square wave signal is a logical negation signal of the input signal to the oscillator circuit; In the oscillation circuit, the output rectangular wave signal is output from the final-stage signal delay circuit among the plurality of stages of signal delay circuits, and the output rectangular wave signal is input to the first-stage signal delay circuit as an input signal to the oscillation circuit, thereby performing the oscillation operation.

5. The oscillator according to claim 1 .

8. further comprising a waveform shaping circuit configured to shape the output square wave signal.

5. The oscillator according to claim 1 .

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