A quantum device and a method of manufacturing a quantum device.

Abstract

To provide a quantum device in which electromagnetic noise is hardly applied to a quantum bit circuit, and to provide a method of manufacturing the quantum device.SOLUTION: A quantum device includes a quantum chip, an interposer including a first wiring layer on which the quantum chip is mounted, a socket disposed to face the first wiring layer and including a plurality of terminals, and a board including a second wiring layer facing the first wiring layer, wherein each of the terminals electrically connects the first wiring layer and the second wiring layer, the socket includes a recess that houses the quantum chip, and the recess includes a first metal face that covers at least a part of the quantum chip.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to quantum devices and methods for fabricating quantum devices. [Background technology]

[0002] Quantum devices that include quantum bit circuits are known.

[0003] For example, Patent Document 1 describes a quantum device comprising: "a quantum chip; an interposer on which the quantum chip is mounted; and a socket arranged opposite the interposer and including a movable pin and a housing supporting the movable pin, wherein at least one end of the movable pin electrically contacts a terminal of the interposer and the other end opposite the one end is movable relative to the housing, and the other end electrically contacts a terminal of a board on which a connector for input / output to the outside is formed." The interposer in the fifth embodiment disclosed in Patent Document 1 has a mounting surface on which the quantum chip is mounted and an opposite surface opposite the mounting surface, and the socket is mounted on the mounting surface. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-002234 Summary of the Invention [Problem to be solved by the invention]

[0005] In the quantum device described in embodiment 5 of Patent Document 1, electromagnetic noise may be added to the quantum bit circuit.

[0006] An object of the present disclosure is to provide a quantum device and a method for manufacturing a quantum device that solves the above-mentioned problems. [Means for solving the problem]

[0007] The quantum device of the present disclosure comprises a quantum chip, an interposer having a first wiring layer on which the quantum chip is mounted, a socket arranged opposite the first wiring layer and including a plurality of terminals, and a board having a second wiring layer opposite the first wiring layer, wherein each terminal electrically connects the first wiring layer and the second wiring layer, and the socket has a recess that accommodates the quantum chip, and the recess has a first metal surface that covers at least a portion of the quantum chip.

[0008] The method for manufacturing a quantum device disclosed herein includes the steps of mounting a quantum chip on a first wiring layer of an interposer and arranging a socket including a plurality of terminals opposite the first wiring layer, wherein in the arranging step, a board having a second wiring layer is arranged opposite the first wiring layer, and in the arranging step, each terminal electrically connects the first wiring layer and the second wiring layer, and the socket has a recess that accommodates the quantum chip, and the recess has a first metal surface that covers at least a portion of the quantum chip. [Effects of the Invention]

[0009] According to the quantum device and the method for manufacturing the quantum device according to the present disclosure, electromagnetic noise is less likely to be applied to the quantum bit circuit. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view I showing an example of the configuration of a quantum device according to the present disclosure. [Figure 2] 1 is a flowchart I showing an example of a process for manufacturing a quantum device according to the present disclosure. [Figure 3] 10 is a cross-sectional view I showing an example of the configuration of a quantum device according to a modified example. [Figure 4] 10 is a cross-sectional view II showing an example of the configuration of a quantum device according to a modified example. [Figure 5] FIG. 10 is a bottom view of an example of the configuration of a quantum device according to a modified example. [Figure 6] 2 is a cross-sectional view II showing an example of the configuration of a quantum device according to the present disclosure. [Figure 7] 10 is a flowchart II illustrating an example of a process for manufacturing a quantum device according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, examples of each embodiment according to the present disclosure will be described using the drawings. Note that the drawings and specific configurations used in each embodiment should not be used to interpret the disclosure. The same or corresponding configurations in all drawings will be assigned the same reference numerals, and common descriptions will be omitted. It should be noted that in this disclosure, the drawings may relate to one or more embodiments.

[0012] First Embodiment Hereinafter, an embodiment according to the present disclosure will be described with reference to the drawings. An example of the configuration of a quantum device according to the present disclosure will be described below with reference to FIG.

[0013] Hereinafter, the direction in which the surface 21s of the substrate 21 included in the interposer 2 faces will be referred to as the Z direction. The direction that runs along the surface 21s and intersects the Z direction will be referred to as the X direction. The direction that intersects the Z direction and the X direction will be referred to as the Y direction. One side of the X direction will be referred to as the +X direction, and the other side of the X direction will be referred to as the -X direction. One side of the Y direction will be referred to as the +Y direction, and the other side of the Y direction will be referred to as the -Y direction. One side of the Z direction will be referred to as the +Z direction, and the other side of the Z direction will be referred to as the -Z direction.

[0014] (Quantum device configuration) As shown in FIG. 1, the quantum device 100 includes a quantum chip 1, an interposer 2, a socket 3, a board 4, a connector 5, and a cooling unit 6.

[0015] This quantum device 100 has a basic configuration in which a quantum chip 1 is connected to a board 4 via an interposer 2, and terminals 32 are used to connect the interposer 2 to the board 4. Furthermore, a cooling unit 6 stores the quantum chip 1 and interposer 2 and maintains them at an ultra-low temperature at which a quantum state can be realized.

[0016] (Quantum chip configuration) The quantum chip 1 includes a substrate 11 and a connection portion 12. Note that as long as the conductor can be connected to the circuit elements in the quantum chip 1, it does not necessarily have to be a conductor wiring layer forming a circuit pattern. The wiring layer (connecting portion 12) of the quantum chip 1 is mounted on the interposer 2 via bumps 24. Thus, the quantum chip 1 is flip-chip mounted on the interposer 2.

[0017] The connection 12 is preferably a superconducting material. More specifically, the substrate 11 is made of a material that is less likely to deform in a superconducting environment, such as silicon (Si), gallium arsenide (GaAs), sapphire, glass, etc. Furthermore, the connection portion 12 that constitutes the quantum bit circuit formed on the substrate 11 is made of niobium (Nb), niobium nitride such as niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, or a superconducting alloy containing at least one of these.

[0018] (Interposer configuration) The interposer 2 includes a substrate 21, a first wiring layer 22, and at least one bump 24. A first wiring layer 22 is provided on the front surface 21s of the substrate 21. The entire back surface 21bs of the substrate 21 is in contact with the cooling unit 6. In this case, the interposer 2 may be arranged with a space between it and the inner surface of the recess 61 included in the cooling unit 6. This configuration makes it possible to suppress stress and strain caused by the difference in contraction between the interposer 2 and the cooling unit 6 that occurs when the temperature changes to an extremely low temperature. Furthermore, the interposer 2 may be arranged so as to abut against a portion of the inner surface of the recess 61. When the interposer 2 abuts, movement of the interposer 2 in the Y direction is restricted. Like the quantum chip 1, the substrate 21 is made of a material that is less likely to deform in a superconducting environment, such as silicon (Si), gallium arsenide (GaAs), sapphire, or glass.

[0019] In addition, the first wiring layer 22 is composed of niobium (Nb), niobium nitrides such as niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, and a superconducting alloy containing at least any of these.

[0020] Furthermore, a metal layer such as gold (Au), platinum (Pt), or palladium (Pd) may be formed on the surface of the first wiring layer 22. For example, a metal layer such as gold (Au), platinum (Pt), or palladium (Pd) may be formed on the surface of the first wiring layer 22 in a region outside a cavity resonator, which will be described later.

[0021] The interposer 2 may include a through via (TV). The TV is used to obtain a ground potential from the cooling unit 6.

[0022] Bump 24 may contain the same superconducting material as connecting portion 12, or may contain a different superconducting material from connecting portion 12. Furthermore, when bump 24 contains multiple metal layers, it is preferable that at least one layer contains a superconducting material.

[0023] (Socket configuration) The socket 3 includes a housing 31, two or more terminals 32, a recess 33, and a first metal portion 34. The socket 3 also has a hole on the surface that comes into contact with the board 4, through which a fastener such as a screw can be inserted. The socket 3 has an opposing surface 31cs and another end surface 31es in the Z direction. For example, in this embodiment, the opposing surface 31cs faces the −Z direction, and the other end surface 31es faces the +Z direction. The socket 3 is disposed so as to face the first wiring layer 22 of the interposer 2. For example, in this embodiment, the socket 3 is disposed so that the facing surface 31cs faces the first wiring layer 22.

[0024] The socket 3 has a recess 33 that accommodates the quantum chip 1. In this embodiment, the socket 3 is placed on the interposer 2, and the quantum chip 1 is accommodated in the space formed by the recess 33 and the interposer 2. The inner surface of the recess 33 is covered with a first metal portion 34. The first metal portion 34 is formed to include a metal surface made of gold (Au), platinum (Pt), palladium (Pd), or the like. The metal surface of the first metal portion 34 may be exposed to the outside, or may be covered and then exposed to the outside. That is, the first metal portion 34 may be a thin film or a layer. For example, in this embodiment, a metal surface (first metal surface) is formed on the surface of the first metal portion 34. The metal surface (first metal surface) is formed by means of sputtering, vapor deposition, electroless plating, electrolytic plating, or the like.

[0025] In this way, the quantum chip 1 is surrounded by the metal surface (first metal surface) of the first metal portion 34 and the first wiring layer 22 made of a superconducting alloy. At this time, a gap is formed between the quantum chip 1 and the recess 33. A cavity resonator is obtained by the metal surface (first metal surface) of the first metal portion 34 and the first wiring layer 22. The cavity resonator also has the gap. As the gap becomes smaller, the resonance mode of the cavity resonator shifts to a higher frequency band. Since the resonance mode generated in the quantum chip is about 5 GHz to 10 GHz, if the gap is reduced to shift the resonance mode to a frequency band higher than this frequency band (for example, 20 GHz to 30 GHz), electromagnetic noise is less likely to be applied to the quantum bit circuit.

[0026] The housing 31 preferably contains an insulating material. At least the portion of the housing 31 that contacts the terminals 32 contains an insulating material. The housing 31 also preferably contains a non-magnetic material. Furthermore, the housing 31 preferably contains a material with a thermal expansion coefficient equivalent to that of the interposer 2.

[0027] Housing 31 may include quartz or a plastic such as an engineering plastic. Housing 31 may also include aluminum oxide (Al2O3, also called alumina), mica-based machinable ceramic, aluminum nitride (AlN), zirconia (ZrO2), macor-based machinable ceramic, glass, a composite material with low linear expansion containing a resin and a silica filler. Housing 31 may also include a superconducting material, provided that insulation between housing 31 and terminals 32 is ensured.

[0028] A plurality of terminals 32 made of conductors penetrate the housing 31 . In this embodiment, the dimension of the socket 3 in the X direction is larger than the dimension of the interposer 2 in the X direction.

[0029] One end of the terminal 32 contacts the first wiring layer 22, and the other end of the terminal 32 contacts the second wiring layer 42, thereby electrically connecting the first wiring layer 22 and the second wiring layer 42. At this time, the interposer 2 and the board 4 are electrically connected. Furthermore, the second wiring layer 42 is connected to the connector 5, and a circuit is formed from the interposer 2 to the connector 5 via the first wiring layer 22, the terminal 32, and the second wiring layer 42.

[0030] (Terminal configuration) Terminal 32 is a pin. The pin is extendable in the longitudinal direction. One end of the pin extends in the -Z direction, and the other end of the pin extends in the +Z direction. The pin contains a compression spring, and when the compression spring elastically deforms in the Z direction, one end or the other end of terminal 32 is biased in the Z direction.

[0031] By biasing one end or the other end of the terminal 32 in the Z direction, one end of the terminal 32 can be electrically connected to the first wiring layer 22 while being in close contact with the terminal. By biasing one end or the other end of the terminal 32 in the Z direction, the other end of the terminal 32 can be electrically connected to the second wiring layer 42 while being in close contact with the terminal. At this time, a large contact area is ensured due to plastic deformation of the metal constituting the first wiring layer 22 and / or the second wiring layer 42, and the terminal 32 can be closely contacted due to stress generated in the elastically deformed first wiring layer 22 and / or the second wiring layer 42. This can improve the reliability of the electrical connection between the terminal 32 and the first wiring layer 22 between the interposer 2 and the board 4. This can improve the reliability of the electrical connection between the terminal 32 and the second wiring layer 42 between the interposer 2 and the board 4.

[0032] The terminal 32 may include a superconducting material. For example, the terminal 32 may include the same superconducting material as the connection portion 12, etc., or may include a different superconducting material from the first wiring layer 22, etc. Furthermore, the terminal 32 may include the same normal-conducting material as the metal layer formed on the surface of the first wiring layer 22, or may include a different normal-conducting material from the first wiring layer 22. This metal layer is formed on the surface of the first wiring layer 22 in the region outside the cavity resonator as necessary, as described above. The terminal 32 is preferably made of a non-magnetic material. The terminal 32 preferably includes, for example, a palladium alloy, a gold alloy, beryllium copper (BeCu), gold (plated), niobium (Nb), niobium titanium (Nb-Ti), or titanium (Ti).

[0033] (Board configuration) The board 4 is disposed opposite the first wiring layer 22. The board 4 includes a base material 41 and a second wiring layer 42. For example, in this embodiment, the base material 41 is plate-shaped and has an upper surface 41s and a lower surface 41bs in the Z direction. A second wiring layer 42 facing the first wiring layer 22 is provided on the lower surface 41bs. A connector 5 that can be connected to an external device is provided on the upper surface 41s. The lower surface 41bs faces the other end surface 31es of the socket 3.

[0034] The base material 41 has a plurality of bearing surfaces on its upper surface 41s for supporting fasteners such as screws, and each bearing surface has a through-hole. The board 4 is connected to the socket 3 with fasteners such as screws. The board 4 is connected to the cooling unit 6 with fasteners such as screws.

[0035] The substrate 41 may include materials such as epoxy, acrylic, urethane, polyimide, phenol, and liquid crystal polymer, and may further include silica, organic resin, ceramic filler, glass fiber, etc. The substrate 41 may also include solidified ceramic powder.

[0036] The second wiring layer 42 provided on the lower surface 41bs is made of a material such as copper (Cu), aluminum (Al), or the like, and is formed into a predetermined circuit pattern by means of sputtering, vapor deposition, electroless plating, electrolytic plating, etc. Specific methods that can be used to form the conductive material layer into a predetermined circuit pattern include a subtractive method using a resist applied to the surface as a mask, an additive method using plating, a SEMI additive method, and a lift-off method in which the pattern is formed by removing the applied resist.

[0037] (Connector configuration) The connector 5 is used for exchanging input and output with an external device. For example, an external device inputs and outputs power, signals, and the like to and from the quantum chip 1 via the socket 3. The connector 5 is electrically connectable to the second wiring layer 42.

[0038] (Cooling section configuration) The cooling unit 6 has a cooling function. An example of the cooling unit 6 is a sample stage. The sample stage is a so-called cold stage equipped with a cryogenic refrigerator (not shown) at a temperature of about millikelvin [mK], which can realize a superconducting state in the materials constituting the quantum chip 1 and the interposer 2.

[0039] The cooling section 6 includes a recess 61 and a counterbore 62. The cooling section 6 also has holes on the surface that comes into contact with the board 4, through which fasteners such as screws can be inserted. The recess 61 is open in the +Z direction and has a shape corresponding to the planar shape of the interposer 2 in the XY plane. The countersunk 62 is formed around the opening of the recess 61 and has a shape corresponding to the planar shape of the socket 3 in the XY plane. At this time, a step surface 62s having a step with the bottom of the recess 61 is formed around the opening of the recess 61. The interposer 2 is disposed at the bottom of the recess 61 .

[0040] The step surface 62s is, for example, parallel to the surface 21s of the substrate 21. The step surface 62s is formed around the recess 61. The step surface 62s surrounds the recess 61. The position of the step surface 62s in the +Z direction is approximately the same as the surface 21s or higher than the surface 21s. For example, in this embodiment, the position of the step surface 62s in the +Z direction is approximately the same as the surface 21s. This allows a portion of the facing surface 31cs of the socket 3 to come into contact with the step surface 62s. In this case, the socket 3 may be arranged with a space between it and the inner surface of the counterbore 62 of the cooling unit 6. This configuration can suppress stress and strain caused by differential contraction between the socket 3 and the cooling unit 6 due to a temperature change to an extremely low temperature. The socket 3 may also be arranged to abut against a portion of the inner surface of the counterbore 62. When the socket 3 abuts, movement of the socket 3 in the Y direction is restricted. Arranging the interposer 2 to abut against a portion of the inner surface of the recess 61 when the socket 3 abuts has the following advantages. By restricting the movement of the interposer 2 and the socket 3 in the Y direction, the relative positional relationship between the quantum chip 1 and the socket 3 arranged inside the cooling unit 6 in the Y direction is less likely to shift.

[0041] The cooling unit 6 is preferably made of a metal such as copper (Cu), a copper alloy, etc. For example, when the quantum chip 1 contains niobium (Nb) as a superconducting material, the superconducting phenomenon is utilized at an ultra-low temperature of 9.2 Kelvin [K] or less, and when the quantum chip 1 contains aluminum (Al), the superconducting phenomenon is utilized at an ultra-low temperature of 1.2 Kelvin [K] or less, so the cooling unit 6 is required to have a cooling capacity capable of realizing the ultra-low temperatures exemplified above.

[0042] At least one of the interposer 2 and the socket 3 is in contact with a cooling unit 6 having a cooling function. For example, in this embodiment, the back surface 21bs of the interposer 2 and a part of the opposing surface 31cs of the socket 3 are in contact with the cooling unit 6.

[0043] By bringing at least a portion of the interposer 2 into contact with the cooling unit 6, the interposer 2 functions as a heat transfer path, and the quantum bit circuit included in the quantum chip 1 is cooled to an extremely low temperature. In this way, the superconducting phenomenon can be utilized. At this time, the entire back surface 21bs of the interposer 2 is in contact with the cooling unit 6, so the amount of heat transfer is increased compared to when only a portion of the interposer 2 is in contact with the cooling unit 6. This improves the cooling efficiency of the interposer 2, and the quantum chip 1 is cooled more efficiently.

[0044] The ground potential of the interposer 2 may be obtained from the cooling unit 6. For example, it is obtained from the cooling unit 6 via the TV of the interposer 2. At this time, the metal layer of the socket 3 obtains the ground potential by contacting with the interposer 2.

[0045] (Manufacturing method) A method for manufacturing a quantum device according to this embodiment will now be described. The method for manufacturing a quantum device in this embodiment is carried out according to the flow shown in FIG.

[0046] First, the manufacturer mounts the quantum chip 1 on the first wiring layer 22 of the interposer 2 (step ST10: mounting step).

[0047] Next, the manufacturer places a socket including a plurality of terminals opposite the first wiring layer 22 (step ST11: placing step). The socket 3 used in step ST11 includes a recess 33 that accommodates the quantum chip 1, and the recess 33 has a first metal surface that covers at least a portion of the quantum chip 1. For example, a first metal portion 34 that covers the inner surface of the recess 33 may be provided. The first metal portion 34 is formed to include a metal surface made of gold (Au), platinum (Pt), palladium (Pd), or the like. The metal surface of the first metal portion 34 may be exposed to the outside, or the metal surface (first metal surface) may be coated and then exposed to the outside. In other words, the first metal portion 34 may be a thin film or a layer. The first metal surface may be a membrane surface such as a mesh membrane or porous membrane having openings in some parts.

[0048] In step ST11, the board 4 having the second wiring layer 42 is placed opposite the first wiring layer 22 (step ST11A).

[0049] In step ST11, each terminal (terminal 32) electrically connects the first wiring layer 22 and the second wiring layer 42 (step ST11B).

[0050] Here, quantum device 100 is manufactured, which has a structure that makes it difficult for electromagnetic noise to be applied to the quantum bit circuit. (Complete)

[0051] (Action and effect) According to the quantum device of the present disclosure, at least a portion of the quantum chip 1 is covered by the metal surface (first metal surface) of the first metal portion 34. The quantum chip 1 covered by the metal surface (first metal surface) of the first metal portion 34 is provided with an electromagnetic shield. Therefore, the quantum device according to the present disclosure is less susceptible to electromagnetic noise being applied to the quantum bit circuit.

[0052] In the above disclosure, the first metal surface of the socket 3 has an electromagnetic shielding function for the quantum chip 1 . As a comparative example, in a configuration in which the entire structure, including the quantum chip and the socket to be shielded, is covered by a cover having a first metal surface, additional space is required to accommodate the cover having the first metal surface. The need for such space limits the space available for wiring to external devices. For example, such space limitations may limit the number of terminals for exchanging signals with external devices. In contrast, according to the quantum device 100 of the present disclosure, the first metal surface provided on the socket 3 covers at least a portion of the quantum chip 1 to be shielded. Therefore, according to quantum device 100 of the present disclosure, the space for wiring to external devices is less limited compared to the comparative example. For example, according to quantum device 100 of the present disclosure, the number of terminals 32 for exchanging signals with external devices is less limited compared to the comparative example.

[0053] Furthermore, the quantum device 100 of the present disclosure "comprises a quantum chip 1, an interposer 2 having a first wiring layer 22 on which the quantum chip 1 is mounted, a socket 3 arranged opposite the first wiring layer 22 and including a plurality of terminals, and a board 4 having a second wiring layer 42 opposite the first wiring layer 22, each terminal (terminal 32) electrically connecting the first wiring layer 22 and the second wiring layer 42, the socket 3 having a recess 33 for accommodating the quantum chip 1, and the recess 33 having a first metal surface covering at least a portion of the quantum chip 1," thereby achieving the following effects. According to the quantum device 100 of the present disclosure, at least a portion of the quantum chip 1 is covered with the metal surface (first metal surface) of the first metal portion . This provides the effect that "quantum chip 1 covered with the metal surface (first metal surface) of first metal portion 34 is electromagnetically shielded." Therefore, the quantum device according to the present disclosure is less susceptible to electromagnetic noise in the quantum bit circuit.

[0054] Additionally, in the quantum device 100 of the present disclosure, "the terminals 32 are pins that can expand and contract in the longitudinal direction," which also provides the effect that "the pins can expand and contract in the longitudinal direction in response to volume changes in the terminals, etc. that occur when the quantum device 100 is cooled to extremely low temperatures, thereby preventing breakage of the first wiring layer 22 and / or the second wiring layer 42 that come into contact with the terminals 32."

[0055] Furthermore, in the quantum device 100 of the present disclosure, "the socket 3 is mounted on the interposer 2," so that the quantum chip 1 is housed in the space formed by the recess 33 and the interposer 2. Since electromagnetic waves are less likely to penetrate between the socket 3 and the interposer 2, an effect can be obtained in which "electromagnetic noise is less likely to be applied to the quantum bit circuit."

[0056] In addition, in the quantum device 100 of the present disclosure, "at least one of the interposer 2 and the socket 3 is in contact with a cooling section 6 having a cooling function," which also provides the effect that "the quantum chip 1 mounted on the interposer 2 is easily cooled."

[0057] Furthermore, the inspection device of the present disclosure can further obtain the following effect by "the interposer 2 having a first wiring layer 22 on the surface 21s, and the first wiring layer 22 being made of an alloy having superconductivity." According to the quantum device 100 of the present disclosure, the quantum chip 1 is surrounded by the metal surface (first metal surface) of the first metal portion 34 and the first wiring layer 22 made of an alloy having superconductivity. This provides the effect that "quantum chip 1 surrounded by the metal surface (first metal surface) of first metal portion 34 and first wiring layer 22 is further electromagnetically shielded."

[0058] In addition, the quantum device 100 of the present disclosure further has the following effect by "having a gap between the quantum chip 1 and the recess 33." In the cavity resonator obtained by the quantum chip 1 surrounded by the metal surface (first metal surface) of the first metal portion 34 and the first wiring layer 22 made of a superconducting alloy, the smaller the gap, the more the resonance mode shifts to a higher frequency band. Therefore, by reducing the gap, the resonance mode shifts to a higher frequency band, which has the effect of making it less susceptible to electromagnetic noise being applied to the quantum bit circuit.

[0059] (First Modification) For example, although a through hole has been provided in the seating surface on the upper surface 41s, a protrusion that protrudes a part of the lower surface 41bs of the base material in the -Z direction may be provided on the base material 41 instead of the through hole. The protrusion can be fitted into holes provided in the cooling unit 6 and the socket 3, respectively.

[0060] (Second Modification) The first metal surface may contain a superconducting material. The superconducting material functions as a magnetic shield when cooled. Therefore, the quantum chip 1, which is surrounded by the metal surface (first metal surface) of the first metal portion 34 and the first wiring layer 22 made of a superconducting alloy, is provided with a magnetic shield in addition to an electromagnetic shield. Therefore, electromagnetic noise is less likely to be applied to the quantum bit circuit.

[0061] (Third Modification) In the above disclosure, the other end surface 31es of the socket 3 is in contact with the board 4, but a space may be formed between the other end surface 31es and the interposer 2 as long as the other end of the terminal 32 can contact the second wiring layer 42.

[0062] (Fourth Modification) In the above disclosure, the opposing surface 31cs of the socket 3 and the interposer 2 are in contact, but a space may be formed between the opposing surface 31cs and the interposer 2 if the quantum chip 1 is surrounded by the metal surface (first metal surface) of the first metal portion 34 and another metal surface.

[0063] (Fifth Modification) The quantum device 200 shown in FIG. 3 is similar to that disclosed above, except as described below. The quantum device 200 includes a quantum chip 1, an interposer 2, a socket 3B, a board 4, a connector 5, and a cooling unit 6. The socket 3B includes a housing 31, two or more terminals 32, a recess 33, a first metal portion , and a connection portion . The connecting portion 35 connects the opposing surface 31cs and the first metal surface. The connection portion 35 is formed to include a metal surface made of gold (Au), platinum (Pt), palladium (Pd), or the like. The metal surface of the connection portion 35 may be exposed to the outside, or may be coated and then exposed to the outside. That is, the connection portion 35 may be a thin film or a layer. For example, in this modification, a metal surface (second metal surface) is formed on the surface of the connection portion 35. The metal surface (second metal surface) is formed by means of sputtering, vapor deposition, electroless plating, electrolytic plating, or the like.

[0064] At least one of the interposer 2 and the socket 3B is in contact with a cooling unit 6 having a cooling function. For example, in this embodiment, the entire back surface 21bs of the interposer 2 is in contact with the cooling unit 6.

[0065] In this modification, compared to the quantum device 100 disclosed above, electromagnetic waves are less likely to penetrate between the socket 3 and the interposer 2. In the quantum device 200 of this modification, electromagnetic noise is less likely to be applied to the quantum bit circuit.

[0066] The second metal surface may include a superconducting material.

[0067] (Sixth Modification) The quantum device 300 shown in FIG. 4 is similar to that disclosed above, except as described below. The quantum device 300 includes a quantum chip 1, an interposer 2, a socket 3C, a board 4, a connector 5, and a cooling unit 6. Socket 3C differs from socket 3B in that connecting portion 35 covers opposing surface 31cs. 5 is a view of connection portion 35 as viewed from the -Z direction. Connection portion 35 has opening 35EX in the portion where it overlaps with terminal 32 in the Z direction. Opening 35EX includes the projected area of ​​terminal 32 projected in the Z direction, and is larger than the projected area of ​​terminal 32. This makes it less likely to obstruct the electric field of a high-frequency signal propagating through terminal 32. The arrangement of the terminals 32 is merely an example and is not limited to this.

[0068] At least one of the interposer 2 and the socket 3 is in contact with a cooling unit 6 having a cooling function. For example, in this embodiment, the entire back surface 21bs of the interposer 2 and a part of the connection portion 35 of the socket 3 are in contact with the cooling unit 6.

[0069] In this modification, a larger contact area is ensured between the connection portion 35 and the interposer 2 compared to the quantum device 200 disclosed above, making it more difficult for electromagnetic waves to penetrate between the socket 3 and the interposer 2. In the quantum device 300 of this modification, electromagnetic noise is less likely to be applied to the quantum bit circuit.

[0070] Furthermore, when the opposing surface 31cs of the socket 3 is covered with a metal surface (second metal surface), a portion of the connection portion 35 covering the opposing surface 31cs is in contact with the cooling portion 6, which makes it easier to improve the cooling efficiency of the interposer 2 and more efficiently cools the quantum chip 1.

[0071] (Seventh Modification) In the above disclosure, as a means for restraining the movement of the socket 3 and / or the interposer 2 in the Y direction, it has been shown that the socket 3 and / or the interposer 2 are arranged to abut against a portion inside the cooling unit 6. However, in this modified example, the socket 3 and / or the interposer 2 may abut against the inside of the cooling unit 6 via a separate member such as a spacer, rather than directly abutting against the inside of the cooling unit 6. Furthermore, a method of using positioning pins or the like to prevent the mutual positional relationship between the socket 3 and the interposer 2 in the Y direction from shifting, or various other methods may be employed as a means for restricting their movement in the Y direction.

[0072] Second Embodiment Hereinafter, an embodiment according to the present disclosure will be described with reference to the drawings. An example of the configuration of a quantum device according to the present disclosure will be described below with reference to FIG.

[0073] (composition) The quantum device 100m comprises a quantum chip 1m, an interposer 2m having a first wiring layer on which the quantum chip 1m is mounted, a socket 3m arranged opposite the first wiring layer and including a plurality of terminals, and a board 4m having a second wiring layer opposite the first wiring layer, each terminal (terminal 32m) electrically connecting the first wiring layer and the second wiring layer, the socket 3m having a recess 33m that accommodates the quantum chip 1m, and the recess 33m having a first metal surface that covers at least a portion of the quantum chip 1m.

[0074] (Action and effect) According to the quantum device of the present disclosure, at least a portion of the quantum chip 1m is covered with a first metal surface. The quantum chip 1m covered with the first metal surface is provided with an electromagnetic shield. Therefore, the quantum device according to the present disclosure is less susceptible to electromagnetic noise being applied to the quantum bit circuit.

[0075] Third Embodiment Hereinafter, an embodiment according to the present disclosure will be described with reference to the drawings. An example of a method for manufacturing a quantum device according to the present disclosure will now be described with reference to FIG. The method for manufacturing a quantum device according to the present disclosure is carried out according to the flow shown in FIG.

[0076] The manufacture of the quantum device includes mounting a quantum chip on a first wiring layer of an interposer (step ST10m: mounting step), and arranging a socket including a plurality of terminals opposite the first wiring layer (step ST11m: placing step), wherein in the placing step, a board having a second wiring layer is placed opposite the first wiring layer (step ST11Am), and in the placing step, each terminal electrically connects the first wiring layer and the second wiring layer (step ST11Bm), and the socket has a recess for accommodating the quantum chip, and the recess has a first metal surface covering at least a portion of the quantum chip.

[0077] (Action and effect) According to the method for manufacturing a quantum device of the present disclosure, at least a portion of a quantum chip is covered with a first metal surface, and the quantum chip covered with the first metal surface is provided with an electromagnetic shield. Therefore, the quantum device according to the present disclosure is less susceptible to electromagnetic noise being applied to the quantum bit circuit.

[0078] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0079] A part or all of the above-described embodiments can be described as, but not limited to, the following supplementary notes.

[0080] (Appendix 1) Quantum chips and an interposer having a first wiring layer on which the quantum chip is mounted; a socket disposed opposite the first wiring layer and including a plurality of terminals; a board having a second wiring layer facing the first wiring layer; Equipped with Each terminal electrically connects the first wiring layer and the second wiring layer, the socket has a recess for accommodating the quantum chip; The recess has a first metal surface covering at least a portion of the quantum chip. Quantum devices.

[0081] (Appendix 2) the terminal is a pin, The pin can be extended or contracted in the longitudinal direction. 10. The quantum device of claim 1.

[0082] (Appendix 3) The socket is mounted on the interposer. 10. The quantum device of claim 1 or 2.

[0083] (Appendix 4) At least one of the interposer and the socket is in contact with a cooling unit having a cooling function. 4. The quantum device of claim 1.

[0084] (Appendix 5) the socket has an opposing surface facing the first wiring layer, the socket further includes a connection portion connecting the opposing surface and the first metal surface, The connection portion has a second metal surface. 5. The quantum device of any one of Supplementary Notes 1 to 4.

[0085] (Appendix 6) The connection portion covers the opposing surface. 6. The quantum device of claim 5.

[0086] (Appendix 7) the interposer has the first wiring layer on a surface thereof; the first wiring layer is made of a superconducting alloy; 7. The quantum device of any one of Supplementary Notes 1 to 6.

[0087] (Appendix 8) the first metal surface comprises a superconducting material; 8. The quantum device of claim 7.

[0088] (Appendix 9) A gap is formed between the quantum chip and the recess. 9. The quantum device of any one of Supplementary Notes 1 to 8.

[0089] (Appendix 10) Mounting a quantum chip on a first wiring layer of an interposer; disposing a socket including a plurality of terminals facing the first wiring layer; Including, In the step of placing, a board having a second wiring layer is placed opposite the first wiring layer; In the step of placing, each terminal electrically connects the first wiring layer and the second wiring layer; the socket has a recess for accommodating the quantum chip; The recess has a first metal surface covering at least a portion of the quantum chip. A method for manufacturing quantum devices. [Explanation of symbols]

[0090] 1. Quantum chip 11 Base material 12 Connection 2 Interposer 21 Base material 21bs back side 21s surface 22 First wiring layer 24 Bump 3 sockets 31 Housing 31cs facing side 31es Other end surface 32 terminals 33 Recess 34 First Metal Department 3B socket 35 Connection 3C socket 35EX aperture 4. Board 41 Base material 41bs bottom 41s top surface 42 Second wiring layer 5 Connectors 6 Cooling section 61 Recess 62 Countersink 62s step surface 1m quantum chip 2m Interposer 3m socket 32m terminal 33m recess 4m board

Claims

1. Quantum chips and an interposer having a first wiring layer on which the quantum chip is mounted; a socket disposed opposite the first wiring layer and including a plurality of terminals; a board having a second wiring layer facing the first wiring layer; Equipped with Each terminal electrically connects the first wiring layer and the second wiring layer, the socket has a recess for accommodating the quantum chip; The recess has a first metal surface covering at least a portion of the quantum chip. Quantum devices.

2. the terminal is a pin, The pin can be extended or contracted in the longitudinal direction. The quantum device of claim 1 .

3. The socket is mounted on the interposer. The quantum device of claim 1 .

4. At least one of the interposer and the socket is in contact with a cooling unit having a cooling function. The quantum device of claim 3 .

5. the socket has an opposing surface facing the first wiring layer, the socket further includes a connection portion connecting the opposing surface and the first metal surface, The connection portion has a second metal surface. The quantum device according to any one of claims 1 to 4.

6. The connection portion covers the opposing surface. The quantum device of claim 5 .

7. the interposer has the first wiring layer on a surface thereof; the first wiring layer is made of a superconducting alloy; The quantum device according to any one of claims 1 to 4.

8. the first metal surface comprises a superconducting material; The quantum device of claim 7.

9. A gap is formed between the quantum chip and the recess. The quantum device according to any one of claims 1 to 4.

10. Mounting a quantum chip on a first wiring layer of an interposer; disposing a socket including a plurality of terminals facing the first wiring layer; Including, In the step of placing, a board having a second wiring layer is placed opposite the first wiring layer; In the step of placing, each terminal electrically connects the first wiring layer and the second wiring layer; the socket has a recess for accommodating the quantum chip; The recess has a first metal surface covering at least a portion of the quantum chip. A method for manufacturing quantum devices.

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