Semiconductor device and method of manufacturing the same

Abstract

To prevent leakage of an adhesive member.SOLUTION: And a sealing member 35 that seals an upper surface and a side surface of the insulated circuit substrate 20, has a lower surface 22a positioned lower than the lower surface 22a of the insulated circuit substrate 20, has the lower surface 35a opened to expose the entire lower surface 35a, and includes a space 22a below the lower surface 22a. 35e. In the sealing member 35, a lateral space side 35e connected to the space side 35e is formed on a side part of the space side 35f, and an upper part of the lateral space side 35f is defined by an inclined surface side 35e inclined downward from the space side 35f2 toward the side part.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The semiconductor device includes a semiconductor module and a cooling module provided to the semiconductor module via a thermally conductive joining member (see, for example, Patent Documents 1 to 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-033872 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-065648 [Patent Document 3] International Publication No. 2013 / 099545 [Patent Document 4] International Publication No. 2019 / 239997 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which leakage of an adhesive member is prevented. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising: a substrate having a first lower surface; a sealing member that seals an upper surface and a side surface of the substrate, the sealing member having a second lower surface located below the first lower surface of the substrate, the second lower surface being open so that the entire first lower surface is exposed, and the sealing member having a lateral space formed on a side of the space that is connected to the space, and the upper part of the lateral space being defined by an inclined surface that slopes downward from the space toward the side.

[0006] The device may further include a cooling module having a cooling surface on which the second lower surface of the sealing member is placed, and a thermally conductive material provided in the space of the sealing member and between the first lower surface of the substrate and the cooling surface.

[0007] The thermally conductive material may be an adhesive material. The device may further include a cooling module having a cooling surface on which the second lower surface of the sealing member is placed, and an adhesive member provided in the space of the sealing member and bonding the first lower surface of the substrate and the cooling surface.

[0008] The adhesive member may also include a conductive filler. Additionally, an edge of the adhesive member may extend from the space to the lateral space. The angle of the inclined surface relative to the second lower surface may be smaller than 45°.

[0009] The sealing member may be configured so that the lateral space is formed continuously around the entire periphery of the side portion of the space. The inclined surface of the lateral space may include a portion that curves from the inside toward the outside. In addition, in a plan view, the lateral space may be formed on the side of a corner of the space that corresponds to a corner of the first lower surface of the substrate.

[0010] The present invention also provides a method for manufacturing a semiconductor device, including: a preparation step of preparing a substrate having a first lower surface and a sealing member; a sealing step of placing the first lower surface of the substrate on the sealing upper surface of a mold including a sealing upper surface having a size and shape similar to the first lower surface, a sealing lower surface facing the sealing upper surface, and a sealing side surface provided on a side of the sealing upper surface in a plan view and inclined downward from the sealing upper surface, thereby exposing the sealing lower surface and sealing the substrate and the mold with the sealing member; and a demolding step of releasing the mold after the sealing member has solidified.

[0011] The angle of the sealing side surface relative to the sealing top surface may be less than 45°. Furthermore, the preparation process may further include a bonding process in which a cooling module having an adhesive member and a cooling surface is prepared, and the first lower surface of the substrate exposed to the storage area formed after the mold of the sealing member is released is bonded to the cooling surface of the cooling module with the adhesive member.

[0012] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Effects of the Invention]

[0013] According to the disclosed technology, leakage of the adhesive member can be prevented. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a side view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a first cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a second cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] 2 is an enlarged view of a first cross section of the semiconductor device according to the first embodiment. FIG. [Figure 5] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 1 is a first diagram for explaining the assembly process of a semiconductor unit in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] FIG. 2 is a second diagram for explaining the assembly process of the semiconductor unit in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] FIG. 1 is a first diagram for explaining the sealing step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 3 is a diagram showing a storage mold used in a sealing step in the manufacturing method of the semiconductor device according to the first embodiment; FIG. [Figure 10]3 is a perspective view of a storage mold used in a sealing step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 11] FIG. 2 is a second diagram for explaining the sealing step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 3 is a third diagram for explaining the sealing step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] FIG. 4 is a fourth diagram for explaining the sealing step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 5A to 5C are diagrams for explaining an attachment step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 10 is an enlarged view of a first cross section of a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a second cross-sectional view of the semiconductor device according to the third embodiment. [Figure 17] FIG. 10 is a third cross-sectional view of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the XY plane facing upward (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "top" refers to the upward direction (+Z direction) in the semiconductor device 1 shown in the drawings. The terms "back surface" and "bottom surface" refer to the XY plane facing downward (-Z direction) in the semiconductor device 1 shown in the drawings. Similarly, the term "bottom" refers to the downward direction (-Z direction) in the semiconductor device 1 shown in the drawings. As necessary, the same directionality as above will be used in all drawings. The terms "higher" and "upper" refer to the upper position (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, the terms "lower" and "lower" refer to the lower position (-Z direction) in the semiconductor device 1 shown in the drawings. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. In the following description, "main component" refers to a component containing 80 vol% or more. Furthermore, "substantially the same" means that the difference is within a range of ±10%. Furthermore, "perpendicular," "orthogonal," and "parallel" means that the difference is within a range of ±10°. Furthermore, in the drawings, once a symbol is assigned to a component, the symbol may be omitted in subsequent drawings.

[0016] [First embodiment] A semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a side view of the semiconductor device according to the first embodiment. The semiconductor device 1 includes a semiconductor module 2 and a cooling module 3. Note that the semiconductor device 1 may include other necessary components in addition to these.

[0017] The components of the semiconductor module 2 are sealed with a sealing member 35. That is, the sealing member 35 forms the outer periphery of the semiconductor module 2. The outer periphery of the semiconductor module 2 has, for example, a rectangular parallelepiped shape. The semiconductor module 2 (sealing member 35) also includes a lower surface 35a (second lower surface). The sealing member 35 will be described in detail later.

[0018] The cooling module 3 has a cooling surface 3a on its upper surface on which the lower surface 35a of the semiconductor module 2 is placed. The cooling surface 3a is wider and flatter than the lower surface of the semiconductor module 2. The cooling module 3 may be, for example, a heat dissipation base equipped with heat dissipation fins, or a cooling device in which a refrigerant circulates inside.

[0019] Next, details of such a semiconductor module 2 will be described with reference to FIGS. 2 to 4. FIG. 2 is a first cross-sectional view of the semiconductor device of the first embodiment. FIG. 3 is a second cross-sectional view of the semiconductor device of the first embodiment. FIG. 4 is an enlarged view of the first cross-section of the semiconductor device of the first embodiment. Note that FIG. 2 is a cross-sectional view of FIG. 1 taken along the ZX plane at the center line in the ±Y directions and viewed in the +Y direction. FIG. 3 is a cross-sectional view taken along the dashed dotted line II in FIG. 2 (a rear view of the semiconductor module 2). FIG. 4 is an enlarged view of the vicinity including the lateral space 35f in FIG. 2. Also, FIGS. 2 and 3 show a case in which the adhesive member 4 is applied to the entire lower surface 22a of the insulating circuit board 20 of the semiconductor module 2.

[0020] As described above, the semiconductor device 1 includes a semiconductor module 2 and a cooling module 3. The semiconductor module 2 and the cooling module 3 are joined together with an adhesive member 4. In the semiconductor module 2, the semiconductor chips 10a, 10b, 10d, and 10e, the insulating circuit board 20, and the printed circuit board 30 are sealed with a sealing member 35. The structure of the semiconductor module 2 excluding the sealing member 35 is referred to as a semiconductor unit 25 (see FIG. 7 ). That is, the semiconductor unit 25 includes the semiconductor chips 10a, 10b, 10d, and 10e, the insulating circuit board 20, and the printed circuit board 30. In the semiconductor module 2, the semiconductor unit 25 is sealed with the sealing member 35. The semiconductor unit 25 may be provided with a main current terminal and a control terminal (not shown). The main current terminal and the control terminal may extend outside the sealing member 35.

[0021] The semiconductor chips 10a, 10b, 10d, and 10e may be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) primarily composed of silicon carbide. The body diode of the power MOSFET may function as a free wheeling diode (FWD). Each of the semiconductor chips 10a, 10b, 10d, and 10e may have, for example, an input electrode (drain electrode) as a main electrode on its bottom surface, and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on its top surface. The control electrode may be located at the center of one side of the top surface of the semiconductor chips 10a, 10b, 10d, and 10e or offset from the center along the side.

[0022] The semiconductor chips 10a, 10b, 10d, and 10e may also include a switching element primarily made of silicon. The switching element may be, for example, a reverse-conducting (RC)-IGBT (insulated gate bipolar transistor). The RC-IGBT is a semiconductor element in which an IGBT and a FWD are arranged in anti-parallel within a single chip. Each of the semiconductor chips 10a, 10b, 10d, and 10e has an input electrode (collector electrode) as a main electrode on its bottom surface and an output electrode (emitter electrode) and a control electrode (gate electrode) as main electrodes on its top surface. The control electrode may be located at the center of one side of the top surface of the semiconductor chip 10a, 10b, 10d, or 10e, or may be offset from the center along the side, as in the case of a power MOSFET.

[0023] Furthermore, for example, the semiconductor chips 10a, 10b, 10d, and 10e may be semiconductor chips mainly composed of silicon and each including a pair of switching elements and diode elements. Specifically, the semiconductor chips 10a and 10d may be switching elements, and the semiconductor chips 10b and 10e may be diode elements. The switching elements may be, for example, power MOSFETs or IGBTs. The semiconductor chips including the switching elements have, for example, an input electrode (a drain electrode in a power MOSFET or a collector electrode in an IGBT) as a main electrode on the bottom surface, and a gate electrode (a control electrode) and an output electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as main electrodes on the top surface. The diode elements may be, for example, Schottky Barrier Diodes (SBDs) or P-intrinsic-N (PiN) diodes used as FWDs. The semiconductor chips including the diode elements have, for example, an output electrode (a cathode electrode) as a main electrode on the bottom surface and an input electrode (anode electrode) as a main electrode on the top surface.

[0024] The semiconductor chips 10a, 10b and the semiconductor chips 10d, 10e are joined to the conductive patterns 23a, 23b (described later) with solder 12, respectively. The solder 12 is composed of solder components. The solder components are materials constituting the solder 12 and include lead-free solder primarily composed of a predetermined alloy. The predetermined alloy includes tin. Such alloys include, for example, at least one of a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, and a tin-antimony alloy. Furthermore, such solder components may include additives. Examples of additives include nickel, germanium, cobalt, or silicon. Therefore, examples of the solder components include at least one of silver, zinc, copper, bismuth, indium, and antimony, along with tin. Furthermore, the solder components may include, for example, at least one of nickel, germanium, cobalt, and silicon. The solder components of the solder 32, which will be described later, are the same as those of the solder 12. A sintered body may be used instead of the solder 12. The sintered material when joining with a sintered body is, for example, a powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum.

[0025] The insulating circuit board 20 includes an insulating plate 21, a metal plate 22, and conductive patterns 23a and 23b. The insulating plate 21 and the metal plate 22 are rectangular in plan view. The corners of the insulating plate 21 and the metal plate 22 may be round-chamfered or C-chamfered. The size of the metal plate 22 is smaller than the size of the insulating plate 21 in plan view and is formed inside the insulating plate 21. The top surface of the insulating circuit board 20 may be the area visible in plan view of the insulating circuit board 20. Specifically, it includes the top surfaces of conductive patterns 23a and 23b (described later) and the top surface of the insulating plate 21 excluding the conductive patterns 23a and 23b. The side surface of the insulating circuit board 20 may be the area visible from each of the four sides of the insulating circuit board 20 in side view. Specifically, this includes side surfaces surrounding the insulating plate 21 (described later) on all four sides, side surfaces surrounding the metal plate 22 on all four sides, and side surfaces surrounding the conductive patterns 23a and 23b on all four sides excluding the opposing side surfaces.

[0026] The insulating plate 21 is made of, for example, a resin. The resin may be a material with low thermal resistance and high insulation properties. An example of such a resin is a thermosetting resin. The thermosetting resin may further contain a filler. The thermal resistance of the insulating plate 21 can be further reduced by controlling the material and content of the filler. Furthermore, depending on the filler, the linear expansion coefficient of the insulating plate 21 can be made approximately equal to the linear expansion coefficients of the metal plate 22 and the conductive patterns 23a and 23b described below. By reducing the difference in linear expansion coefficients in this way, the insulating circuit board 20 can reduce the occurrence of warping caused by the difference in linear expansion coefficients even when the temperature changes.

[0027] Examples of such thermosetting resins include at least one of epoxy resin, cyanate resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenol resin, melamine resin, silicone resin, maleimide resin, acrylic resin, and polyamide resin. The filler is composed of at least one of an oxide and a nitride. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, the filler may be hexagonal boron nitride.

[0028] The insulating plate 21 may be a ceramic substrate instead of a resin. The ceramic substrate is made of ceramic with good thermal conductivity. The ceramic is made of a material whose main components are, for example, aluminum oxide, aluminum nitride, or silicon nitride. The insulating circuit board 20 including the insulating plate 21 having such a configuration can be, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate.

[0029] In this embodiment, insulating plate 21 is made of resin, and the difference between the linear expansion coefficient of insulating plate 21 and the linear expansion coefficient of metal plate 22 and conductive patterns 23a and 23b is small.

[0030] The metal plate 22 is made of a metal with excellent thermal conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. In this example, copper is included. Furthermore, to improve corrosion resistance, the surface of the metal plate 22 may be plated. In this case, the plating material includes nickel. Examples of such plating materials include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The lower surface 22a (first lower surface) of the metal plate 22 also serves as the lower surface of the insulating circuit board 20. The lower surface 22a of the metal plate 22 is located above the lower surface 35a of the sealing member 35, and is entirely exposed from the sealing member 35. That is, the lower surface 35a of the sealing member 35 is located below the lower surface 22a of the metal plate 22. The lower surface 22a of the metal plate 22 and the lower surface 35a of the sealing member 35 are substantially parallel to each other. Furthermore, the thickness of the metal plate 22 may be 3 times or more and 15 times or less the thickness of the insulating plate 21 when the insulating plate 21 is made of resin.

[0031] The conductive patterns 23a and 23b are provided with the semiconductor chips 10a and 10b and the semiconductor chips 10d and 10e, respectively. The conductive patterns 23a and 23b are formed over the entire surface of the insulating plate 21 except for the edges. Preferably, in a plan view, the ends of the conductive patterns 23a and 23b facing the outer periphery of the insulating plate 21 overlap with the outer periphery of the metal plate 22. This maintains a stress balance between the insulating circuit board 20 and the metal plate 22 on the underside of the insulating plate 21. Damage to the insulating plate 21, such as excessive warping and cracking, is further suppressed.

[0032] The conductive patterns 23a, 23b are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The conductive patterns 23a, 23b can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The conductive patterns 23a, 23b for the insulating plate 21 are obtained by forming a metal plate on the upper surface of the insulating plate 21 and then etching or other processes on the metal plate. Alternatively, the conductive patterns 23a, 23b may be cut out from a metal plate in advance and bonded to the upper surface of the insulating plate 21. The conductive patterns 23a, 23b included in the semiconductor device 1 are merely an example. The number, shape, size, and other factors of the conductive patterns may be appropriately selected as needed.

[0033] The printed circuit board 30 includes an insulating layer and multiple upper circuit pattern layers formed on the upper surface of the insulating layer. The printed circuit board 30 may also include multiple lower circuit pattern layers on the lower surface of the insulating layer. This type of printed circuit board 30 faces the upper surface of the insulating circuit board 20 in a plan view. This type of printed circuit board 30 is electrically connected to the output electrodes, input electrodes, and control electrodes of the semiconductor chips 10a, 10b, 10d, and 10e. The implant pins 31a, 31b, 31d, and 31e shown in FIG. 2 are merely examples, and may also include implant pins not shown in FIG. 2. The upper portions of the implant pins 31a, 31b, 31d, and 31e, along with the implant pins not shown, are electrically connected to the upper and lower circuit pattern layers of the printed circuit board 30, and the lower portions are connected to the output and control electrodes of the semiconductor chips 10a, 10b, 10d, and 10e by solder 32.

[0034] For example, the printed circuit board 30 is electrically connected to the output electrodes on the upper surfaces of the semiconductor chips 10a and 10b through implant pins 31a and 31b, and to the output electrodes on the upper surfaces of the semiconductor chips 10d and 10e through implant pins 31d and 31e.

[0035] The printed circuit board 30 is electrically connected to the input electrodes on the undersides of the semiconductor chips 10a and 10b via implant pins 31c and conductive patterns 23a, and is also electrically connected to the input electrodes on the undersides of the semiconductor chips 10d and 10e via implant pins 31f and conductive patterns 23b.

[0036] The printed circuit board 30 is electrically connected to the control electrodes of the semiconductor chips 10a and 10b via implant pins (not shown) and to the control electrodes of the semiconductor chips 10d and 10e via conductive posts (not shown).

[0037] Semiconductor unit 25 includes the above-described semiconductor chips 10a, 10b, 10d, and 10e, insulating circuit board 20, and printed circuit board 30. Note that semiconductor unit 25 is not limited to the configuration shown in FIG. 2 (and FIG. 7) as long as it realizes a circuit configuration that realizes a desired function.

[0038] The sealing member 35 seals the entire insulating circuit board 20, semiconductor chips 10a, 10b, 10d, and 10e, solders 12 and 32, printed circuit board 30, and implant pins 31a, 31b, 31c, 31d, 31e, and 31f. The sealing member 35 has a rectangular parallelepiped shape and includes a lower surface 35a and an upper surface 35b. The lower surface 35a and the upper surface 35b have the same shape and form a rectangular shape in a plan view. The sealing member 35 also includes side surfaces 35c1, 35c2, 35c3, and 35c4 that surround the lower surface 35a and the upper surface 35b on all four sides. The side surfaces 35c1 and 35c3 extend along the longitudinal direction (±X direction) of the sealing member 35, and the side surfaces 35c2 and 35c4 extend along the lateral direction (±Y direction) of the sealing member 35. Side surfaces 35c1, 35c2, 35c3, and 35c4 are connected to the lower surface 35a and the upper surface 35b, respectively. The side surfaces 35c1, 35c2, 35c3, and 35c4 are also connected to each other. Each connection point may be round-chamfered or C-chamfered.

[0039] The lower surface 35a of the sealing member 35 is located lower than the lower surface 22a of the insulating circuit board 20. The lower surface 35a of the sealing member 35 is opened to expose the entire lower surface 22a of the insulating circuit board 20, and includes a space 35e below the lower surface 22a. In plan view, the space 35e has the same shape and size as the lower surface 22a of the insulating circuit board 20. The thickness (height) of the space 35e is the height of the gap between the lower surface 22a of the insulating circuit board 20 and the lower surface 35a of the sealing member 35. That is, as shown in FIG. 2 , it is the gap between the lower surface 22a of the insulating circuit board 20 and the cooling surface 3a of the cooling module 3.

[0040] Furthermore, the sealing member 35 has horizontal spaces 35f formed on the sides of the space 35e, which are connected to the space 35e. The horizontal spaces 35f may be formed on any of the sides of the space 35e. In this embodiment, as an example, the horizontal spaces 35f are configured to surround the space 35e on all four sides and protrude outward from all of the sides. In this case, the horizontal spaces 35f may be connected to each other.

[0041] The upper portion of horizontal space 35f is defined by inclined surfaces 35f1, 35f2, 35f3, and 35f4 (in FIG. 4, inclined surface 35f2 is shown) that slope downward from space 35e toward the side (outside). Upper end edges 35g1, 35g2, 35g3, and 35g4 of inclined surfaces 35f1, 35f2, 35f3, and 35f4 are connected to the respective sides of lower surface 22a of insulating circuit board 20, and lower end edges 35h1, 35h2, 35h3, and 35h4 of inclined surfaces 35f1, 35f2, 35f3, and 35f4 are connected to the lower surface 35a of sealing member 35, respectively.

[0042] That is, storage area 35d, which is a combination of space 35e and lateral space 35f, is opened (formed) on lower surface 35a of sealing member 35. Storage area 35d has a quadrangular pyramid shape surrounded by an area surrounded by lower surface 22a of insulating circuit board 20 and the lower edges of inclined surfaces 35f1, 35f2, 35f3, and 35f4, and by inclined surfaces 35f1, 35f2, 35f3, and 35f4.

[0043] The inclined surfaces 35f1, 35f2, 35f3, and 35f4 may be angled at less than 45° with respect to the lower surface 35a of the sealing member 35. Furthermore, the lower surface 22a of the insulating circuit board 20 is exposed to the space 35e without protruding from the upper end edges 35g1, 35g2, 35g3, and 35g4 of the inclined surfaces 35f1, 35f2, 35f3, and 35f4 toward the space 35e.

[0044] Furthermore, the lower end edges 35h1, 35h2, 35h3, and 35h4 of the inclined surfaces 35f1, 35f2, 35f3, and 35f4 may be positioned so that the horizontal space 35f can maintain a predetermined volume. As described below, the adhesive member 4 expands into the horizontal space 35f. At this time, the horizontal space 35f may have a volume that can reliably accommodate the expanded adhesive member 4. For example, the lower end edges 35h1, 35h2, 35h3, and 35h4 of the inclined surfaces 35f1, 35f2, 35f3, and 35f4 are preferably spaced from the side of the space 35e by at least the height of the space 35e. Furthermore, in this embodiment, the storage area 35d has a rectangular shape in a plan view. The corners of the storage area 35d may be rounded or chamfered.

[0045] Such a sealing member 35 may be a thermosetting resin containing a filler. That is, the sealing member 35 is composed mainly of an insulating filler (described later) and a resin (thermosetting resin). In this case, the thermosetting resin is, for example, an epoxy resin, a phenolic resin, a maleimide resin, or a polyester resin. The filler may be mainly composed of an insulating ceramic having high thermal conductivity. Such a filler is, for example, silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. The content of the filler is 10% by volume or more and 70% by volume or less of the entire sealing member 35.

[0046] In the semiconductor module 2, an adhesive member 4 is provided on the lower surface 22a of the insulating circuit board 20 within the space 35e. In the semiconductor device 1, the cooling module 3 is attached to the lower surface 35a of the semiconductor module 2 via the adhesive member 4.

[0047] The adhesive member 4 is provided in the space 35e between the lower surface 22a of the insulating circuit board 20 of the semiconductor module 2 and the cooling surface 3a of the cooling module 3, and bonds the lower surface 22a of the insulating circuit board 20 of the semiconductor module 2 to the cooling surface 3a of the cooling module 3. In this way, the adhesive member 4 fixes the semiconductor module 2 and the cooling module 3 and also thermally connects the metal plate 22 to the cooling module 3. It is sufficient for the adhesive member 4 to be in contact with at least the entire lower surface 22a of the metal plate 22 of the semiconductor module 2. The adhesive member 4 shown in FIG. 4 is in contact with the entire lower surface 22a of the metal plate 22 of the semiconductor module 2 and also protrudes into the lateral space 35f.

[0048] The adhesive member 4 is an organic resin adhesive whose main component is a thermosetting resin and contains a conductive filler (not shown). Examples of the thermosetting resin include epoxy resin, phenol resin, and polyimide resin. Here, epoxy resin is used.

[0049] The filler of the adhesive member 4 may contain a conductive metal. Examples of the metal include silver, copper, gold, nickel, chromium, aluminum, and alloys containing at least one of these. The filler may be, for example, spherical or flake-shaped. The filler may contain such a metal as a main component, and may also contain an inorganic filler in addition to the metal. Examples of such inorganic fillers include highly insulating and highly thermally conductive ceramics. Examples of ceramics include at least one of aluminum oxide, aluminum nitride, silicon nitride, and boron nitride.

[0050] The filler may connect the lower surface 22a of the metal plate 22 and the cooling surface 3a of the cooling module 3 within the adhesive member 4. That is, the filler forms a thermal path between the lower surface 22a of the metal plate 22 and the cooling surface 3a of the cooling module 3. This improves the thermal conductivity of the metal plate 22 with respect to the cooling module 3. The filler may also include a sintered portion within the adhesive member 4. The adhesive member 4 must have low thermal resistivity (high thermal conductivity) and therefore must be as thin as possible. However, if the thickness is less than 50 μm, the stress in the adhesive member 4 increases. This thickness may be, for example, 50 μm or more and 300 μm or less. A non-adhesive thermally conductive material may be used instead of the adhesive member 4. In this case, the thermally conductive material may be thermally conductive grease, elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, or phase change material.

[0051] Next, a method for manufacturing the semiconductor device 1 shown in FIGS. 1 and 2 will be described with reference to FIG. 5. FIG. 5 is a flowchart showing the manufacturing method of the semiconductor device according to the first embodiment. First, a preparation step is performed to prepare components of the semiconductor device 1 (step P1). Examples of the components prepared here include the semiconductor chips 10a, 10b, 10d, and 10e that constitute the semiconductor module 2, the insulating circuit board 20, the printed circuit board 30 with implant pins 31a, 31b, 31c, 31d, 31e, and 31f, and the sealing member 35. Another example is the cooling module 3. Components not listed here that are necessary for manufacturing the semiconductor device 1 may also be prepared. Manufacturing equipment used in manufacturing the semiconductor device 1 may also be prepared. Examples of the manufacturing equipment include a coating device that coats solder and a molding device that seals with a sealing member.

[0052] Next, a semiconductor unit assembling process is performed to assemble the semiconductor unit 25 (process P2). This semiconductor unit assembling process will be described with reference to FIGS. 6 and 7. FIG. 6 is a first diagram for explaining the semiconductor unit assembling process in the semiconductor device manufacturing method of the first embodiment. FIG. 7 is a second diagram for explaining the semiconductor unit assembling process in the semiconductor device manufacturing method of the first embodiment. Note that FIGS. 6 and 7 correspond to the cross section of FIG. 2.

[0053] Semiconductor chips 10a, 10b, 10d, and 10e are joined to conductive patterns 23a and 23b of insulating circuit board 20 via solder 12. Conventional solder joining is used for this joining. As a result, a structure is obtained in which semiconductor chips 10a and 10b are joined to conductive pattern 23a of insulating circuit board 20 via solder 12, and semiconductor chips 10d and 10e are joined to conductive pattern 23b via solder 12, as shown in FIG.

[0054] Thereafter, implant pins 31a, 31b, 31c, 31d, 31e, and 31f of printed circuit board 30 are bonded to semiconductor chips 10a and 10b, conductive pattern 23a of insulating circuit board 20, semiconductor chips 10d and 10e, and conductive pattern 23b of insulating circuit board 20.

[0055] The printed circuit board 30 is provided with implant pins 31a, 31b, 31c, 31d, 31e, and 31f in advance. These implant pins 31a, 31b, 31c, 31d, 31e, and 31f are joined by conventional soldering. As a result, as shown in FIG. 7, the printed circuit board 30 is attached to the insulating circuit board 20 to which the semiconductor chips 10a, 10b, 10d, and 10e are joined, thereby obtaining the semiconductor unit 25.

[0056] Next, an encapsulation step is performed to encapsulate the semiconductor unit 25 (step P3). The encapsulation step will be described with reference to FIGS. 8 to 13. FIG. 8 is a first diagram for explaining the encapsulation step of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 9 is a diagram showing a storage mold used in the encapsulation step of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 10 is a perspective view of the storage mold used in the encapsulation step of the method for manufacturing a semiconductor device according to the first embodiment. Also, FIGS. 11 to 13 are second to fourth diagrams for explaining the encapsulation step of the method for manufacturing a semiconductor device according to the first embodiment.

[0057] The sealing step of step P3 includes the following steps. First, the semiconductor unit 25 obtained in step P2 is set in a mold 50, for example, as shown in FIG. 8 (step P3a). The mold 50 includes an outer casing 51 and a storage portion 52. The mold 50 is made of a heat-resistant material with a small thermal expansion coefficient. An example of such a material is steel. Another example of the steel material is stainless steel. The inner surface of such a mold 50 may be coated with a material that has high releasability against the sealing member 35.

[0058] The outer casing 51 has a box shape, and an internal cavity 51a is surrounded by an upper surface 51b, a lower surface 51c, and sealing surfaces (sealing surfaces 51d2 and 51d4 are shown in FIG. 8 ) that surround the four sides of the upper surface 51b and the lower surface 51c in that order. The cavity 51a corresponds to the shape of the sealing member 35 of the semiconductor module 2. The outer casing 51 may have a gate (not shown) formed on one of its surfaces through which a sealing material, which is a raw material of the sealing member 35, is injected. Although details of the outer casing 51 are omitted, for example, a lid including the upper surface 51b may be provided so as to be able to open and close. When the semiconductor unit 25 is to be stored in the outer casing 51, the lid is opened, and the lid is closed once the semiconductor unit 25 is stored. This function of the outer casing 51 to store the semiconductor unit 25 is one example, and another mechanism may be used.

[0059] The storage portion 52 is provided on the lower surface 51c of the surrounding portion 51. The storage portion 52 may be integrally formed with the lower surface 51c of the surrounding portion 51. The storage portion 52 and the surrounding portion 51 may be made of the same material. The storage portion 52 has a shape that combines the space 35e and the lateral space 35f of the semiconductor module 2. This shape may be, for example, a quadrangular pyramid shape. Specifically, as shown in FIGS. 9 and 10, the storage portion 52 includes a sealed upper surface 52b, a lower surface 52c, and sealed side surfaces 52d1, 52d2, 52d3, and 52d4 that surround these surfaces on all four sides. The sealed upper surface 52b has the same size and shape as the lower surface 22a of the insulating circuit board 20. The sealed side surfaces 52d1, 52d2, 52d3, and 52d4 may be angled less than 45° with respect to the lower surface 52c.

[0060] The semiconductor unit 25 is placed on the sealed upper surface 52b of the storage section 52 in the outer casing 51 of the mold 50 having such a configuration (see FIG. 8). In this manner, the semiconductor unit 25 is set in the cavity 51a of the mold 50 and housed in the mold 50.

[0061] Next, the cavity 51a of the mold 50 in which the semiconductor unit 25 was housed in step P3a is filled with a sealing material to seal the semiconductor unit 25 (step P3b). At this time, the mold 50 is maintained in a heated state, and the molten sealing material is filled. When the entire cavity 51a is filled with the sealing material, the heating of the mold 50 is stopped, and the mold 50 is cooled and the sealing material is solidified. As a result, the semiconductor unit 25 is sealed in the mold 50 by the sealing member 35, as shown in FIG.

[0062] Next, the mold 50 is released from the semiconductor unit 25 sealed with the sealing member 35 in step P3b (step P3c). For example, a lid portion including the upper surface 51b of the outer casing 51 of the mold 50 is removed, and the mold 50 is released from the semiconductor module 2 in which the semiconductor unit 25 is sealed with the sealing member 35. Specifically, as shown in FIG. 12, the mold 50 is released in the -Z direction. The sealing side surfaces 52d1, 52d2, 52d3, and 52d4 of the storage portion 52 are connected at an obtuse angle to the sealing upper surface 52b. Therefore, when the mold 50 is released from the semiconductor module 2, the storage portion 52 can also be easily released from the sealing member 35.

[0063] In this manner, the semiconductor module 2 is obtained. On the underside 35a of the semiconductor module 2 obtained in this manner, a space 35e is formed in the center and lateral spaces 35f are formed around the space 35e, as shown in Fig. 13. In addition, the underside 22a of the insulating circuit board 20 is exposed from the space 35e of the semiconductor module 2.

[0064] Next, an application step is performed in which an adhesive material is applied to the back side of the semiconductor module 2 (step P4). The adhesive material 4 is applied to the entire lower surface 22a of the insulating circuit board 20 that is exposed from the space 35e of the semiconductor module 2. The adhesive material 4 applied at this time may have a thickness that exceeds, for example, the thickness that extends from the lower surface 22a of the insulating circuit board 20 to the lower surface 35a of the sealing member 35. Note that the adhesive material 4 may also be applied to the cooling surface 3a side of the cooling module 3, rather than the semiconductor module 2 side.

[0065] Next, an attachment step (bonding step) of attaching the semiconductor module 2 to the cooling module 3 is performed (step P5). The attachment step will be described with reference to Fig. 14. Fig. 14 is a diagram for explaining the attachment step in the method for manufacturing the semiconductor device according to the first embodiment.

[0066] The semiconductor module 2 to which the adhesive material 4 has been applied in step P4 is placed on the cooling surface 3a of the cooling module 3, as shown in FIG. 14. Then, the adhesive material 4 is sandwiched between the lower surface 22a of the insulating circuit board 20 and the cooling surface 3a of the cooling module 3, and a portion of the adhesive material 4 spreads outward from the space 35e. The semiconductor module 2 has lateral spaces 35f formed on all four sides of the space 35e. Therefore, the adhesive material 4 spreading to the sides of the space 35e is stored in the lateral spaces 35f (see, for example, FIG. 4). Therefore, in the semiconductor device 1, even when the semiconductor module 2 and the cooling module 3 are joined, the adhesive material 4 is prevented from leaking outward from between the lower surface 35a of the semiconductor module 2 and the cooling surface 3a of the cooling module 3.

[0067] 5, the semiconductor device 1 is obtained in which the cooling module 3 is attached to the semiconductor module 2. Note that the configuration of the semiconductor device 1 is an example, and in particular, the semiconductor unit 25 may have a different structure.

[0068] The semiconductor device 1 includes a semiconductor module 2 having an insulating circuit board 20 having a lower surface 22a, and a sealing member 35 that seals the upper and side surfaces of the insulating circuit board 20 and has a lower surface 35a located below the lower surface 22a of the insulating circuit board 20, with the lower surface 35a being open to expose the entire lower surface 22a, and including a space 35e below the lower surface 22a. The sealing member 35 also has a lateral space 35f formed on the side of the space 35e, which is connected to the space 35e. The upper portion of the lateral space 35f is defined by inclined surfaces 35f1, 35f2, 35f3, and 35f4 that slope downward from the space 35e toward the side. When the semiconductor module 2 is attached to the cooling surface 3a of the cooling module 3 via an adhesive member 4 provided on the lower surface 22a of the insulating circuit board 20, the semiconductor module 2 remains contained within the lateral space 35f even if the adhesive member 4 expands. Therefore, in the semiconductor device 1, leakage to the outside from between the lower surface 35a of the semiconductor module 2 and the cooling surface 3a of the cooling module 3 is prevented.

[0069] For example, if the semiconductor module 2 does not include the lateral space 35f, the adhesive member 4 sandwiched between the lower surface 22a of the insulating circuit board 20 of the semiconductor module 2 and the cooling surface 3a of the cooling module 3 may leak out of the semiconductor device 1 through the gap between the lower surface 35a of the semiconductor module 2 (sealing member 35) and the cooling surface 3a. If the adhesive member 4 leaks out, it will adhere to the periphery of the semiconductor device 1. In this case, if the filler material of the adhesive member 4 is a conductive metal, the leaked adhesive member 4 will adhere to the side surface of the semiconductor module 2, thereby reducing the insulation distance and thereby reducing the insulation. If the insulation is not maintained in this way, the reliability of the semiconductor device 1 will be reduced.

[0070] On the other hand, the semiconductor module 2 of the present embodiment includes the lateral space 35f, which prevents the adhesive member 4 from leaking out, and therefore the adhesive member 4 may include a filler made of a conductive metal. This improves the thermal conductivity of the adhesive member 4, and improves the heat dissipation of the semiconductor device 1.

[0071] Furthermore, the adhesive member 4 may be applied so as to fill the space 35e and the lateral space 35f when the semiconductor module 2 is attached to the cooling surface 3a of the cooling module 3. In this case, the upper surface of the adhesive member 4 extends at an angle of less than 45° from the outer edge of the lower surface 22a of the insulating circuit board 20. By applying the adhesive member 4 in this manner, heat from the lower surface 22a of the insulating circuit board 20 is conducted through the adhesive member 4 with a 45° diffusion. Compared to the case where only the space 35e is present, the inclusion of the lateral space 35f expands the range of the adhesive member 4, improving the heat dissipation of the semiconductor device 1.

[0072] [Second embodiment] A semiconductor device according to a second embodiment will be described with reference to Fig. 15. Fig. 15 is an enlarged view of a first cross section of the semiconductor device according to the second embodiment. Fig. 15 is an enlarged view of a cross section of the semiconductor device 1a according to the second embodiment, which corresponds to Fig. 4.

[0073] In the semiconductor device 1a of the second embodiment, the inclined surfaces 35f1, 35f2, 35f3, and 35f4 of the horizontal space 35f included in the semiconductor module 2 include portions that curve from the inside to the outside. Note that the semiconductor device 1a of the second embodiment has the same configuration as the semiconductor device 1 of the first embodiment except for the inclined surfaces 35f1, 35f2, 35f3, and 35f4 of the horizontal space 35f.

[0074] For example, the inclined surface 35f2 of the horizontal space 35f shown in Figure 15 inclines downward from the space 35e (the edge of the lower surface 22a of the insulating circuit board 20) toward the side (-X direction), bends midway, and extends to the lower surface 35a.

[0075] The adhesive member 4 may spread from the space 35e into the lateral space 35f, filling the lateral space 35f with the adhesive member 4. In this case, the inclined surface 35f2 includes a curved portion, so the adhesive member 4 can sufficiently spread throughout the lateral space 35f. This prevents voids from forming in the lateral space 35f filled with the adhesive member 4. Therefore, in the semiconductor device 1a, even if the adhesive member 4 spreading from the space 35e fills the lateral space 35f, the generation of voids is prevented, and a decrease in heat dissipation performance is prevented.

[0076] For example, if the bent portion of the inclined surface 35f2 is higher than the lower surface 22a of the insulating circuit board 20, it will be difficult to release the mold 50 (step P3c) during the sealing step (step P3). For this reason, even if the inclined surface 35f2 of the lateral space 35f is bent partway, it is preferable that the inclined surface 35f2 be inclined downward from the space 35e (the edge of the lower surface 22a of the insulating circuit board 20) toward the side (in the -X direction).

[0077] [Third embodiment] In the third embodiment, a case will be described in which horizontal spaces 35f are provided at the corners of space 35e in a plan view. Such a semiconductor device according to the third embodiment will be described with reference to FIGS. 16 and 17. FIG. 16 is a second cross-sectional view of the semiconductor device according to the third embodiment. FIG. 17 is a third cross-sectional view of the semiconductor device according to the third embodiment. Note that FIG. 16 is a cross-section of semiconductor device 1b according to the third embodiment, corresponding to FIG. 3. FIG. 17 shows a cross-section taken along dashed line II-II in FIG. 16. Furthermore, since the cross-section taken along dashed line III-III in FIG. 16 corresponds to the cross-section of semiconductor module 2 in FIG. 2, FIG. 2 can be referenced.

[0078] 16 and 2, in the sealing member 35 included in the semiconductor module 2 of the semiconductor device 1b according to the third embodiment, horizontal spaces 35f are formed on the sides of the corners of the space 35e that correspond to the corners of the underside 22a of the insulating circuit board 20 in a plan view. While the horizontal spaces 35f are preferably formed so as to include the corners of the space 35e in a plan view as shown in FIG. 16, they may be formed on only one of the two sides that form the corners of the space 35e in a plan view as long as they are connected to the corners of the space 35e. Furthermore, in the semiconductor module 2, the areas in which the horizontal spaces 35f are not formed, excluding the corners of the space 35e in a plan view, are surrounded by the sealing member 35 as shown in FIG. 17.

[0079] The horizontal space 35f of the third embodiment also has an inclined surface (reference numeral omitted) at its upper portion that slopes downward from the space 35e toward the side (outside). Therefore, Fig. 16 merely illustrates a case in which the horizontal space 35f has a rectangular shape in a plan view, but the shape need not be rectangular. Furthermore, the corners of the horizontal space 35f may be rounded in a plan view.

[0080] In this semiconductor device 1b, the semiconductor module 2 coated with the adhesive material 4 is placed on the cooling surface 3a of the cooling module 3, and the spreading adhesive material 4 flows into the lateral space 35f connected to the corner of the space 35e. Therefore, similar to the first embodiment, in the semiconductor device 1b, the adhesive material 4 is prevented from leaking out from between the lower surface 35a of the semiconductor module 2 and the cooling surface 3a of the cooling module 3. Note that FIG. 16 shows a case where the adhesive material 4 is coated over the entire lower surface 22a of the insulating circuit board 20 of the semiconductor module 2.

[0081] Furthermore, in semiconductor device 1b, temperature changes occur in response to the operation of semiconductor chips 10a, 10b, 10d, and 10e. Consequently, stress may be generated at the corners of insulating circuit board 20 due to differences in the linear expansion coefficients of the components. This increases the likelihood that the corners of bottom surface 22a of insulating circuit board 20 will peel off from adhesive member 4. Such peeling reduces the heat dissipation performance of semiconductor device 1b.

[0082] However, in the semiconductor module 2 of the semiconductor device 1b, the horizontal space 35f is formed to include the corners of the space 35e in a plan view. Therefore, when the semiconductor module 2, to which the adhesive material 4 is applied, is attached to the cooling module 3, the spreading adhesive material 4 flows from the space 35e into the horizontal space 35f at the corners. This reduces the occurrence of peeling of the adhesive material 4 at the corners of the underside 22a of the insulating circuit board 20. As a result, a decrease in the heat dissipation performance of the semiconductor device 1b can also be suppressed.

[0083] In consideration of the semiconductor devices 1 and 1b of the first and third embodiments, it is preferable that the semiconductor module 2 has horizontal spaces 35f formed at least at the corners of the space 35e in a plan view, the horizontal spaces 35f being connected to the space 35e.

[0084] Furthermore, the configurations disclosed in the above embodiments can be combined as appropriate within the scope of not causing any contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0085] 1, 1a, 1b Semiconductor device 2. Semiconductor Module 3 Cooling Module 3a Cooling surface 4 Adhesive material 4a Filler 10a, 10b, 10d, 10e Semiconductor chips 12 Solder 20 Insulated circuit board 21 Insulating plate 22 Metal plate 22a Bottom surface (first bottom surface) 23a, 23b Conductive patterns 25 Semiconductor Unit 30 Printed Circuit Board 31a, 31b, 31c, 31d, 31e, 31f Implant pins 32 Solder 35 Sealing member 35a Lower surface (2nd lower surface) 35b Top surface 35c1,35c2,35c3,35c4 Side 35d Storage area 35e space 35f horizontal space 35f1,35f2,35f3,35f4 Slope 35g1, 35g2, 35g3, 35g4 top edge 35h1, 35h2, 35h3, 35h4 bottom edge 50 molds 51 Outer enclosure 51a cavity 51b Top side 51c Bottom 51d2,51d4 Sealing surface 52 Storage Department 52b Seal above Below 52c 52d1, 52d2, 52d3, 52d4 Side sealing

Claims

1. a substrate having a first lower surface; a sealing member that seals the upper and side surfaces of the substrate, has a second lower surface located below the first lower surface of the substrate, the second lower surface being open to expose the entire first lower surface, and has a space below the first lower surface; and The sealing member has a lateral space formed on a side of the space, the lateral space being connected to the space, The upper portion of the lateral space is defined by an inclined surface that slopes downward from the space toward the side. Semiconductor device.

2. a cooling module having a cooling surface on which the second lower surface of the sealing member is disposed; a thermally conductive material provided in the space of the sealing member and between the first lower surface of the substrate and the cooling surface; The semiconductor device according to claim 1 , further comprising:

3. The thermally conductive material is an adhesive material. The semiconductor device according to claim 2 .

4. a cooling module having a cooling surface on which the second lower surface of the sealing member is disposed; an adhesive member provided in the space of the sealing member and joining the first lower surface of the substrate and the cooling surface; The semiconductor device according to claim 1 , further comprising:

5. The adhesive member includes a conductive filler. The semiconductor device according to claim 4 .

6. The edge of the adhesive member extends from the space to the lateral space. The semiconductor device according to claim 4 .

7. The angle of the inclined surface relative to the second lower surface is less than 45°. The semiconductor device according to claim 1 .

8. The sealing member has the lateral space formed continuously around the entire periphery of the side portion of the space. The semiconductor device according to claim 1 .

9. The inclined surface of the lateral space includes a portion curved from the inside to the outside. The semiconductor device according to claim 1 .

10. In a plan view, the lateral space is formed on a side of a corner of the space corresponding to a corner of the first lower surface of the substrate. The semiconductor device according to claim 1 .

11. a preparation step of preparing a substrate having a first lower surface and a sealing member; a sealing step of placing the first lower surface of the substrate on the upper sealing surface of a mold including a sealing upper surface having a size and shape similar to that of the first lower surface, a sealing lower surface facing the sealing upper surface, and a sealing side surface provided on a side of the sealing upper surface in a plan view and inclined downward from the sealing upper surface, and exposing the sealing lower surface to seal the substrate and the mold with the sealing member; a demolding step of demolding the mold after the sealing member is solidified; A method for manufacturing a semiconductor device having the above structure.

12. The angle of the sealing side surface relative to the sealing top surface is less than 45°. The method for manufacturing a semiconductor device according to claim 11 .

13. In the preparation step, a cooling module having an adhesive member and a cooling surface is further prepared; a bonding step of bonding the first lower surface of the substrate, which is exposed in a storage area formed after the mold for the sealing member is released, to the cooling surface of the cooling module with the adhesive member; The method for manufacturing a semiconductor device according to claim 11, further comprising:

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