Method of plasma dicing a semiconductor wafer

Abstract

To provide a plasma dicing method for reducing deposition of an undesirable polymer material on a die adjacent to a side surface of a mask and / or an etching region.SOLUTION: The method includes providing a semiconductor wafer 103 comprising a thick silicon substrate layer 107 and a top silicon oxide layer 109 covered with an organic soft mask. The polymer organic mask 111 defines a plurality of scribe line regions 113 to be etched. The method also includes plasma etching to remove the top silicon-oxide layer in the scribe-line area to expose the thick silicon substrate layer, wherein the plasma etching is performed using an etching chemistry including a gaseous SF6 gas mixed with gaseous Ar. The method further includes plasma etching to remove the thick silicon substrate layer in the scribe line region to provide a plurality of individual semiconductor dies.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for plasma dicing a semiconductor wafer, and in particular to a method for plasma dicing a semiconductor wafer by inductively coupled plasma reactive ion (ICP-RIE) etching through an organic mask. The present invention also relates to a plasma etching apparatus configured to perform the method for plasma dicing a semiconductor wafer. [Background technology]

[0002] During the fabrication of semiconductor or microelectromechanical systems (MEMS) devices on a semiconductor wafer, a wafer dicing or scribing process is required to separate the wafer into individual dies (i.e., semiconductor chips). Prior to the wafer dicing or scribing process, the wafer is attached to a support structure to support the separated dies after singulation. Once the singulation operation is complete, the individual dies can be removed from the support structure, tested, and incorporated into packaged devices.

[0003] The division of a semiconductor wafer into individual dies can be achieved by mechanical scribing, cutting, laser scribing, plasma etching, or a combination of such techniques.

[0004] However, it has been found that both scribing and cutting wafers can create scratches or other defects along the edges of the separated dies. Such defects can be problematic, for example, in applications requiring hybrid and fusion bonding of dies, where surfaces must be very smooth, typically less than 1 nm. The presence of minute particles can result in poor bonding between the dies. Cleanliness is crucial. Additionally, cracks can form and propagate from the edge of the die to the substrate, rendering the integrated circuits located thereon inoperable. The problem of chip and crack propagation necessitates additional spacing between dies on the wafer to prevent damage to the integrated circuits.

[0005] The increased spacing requirements effectively reduce the economic value obtained from the wafer.

[0006] A more recent approach to separating die on a semiconductor wafer utilizes plasma etching of the wafer in defined patterns (e.g., orthogonal "streets" or "lanes"). Plasma dicing has been found to reduce damage to the edges of the die. As a result, narrower cuts can be achieved, thereby providing for denser placement of die on the wafer. Furthermore, plasma dicing makes it possible to fabricate die with different shapes and layouts that cannot be achieved with mechanical scribing.

[0007] Dicing a wafer using plasma requires first coating the wafer with a mask to define the dicing pattern (i.e., multiple etching regions). The mask may be a hard mask formed from a material such as silicon nitride, or an organic soft mask. Advantageously, using a soft mask allows a resist mask to be applied directly onto the silicon oxide layer, thereby saving costs. In applications, the mask is typically a photoresist mask applied via a photolithography process to form the dicing pattern. After etching according to the dicing pattern to create deep channels in the wafer, the mask is removed in a strip process.

[0008] A drawback of plasma dicing using an organic mask is the deposition of undesired polymer material on the sides of the mask and / or on the die adjacent to the etching area. During the etching process, inorganic substances such as fluorine compounds and / or elements such as silicon can become incorporated into the polymer deposit. When the mask is removed, residue can remain near the mask's open areas, exposing the filaments. The filaments are difficult to remove and can become an obstacle. Furthermore, the fluorine present in the filaments can pose a corrosion concern to the exposed metal areas of the die. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Patent Application Publication No. 2005 / 0037608 [Patent Document 2] U.S. Patent Application Publication No. 2015 / 0115417 Summary of the Invention [Problem to be solved by the invention]

[0010] There is a need for an improved method for plasma dicing of semiconductor wafers that alleviates the above-mentioned problems. [Means for solving the problem]

[0011] According to a first aspect of the present invention, a method for plasma dicing a semiconductor wafer is provided. The method includes providing a semiconductor wafer including a primary silicon layer and an upper silicon oxide layer. The upper silicon oxide layer is covered with an organic soft mask, the mask defining a plurality of scribe line regions to be etched. The method includes plasma etching to remove the upper silicon oxide layer in the scribe line regions to expose the primary silicon layer, the plasma etching being performed using an etching chemistry including gaseous SF6 gas mixed with gaseous Ar. The method includes plasma etching to remove the primary silicon layer in the scribe line regions to provide a plurality of individual semiconductor dies, for example, using a cyclic Bosch process.

[0012] The inventors have found that by using a plasma formed from Ar and SF6 gases for silicon oxide etching, the formation of polymer deposits on the sidewalls of the mask and / or silicon oxide layer during etching can be reduced or completely prevented. Furthermore, the incorporation of inorganic materials, such as silicon, into any polymer deposits that form is significantly reduced or prevented. In the present method, which utilizes different etching chemistries than prior art methods, some polymer may still deposit, but it is relatively small and there is no incorporation of inorganic materials. Thus, the deposited polymer can be removed by plasma ashing. It is believed that the fluorine in the etching plasma helps prevent silicon or other inorganic materials from depositing in the polymer.

[0013] The etch chemistry for the silicon oxide etch may be an oxygen-free etch chemistry. Alternatively or additionally, the etch chemistry may be a carbon monoxide-free etch chemistry.

[0014] The plasma etching step to remove the primary silicon layer may be performed using an etching chemistry including SF gas mixed with Ar gas, which may be the same etching chemistry used for silicon oxide etching.

[0015] The organic soft mask may include a polymer-based mask. The organic soft mask may include a photoresist mask.

[0016] The semiconductor wafer may be supported on a substrate support, which may be a glass or silicon support structure, or a tape and frame assembly.

[0017] The method may further include plasma ashing to remove the mask. The plasma ashing may be performed using oxygen or argon based ashing chemistries.

[0018] The step of plasma etching to remove the primary silicon layer may include a cyclic Bosch etch process.

[0019] The semiconductor wafer may further comprise one or more metal layers, which may be embedded in, for example, a silicon oxide layer.

[0020] The plasma etching step to remove the top silicon oxide layer may be carried out at a pressure of 20 to 50 millitorr.

[0021] The plasma etching step to remove the top silicon oxide layer may be carried out using an Ar flow rate of 100-350 sccm.

[0022] The plasma etching step to remove the top silicon oxide layer may be carried out using an Ar flow rate of 140-170 sccm.

[0023] The plasma etching step to remove the top silicon oxide layer may be carried out using a flow rate of 30-100 sccm of SF6.

[0024] The plasma etching step to remove the top silicon oxide layer may be carried out using a flow rate of 40-50 sccm of SF6.

[0025] 10. The method of any preceding claim, wherein the etching chemistry for silicon oxide etching further comprises the gas C4F8, wherein the flow rate of C4F8 may be less than the flow rate of SF6, for example less than 50% of the flow rate of SF6.

[0026] The step of plasma etching to remove the upper silicon oxide layer may be performed at an RF power in the range of 1000 to 3000 W. The step of plasma etching to remove the upper silicon oxide layer may be performed at an RF bias power in the range of 1500 to 5000 W.

[0027] According to a second aspect of the present invention, there is provided a plasma etching apparatus configured to perform the method according to the first aspect of the present invention. The plasma etching apparatus includes a chamber. The plasma etching apparatus includes a plasma generator associated with the chamber and configured to generate a plasma from at least Ar and SF6 gases received in the chamber. The plasma etching apparatus includes a substrate support configured to support a semiconductor wafer including a primary silicon layer and an upper SiO2 layer covered by a mask, the mask defining a plurality of scribe line regions to be etched, the substrate support being positioned relative to the chamber in use such that the plasma contacts the semiconductor wafer. The plasma etching apparatus includes a controller configured to cause the apparatus to perform a plasma etch to remove the upper silicon oxide layer in the scribe line regions, and then to perform a plasma etch to remove the primary silicon layer in the scribe line regions. [Brief explanation of the drawings]

[0028] Prior art methods and embodiments of the present invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:

[0029] [Figure 1] FIG. 1 illustrates a first step in a prior art method for plasma dicing a semiconductor wafer. [Figure 2] FIG. 1 illustrates a second step in a prior art method for plasma dicing a semiconductor wafer. [Figure 3] FIG. 1 illustrates a third step in a prior art method for plasma dicing a semiconductor wafer. [Figure 4] FIG. 1 illustrates a fourth step in a prior art method of plasma dicing a semiconductor wafer. [Figure 5] FIG. 1 is a flow diagram of a method for plasma dicing a semiconductor wafer in accordance with an exemplary embodiment of the present invention. [Figure 6] 1A-1C illustrate a first step in a method for plasma dicing a semiconductor wafer according to an exemplary embodiment of the present invention. [Figure 7] 1A-1C illustrate a second step in a method for plasma dicing a semiconductor wafer according to an exemplary embodiment of the present invention. [Figure 8] 10A-10C illustrate a third step in a method for plasma dicing a semiconductor wafer according to an exemplary embodiment of the present invention. [Figure 9] FIG. 10 illustrates a fourth step in a method for plasma dicing a semiconductor wafer according to an exemplary embodiment of the present invention. [Figure 10] 1 is a schematic side view of an etching apparatus configured to perform a method of plasma dicing a semiconductor wafer, according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0030] Conventional technology In the first step of a prior art method for plasma dicing a semiconductor wafer (FIG. 1), a semiconductor wafer assembly 1 is placed in the chamber of an etcher. The semiconductor wafer assembly 1 comprises a semiconductor wafer 3 supported on tape 5. The semiconductor wafer 3 comprises a thick silicon substrate layer 7 on the tape 5, and a silicon oxide (SiO2) layer 9 on the silicon substrate layer 7. The wafer 3 is covered with a polymeric organic mask 11 that is patterned to define scribe line areas 13 where the wafer 3 will be plasma etched to separate the wafer into individual dies.

[0031] In the second step of the prior art method (FIG. 2), C with O or CO and Ar gas is used. x F y and / or C. x H y F zThe silicon oxide layer 9 is plasma etched in an etcher chamber using a plasma formed from fluorine. The etching is directional (anisotropic), resulting in straight sidewalls in the silicon oxide layer 9. Meanwhile, the edges of the mask 11 are slightly etched, providing angled edges. The mask is etched by the incident ions and radicals. However, because not all ions approach perpendicular to the wafer surface, some of the mask is removed laterally (most notably at the top of the mask), resulting in sloped edges. During etching, fluorine-containing inorganic deposits 8 accumulate at the edges of the mask 11 and silicon oxide layer 9 in the scribe line regions 13.

[0032] In the third step of the prior art method (FIG. 3), the silicon layer 7 is etched in an etcher chamber using a plasma formed from SF or SF+Ar gas (with a C4F8 deposition step). The etching is performed as a rapid anisotropic etch in a cyclic Bosch process (well known to those skilled in the art and not further described herein) to form deep channels in the silicon layer 7 with scalloped edges 12.

[0033] In the fourth step of the prior art method (FIG. 4), the polymer mask 11 is removed by plasma ashing in an oxygen-based strip step. The process of plasma ashing to strip the mask is well known to those skilled in the art and will not be further described herein. The inorganic deposits 8 remain after the plasma ashing step as filaments of unwanted polymer residue protruding from the sides of the silicon oxide layer at the edge of the separated die.

[0034] invention The present invention provides a method for plasma dicing a semiconductor wafer that avoids the formation of filaments at the edge of the die.

[0035] In an embodiment of the present invention, a method for plasma dicing a semiconductor wafer (FIG. 5) includes at least three steps. The method includes a first step 101 of providing a semiconductor wafer (e.g., the wafer shown in FIG. 6 and described in more detail below) comprising a primary silicon layer and an upper silicon oxide (SiO) layer covered with a mask, the mask defining a plurality of scribe line regions to be etched. The method includes a second step 103 of plasma etching to remove the upper silicon oxide layer in the scribe line regions to expose the primary silicon layer, the plasma etching being performed using an etching chemistry including gaseous SF gas mixed with gaseous Ar. The method includes a third step 105 of plasma etching to remove the primary silicon layer in the scribe line regions to provide a plurality of separated semiconductor dies. By utilizing an etching chemistry including gaseous SF gas mixed with gaseous Ar for the silicon oxide etch, the formation of filaments at the edges of the separated dies during etching is avoided.

[0036] More specifically, in an exemplary embodiment of the present invention, in a first step (FIG. 6), a semiconductor wafer assembly 101 is provided in a chamber of an etching apparatus. The semiconductor wafer assembly 101 comprises a semiconductor wafer 103 supported on a support structure, which in an exemplary embodiment is a tape 105. The semiconductor wafer 103 comprises a thick silicon substrate layer 107 on the support structure 105 and a silicon oxide (SiO2) layer 109 on the silicon substrate layer 107. The wafer 103 is covered with a polymeric organic mask 111 patterned to define scribe line regions 113 where the wafer 103 will be plasma etched. In another embodiment, for example, one or more metal layers may be embedded in the silicon oxide layer 109 forming a laminate structure. In an exemplary embodiment of the present invention, the semiconductor wafer 103 is a 300 mm wafer. The silicon layer 107 is approximately 40-60 μm thick, and the silicon oxide layer 109 is approximately 5-10 μm thick. In an exemplary embodiment, mask 111 is a photoresist mask approximately 3-15 μm thick, with an open area of ​​approximately 15% and defining scribe line regions 113 including lanes 7-43 μm wide. During curing of the photoresist, the mask deforms slightly, causing the corners of the mask in the scribe line regions to tilt by an angle greater than 55% in the exemplary embodiment.

[0037] In an exemplary embodiment of the present invention, in the second step (FIG. 7), the silicon oxide layer 109 is plasma etched in an etcher chamber using a plasma formed from SF and Ar gases. The etching is highly directional (anisotropic), resulting in straight sidewalls in the silicon oxide layer 109. In contrast to prior art methods, the use of an etching chemistry including SF and Ar gases has been found to eliminate the incorporation of inorganic materials, such as silicon or fluorine compounds, into the polymer layer on the walls of the mask and silicon oxide layer near the etching area, thereby preventing the formation of residual filaments after ashing of the mask. Unwanted contamination of the wafer assembly by fluorine compounds is therefore significantly reduced and / or avoided, and corrosion of the die pad and die surface is prevented. During etching, the mask may also be somewhat etched and thinned.

[0038] In an exemplary embodiment of the present invention, in a third step (FIG. 8), silicon layer 107 is etched in an etcher chamber, also using a plasma formed from SF and Ar gases. The etching is performed as a rapid anisotropic etch in a cyclic Bosch process (well known to those skilled in the art and therefore not further described herein), forming deep channels 110 in the silicon with scalloped edges 112. In this manner, wafer 103 is separated into individual dies.

[0039] In an exemplary embodiment of the present invention, in the fourth step (FIG. 9), the polymer mask 111 is removed by plasma ashing in an oxygen-based strip step. Plasma ashing to strip the mask is a process well known to those skilled in the art and will not be further described herein. Due to the use of etching chemistries including Ar and SF6 in the silicon oxide etching step, the separated dies are substantially free of polymer residue, resulting in no filament formation at the edges of the silicon oxide layer adjacent to the scribe lines. The mask is removed, leaving no residual filaments.

[0040] According to exemplary embodiments of the present invention, all steps of the method are performed using a plasma etching apparatus (FIG. 10), for example, a Rapier XE™ in a first exemplary embodiment of the present invention. In alternative embodiments, some steps, such as, for example, the plasma ashing step, may be performed in a different apparatus.

[0041] The plasma etching apparatus 301 comprises a first chamber 303 disposed above a second, larger chamber 305. A first plasma generator 308 in the form of a cylindrical ICP source 309 connected to a first RF (approximately 13.56 MHz) power source 311 is disposed about the periphery of the first chamber and configured to generate a varying magnetic field and induce an electric field to excite electrons in a gas within the first chamber. A first gas inlet 307 supplies a first process gas (Ar in an exemplary embodiment of the invention) to the first chamber 303, and a primary plasma is generated via electromagnetic induction and subsequent ion generation.

[0042] A DC coil 313 is used to control the shape of the plasma exiting the first chamber 303. A Faraday shield 315 reduces the capacitive coupling from the ICP source, making it primarily inductive.

[0043] The plasma flows into the second chamber 305 and contacts the semiconductor wafer assembly 101 supported on an electrostatic chuck 317. The semiconductor wafer assembly 101 (including the tape 105) is held in a frame 323. In an exemplary embodiment, the edge of the semiconductor wafer assembly 101 is protected by a wafer edge protection (WEP) device 319. A baffle 325 above the electrostatic chuck 317 is positioned to control gas flow in the vicinity of the semiconductor wafer assembly.

[0044] A second gas inlet 327 is annularly disposed at the top of the second chamber 305 and configured to supply a second process gas (SF6 in an exemplary embodiment of the present invention) to the second chamber. A second plasma generator 329 connected to a second RF (approximately 13.56 MHz) power source 331 provides a second cylindrical ICP source. The coaxial source serves to increase the etch rate toward the edge of the semiconductor wafer assembly. The second plasma generator 329 is disposed at the periphery of the second chamber and configured to generate a secondary plasma from the second process gas at the periphery of the second chamber 305. The two plasmas mix within the chamber, providing a more uniformly distributed plasma over the semiconductor wafer assembly 101.

[0045] Gas flow through the chamber is facilitated by pump 335 and valve 333. A separate power supply 337 (similarly approximately 13.56 MHz, although frequencies between 2 and 20 MHz are available) provides RF bias power on an electrode, i.e., a support associated with semiconductor wafer assembly 101.

[0046] In an exemplary embodiment of the present invention, electrostatic chuck 317 is used to control the wafer temperature in the range of −15° C. to 10° C. The conditions for the silicon oxide etch were low pressure (20-50 mTorr range, e.g., about 30 mTorr), high RF power (1000-3000 W range, e.g., about 2000 W and about 2450 W for the first and second RF power sources, respectively), high RF bias power (1500-5000 W range, e.g., about 2500 W), and moderate gas flow rates (100-350 sccm range for Ar and 30-100 sccm range for SF6, e.g., about 152 sccm and about 48 sccm, respectively).

[0047] In alternative embodiments of the present invention, a third process gas may be provided, e.g., CF₈, provided to the second chamber and mixed with the second process gas. In such embodiments, the gaseous CF₈ may be provided at a flow rate in the range of 5-30 sccm, e.g., approximately 10 sccm. In such embodiments, the flow rate of Ar may be adjusted to approximately 162 sccm, while all other etching parameters remain the same. It has been found that adding CF₈ as a third process gas provides an improved mask / silicon oxide selectivity of approximately 1.2:1 compared to approximately 1:1, while maintaining a residue-free die exterior surface. Thus, SiO₂ etches 1.2 times faster than the mask, unlike the same etch rate, which is advantageous because it allows for the use of a thinner mask. [Explanation of symbols]

[0048] 101 Semiconductor Wafer Assembly 103 Semiconductor wafer 105 Tape 107 Silicon substrate layer 109 Silicon oxide layer 110 Deep Channel 111 Polymer organic mask 112 En 113 Scribe line area 301 Plasma Etching Equipment 303 First Chamber 305 Second Chamber 307 First gas inlet 308 First Plasma Generator 309 Cylindrical ICP Source 311 First RF (approximately 13.56MHz) power supply 313 DC coil 315 Faraday Shield 317 Electrostatic Chuck 319 Wafer Edge Protection WEP Device 323 frames 325 Baffle 327 Second Gas Inlet 329 Second Plasma Generator 331 Second RF (approximately 13.56MHz) power supply 333 Valve 335 Pump 337 Separate Power Supply

Claims

1. 1. A method for plasma dicing a semiconductor wafer, comprising: providing a semiconductor wafer comprising a primary silicon layer and an upper silicon oxide layer covered with an organic soft mask, the mask defining a plurality of scribe line regions to be etched; plasma etching to remove the upper silicon oxide layer in the scribe line area to expose the primary silicon layer, the plasma etching being performed using SF gas mixed with Ar gas. ６ plasma etching, which is carried out using an etching chemistry comprising a gas; plasma etching to remove the main silicon layer in the scribe line areas to provide a plurality of individual semiconductor dies; A method comprising:

2. The method of claim 1 , wherein the etching chemistry is an oxygen-free etching chemistry.

3. 3. The method of claim 1, wherein the etching chemistry is a carbon monoxide-free etching chemistry.

4. The plasma etching step for removing the primary silicon layer comprises using SF gas mixed with Ar gas. ６ The method of any of claims 1 to 3, carried out using an etching chemistry comprising a gas.

5. The method of any of claims 1 to 4, wherein the organic soft mask comprises a polymer-based mask.

6. The method of claim 5 , wherein the organic soft mask comprises a photoresist mask.

7. The method of any of claims 1 to 6, wherein the semiconductor wafer is supported on a substrate support.

8. The method of claim 7 , wherein the substrate support is a glass or silicon support structure.

9. The method of claim 7 , wherein the substrate support is a tape and frame assembly.

10. The method according to any one of claims 1 to 9, further comprising the step of plasma ashing to remove the mask.

11. The method of claim 10, wherein the plasma ashing is performed using an oxygen or argon based ashing chemistry.

12. The method of any of claims 1 to 11, wherein the plasma etching to remove the primary silicon layer comprises a cyclic Bosch etch process.

13. The method of any of claims 1 to 12, wherein the semiconductor wafer further comprises one or more metal layers.

14. The method of any of claims 1 to 13, wherein the plasma etching to remove the top silicon oxide layer is carried out at a pressure of 20 to 50 millitorr.

15. The method according to any of the preceding claims, wherein the plasma etching to remove the top silicon oxide layer is carried out using an Ar flow rate of 100 to 350 sccm.

16. 16. The method of claim 15, wherein the plasma etching to remove the top silicon oxide layer is performed using an Ar flow rate of 140-170 sccm.

17. The plasma etching step for removing the upper silicon oxide layer comprises plasma etching with 30 to 100 sccm of SF ６ The method of any one of claims 1 to 16, wherein the method is carried out using a flow rate of

18. The plasma etching step for removing the upper silicon oxide layer comprises plasma etching with 40-50 sccm of SF ６ 18. The method of claim 17, wherein the method is carried out using a flow rate of

19. The etching chemistry for the silicon oxide etch is gas C ４ F ８ The method of any one of claims 1 to 18, further comprising:

20. The method according to any of claims 1 to 19, wherein the plasma etching to remove the top silicon oxide layer is performed at an RF power in the range of 1000 to 3000W and an RF bias power in the range of 1500 to 5000W.

21. 21. A plasma etching apparatus configured to carry out the method according to any one of claims 1 to 20, said plasma etching apparatus comprising: a chamber; At least Ar and SF associated with and received within the chamber. ６ a plasma generator configured to generate a plasma from the gas; The main silicon layer and the upper SiO ２ a substrate support configured to support a semiconductor wafer having a layer, the mask defining a plurality of scribe line regions to be etched, the substrate support being positioned relative to the chamber, in use, such that the plasma contacts the semiconductor wafer; a controller configured to cause the apparatus to perform a plasma etch to remove the top silicon oxide layer in the scribe line area, and then to perform a plasma etch to remove the main silicon layer in the scribe line area; A plasma etching apparatus comprising:

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