Semiconductor device

Abstract

To provide a semiconductor device having improved characteristics by effectively arranging a memory cell, a peripheral circuit pattern, and a wiring structure.SOLUTION: The semiconductor device includes a capacitor disposed on a first substrate, a channel disposed on the capacitor, a gate electrode at least partially overlapping the channel in a horizontal direction, a bit line structure disposed on the gate electrode and the channel, a first wiring structure disposed on the bit line structure, a bonding pad structure disposed on the first wiring structure, a second wiring structure disposed on the bonding pad structure, a second substrate disposed on the second wiring structure, a transistor formed under the second substrate, a third wiring structure disposed on the second substrate, an isolation pattern penetrating the second substrate, and a through via penetrating the isolation pattern.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to DRAM memory devices. [Background technology]

[0002] In order to increase the integration density of semiconductor devices, a method for effectively arranging memory cells and peripheral circuit patterns that generate electrical signals for driving the memory cells is required. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device having improved characteristics. [Means for solving the problem]

[0004] In order to achieve the above object, one aspect of the present invention provides a semiconductor device comprising: a capacitor disposed on a first substrate; a channel disposed on the capacitor; a gate electrode at least partially overlapping the channel in a horizontal direction; a bit line structure disposed on the gate electrode and the channel; a first wiring structure disposed on the bit line structure; a bond pad structure disposed on the first wiring structure; a second wiring structure disposed on the bond pad structure; a second substrate disposed on the second wiring structure; a transistor disposed below the second substrate; a third wiring structure disposed on the second substrate; an isolation pattern penetrating the second substrate; and a through via penetrating the isolation pattern.

[0005] In order to achieve the above object, another aspect of the present invention provides a semiconductor device comprising: a capacitor disposed on a first substrate; a channel disposed on the capacitor; a gate electrode at least partially overlapping the channel in a horizontal direction; a bit line structure disposed on the gate electrode and the channel; a first wiring structure disposed on the bit line structure; a bond pad structure disposed on the first wiring structure; a second wiring structure disposed on the bond pad structure; a second substrate disposed on the second wiring structure; a transistor disposed below the second substrate; an isolation pattern penetrating the second substrate; and a through via penetrating the isolation pattern, wherein the through via is connected to an input / output device to transmit input / output signals generated by the input / output device.

[0006] In order to achieve the above object, according to yet another aspect of the present invention, a semiconductor device includes a capacitor disposed on a first substrate, a channel disposed on the capacitor, a gate electrode at least partially overlapping the channel in a horizontal direction, a bit line structure disposed on the gate electrode and the channel, a first wiring structure disposed on the bit line structure, a bond pad structure disposed on the first wiring structure, a second wiring structure disposed on the bond pad structure, a second substrate disposed on the second wiring structure, a transistor formed on an upper portion of the second substrate, a third wiring structure disposed on the second substrate, an isolation pattern penetrating the second substrate, and a plurality of through vias each penetrating the isolation pattern and spaced apart from each other in the horizontal direction. [Effects of the Invention]

[0007] In the semiconductor device according to the present invention, memory cells, peripheral circuit patterns, and wiring structures are effectively arranged, thereby ensuring improved integration density.

[0008] However, the effects of the present invention are not limited to the effects mentioned above. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view illustrating a first example of a semiconductor device according to an embodiment of the present invention. [Figure 2] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] FIG. 4 is a cross-sectional view for explaining a second example of a semiconductor device according to an embodiment of the present invention. [Figure 18] FIG. 10 is a cross-sectional view illustrating a third example of a semiconductor device according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] FIG. 10 is a cross-sectional view illustrating a fourth example of a semiconductor device according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] FIG. 10 is a cross-sectional view illustrating a fifth example of a semiconductor device according to an embodiment of the present invention. [Figure 28] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] FIG. 10 is a cross-sectional view illustrating a sixth example of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Specific examples of embodiments of the present invention will be described in detail below with reference to the drawings. In this specification, when a material, a layer (film), a region, a pad, an electrode, a pattern, a structure, or a process is referred to as a "first," a "second," and / or a "third," this is not intended to limit such components, but simply to distinguish between each material, layer (film), region, electrode, pad, pattern, structure, and process. Therefore, "first," "second," and / or "third" are used selectively or interchangeably with respect to each material, layer (film), region, electrode, pad, pattern, structure, and process.

[0011] Hereinafter, in the detailed description of the invention (excluding the claims), two mutually intersecting horizontal directions parallel to the upper surfaces of the first to third substrates are defined as first and second directions (D1, D2), respectively, and a vertical direction perpendicular to the upper surfaces of the first to third substrates is defined as a third direction (D3). In one embodiment of the present invention, the first and second directions (D1, D2) are orthogonal to each other.

[0012] Meanwhile, the first to third directions (D1, D2, D3) may refer not only to the directions shown in the drawings but also to the opposite directions.

[0013] FIG. 1 is a cross-sectional view for explaining a first example of a semiconductor device according to an embodiment of the present invention.

[0014] As shown in FIG. 1, the semiconductor device includes memory cells formed on a second substrate 380 (referred to as a "first substrate" in the claims, the same below), and a peripheral circuit pattern formed on a third substrate 510 (referred to as a "second substrate" in the claims, the same below) that generates electrical signals for driving the memory cells. Hereinafter, the regions in which the memory cells and the peripheral circuit pattern are formed will be referred to as a cell array region and a peripheral circuit region, respectively.

[0015] As a result, the semiconductor device is a memory device having a POC (Periphery Over Cell) structure in which the peripheral circuit region is arranged above the cell array region. However, the present invention is not limited thereto and may be a memory device having a COP (Cell Over Periphery Over) structure in which the peripheral circuit region is arranged below the cell array region.

[0016] The semiconductor device includes a capacitor 220, a plate electrode 230, first to third conductive pads (180, 184, 186), first and second gate electrodes (140, 160), first and second gate insulating patterns (130, 150), a channel 125, a bit line structure 430, a transistor, and a wiring structure.

[0017] The semiconductor device further includes a first bonding film 390, first to tenth interlayer insulating films (300, 170, 330, 370, 490, 750, 500, 880, 890, 930), and first and second isolation patterns (540, 550).

[0018] The second substrate 380 includes a semiconductor material such as silicon or an insulating material such as glass. The first bonding film 390 is bonded to the upper surface of the second substrate 380 and includes, for example, silicon carbonitride, silicon oxide, etc. The fourth interlayer insulating film 370 is bonded to the upper surface of the first bonding film 390 and includes, for example, an oxide such as silicon oxide or a low-k material.

[0019] The first wiring 360 and the second etch stop film 340 are sequentially stacked along the third direction (D3) in the fourth interlayer insulating film 370. The second etch stop film 340 includes an insulating nitride such as silicon nitride.

[0020] Each of the second and third contact plugs (354, 356) extends in a third direction (D3) through the third interlayer insulating film 330 and the second etch stop film 340 and contacts the top surface of the first interconnect 360. In one embodiment of the present invention, the horizontal width of each of the second and third contact plugs (354, 356) decreases from the bottom to the top.

[0021] The capacitor 220 and the plate electrode 230 are formed on the second etch stop film 340 in the third interlayer insulating film 330, and the bottom surface and sidewall of the plate electrode 230 are covered by the third interlayer insulating film 330. The capacitor 220 includes a first capacitor electrode 190, a dielectric film 200, and a second capacitor electrode 210.

[0022] The first capacitor electrodes 190 extend in a third direction (D3) and are spaced apart from one another in the first and second directions (D1, D2). In one embodiment of the present invention, the first capacitor electrodes 190 are arranged in a lattice pattern or a honeycomb pattern when viewed from above.

[0023] A support film 320 and a first etch stop film 310 are formed on the sidewall of each first capacitor electrode 190. Here, the first etch stop film 310 is formed on the uppermost sidewall of each first capacitor electrode 190, and a plurality of support films 320 are formed on the sidewall of each first capacitor electrode 190, spaced apart from each other along the third direction (D3).

[0024] The dielectric film 200 is formed on the sidewalls of the first capacitor electrode 190, the upper and lower surfaces and sidewalls of the support film 320, and the lower surface and sidewalls of the first etch stop film 310, and the second capacitor electrode 210 is formed between the support films 320 adjacent to each other in the third direction (D3) and between the top support film 320 and the first etch stop film 310, and its upper and lower surfaces and one sidewall are covered by the dielectric film 200.

[0025] The plate electrode 230 surrounds the lower surface and sidewalls of the capacitor 220 , the support film 320 , and the first etch stop film 310 .

[0026] Each of the first and second capacitor electrodes (190, 210) includes, for example, a metal, a metal nitride, or a metal silicide, and the dielectric film 200 includes, for example, a metal oxide. The support film 320 includes, for example, an insulating nitride such as silicon nitride, and the first etch stop film 310 includes, for example, an insulating nitride such as silicon boronitride. The plate electrode 230 includes, for example, a metal such as impurity-doped silicon-germanium or tungsten.

[0027] The first contact plug 352 penetrates the lower part of the third interlayer insulating film 330 and the second etch stop film 340 to contact the upper surface of the first interconnect 360 and the lower surface of the plate electrode 230. Here, the first contact plug 352 partially penetrates the lower part of the plate electrode 230.

[0028] The second interlayer insulating film 170 is formed on the third interlayer insulating film 330, the capacitor 220, the plate electrode 230, and the second and third contact plugs (354, 356), and the first to third conductive pads (180, 184, 186) pass through it to contact the upper surfaces of the first capacitor electrode 190, the second contact plug 354, and the third contact plug 356, respectively. The first capacitor electrodes 190 are arranged in, for example, a grid pattern or a honeycomb pattern, and the first conductive pads 180 are also arranged in a corresponding grid pattern or honeycomb pattern.

[0029] The second interlayer insulating film 170 includes an oxide such as silicon oxide or a low-k material. In one embodiment, each of the first to third conductive pads (180, 184, 186) includes a second conductive pattern and a first conductive pattern sequentially stacked along a third direction (D3), the second conductive pattern including, for example, a metal, a metal nitride, a metal silicide, etc., and the first conductive pattern including, for example, impurity-doped polysilicon.

[0030] In one embodiment of the present invention, the first gate electrodes 140 extend in a first direction (D1) on the second interlayer insulating film 170, and are formed in plurality at intervals along a second direction (D2). The second gate electrodes 160 also extend in the first direction (D1) on the second interlayer insulating film 170, and are formed in plurality at intervals along the second direction (D2). In one embodiment of the present invention, the first and second gate electrodes (140, 160) are alternately and repeatedly arranged along the second direction (D2).

[0031] In one embodiment of the present invention, the first gate electrode 140 has a line shape extending straight in a first direction (D1) when viewed from above, and the second gate electrode 160, in addition to having a line shape extending straight in the first direction (D1) when viewed from above, further includes protrusions that protrude in a second direction (D2) spaced apart from each other along the first direction (D1).

[0032] Each of the first and second gate electrodes (140, 160) comprises a metal such as, for example, tungsten, copper, aluminum, or the like.

[0033] In one embodiment of the present invention, the second gate electrode 160 serves as a word line of the semiconductor device, and the first gate electrode 140 serves as a back gate electrode. However, the concept of the present invention is not limited thereto, and the first and second gate electrodes 140 and 160 may serve as a word line and a back gate electrode, respectively.

[0034] In one embodiment of the present invention, the first gate insulating pattern 130 is formed on the second interlayer insulating film 170 and the first conductive pad 180, and extends in a first direction (D1) while covering an upper surface and a sidewall of the first gate electrode 140. The second gate insulating pattern 150 is formed on the second interlayer insulating film 170 and the first conductive pad 180, and extends in the first direction (D1) while covering an upper surface and a sidewall of the second gate electrode 160. Here, the cross section of each of the first and second gate insulating patterns (130, 150) in the second direction (D2) has, for example, an upside-down cup shape.

[0035] As the first and second gate electrodes (140, 160) are alternately and repeatedly arranged along the second direction (D2), the first and second gate insulating patterns (130, 150) are also alternately and repeatedly arranged along the second direction (D2).

[0036] In one embodiment of the present invention, the sidewalls of the first gate insulating pattern 130 in the second direction (D2) have a line shape extending straight in the first direction (D1) when viewed from above, whereas the sidewalls of the second gate insulating pattern 150 in the second direction (D2) have a staggered shape instead of extending straight in the first direction (D1) when viewed from above. Each of the first and second gate insulating patterns (130, 150) includes an oxide such as silicon oxide.

[0037] The channels 125 are formed on the first conductive pad 180 and on the outer wall of the first gate insulating pattern 130 in the second direction (D2), and are spaced apart from one another along the first direction (D1). One sidewall of each channel 125 in the second direction (D2) contacts the outer wall of the first gate insulating pattern 130 in the second direction (D2), and the other sidewall of each channel 125 in the second direction (D2) and both sidewalls in the first direction (D1) contact the outer wall of the second gate insulating pattern 150 in the second direction (D2).

[0038] In one embodiment of the present invention, the channel 125 comprises a semiconductor material such as, for example, silicon, germanium, silicon-germanium, etc. Alternatively, the channel 125 can comprise an oxide semiconductor material such as, for example, IGZO.

[0039] The first interlayer insulating film 300 is formed on the second interlayer insulating film 170 and the second and third conductive pads 184, 186, and contacts the sidewalls of the first gate insulating pattern 130 formed on both sides in the second direction (D2). The first interlayer insulating film 300 includes an oxide such as silicon oxide or a low-k material.

[0040] The bit line structures 430 extend in the second direction (D2) on the channel 125, the first and second gate insulating patterns (130, 150), and the first interlayer insulating film 300, and are formed in plurality at intervals along the first direction (D1). Here, each bit line structure 430 commonly contacts the upper surface of the channel 125 arranged in the second direction (D2).

[0041] In one embodiment, each bit line structure 430 includes third and fourth conductive patterns (400, 420) stacked along a third direction (D3), which may include, for example, impurity-doped polysilicon and metal, respectively.

[0042] The second to sixth wirings (440, 460, 480, 484, 486) (referred to as "first wiring structures" in the claims), the fourth to seventh contact plugs (452, 454, 474, 476), and the first via 470 are formed in a fifth interlayer insulating film 490 formed on the channel 125, the first and second gate insulation patterns (130, 150), the first interlayer insulating film 300, and the second and third conductive pads (184, 186).

[0043] The second to fourth wirings (440, 460, 480) are stacked in this order along the third direction (D3), and the fifth and sixth wirings (484, 486) are formed in substantially the same layer as the fourth wiring 480, but separated horizontally from it.

[0044] The fourth contact plug 452 penetrates a portion of the fifth interlayer insulating film 490 and the second gate insulating pattern 150 to contact the lower surface of the third interconnection 460 and the upper surface of the second gate electrode 160, the fifth contact plug 454 penetrates a portion of the fifth interlayer insulating film 490 to contact the lower surface of the third interconnection 460 and the upper surface of the bit line structure 430, the sixth contact plug 474 penetrates the fifth interlayer insulating film 490 to contact the lower surface of the fifth interconnection 484 and the upper surface of the second conductive pad 184, and the seventh contact plug 476 penetrates the fifth interlayer insulating film 490 to contact the lower surface of the sixth interconnection 486 and the upper surface of the third conductive pad 186.

[0045] In one embodiment of the present invention, each of the fourth to seventh contact plugs (452, 454, 474, 476) has a width that increases from the bottom to the top.

[0046] On the other hand, the first via 470 penetrates a part of the fifth interlayer insulating film 490 and contacts the upper surface of the third wiring 460 and the lower surface of the fourth wiring 480 .

[0047] The seventh interlayer insulating film 500 includes an oxide such as silicon oxide or silicon carbonitride.

[0048] A third substrate 510 is disposed on the seventh interlayer insulating film 500. The third substrate 510 includes a semiconductor material such as silicon, germanium, or silicon-germanium, and has a well region doped with, for example, p-type impurities.

[0049] A first separated pattern 540 is formed on the third substrate 510, and a second separated pattern 550 penetrates the third substrate 510. Although three second separated patterns 550 are shown in the drawing, the present invention is not limited thereto, and any number of second separated patterns may be formed.

[0050] Each of the first and second isolation patterns (540, 550) comprises an oxide, such as silicon oxide.

[0051] For example, a gate structure 630 is formed on the third substrate 510, and an impurity region 640 is formed in the upper part of the third substrate 510 adjacent to the gate structure 630.

[0052] The gate structure 630 includes a third gate insulating pattern 620 and a third gate electrode 610 stacked in a third direction (D3), and the gate structure 630 and the impurity region 640 form a transistor.

[0053] The third gate electrode 610 includes a conductive material such as a metal, a metal nitride, a metal silicide, or impurity-doped polysilicon, and the third gate insulating pattern 620 includes an oxide such as silicon oxide.

[0054] The sixth and eighth interlayer insulating films (750, 880) are stacked along the third direction (D3) on the third substrate 510. Each of the sixth and eighth interlayer insulating films (750, 880) includes an oxide or a low-k material, such as silicon oxide.

[0055] The eighth contact plug 650 penetrates the sixth interlayer insulating film 750 and contacts the upper surface of the impurity region 640, and the through via 660 penetrates the sixth interlayer insulating film 750, the second isolation pattern 550, the seventh interlayer insulating film 500, and the upper part of the fifth interlayer insulating film 490 and contacts the upper surface of the fourth wiring 480. In one embodiment of the present invention, each of the eighth contact plugs 650 and the through via 660 has a width that decreases from the top to the bottom.

[0056] The seventh to twelfth wirings (770, 790, 810, 830, 850, 870) are stacked in this order along the third direction (D3).

[0057] The second via 780 penetrates a portion of the eighth interlayer insulating film 880 and contacts the upper surface of the seventh wiring 770 and the lower surface of the eighth wiring 790; the third via 800 penetrates a portion of the eighth interlayer insulating film 880 and contacts the upper surface of the eighth wiring 790 and the lower surface of the ninth wiring 810; the fourth via 820 penetrates a portion of the eighth interlayer insulating film 880 and contacts the upper surface of the ninth wiring 810 and the lower surface of the tenth wiring 830; the fifth via 840 penetrates a portion of the eighth interlayer insulating film 880 and contacts the upper surface of the tenth wiring 830 and the lower surface of the eleventh wiring 850; and the sixth via 860 penetrates a portion of the eighth interlayer insulating film 880 and contacts the upper surface of the eleventh wiring 850 and the lower surface of the twelfth wiring 870.

[0058] In the drawing, the seventh to twelfth wirings (770, 790, 810, 830, 850, 870) are shown stacked at six heights along the third direction (D3) within the eighth interlayer insulating film 880, but the present invention is not limited to this.

[0059] Furthermore, a ninth interlayer insulating film 890 and a third etch stop film 900 are sequentially stacked along the third direction (D3) on the eighth interlayer insulating film 880 and the twelfth interconnect 870, and a thirteenth interconnect 920 and a tenth interlayer insulating film 930 covering its sidewall are formed on the third etch stop film 900. Meanwhile, a seventh via 910 penetrates the ninth interlayer insulating film 890 and the third etch stop film 900 and contacts the upper surface of the twelfth interconnect 870. In one embodiment, the thirteenth interconnect 920 applies an input / output signal.

[0060] The first to thirteenth wires (360, 440, 460, 480, 484, 486, 770, 790, 810, 830, 850, 870, 920), the first to eighth contact plugs (352, 354, 356, 452, 454, 474, 476, 650), the through via 660, and the first to seventh vias (470, 780, 800, 820, 840, 860, 910) included in the wiring structure each contain, for example, a metal, a metal nitride, a metal silicide, or the like.

[0061] The wiring structure includes signal lines for transmitting electrical signals generated from the peripheral circuit patterns to the memory cells, the peripheral circuit patterns, and power lines for supplying power to the memory cells.

[0062] In one embodiment, the signal lines are arranged on the lower and upper parts of the third substrate 510, and the power lines are arranged on the upper part of the third substrate 510. The power lines include, for example, the ninth to twelfth wirings (810, 830, 850, 870) and the third to sixth vias (800, 820, 840, 860), but the present invention is not limited thereto.

[0063] In the semiconductor device, current flows in a third direction (D3), i.e., a vertical direction, within the channel 125 formed between the bit line structure 430 and the first conductive pad 180, and thus the semiconductor device is a VCT DRAM device including a vertical channel transistor (VCT) having a vertical channel.

[0064] In the semiconductor device in FIG. 1, the plate electrode 230 formed in the cell array region is arranged downward along the third direction (D3), and the transistor formed in the peripheral circuit region is arranged on the top of the third substrate 510 so as to be upward along the third direction (D3).

[0065] However, the present invention is not limited to this, and the plate electrode 230 may be arranged upward along the third direction (D3), or the transistor may be arranged at the bottom of the third substrate 510 so as to face downward along the third direction (D3).

[0066] 2 to 16 are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Specifically, Fig. 2, Fig. 4, and Fig. 6 are plan views, and Fig. 3, Fig. 5, and Fig. 7 to Fig. 16 are cross-sectional views taken along line A-A' of the corresponding plan views.

[0067] As shown in FIGS. 2 and 3, the second bulk substrate of the first substrate structure including the first bulk substrate 100, the buried oxide layer 110, and the second bulk substrate is patterned to form a preliminary channel 120.

[0068] In one embodiment of the present invention, the preliminary channels 120 extend in a first direction (D1) and are spaced apart from one another along a second direction (D2). A first opening exposing the top surface of the buried oxide film 110 is formed between the preliminary channels 120 adjacent to one another in the second direction (D2).

[0069] Thereafter, a first gate insulating film is formed on the preliminary channel 120 and the buried oxide film 110, and then an anisotropic etching process is performed to remove the first gate insulating film formed on the upper surface of the preliminary channel 120, thereby forming a first gate insulating pattern 130 on the sidewall of the first opening and on the upper surface of the buried oxide film 110. In one embodiment of the present invention, the first gate insulating pattern 130 contacts both sidewalls of the preliminary channels 120 adjacent to each other in the second direction (D2) that face each other in the second direction (D2) and an upper surface of the buried oxide film 110 formed therebetween, and extends in the first direction (D1).

[0070] Thereafter, a first gate electrode film is formed on the preliminary channel 120 and the first gate insulating pattern 130, and then a planarization process is performed on the first gate electrode film until the top surfaces of the preliminary channel 120 and the first gate insulating pattern 130 are exposed, thereby forming the first gate electrode 140. The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0071] In one embodiment of the present invention, a plurality of first gate electrodes 140 are formed extending in a first direction (D1) and spaced apart from each other along a second direction (D2).

[0072] Then, the preliminary channel 120, the first gate insulation pattern 130, and the first gate electrode 140 formed outside the certain region are removed to form a second opening that exposes the top surface of the buried oxide film 110, and then a first interlayer insulating film 300 is formed in the second opening.

[0073] As shown in FIGS. 4 and 5, preliminary channel 120 is patterned to form channel 125.

[0074] In one embodiment of the present invention, a plurality of channels 125 are formed spaced apart from one another along the first direction (D1) on one sidewall in the second direction (D2) of each first gate insulating pattern 130 extending in the first direction (D1). Here, a third opening exposing the top surface of the buried oxide film 110 is formed between the channels 125 formed between the first gate insulating patterns 130 adjacent to each other in the second direction (D2).

[0075] Thereafter, a second gate insulating film is formed on the channel 125, the first gate insulating pattern 130, the first gate electrode 140, and the buried oxide film 110, and then an anisotropic etching process is performed to remove portions of the second gate insulating film formed on the upper surfaces of the channel 125, the first gate insulating pattern 130, and the first gate electrode 140, thereby forming a second gate insulating pattern 150.

[0076] In one embodiment of the present invention, the second gate insulating pattern 150 extends in the first direction (D1) and contacts both sidewalls of the first gate insulating patterns 130 adjacent to each other in the second direction (D2) that face each other in the second direction (D2), both sidewalls of the channels 125 adjacent to each other in the second direction (D2) that face each other in the second direction (D2), and an upper surface of the buried oxide film 110 portion formed therebetween.

[0077] Thereafter, a second gate electrode film is formed on the channel 125, the first and second gate insulation patterns (130, 150), the first gate electrode 140, and the first interlayer insulating film 300, and then a planarization process is performed on the second gate electrode film until the upper surfaces of these are exposed, thereby forming the second gate electrode 160. The planarization process includes, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0078] In one embodiment of the present invention, the second gate electrodes 160 extend in a first direction (D1) and are formed in plurality at intervals along a second direction (D2). In one embodiment of the present invention, the second gate electrodes 160, when viewed from above, have a linear shape extending straight in the first direction (D1) and further include protrusions that are spaced apart from each other along the first direction (D1) and protrude in a second direction (D2).

[0079] As shown in Figures 6 and 7, a second interlayer insulating film 170 is formed on the first and second gate electrodes (140, 160), the channel 125, the first and second gate insulating patterns (130, 150), and the first interlayer insulating film 300, and then first to third conductive pads (180, 184, 186) are formed penetrating the second interlayer insulating film 170.

[0080] In one embodiment of the present invention, a plurality of first conductive pads 180 are formed spaced apart from each other along the first and second directions (D1, D2) and contact the upper surfaces of the corresponding channels 125. Meanwhile, the second and third conductive pads (184, 186) are formed to penetrate the second interlayer insulating film 170 formed on the first interlayer insulating film 300.

[0081] In one embodiment, each of the first to third conductive pads (180, 184, 186) includes first and second conductive patterns sequentially stacked along a third direction (D3), the first conductive pattern including, for example, impurity-doped polysilicon, and the second conductive pattern including, for example, a metal, a metal nitride, a metal silicide, etc.

[0082] Thereafter, the capacitor 220 and the plate electrode 230 are formed on the second interlayer insulating film 170 and the first conductive pad 180. The capacitor 220 and the plate electrode 230 are formed, for example, by the following process.

[0083] That is, after forming a first etch stop film 310 on the second interlayer insulating film 170 and the first to third conductive pads (180, 184, 186), mold films and support films 320 are alternately and repeatedly laminated on the first etch stop film 310. Here, the etch stop film 310 contains an insulating nitride such as silicon boron nitride, the mold film contains an oxide such as silicon oxide, and the support film 320 contains an insulating nitride such as silicon nitride.

[0084] Then, a fourth opening is formed through the support film 320, the mold film, and the first etch stop film 310 to expose the upper surface of each first conductive pad 180, and a first capacitor electrode film is formed on the upper surfaces of the first conductive pads 180 exposed by the fourth opening, the sidewalls of the fourth opening, and the upper surface of the top-layer support film 320.After that, a planarization process is performed on the first capacitor electrode film until the upper surface of the top-layer support film 320 is exposed, thereby forming a first capacitor electrode 190 in the fourth opening.

[0085] Planarization processes include, for example, chemical mechanical polishing (CMP) processes and / or etch-back processes.

[0086] Thereafter, the support film 320 and the mold film are partially removed to form a fifth opening that exposes the upper surface of the first etch stop film 310, and then the mold film is removed through the fifth opening.

[0087] In one embodiment of the present invention, the mold film is removed by a wet etching process, and the wet etching process forms sixth openings that expose the sidewalls of the first capacitor electrodes 190 and the top surface of the first etch stop film 310. However, the support film 320 remains on the sidewalls of each first capacitor electrode 190, thereby exposing the surface of each support film 320 through the sixth opening.

[0088] Thereafter, a dielectric film 200 is formed on the sidewalls of each first capacitor electrode 190 exposed by the sixth opening, the upper surface of the first etch stop film 310, and the surface of each support film 320, and then a second capacitor electrode film filling the remaining portions of the sixth openings is formed on the dielectric film 200. Here, the dielectric film 200 and the second capacitor electrode film are also laminated on the upper surfaces of the first capacitor electrodes 190 and the upper surface of the uppermost support film 320.

[0089] Thereafter, the second capacitor electrode film is subjected to, for example, a wet etching process to form the second capacitor electrode 210 in the sixth opening. The first capacitor electrode 190, the dielectric film 200, and the second capacitor electrode 210 form a capacitor 220.

[0090] Thereafter, a plate electrode 230 is formed on the upper surface and sidewalls of the capacitor 220 and on the upper surface of the second interlayer insulating film 170 .

[0091] As shown in FIG. 8, a third interlayer insulating film 330 covering the plate electrode 230 is formed on the second interlayer insulating film 170 and the second and third conductive pads (184, 186), and a second etch stop film 340 is formed on the third interlayer insulating film 330. Then, a first contact plug 352 is formed that penetrates the second etch stop film 340 and contacts the upper surface of the plate electrode 230, and second and third contact plugs (354, 356) are formed that penetrate the second etch stop film 340 and the third interlayer insulating film 330 and contact the upper surfaces of the second and third conductive pads (184, 186), respectively.

[0092] In one embodiment of the present invention, the second and third contact plugs 354 and 356 are formed to have widths that decrease from the top to the bottom due to the characteristics of the etching process.

[0093] Thereafter, a first wiring film is formed on the second etch stop film 340 and the first to third contact plugs (352, 354, 356), and then the first wiring film is partially etched to form the first wiring 360, at which point the second etch stop film 340 is also partially etched to expose a portion of the upper surface of the third interlayer insulating film 330.

[0094] As shown in FIG. 9, a fourth interlayer insulating film 370 covering the first wiring 360 is formed on the third interlayer insulating film 330, and a second substrate 380 is bonded to the upper surface of the fourth interlayer insulating film 370 via a first bonding film 390.

[0095] The second substrate 380 includes a semiconductor material such as silicon or an insulating material such as glass, and the first bonding film 390 includes, for example, silicon carbonitride, silicon oxide, or the like.

[0096] Thereafter, the second substrate 380 is turned over, and as a result, the structure formed on the second substrate 380 is turned upside down, the following description will be based on the upside-down state.

[0097] As shown in FIG. 10, the first bulk substrate 100 and the buried oxide film 110 included in the first substrate structure are removed, for example, by a grinding process, thereby exposing the channel 125, the first and second gate insulation patterns (130, 150), and the upper surface of the first interlayer insulating film 300.

[0098] Thereafter, bit line structures 430 are formed on the exposed channel 125, the first and second gate insulating patterns 130 and 150, and the upper surface of the first interlayer insulating film 300. In one embodiment of the present invention, the bit line structures 430 extend in the second direction (D2) and are formed in plurality at intervals along the first direction (D1). Here, each bit line structure 430 commonly contacts the upper surface of the channel 125 arranged in the second direction (D2).

[0099] In one embodiment, each bit line structure 430 includes third and fourth conductive patterns (400, 420) stacked along a third direction (D3), which may include, for example, impurity-doped polysilicon and metal, respectively.

[0100] As shown in FIG. 11, second to sixth wirings (440, 460, 480, 484, 486), fourth to seventh contact plugs (452, 454, 474, 476), and a first via 470 are formed on the bit line structure 430, and a fifth interlayer insulating film 490 is formed on and covers the channel 125, the first and second gate insulating patterns (130, 150), and the first interlayer insulating film 300.

[0101] In one embodiment of the present invention, due to the characteristics of the etching process, the fourth to seventh contact plugs (452, 454, 474, 476) and the first via 470 are formed to have widths that decrease from the top to the bottom.

[0102] As shown in FIG. 12, first and second separated patterns (540, 550) are formed on the top of a third substrate 510.

[0103] The first and second isolation patterns (540, 550) are formed by partially removing the upper portion of the third substrate 510 to form first and second trenches, forming an isolation film on the third substrate 510 to fill the first and second trenches, and then performing a planarization process, such as a chemical mechanical polishing (CMP) process and / or an etch back process, on the isolation film.

[0104] In one embodiment of the present invention, the bottom surface of the first isolated pattern 540 is higher than the bottom surface of the second isolated pattern 550. Each of the first and second isolated patterns (540, 550) comprises an oxide, for example silicon oxide.

[0105] Thereafter, a gate structure 630 is formed on the third substrate 510, and an impurity region 640 is formed on the upper portion of the third substrate 510 adjacent to the gate structure 630.

[0106] The gate structure 630 includes a third gate insulating pattern 620 and a third gate electrode 610 stacked in a third direction (D3), and the gate structure 630 and the impurity region 640 form a transistor.

[0107] Thereafter, a sixth interlayer insulating film 750 is formed on the third substrate 510 to cover the transistors.

[0108] As shown in FIG. 13, a fourth substrate 1200 is bonded to the upper surface of the sixth interlayer insulating film 750 via a second bonding film 1210.

[0109] The fourth substrate 1200 includes a semiconductor material such as silicon or an insulating material such as glass, and the second bonding film 1210 includes, for example, silicon carbonitride, silicon oxide, or the like.

[0110] Thereafter, the fourth substrate 1200 is turned over, and as a result, the structure formed on the fourth substrate 1200 is turned upside down, so the following description will be based on the upside-down state.

[0111] Thereafter, the upper portion of the third substrate 510 is removed, for example, by a grinding process. In one embodiment of the present invention, the grinding process is performed until the upper surface of the second separation pattern 550 is exposed. That is, the second separation pattern 550 serves as the end point of the grinding process.

[0112] As shown in FIG. 14, a seventh interlayer insulating film 500 is formed on the upper surfaces of the third substrate 510 and the second isolated pattern 550 .

[0113] In one embodiment of the present invention, the seventh interlayer insulating layer 500 comprises an oxide, such as silicon dioxide, or silicon carbonitride. In one embodiment, the seventh interlayer insulating layer 500 comprises substantially the same material as the second isolation pattern 550, such as silicon dioxide, and may be merged therewith.

[0114] As shown in FIG. 15, after the fourth substrate 1200 is turned over, the seventh interlayer insulating film 500 is brought into contact with the fifth interlayer insulating film 490, and they are bonded together.

[0115] Thereafter, the fourth substrate 1200 and the second bonding film 1210 are removed by, for example, a grinding process.

[0116] As shown in FIG. 16, after forming a seventh opening that penetrates the sixth interlayer insulating film 750 to expose the upper surface of the impurity region 640, and an eighth opening that penetrates the sixth interlayer insulating film 750, the second isolation pattern 550, the seventh interlayer insulating film 500, and the upper portion of the fifth interlayer insulating film 490 to expose the upper surfaces of each of the fourth to sixth wirings (480, 484, 486), an eighth contact plug 650 and a through via 660 are formed in the seventh and eighth openings, respectively.

[0117] Due to the characteristics of the etching process for forming the seventh and eighth openings, each of the eighth contact plugs 650 and the through vias 660 is formed to have a width that decreases from top to bottom.

[0118] Referring again to Figure 1, seventh to twelfth wirings (770, 790, 810, 830, 850, 870) and second to sixth vias (780, 800, 820, 840, 860) are formed on the sixth interlayer insulating film 750, the eighth contact plug 650, and the through via 660, and an eighth interlayer insulating film 880 is formed to cover them.

[0119] Then, a ninth interlayer insulating film 890 and a third etch stop film 900 are sequentially formed on the eighth interlayer insulating film 880 and the twelfth wiring 870, and a seventh via 910 is formed through these to contact the upper surface of the twelfth wiring 870.After that, a thirteenth wiring 920 is formed on the third etch stop film 900 to contact the upper surface of the seventh via 910, and a tenth interlayer insulating film 930 is formed to cover the sidewall of this thirteenth wiring 920, thereby completing the manufacture of the semiconductor device.

[0120] As described above, when forming the first isolation pattern 540 on the third substrate 510, the second isolation pattern 550 having a deeper bottom surface can be formed, and after the third substrate 510 is turned over, when the upper portion thereof is removed by a grinding process, the second isolation pattern 550 can be used as an end point of the grinding process. This allows the third substrate 510, on which a peripheral circuit pattern such as a transistor is formed, to be bonded with an appropriate thickness onto the second substrate 380 on which the memory cells are formed.

[0121] Furthermore, since the second separation pattern 550 is formed to penetrate the third substrate 510 after the grinding process, through vias 660 that contact wiring electrically connected to the peripheral circuit pattern, such as the seventh wiring 770, and wiring arranged on the memory cell and electrically connected thereto, such as the fourth to sixth wirings (480, 484, 486), are formed to penetrate the second separation pattern 550, thereby electrically insulating them from the third substrate 510.

[0122] Fig. 17 is a cross-sectional view for explaining a second example of a semiconductor device according to an embodiment of the present invention, and is a view corresponding to Fig. 1. The semiconductor device is similar to the semiconductor device in Fig. 1 except for the through via, and therefore a duplicated description will be omitted.

[0123] As shown in FIG. 17, a plurality of through vias 660 penetrate the second isolated pattern 550.

[0124] That is, the through vias 660 are spaced apart from each other along the first and second directions (D1, D2) within the second isolated pattern 550 when viewed from above.

[0125] Since the through via 660 is formed to penetrate the sixth interlayer insulating film 750, the second isolation pattern 550, the seventh interlayer insulating film 500, and the upper part of the fifth interlayer insulating film 490, there is no need to form any additional insulating spacers to ensure insulation between them.

[0126] That is, if the through vias 660 are formed through the third substrate 510 without forming the second separation pattern 550 on the third substrate 510, openings must be formed through the third substrate 510 to prevent an electrical short between them, insulating spacers must be formed on the sidewalls of the openings, and then the through vias 660 must be formed in the remaining portions of the openings. As a result, the openings for forming the through vias 660 must have an additional width of about twice the thickness of the insulating spacers, which means that the openings have to have an increased width, making it difficult to form the through vias 660 densely.

[0127] However, in one embodiment of the present invention, the through vias 660 are formed to penetrate the second isolated pattern 550 formed in the third substrate 510, so there is no need to form separate insulating spacers in the openings used to form them. This allows the openings to be formed to have a relatively small size, and the through vias 660 are formed at a high density within a desired area. This allows the wiring included in the wiring structure to be arranged with a higher degree of freedom, thereby ensuring an improved integration density of the semiconductor device.

[0128] Fig. 18 is a cross-sectional view for explaining a third example of a semiconductor device according to an embodiment of the present invention, and is a view corresponding to Fig. 1. The semiconductor device is similar to the semiconductor device in Fig. 1 except for the through via and the second isolation pattern, and therefore a duplicated description will be omitted.

[0129] As shown in FIG. 18, the second separated pattern 550 is formed not only on the third substrate 510 but also on the sixth interlayer insulating film 750 and the third bonding film 950, and the through via 660 penetrates the second separated pattern 550 and contacts the lower surface of the seventh wiring 770 and the upper surfaces of each of the fourth to sixth wirings (480, 484, 486).

[0130] 19 to 22 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention, and are cross-sectional views for explaining a method for manufacturing the semiconductor device in Fig. 18. The method for manufacturing a semiconductor device includes steps similar to those explained in Fig. 2 to Fig. 16 and Fig. 1, and therefore redundant explanations relating to these steps will be omitted.

[0131] Referring to FIG. 19, the same steps as those described with reference to FIGS. 2 to 12 are carried out.

[0132] However, the fifth interlayer insulating film 490 covers the side walls of the fourth to sixth wirings (480, 484, 486), but leaves the upper surfaces thereof exposed.

[0133] The second isolated pattern 550 is formed so as to penetrate not only the third substrate 510 but also the sixth interlayer insulating film 750. In the second isolated pattern 550, a through via 660 is formed.

[0134] In one embodiment, the second isolation pattern 550 and the through via 660 are formed by forming a third trench that penetrates the sixth interlayer insulating film 750 and the upper part of the third substrate 510, forming a second isolation film on the inner wall of the third trench and on the upper surface of the sixth interlayer insulating film 750, forming a through via film on the second isolation film that fills the third trench, and performing a planarization process, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, on the through via film until the upper surface of the sixth interlayer insulating film 750 is exposed.

[0135] As a result, the sidewalls and bottom surface of the through via 660 are covered with the second isolation pattern 550.

[0136] Alternatively, a through via 660 can be formed by forming a second isolation pattern 550 that fills the third trench, partially removing the second isolation pattern 550 to form a fourth trench, forming a through via film that fills the fourth trench, and then performing a planarization process on the through via film.

[0137] Referring to FIG. 20, steps similar to those described in FIG. 13 are performed.

[0138] As a result, the fourth substrate 1200 is bonded to the upper surfaces of the sixth interlayer insulating film 750, the second isolation pattern 550, and the through via 660 via the second bonding film 1210. After the fourth substrate 1200 is flipped over, the upper portion of the third substrate 510 is removed by, for example, a grinding process, whereby the upper surface of the through via 660 is exposed and the portion of the second isolation pattern 550 formed on the upper surface of the through via 660 is removed.

[0139] As shown in FIG. 21, the upper portion of the third substrate 510 is further removed to expose the upper portion of the through via 660 and the upper portion of the second isolation pattern 550 surrounding it on the third substrate 510.

[0140] Then, a third bonding film 950 is formed on the third substrate 510, the second separation pattern 550, and the through via 660, and then a planarization process is performed on the third bonding film 950 until the top surfaces of the through via 660 and the second separation pattern 550 are exposed, so that the third bonding film 950 covers the sidewalls of the second separation pattern 550.

[0141] Referring to FIG. 22, steps similar to those described with reference to FIG. 15 are performed.

[0142] As a result, after the fourth substrate 1200 is flipped over, the third bonding film 950 comes into contact with the fifth interlayer insulating film 490, bonding them together, and here the through via 660 and the second separation pattern 550 covering its sidewall come into contact with the upper surfaces of each of the fourth to sixth wirings (480, 484, 486).

[0143] Thereafter, the fourth substrate 1200 and the second bonding film 1210 are removed by, for example, a grinding process.

[0144] Referring again to FIG. 18, the manufacturing of the semiconductor device is completed by carrying out steps similar to those described with reference to FIG. 16 and FIG.

[0145] Fig. 23 is a cross-sectional view for explaining a fourth example of a semiconductor device according to an embodiment of the present invention, and is a view corresponding to Fig. 1. The semiconductor device is similar to the semiconductor device in Fig. 1 except for some components, so duplicated explanations will be omitted.

[0146] As shown in FIG. 23, a peripheral circuit pattern including, for example, a transistor is formed on the lower part of the third substrate 510 and is arranged to face downward along the third direction (D3).

[0147] In addition, a bonding film structure for receiving a bonding pad structure is formed between a portion of the wiring structure formed on the memory cell and a portion of the wiring structure formed under the peripheral circuit pattern.

[0148] The bonding film structure includes fourth and fifth bonding films (1030, 1070) stacked in a third direction (D3), and the bonding pad structure includes first and second bonding pads (1020, 1060) stacked in the third direction (D3).

[0149] In one embodiment of the present invention, first interface pad 1020 includes a lower portion having a first width and an upper portion stacked on the lower portion and having a second width greater than the first width, and second interface pad 1060 includes a lower portion having a third width and an upper portion stacked on the lower portion and having a fourth width less than the third width. In one embodiment, the second width of the upper portion of first interface pad 1020 is substantially the same as the third width of the lower portion of second interface pad 1060, although the invention is not limited in this respect.

[0150] Each of the first and second bonding pads (1020, 1060) comprises a metal such as copper, and each of the fourth and fifth bonding films (1030, 1070) comprises a material such as silicon carbonitride, silicon oxide, or the like.

[0151] Meanwhile, an eighth via 1000 and a fourteenth wire 1010 are formed between the fourth wire 480 and the first bonding pad 1020 and are in contact with these, respectively. In addition, a fifteenth wire 775, a ninth via 785, a sixteenth wire 795, a tenth via 1040, and a seventeenth wire 1050 (the fifteenth to seventeenth wires are referred to as "second wiring structures" in the claims) are sequentially stacked downward along the third direction (D3) and are in contact with these, respectively, between the eighth contact plug 650 and the second bonding pad 1060.

[0152] A part of a wiring structure (referred to as a "third wiring structure" in the claims) that transmits electrical signals to the peripheral circuit pattern is formed on the third substrate 510. For example, seventh to thirteenth wirings (770, 790, 810, 830, 850, 870, 920) and second to seventh vias (780, 800, 820, 840, 860, 910) are formed on the third substrate 510, and an eighth interlayer insulating film 880, a third etch stop film 900, and a tenth interlayer insulating film 930 that cover these are formed on the third substrate 510.

[0153] Meanwhile, a through via 660 that penetrates the third substrate 510 and the upper portion of the sixth interlayer insulating film 750 and contacts the seventh and fifteenth wirings (770, 775), and a second isolated pattern 550 that covers the sidewall of the through via 660 are formed. Although the drawing shows one through via 660 formed in the second isolated pattern 550, the present invention is not limited thereto, and for example, a plurality of through vias 660 may be formed in the second isolated pattern 550, similar to that shown in FIG.

[0154] In the semiconductor device, signal lines are arranged on the lower and upper parts of the third substrate 510, and power lines are arranged on the upper part of the third substrate 510.

[0155] 24 to 26 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention, and are cross-sectional views for explaining a method for manufacturing the semiconductor device in Fig. 23. The method for manufacturing a semiconductor device includes steps similar to those explained in Fig. 2 to Fig. 16 and Fig. 1, and therefore redundant explanations relating to these steps will be omitted.

[0156] As shown in FIG. 24, the same steps as those described with reference to FIGS. 2 to 11 are carried out.

[0157] However, an eighth via 1000 and a fourteenth wire 1010 are further formed on the fourth wire 480 , and these are covered with a fifth interlayer insulating film 490 .

[0158] Thereafter, a fourth bonding film 1030 and a first bonding pad 1020 are formed on the fifth interlayer insulating film 490 and the fourteenth interconnect 1010. In one embodiment of the present invention, the first bonding pad 1020 is formed using a dual damascene process, thereby including a lower portion and an upper portion stacked on the lower portion and having a larger width than the lower portion.

[0159] As shown in FIG. 25, a gate structure 630 is formed on a third substrate 510, and an impurity region 640 is formed in an upper portion of the third substrate 510 adjacent to the gate structure 630, thereby forming a transistor including these.

[0160] Then, an eighth contact plug 650 is formed in contact with the upper surface of the impurity region 640, and then a fifteenth wiring 775, a ninth via 785, a sixteenth wiring 795, a tenth via 1040, and a seventeenth wiring 1050 are formed, stacked sequentially along the third direction (D3), and a sixth interlayer insulating film 750 is formed to cover them.

[0161] Thereafter, a fifth bonding film 1070 and a second bonding pad 1060 are formed on the sixth interlayer insulating film 750 and the seventeenth interconnect 1050. In one embodiment of the present invention, the second bonding pad 1060 is formed using a dual damascene process, thereby including a lower portion and an upper portion stacked on the lower portion and having a second width greater than the lower portion.

[0162] As shown in FIG. 26, after the third substrate 510 is flipped over, the fifth bonding film 1070 and the second bonding pad 1060 are brought into contact with the fourth bonding film 1030 and the first bonding pad 1020 formed on the second substrate 380, respectively, and bonded to each other.

[0163] That is, the structure formed on the third substrate 510 and the structure formed on the second substrate 380 are bonded to each other by a hybrid copper bonding (HCB) process.

[0164] Referring again to Figure 23, after forming the second isolation pattern 550 and the through via 660 that penetrate the third substrate 510 and the upper part of the sixth interlayer insulating film 750 and contact the upper surface of the fifteenth wiring 775, the seventh to twelfth wirings (770, 790, 810, 830, 850, 870) and the second to sixth vias (780, 800, 820, 840, 860) are formed in the eighth interlayer insulating film 880.

[0165] Thereafter, a ninth interlayer insulating film 890, a third etch stop film 900, a seventh via 910, a thirteenth wiring 920, and a tenth interlayer insulating film 930 are formed on the eighth interlayer insulating film 880 and the twelfth wiring 870, thereby completing the manufacture of the semiconductor device.

[0166] Fig. 27 is a cross-sectional view for explaining a fifth example of a semiconductor device according to an embodiment of the present invention, and is a view corresponding to Fig. 23. The semiconductor device is similar to the semiconductor device in Fig. 23 except for some components, and therefore, redundant explanations will be omitted.

[0167] As shown in FIG. 27, both the signal lines and the power lines are arranged between the memory cells and the peripheral circuit patterns.

[0168] As a result, unlike Figure 23, the 8th to 13th wirings (790, 810, 830, 850, 870, 920) and the 2nd to 7th vias (780, 800, 820, 840, 860, 910) are not arranged above the third substrate 510, but are arranged below the third substrate 510, specifically below the 16th wiring 795.

[0169] Meanwhile, an eleventh interlayer insulating film 1100 is formed on the third substrate 510, and the second isolation pattern 550 and the through via 660 penetrate through the eleventh interlayer insulating film 1100, the third substrate 510, and the upper portion of the sixth interlayer insulating film 750 to contact the upper surface of the fifteenth wiring 775. Here, the through via 660 is connected to an external input / output device to transmit input / output signals.

[0170] Fig. 28 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention, and is a cross-sectional view for explaining a method for manufacturing the semiconductor device in Fig. 27. The method for manufacturing a semiconductor device includes steps similar to those explained in Figs. 24 to 46 and 23, and therefore redundant explanations relating to these steps will be omitted.

[0171] As shown in FIG. 28, the same steps as those described with reference to FIGS. 24, 25, and 23 are carried out.

[0172] However, the second to sixth vias (780, 800, 820, 840, 860), the tenth via 1040, the eighth to twelfth wires (790, 810, 830, 850, 870), and the seventeenth wire 1050, and the eighth interlayer insulating film 880 covering them, are formed on the sixteenth wire 795 and the sixth interlayer insulating film 750. Meanwhile, the fifth bonding film 1070 and the second bonding pad 1060 are formed on the eighth interlayer insulating film 880 and the seventeenth wire 1050.

[0173] On the other hand, the second isolated pattern 550 and the through via 660 are not formed.

[0174] Referring again to FIG. 27, steps similar to those described with reference to FIG. 26 are performed.

[0175] As a result, after the third substrate 510 is flipped over, the fifth bonding film 1070 and the second bonding pad 1060 come into contact with the fourth bonding film 1030 and the first bonding pad 1020 formed on the second substrate 380, respectively, and are bonded to each other.

[0176] Thereafter, an eleventh interlayer insulating film 1100 is formed on the third substrate 510, and then a second separation pattern 550 and a through via 660 are formed that penetrate the eleventh interlayer insulating film 1100, the third substrate 510, and the upper portion of the sixth interlayer insulating film 750 and contact the upper surface of the fifteenth wiring 775, thereby completing the manufacture of the semiconductor device.

[0177] Fig. 29 is a cross-sectional view for explaining a sixth example of a semiconductor device according to an embodiment of the present invention, and is a view corresponding to Fig. 17. The semiconductor device is similar to the semiconductor device in Fig. 17 except for some components, so duplicated explanations will be omitted.

[0178] As shown in FIG. 29, an eighth via 1000 and a fourteenth wiring 1010 are formed on the fourth wiring 480 and covered with a fifth interlayer insulating film 490, and fourth and fifth bonding films (1030, 1070) and first and second bonding pads (1020, 1060) are arranged on the fifth interlayer insulating film 490 and the fourteenth wiring 1010.

[0179] Furthermore, an 18th wiring 1110 (referred to as a "second wiring structure" in the claims) and an 11th via 1120 are formed between the fifth bonding film 1070, the second bonding pad 1060, and the third substrate 510, and a 12th interlayer insulating film 1130 is formed to cover them. Here, each of the 11th vias 1120 contacts the lower surface of the through via 660 and is electrically connected thereto.

[0180] That is, the semiconductor device is formed by bonding together the memory cells and wiring structures for transmitting electrical signals thereto formed on the second substrate 380 and the peripheral circuit patterns formed on the third substrate 510 using the HCB process.

[0181] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0182] 100 First bulk substrate (first substrate structure) 110 Buried oxide film (first substrate structure) 120 spare channels 125 channels 130, 150, 620 1st to 3rd gate insulation patterns 140, 160, 610: First to third gate electrodes 180, 184, 186 First to third conductive pads 190, 210 First and second capacitor electrodes 200 Dielectric Film 220 Capacitor 230 Plate Electrode 300, 170, 330, 370, 490, 750, 500, 880, 890, 930, 1100 1st to 11th interlayer insulating films 310, 340, 900 1st to 3rd etch stop films 320 Support membrane 352, 354, 356, 452, 454, 474, 476, 650 1st to 8th contact plugs 360 First wiring (wiring structure) 380 Second substrate (in the claims, "first substrate") (first substrate structure) 390, 1210, 950 1st to 3rd bonding films 400, 420 Third and fourth conductive patterns 430 Bit Line Structure 440, 460, 480, 484, 486 Second to sixth wirings (first wiring structures) 470, 780, 800, 820, 840, 860, 910, 1000, 785, 1040, 1120 Vias 1 to 11 510 Third substrate (called "second substrate" in the claims) 540, 550 First and second separation patterns 630 Gate Structure (Transistor) 640 Impurity region (transistor) 660 Through Via 770, 790, 810, 830, 850, 870, 920 7th to 13th wiring (3rd wiring structure) 775, 795, 1050 15th to 17th wiring (second wiring structure) 1010 14th Wiring (Wiring Structure) 1020, 1060 First and second bonding pads (bonding pad structures) 1030, 1070 First and second bonding films (bonding film structure) 1110 18th wiring (second wiring structure) 1130 12th interlayer insulating film 1200 4th board

Claims

1. a capacitor disposed on the first substrate; a channel disposed on the capacitor; a gate electrode at least partially overlapping the channel in a horizontal direction; a bit line structure disposed on the gate electrode and the channel; a first wiring structure disposed on the bit line structure; a bond pad structure disposed on the first wiring structure; a second wiring structure disposed on the bond pad structure; a second substrate disposed on the second wiring structure; a transistor disposed below the second substrate; a third wiring structure disposed on the second substrate; an isolation pattern penetrating the second substrate; a through via that penetrates the isolation pattern.

2. 10. The semiconductor device of claim 1, further comprising a bonding film structure covering a sidewall of the bonding pad structure and including silicon carbonitride or silicon oxide.

3. an interlayer insulating film formed on the bonding film structure to cover the second wiring structure; 3. The semiconductor device according to claim 2, wherein the isolation pattern and the through via penetrate through an upper portion of the interlayer insulating film.

4. The semiconductor device according to claim 1 , wherein a plurality of the through vias are formed in the isolation pattern and spaced apart from each other in the horizontal direction.

5. 2. The semiconductor device according to claim 1, wherein the through via has a width that decreases from the top to the bottom.

6. 2. The semiconductor device according to claim 1, wherein the third wiring structure includes wiring for applying input / output signals.

7. 2. The semiconductor device according to claim 1, wherein the third wiring structure includes a power line.

8. 2. The semiconductor device according to claim 1, further comprising a plate electrode covering a lower surface and a sidewall of the capacitor.

9. a capacitor disposed on the first substrate; a channel disposed on the capacitor; a gate electrode at least partially overlapping the channel in a horizontal direction; a bit line structure disposed on the gate electrode and the channel; a first wiring structure disposed on the bit line structure; a bond pad structure disposed on the first wiring structure; a second wiring structure disposed on the bond pad structure; a second substrate disposed on the second wiring structure; a transistor disposed below the second substrate; an isolation pattern penetrating the second substrate; a through via that penetrates the isolation pattern, The semiconductor device is characterized in that the through via is connected to an input / output device and transmits an input / output signal generated by the input / output device.

10. a capacitor disposed on the first substrate; a channel disposed on the capacitor; a gate electrode at least partially overlapping the channel in a horizontal direction; a bit line structure disposed on the gate electrode and the channel; a first wiring structure disposed on the bit line structure; a bond pad structure disposed on the first wiring structure; a second wiring structure disposed on the bond pad structure; a second substrate disposed on the second wiring structure; a transistor formed on top of the second substrate; a third wiring structure disposed on the second substrate; an isolation pattern penetrating the second substrate; a plurality of through vias each passing through the isolation pattern and spaced apart from one another in the horizontal direction;

Images