Image sensor pixel with multiple lateral overflow integration capacitors

Abstract

To provide a system, an apparatus and a method for an image sensor pixel that achieves a high dynamic range.SOLUTION: The image sensor pixel 300 has a first lateral overflow integration capacitor (LOFIC capacitor) 310 and a second LOFIC capacitor 320. In an image sensor pixel, accumulating charge received from a photodiode 302 in a first LOFIC during a first integration period, reading out first charge from a floating diffusion node 306 and the first LOFIC capacitor at a first time, resetting the first LOFIC capacitor during a first reset period, and collecting second charge at the floating diffusion node and a second LOFIC capacitor from the photodiode during a second integration period that at least partially overlaps with the first reset period can be performed.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application No. 63 / 675,147, filed July 24, 2024, the contents of which are incorporated herein by reference as if fully disclosed herein.

[0002] The described embodiments relate generally to image sensors, and more particularly to systems, apparatus, and methods for operating image sensor pixels having multiple lateral overflow integration capacitors. [Background technology]

[0003] Modern consumer electronic devices come in many shapes and forms and have numerous uses and functions. Cameras continue to be an important feature of consumer electronic devices. Wearable devices, including smartphones, wrist-worn devices (e.g., watches or fitness tracking devices) and head-mounted devices (e.g., headsets, glasses, or earphones), and computers (e.g., tablet computers or laptop computers), for example, may use one or more cameras. The imaging capabilities of these consumer electronic devices are steadily increasing as the quality of individual cameras improves and devices begin to integrate multiple camera (“multi-camera”) systems and depth sensors. User demands continue for imaging capabilities that capture high-quality images in an ever-increasing range of situations, including high-dynamic-range imaging applications. Therefore, it may be desirable to continue to improve image sensors, including the design of the pixels that make up the pixel array. Summary of the Invention

[0004] Described herein are devices and methods for an image sensor pixel having multiple lateral overflow integration capacitors.

[0005] Some aspects of the present disclosure are directed to an image sensor pixel. The image sensor pixel includes a photodiode, a floating diffusion node, a first lateral overflow capacitor, a second lateral overflow capacitor, a first reset gate, and a second reset gate. The floating diffusion node is selectively coupled to the photodiode. The first lateral overflow capacitor is selectively coupled to the floating diffusion node. The second lateral overflow capacitor is selectively coupled to the floating diffusion node. The first reset gate is operable to selectively couple the first lateral overflow capacitor to a voltage source during a first reset period to reset the first lateral overflow capacitor. The second reset gate is operable to selectively couple the second lateral overflow capacitor to a voltage source during a second reset period to reset the second lateral overflow capacitor.

[0006] Some aspects of the present disclosure are directed to an image sensing device. The image sensing device includes an array of image sensor pixels including a photodiode, a floating diffusion node, multiple lateral overflow capacitors, and multiple reset gates; and a control circuit coupled to the array of image sensor pixels. The floating diffusion node is selectively coupled to the photodiode. The multiple lateral overflow capacitors are coupled to the floating diffusion node. The multiple reset gates selectively couple the multiple lateral overflow capacitors to a voltage source, each lateral overflow capacitor being associated with at least one of the multiple reset gates. The control circuit is configured to cause the floating diffusion node and at least one of the multiple lateral overflow capacitors to collect charge from the photodiode during at least one integration period. The control circuit is further configured to couple at least one of the multiple lateral overflow capacitors to the voltage source during at least one reset period to reset the multiple lateral overflow capacitors.

[0007] Some aspects of the present disclosure are directed to a method of controlling an image sensor pixel of an image sensing device. The method includes collecting a first charge from a photodiode at a floating diffusion node and a first lateral overflow capacitor of the image sensor pixel during a first integration period. The method further includes reading out the first charge from the floating diffusion node and the first lateral overflow capacitor at a first time. The method further includes resetting the first lateral overflow capacitor by coupling the first lateral overflow capacitor to a voltage source during a first reset period. The method further includes collecting a second charge from the photodiode at the floating diffusion node and a second lateral overflow capacitor of the plurality of lateral overflow capacitors during a second integration period that at least partially overlaps the first reset period.

[0008] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the drawings and by study of the following descriptions.

[0009] To easily identify the discussion of any particular element or act, the most significant digit(s) of a reference number refers to the number of the figure in which that element is first introduced. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 illustrates a back view of an illustrative example of a device including an image sensor array having pixels with multiple lateral overflow integration capacitors as described herein. [Figure 1B] 1B illustrates exemplary components of the device of FIG. 1A.

[0011] [Figure 2] 1 illustrates an exemplary image sensing device according to some aspects of the present disclosure.

[0012] [Figure 3]1 illustrates an exemplary image sensor pixel according to some aspects of the present disclosure.

[0013] [Figure 4] 1 illustrates an example timing diagram for operation of an image sensor pixel in accordance with some aspects of the present disclosure.

[0014] [Figure 5] 10 illustrates another example timing diagram for operation of an image sensor pixel in accordance with some aspects of the present disclosure.

[0015] [Figure 6] 1 illustrates another exemplary image sensor pixel according to some aspects of the present disclosure.

[0016] [Figure 7] 10 illustrates another example timing diagram for operation of an image sensor pixel in accordance with some aspects of the present disclosure.

[0017] [Figure 8] 1 illustrates an example method for controlling image sensor pixels of an image sensing device according to some aspects of the present disclosure.

[0018] [Figure 9] 1 illustrates an exemplary method for controlling an image sensing device according to some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0019] Reference will now be made in detail to exemplary embodiments as illustrated in the accompanying drawings. It should be understood that the following description is not intended to limit these embodiments to a single preferred embodiment. On the contrary, the following description is intended to cover alternatives, modifications, and equivalents, as may be included within the spirit and scope of the described embodiments as defined by the appended claims.

[0020] Image sensors including image sensor pixels with lateral overflow integration capacitors, also referred to herein as “LOFIC pixels,” have been widely adopted for imaging, particularly for high dynamic range imaging applications. In an image sensor pixel including a lateral overflow integration capacitor (also referred to herein as a “LOFIC capacitor”), charge generated from a photodiode can be stored in both a floating diffusion node and a LOFIC capacitor selectively coupled to the floating diffusion node. The LOFIC capacitor provides a charge overflow path, which can increase the amount of charge stored by the image sensor pixel when capturing an image. Thus, the LOFIC capacitor can be used to selectively increase the charge storage capability of the image sensor pixel, which can reduce the likelihood of the image sensor pixel saturating when capturing images of scenes with widely varying brightness. Typically, the LOFIC capacitor may be a metal-insulator-metal (MIM) capacitor. The MIM capacitor for an image sensor pixel can provide a relatively high capacitance per unit area relative to other capacitor designs, such as a metal-oxide-semiconductor (MOS) capacitor or a polysilicon-to-polysilicon capacitor. In some examples, the MIM capacitor for the LOFIC capacitor may be compatible with the pitch of pixels in a pixel array of about 1 micrometer or less.

[0021] However, conventional LOFIC pixels can introduce image lag artifacts that degrade image quality due to dielectric absorption / relaxation effects that occur in the LOFIC capacitor during the reset period of the image sensor pixel. During integration, the polarization of the dipoles in the dielectric of the LOFIC capacitor can change, and resetting the image sensor pixel can cause the dipoles of the LOFIC capacitor to return toward their initial polarization. If the reset time for resetting the LOFIC capacitor is not long enough, the dipoles may not fully return to their original state. Incomplete resetting of the dipoles can affect the readout of the image sensor pixel after integration of a subsequent image frame, creating image lag artifacts during the subsequent image frame.

[0022] Described herein are image sensors including image sensor pixels that utilize multiple charge overflow paths formed by multiple LOFIC capacitors. The use of multiple (e.g., two or more) charge overflow paths can ameliorate image lag artifacts induced by dielectric absorption and relaxation effects in high-density MIM capacitors in image sensor pixels that include multiple LOFIC capacitors. In certain operating modes, the image sensor pixels can alternate between multiple charge overflow paths between integration phases of different image frames. For example, the image sensor pixels switch between different overflow paths for successive integration phases (e.g., the image sensor pixel uses a first charge overflow path associated with a first LOFIC capacitor during the integration phase of a first image frame and a second charge overflow path associated with a second LOFIC capacitor during the integration phase of a subsequent second integration phase). Thus, because a given overflow path may not be used in successive integration phases, the LOFIC capacitor associated with that charge overflow path may experience a longer reset time without affecting the overall frame rate of the image sensor. Each overflow path can be turned on or off separately by a dedicated switch (LOFIC gate) and may also have a dedicated reset switch transistor to independently reset the LOFIC capacitor. The LOFIC capacitors may share a common bias voltage source in some examples, or may have independent bias voltage sources in other examples.

[0023] The image sensor pixel includes a floating diffusion node and at least a first LOFIC capacitor and a second LOFIC capacitor, each of which is selectively coupled to the floating diffusion node. During a first operational mode of the image sensor, the image sensor may capture a first set of image frames and a second set of image frames, the image frames of the first set alternating with the image frames of the second set. In one or more embodiments, the image sensor pixel can selectively collect charge on the first LOFIC capacitor (e.g., during each of the first set of image frames) via the first LOFIC gate and can selectively collect charge on the second LOFIC capacitor (e.g., during each of the second set of image frames) via the second LOFIC gate. The image sensor pixel can independently reset each LOFIC capacitor. For example, a first LOFIC capacitor may be reset while a second LOFIC capacitor is used for charge collection during a first set of image frames, and the second LOFIC capacitor may be reset while the first LOFIC capacitor is used for charge collection during a second set of image frames. This may allow for a longer corresponding reset period for each LOFIC capacitor, which is used for every other image frame during the first mode of operation. If higher charge collection capability is desired, both LOFIC capacitors may be used to collect charge during one or more image frames in the second mode of operation. Additionally or alternatively, in another mode of operation, neither LOFIC capacitor is used to collect charge during one or more image frames.

[0024] These and other embodiments are described below with reference to Figures 1A-9. However, those skilled in the art will readily appreciate that the detailed description provided herein with reference to these figures is for illustrative purposes only and should not be construed as limiting.

[0025] The image sensor pixels having multiple LOFIC capacitors described herein may be incorporated into a camera module, which may be incorporated into an electronic device such as a phone, tablet, computer, etc. Figure 1A shows an example device 100 described herein. As shown, device 100 includes a first camera 102 having an image sensor that uses pixels having multiple LOFIC capacitors.

[0026] In some examples, the first camera 102 is part of a multi-camera system. For example, in the variation shown in FIG. 1A , the first camera 102 is part of a multi-camera system having a second camera 104 and a third camera 106. The second camera 104 and / or the third camera 106 may, but need not, include an image sensor using pixels with multiple LOFIC capacitors as described herein. It should be understood that the device 100 may include a single camera or a multi-camera system having any number of cameras (with any relative positioning) as may be desired. Furthermore, while shown as being located on the back of the device 100, it should be understood that a camera having an image sensor using pixels with multiple LOFIC capacitors may additionally or alternatively be located on the front of the device (e.g., the front face with the display) or any other side face as desired.

[0027] In some examples, device 100 may include a flash module 108. The flash module 108 may provide illumination to some or all of the fields of view of the cameras of device 100 (e.g., the fields of view of the first camera 102, the second camera 104, and / or the third camera 106). This may assist image capture operations in low-light settings. Additionally or alternatively, device 100 may further include a depth sensor 110 that may calculate depth information about a portion of the environment around device 100. Specifically, depth sensor 110 may calculate depth information within a coverage area (i.e., the widest lateral range for which the depth sensor can provide depth information). The coverage area of ​​depth sensor 110 may at least partially overlap with the fields of view of one or more of the cameras (e.g., the fields of view of the first camera 102, the second camera 104, and / or the third camera 106). Depth sensor 110 may be any suitable system capable of calculating distances between depth sensor 110 and various points in the environment around device 100 .

[0028] Depth information can be calculated in any suitable manner. In one non-limiting example, a depth sensor can utilize stereo imaging, in which two images are taken from different positions, and the distance (parallax) between corresponding pixels in the two images can be used to calculate depth information. In another example, a depth sensor can utilize structured light imaging, whereby the depth sensor can image a scene while projecting a known pattern (typically using infrared illumination) toward the scene, and then calculate depth information by looking at how the pattern is distorted by the scene. In yet another example, a depth sensor can utilize time-of-flight sensing, which calculates depth based on the time it takes light (typically infrared) emitted from the depth sensor to return from the scene. Time-of-flight depth sensors can utilize direct or indirect time-of-flight and can illuminate the entire coverage area at once or can illuminate only a subset of the coverage area at a given time (e.g., with one or more spots, stripes, or other patterns that can be either fixed or scanned across the coverage area). In cases where the depth sensor utilizes infrared illumination, this infrared illumination may be utilized in a range of ambient conditions without being perceived by the user.

[0029] In some embodiments, device 100 is a portable multifunction electronic device, such as a mobile phone, that also includes other functions, such as PDA and / or music player functions. Exemplary embodiments of portable multifunction devices include, but are not limited to, iPhone®, iPod Touch®, and iPad® devices from Apple Inc. of Cupertino, California. In other embodiments, device 100 is a head-mounted device, such as an extended reality (XR) device, which may include an augmented reality (AR) or virtual reality (VR) device. Exemplary embodiments of head-mounted devices include, without limitation, the Vision Pro® device from Apple Inc. of Cupertino, California. Optionally, other portable electronic devices, such as a laptop computer or tablet computer, having a touch-sensitive surface (e.g., a touchscreen display and / or touchpad) are also used. It should also be understood that in some embodiments, the device is not a portable communication device, but rather a desktop computer that may have a touch-sensitive surface (e.g., a touchscreen display and / or touchpad). In some embodiments, the electronic device is a computer system in communication (e.g., via wired communication, via wireless communication) with a display generation component. The display generation component is configured to provide a visual output, such as a display via a CRT display, a display via an LED display, or a display via image projection. In some embodiments, the display generation component is integrated with the computer system. In some embodiments, the display generation component is separate from the computer system. As used herein, "displaying" content includes causing the content to be displayed by transmitting data (e.g., image data or video data) over a wired or wireless connection to an integrated or external display generation component to visually generate the content.

[0030] 1B shows exemplary components of device 100. In some embodiments, device 100 has a bus 126 operably coupling an I / O section 134 to one or more computer processors 136 and a memory 138. The I / O section 134 can be connected to a display 128, which can have touch-sensing components 130 and, optionally, an intensity sensor 132 (e.g., a contact intensity sensor). Additionally, the I / O section 134 can be connected to a communication unit 140 that receives application and operating system data using Wi-Fi, Bluetooth, near field communication (NFC), cellular, and / or other wireless communication technologies. Device 100 can include input mechanisms 142 and / or 144. The input mechanism 142 is optionally, for example, a rotatable input device or a depressible and rotatable input device. In some examples, the input mechanism 142 is optionally a button. Device 100 optionally includes various sensors, such as a GPS sensor 146, an accelerometer 148, an orientation sensor 150 (e.g., a compass), a gyroscope 152, a motion sensor 154, and / or combinations thereof, all of which may be operatively connected to I / O section 134. Some of these sensors, such as accelerometer 148 and gyroscope 152, may assist in determining the orientation of device 100 or portions thereof.

[0031] The memory 138 of the device 100 may include one or more non-transitory computer-readable storage media for storing computer-executable instructions that, when executed by one or more computer processors 136, can, for example, cause the computer processors to perform the techniques described herein (such as operating the mechanical iris assembly described herein). A computer-readable storage medium may be any medium that can tangibly contain or store computer-executable instructions used by or in connection with an instruction execution system, apparatus, or device. In some embodiments, the storage medium is a transient computer-readable storage medium. In some embodiments, the storage medium is a non-transitory computer-readable storage medium. Non-transitory computer-readable storage media may include, but are not limited to, magnetic storage devices, optical storage devices, and / or semiconductor storage devices. Examples of such storage devices include magnetic disks, optical disks based on CD, DVD, or Blu-ray technology, as well as persistent solid-state memory such as flash, solid-state drives, and the like.

[0032] Processor 136 may include, for example, special purpose hardware as defined herein, a computing device as defined herein, a processor, a microprocessor, a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a complex programmable logic device (CPLD), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any other programmable logic device (PLD) configurable to execute the operating system and applications of device 100 and to facilitate capturing images as described herein. Device 100 is not limited to the components and configuration of FIG. 1B and may include other or additional components in multiple configurations.

[0033] 2 illustrates an exemplary image sensing device 200 in accordance with some aspects of the present disclosure. In one or more embodiments, the image sensing device 200 supports one or more aspects of an image sensor pixel having multiple LOFIC capacitors, as further described herein. The image sensing device 200 includes an image sensor 210 and an image sensor driver 220 coupled to the image sensor 210.

[0034] The image sensor 210 includes a pixel array 218 that includes an array of image sensor pixels. At least a subset of the pixels of the image sensor pixels of the pixel array 218 may each be configured as an image sensor pixel having multiple LOFIC capacitors, as described further herein. The image sensor 210 further includes column circuitry 212 and row circuitry 214 that are used to selectively access and readout each image sensor pixel in the pixel array 218 during integration, readout, and reset operations during a given image frame. The analog processing circuitry 216 includes one or more amplifiers and an analog-to-digital converter (ADC). The one or more amplifiers are used to read out collected charge from the photodiodes of the pixels of the pixel array 218. The ADC converts analog signals related to the collected charge into digital signals indicative of the value of the charge. The analog processing circuitry 216 may include additional circuitry, such as gain control circuitry (e.g., automatic gain control (AGC) circuitry).

[0035] The image sensor driver 220 includes circuitry for providing signals to control various operations of the image sensor 210. The image sensor driver 220 can drive the column circuits 212 and the row circuits 214 during integration, readout, and reset operations of the image sensor 210. Additionally, the image sensor driver 220 can provide signals to the column circuits 212 and the row circuits 214 to selectively reset capacitors of pixels in the pixel array 218. In some embodiments, the image sensor driver 220 can operate the image sensing device 200 according to one of several different operating modes. For example, the image sensing device 200 may be operated according to different frame rates. During operation of the image sensing device 200, the image sensor 210 can be operated to capture a series of image frames. Each image frame has a corresponding i) reset phase in which the charge accumulated in each image sensor pixel of pixel array 218 is reset to a predetermined level, ii) integration phase in which the image sensor pixels of pixel array 218 generate and accumulate photocurrent based on incident light, and iii) readout phase in which the charge accumulated by the image sensor pixels of pixel array 218 is measured.

[0036] 3 illustrates an exemplary image sensor pixel 300 in accordance with some aspects of the present disclosure. In one or more embodiments, the image sensor pixel 300 supports one or more aspects of an image sensor pixel having multiple LOFIC capacitors, as described further herein. In some examples, the image sensor pixel 300 may be an example of a pixel in the pixel array 218. The use of LOFIC capacitors for the image sensor pixel 300 may enable reduced image artifacts at higher frame rates during high dynamic range imaging.

[0037] The image sensor pixel 300 includes a photodiode 302 selectively coupled to a floating diffusion (FD) node 306 via a transfer gate 304. When exposed to light, the photodiode 302 absorbs photons and generates charge via the photoelectric effect. The photodiode 302 can generate this charge during the integration phase of an image frame, and the FD node 306 serves to receive and temporarily store this charge until it is read out as part of the readout phase of the image frame. Thus, charge can be accumulated in the photodiode 302 and, via the transfer gate 304, in the FD node 306.

[0038] During operation of the image sensor pixel described herein, each gate or transistor can be in either an on state (current flows through the transistor) or an off state (current does not flow through the transistor), depending on the bias across the gate / transistor and the control signal applied to the gate / transistor. For example, when a gate or transistor is described herein as being “closed,” the gate / transistor receives a control signal having a corresponding voltage level selected such that the gate / transistor remains in an off state during operation of the image sensor pixel. Alternatively, when a gate or transistor is described herein as being “open,” the gate / transistor receives a control signal having a corresponding voltage selected such that the gate / transistor can enter an on state. In some examples, an open gate may be “fully” open. In these examples, the control signal may be set to a voltage selected such that the gate remains in an on state during operation of the image sensor pixel. Thus, a fully open gate may act as a short circuit, allowing current to flow freely through the gate. In other examples, an open gate may be “partially” open. In these examples, the control signal may be set to an intermediate voltage selected such that the gate enters an on state only when the potential across the gate reaches a particular level.

[0039] Specifically, a partially open gate can be used to allow collection of overflow current. For example, transfer gate 304 may be partially open during the integration phase of an image frame, allowing FD node 306 to collect overflow current when the charge level in the photodiode exceeds a threshold level. In these examples, transfer gate 304 may receive a control signal having a voltage selected such that transfer gate 304 enters an ON state when the charge level in the photodiode exceeds a threshold level. Although transfer gate 304 is considered open (e.g., partially open) during this integration period, transfer gate 304 may remain in an OFF state if the charge level in the photodiode does not exceed the threshold level.

[0040] The FD node 306 has a capacitance (schematically shown in FIG. 3 as capacitor 308) to surrounding structures within the image sensor pixel 300 that controls how much charge the FD node 306 can hold. Thus, the photodiode 302 and the FD node 306 each have a limited capacity to store charge. It may be desirable for the image sensor pixel 300 to provide storage for more charge than the photodiode 302 and the FD node 306 can hold by themselves, such as when the image sensor performs high dynamic range imaging operations. Accordingly, the image sensor pixel 300 includes a first LOFIC capacitor 310 having a first terminal selectively coupled to the FD node 306 via a first LOFIC gate 312. Charge generated by the photodiode 302 can be further received and stored by the first LOFIC capacitor 310 (e.g., in addition to the charge stored by the FD node 306) while both the transfer gate 304 and the first LOFIC gate 312 are open. In this manner, the first LOFIC gate 312 and the first LOFIC capacitor 310 are operable to define a first charge overflow path 316 .

[0041] In some examples, the transfer gate 304 and the first LOFIC gate 312 may each be partially open during the integration period of an image frame. In these examples, the FD node 306 may receive overflow current through the transfer gate 304 when the charge level of the photodiode 302 reaches a first threshold level, and the first LOFIC capacitor 310 may receive overflow current from the FD node 306 through the first LOFIC gate 312 when the charge level in the FD node 306 reaches a second threshold level. In other examples, the transfer gate 304 may be partially open and the first LOFIC gate 312 may be fully open during the integration period of an image frame. In these examples, the overflow current received through the transfer gate 304 is collectively stored in the FD node 306 and the first LOFIC capacitor 310.

[0042] A first terminal of the first LOFIC capacitor 310 is further selectively coupled to a voltage source 338 via a first reset gate 314. A second terminal of the first LOFIC capacitor 310 may be coupled to a bias voltage source 336. In some embodiments, the bias voltage source may have a value in the range from ground to VDD. In some embodiments, the first LOFIC capacitor 310 may be a MIM capacitor, as described further herein.

[0043] In addition to the first LOFIC capacitor 310, it may be desirable for the image sensor pixel 300 to further include a second LOFIC capacitor 320 to provide storage for additional charge generated by the photodiode 302. Accordingly, the image sensor pixel 300 may further include the second LOFIC capacitor 320 having a first terminal selectively coupled to the FD node 306 via a second LOFIC gate 322. Charge generated by the photodiode 302 may be further received and stored by the second LOFIC capacitor 320 (e.g., in addition to the charge stored by the FD node 306) while both the transfer gate 304 and the second LOFIC gate 322 are open. In this manner, the second LOFIC gate 322 and the second LOFIC capacitor 320 are operable to define a second charge overflow path 326.

[0044] In some examples, the transfer gate 304 and the second LOFIC gate 322 may each be partially open during the integration period of an image frame. In these examples, the FD node 306 may receive overflow current through the transfer gate 304 when the charge level of the photodiode 302 reaches a first threshold level, and the second LOFIC capacitor 320 may receive overflow current from the FD node 306 through the second LOFIC gate 322 when the charge level in the FD node 306 reaches a second threshold level. In other examples, the transfer gate 304 may be partially open and the second LOFIC gate 322 may be fully open during the integration period of an image frame. In these examples, the overflow current received through the transfer gate 304 is collectively stored in the FD node 306 and the second LOFIC capacitor 320.

[0045] The first terminal of the second LOFIC capacitor 320 is further selectively coupled to a voltage source 338 via a second reset gate 324. The second terminal of the second LOFIC capacitor 320 may be coupled to a bias voltage source 336. In some embodiments, the bias voltage source may have a value in a range from ground (e.g., GND) to VDD. In some embodiments, the second LOFIC capacitor 320 may be a MIM capacitor, as described further herein.

[0046] In some embodiments, as shown for image sensor pixel 300, first LOFIC capacitor 310 and second LOFIC capacitor 320 share a common bias voltage source 336. In other embodiments, image sensor pixel 300 can use a first bias voltage source (not shown) for first LOFIC capacitor 310 and a different second bias voltage source (not shown) for second LOFIC capacitor 320.

[0047] The first LOFIC gate 312 and the second LOFIC gate 322 are separately controllable, which can control the flow of charge between the FD node 306 and the first LOFIC gate 312 (e.g., along a first charge overflow path 316) and the flow of charge between the FD node 306 and the second LOFIC gate 322 (e.g., along a second charge overflow path 326), respectively. For example, the image sensor pixel 300 can be controlled to control which charge overflow path is active during the integration phase of a given image frame, for example, in response to control signaling from a processor (e.g., the image sensor driver 220, the processor 136). During certain operating modes, the first LOFIC gate 312 and the second LOFIC gate 322 can be simultaneously open (e.g., partially open or fully open) during the integration phase of an image frame to allow charge to accumulate in parallel from the photodiode 302.

[0048] In other modes of operation, the first LOFIC gate 312 and the second LOFIC gate 322 can be opened at different times (e.g., alternately) to allow charge to be accumulated from the photodiode 302 alternately during different image frames. For example, during the integration phase of some image frames, the second LOFIC gate 322 can be closed and the first LOFIC gate 312 can be opened (e.g., partially opened or fully opened). During these integration phases, charge from the FD node 306 can be accumulated in the first LOFIC capacitor 310 along the first charge overflow path 316, but not in the second LOFIC capacitor 320. During the integration phases of other image frames, the first LOFIC gate 312 can be closed and the second LOFIC gate 322 can be opened (e.g., partially opened or fully opened). During these times, charge from the FD node 306 may be stored in the second LOFIC capacitor 320 along the second charge overflow path 326, but not in the first LOFIC capacitor 310. In yet another mode of operation, the first LOFIC gate 312 and the second LOFIC gate 322 may both be closed during the integration phase of an image frame, such that the image sensor pixel 300 does not utilize either the first charge overflow path 316 or the second charge overflow path 326.

[0049] The image sensor pixel 300 further includes readout circuitry that may include a source follower transistor 330 and a readout select gate 332. The gate of the source follower transistor 330 may be coupled to the FD node 306. The source follower transistor 330 and the readout select gate 332 selectively couple a select line 334 to a voltage source 338. When the readout select gate 332 is open (e.g., to select the image sensor pixel 300 for readout), the source follower transistor 330 allows current to flow between the select line 334 and the voltage source 338, where the amount of current is based on at least the amount of charge accumulated and stored by the image sensor pixel 300 at the FD node 306. Thus, the readout circuitry may be operated to measure at least the amount of charge accumulated by the FD node 306. In some examples, the transfer gate 304 may be fully open during a portion of the readout so that the readout circuitry can also measure the charge accumulated in the photodiode 302. Similarly, the first LOFIC gate 312 and / or the second LOFIC gate 322 may be fully open during a portion of the readout so that the readout circuitry can also measure the charge stored by the first LOFIC capacitor 310 and / or the second LOFIC capacitor 320.

[0050] The image sensor pixel 300 can be operated to perform a single sampling operation or multiple sampling operations (e.g., double sampling operations) during the readout phase of an image frame. For example, during a single sampling operation, the readout circuitry can make a single measurement of the charge accumulated by the image sensor pixel 300. In some of these variations, the transfer gate 304, as well as the corresponding LOFIC gates of any charge overflow paths that were active during the integration period, can be completely opened so that the readout circuitry can measure the collective charge accumulated in the photodiode 302, the FD node 306, and any LOFIC capacitors that were active during the integration period.

[0051] During multiple sampling operations, the readout circuitry may perform multiple separate measurements of the charge accumulated by the image sensor pixel 300. For example, the transfer gate 304 may be in an off state (e.g., the transfer gate 304 may be closed) during a first measurement so that the readout circuitry may measure the charge accumulated in the FD node 306 (and one or more of the LOFIC capacitors, depending on whether one or both of the charge overflow paths were active during the integration period). In these cases, the first measurement may not include the charge accumulated in the photodiode 302. The transfer gate 304 may be fully opened after the first measurement, and a second measurement may be performed that may reflect the charge accumulated in the photodiode 302. It should be understood that, depending on the sampling operations, the image sensor pixel may include additional measurements during the readout phase and / or reset the FD node 306 between some of the individual measurements of the sampling operation.

[0052] 4 illustrates an example timing diagram 400 in accordance with some aspects of the present disclosure. In one or more embodiments, the timing diagram 400 supports one or more aspects of an image sensor pixel having multiple LOFIC capacitors during a first mode of operation, as described further herein. For example, the timing diagram 400 illustrates the timing of the integration, readout, and reset phases of an image frame captured by the image sensor pixel, where the image sensor pixel alternates between utilizing a first LOFIC capacitor (and associated first charge overflow path) and a second LOFIC capacitor (and associated second charge overflow path). In one or more embodiments, one or more aspects of the device 100 (e.g., an image sensor of a camera system) or the image sensing device 200 may operate according to the timing diagram 400. In some embodiments, the image sensor pixel operating according to the timing diagram 400 may be the image sensor pixel 300.

[0053] Timing diagram 400 illustrates the functional operation of an image sensor pixel using at least two LOFIC capacitors. For illustrative purposes, the operation of timing diagram 400 will be described with reference to image sensor pixel 300 of FIG. 3. Timing diagram 400 illustrates the operation of image sensor pixel 300 during a series of image frames captured during a first mode of operation. The series of images illustrated in FIG. 4 includes four consecutive image frames: first image frame 401, second image frame 402, third image frame 403, and fourth image frame 404. It should be understood that the series of image frames can include any suitable number of image frames, and that image sensing device 200 can continue to capture image frames until image sensing device 200 stops operating to change to a different mode of operation. Each image frame includes three phases: a reset phase 406, an integration phase 408, and a readout phase 418.

[0054] The series of image frames includes a first set of image frames (e.g., including a first image frame 401 and a third image frame 403) and a second set of image frames (e.g., including a second image frame 402 and a fourth image frame 404). The series of image frames may be divided into several repeating frame periods 430, each of which includes an image frame from the first set and an image frame from the second set. Thus, the image frames of the first set of image frames alternate with the image frames of the second set of image frames. Each image frame of the first set of image frames includes a corresponding integration phase 408, during which the first LOFIC capacitor 310 is coupled to the FD node 306 to collect charge along the first charge overflow path 316. Conversely, each image frame of the second set of image frames includes a corresponding integration phase 408, during which the second LOFIC capacitor 320 is coupled to the FD node 306 to collect charge along the second charge overflow path 326. Thus, each frame period 430 may include an image frame captured using the first LOFIC capacitor 310 and an image frame captured using the second LOFIC capacitor 320 .

[0055] 4 , during acquisition of a series of image frames, the first LOFIC capacitor 310 may be operated according to a first LOFIC operation 410, and the second LOFIC capacitor 320 may be operated according to a second LOFIC operation 420. Specifically, the first LOFIC operation 410 may include a series of integration periods 412 and reset periods 414 for the first LOFIC capacitor 310. Similarly, the second LOFIC operation 420 may include a series of integration periods 422 and reset periods 424 for the second LOFIC capacitor 320. Within a single frame period 430, the first LOFIC operation 410 includes an integration period 412 for the first LOFIC capacitor 310 and an integration period 422 for the second LOFIC capacitor 320.

[0056] As shown, the timing of the duration of the first LOFIC operation 410 and the duration of the second LOFIC operation 420 may vary within a single frame period 430. For example, the first image frame 401 and the second image frame 402 collectively form the frame period 430 of FIG. 4 , and during the reset phase 406 of the first image frame 401, the first LOFIC operation 410 includes a portion of the reset period 414 of the first LOFIC capacitor 310, and the second LOFIC operation 420 includes a first portion of the reset period 424 of the second LOFIC capacitor 320. During the integration phase 408 of the first image frame 401, the first LOFIC operation 410 includes the integration period 412 of the first LOFIC capacitor 310, and the second LOFIC operation 420 includes a second portion of the reset period 424 of the second LOFIC capacitor 320. During the reset phase 406 of the second image frame 402, the first LOFIC operation 410 includes a first portion of a subsequent reset period 414 for the first LOFIC capacitor 310, and the second LOFIC operation 420 includes a third portion of a reset period 424 for the second LOFIC capacitor 320. During the integration phase 408 of the second image frame 402, the first LOFIC operation 410 includes a second portion of a subsequent reset period 414 for the first LOFIC capacitor 310, and the second LOFIC operation 420 includes an integration period 422 for the second LOFIC capacitor 320.

[0057] In one or more embodiments, during the integration period 412 of the first LOFIC operation 410, charge may be received from the photodiode 302 and stored in the first LOFIC capacitor 310 while the transfer gate 304 and the first LOFIC gate 312 are open. The transfer gate 304 and the first LOFIC gate 312 are open, allowing the photodiode 302 to be coupled to the FD node 306 (e.g., when the transfer gate 304 is in an on state) and the FD node 306 to be coupled to the first LOFIC capacitor 310 (e.g., when the first LOFIC gate 312 is in an on state). During the integration period 412, the first reset gate 314 is closed (resulting in the first LOFIC capacitor 310 being electrically isolated from the voltage source 338). Thus, during the integration phase 408 of an image frame of the first set of image frames (e.g., the first image frame 401 and the third image frame 403), charge can be collected by the first LOFIC capacitor 310 along the first charge overflow path 316. Furthermore, in an image frame in which the second LOFIC capacitor 320 is in a reset period during the integration phase of that image frame, the second LOFIC gate 322 is closed such that the second LOFIC capacitor 320 is electrically isolated from the FD node 306. Thus, during the integration phase 408 of the first set of image frames, at least a portion of the charge generated in the photodiode 302 can flow to the first LOFIC capacitor 310 via the first charge overflow path 316, but the charge is not collected along the second charge overflow path 326.

[0058] Similarly, in one or more embodiments, during the integration period 422 of the second LOFIC operation 420, charge may be received from the photodiode 302 and stored in the second LOFIC capacitor 320 while the transfer gate 304 and the second LOFIC gate 322 are open. The transfer gate 304 and the second LOFIC gate 322 are open, allowing the photodiode 302 to be coupled to the FD node 306 (e.g., when the transfer gate 304 is in an on state) and the FD node 306 to be coupled to the second LOFIC capacitor 320 (e.g., when the second LOFIC gate 322 is in an on state). During the integration period 412, the second reset gate 324 is closed (resulting in the second LOFIC capacitor 320 being electrically isolated from the voltage source 338). Thus, during the integration phase 408 of an image frame of the second set of image frames (e.g., the second image frame 402 and the fourth image frame 404), charge can be collected by the second LOFIC capacitor 320 along the second charge overflow path 326. Furthermore, in image frames in which the first LOFIC capacitor 310 is in a reset period during the integration phase of that image frame, the first LOFIC gate 312 is closed such that the first LOFIC capacitor 310 is electrically isolated from the FD node 306. Thus, during the integration phase 408 of the second set of image frames, at least a portion of the charge generated in the photodiode 302 can flow to the second LOFIC capacitor 320 via the second charge overflow path 326, but the charge is not collected along the first charge overflow path 316.

[0059] In one or more embodiments, during the reset period 414 of the first LOFIC operation 410, the first LOFIC capacitor 310 may be coupled to the voltage source 338 with the first reset gate 314 open (e.g., fully open). The reset period 414 of the first LOFIC capacitor 310 may span multiple image frames and may also span multiple phases within a given image frame. For example, a first portion of the reset period 414 of the first LOFIC capacitor 310 may occur (e.g., overlap) during the reset phase 406 of the second image frame 402, a second portion of the reset period 414 may occur during the integration phase 408 of the second image frame 402, and a third portion of the reset period 414 may occur during the reset phase 406 of the third image frame 403.

[0060] The integration period 422 of the second LOFIC capacitor 320 may at least partially overlap with the reset period 414 of the first LOFIC capacitor 310. For example, a second portion of the reset period 414 of the first LOFIC capacitor 310 may overlap with the integration period 422 of the second LOFIC capacitor 320 during the integration phase 408 of the second image frame 402. The first LOFIC gate 312 changes between an open state and a closed state during different portions of the reset period 414. For example, during the second portion of the reset period 414 (e.g., overlapping with the integration phase 408 of the second image frame 402), the first LOFIC gate 312 may be closed to electrically isolate the first LOFIC capacitor 310 from the FD node 306. During the first and / or third portions of the reset period 414, the first LOFIC gate 312 may be opened (e.g., fully opened) to couple the FD node 306 to the voltage source 338 via the first reset gate 314 and the first LOFIC gate 312. This may facilitate resetting the FD node 306 during the reset phase of a given image frame.

[0061] Similarly, in one or more embodiments, during the reset period of the second LOFIC operation 420, the second LOFIC capacitor 320 may be coupled to the voltage source 338 with the second reset gate 324 open (e.g., fully open). The reset period 424 of the second LOFIC capacitor 320 may span multiple image frames and may also span multiple phases within a given image frame. For example, a first portion of the reset period 424 of the second LOFIC capacitor 320 may occur during the reset phase 406 of the first image frame 401, a second portion of the reset period 424 may occur during the integration phase 408 of the first image frame 401, and a third portion of the reset period 424 may occur during the reset phase 406 of the second image frame 402. Similarly, the subsequent reset period 424 of the second LOFIC capacitor 320 may overlap with each of the reset phase 406 of the third image frame 403, the integration phase 408 of the third image frame 403, and the reset phase 406 of the fourth image frame 404.

[0062] The integration period 412 of the first LOFIC capacitor 310 may at least partially overlap with the reset period 424 of the second LOFIC capacitor 320. For example, a second portion of the reset period 424 of the second LOFIC capacitor 320 may overlap with the integration period 412 of the first LOFIC capacitor 310 during the integration phase 408 of the first image frame 401. The second LOFIC gate 322 changes between an open state and a closed state during different portions of the reset period 424. For example, during the second portion of the reset period 424 (e.g., overlapping with the integration phase 408 of the first image frame 401), the second LOFIC gate 322 may be closed to electrically isolate the second LOFIC capacitor 320 from the FD node 306. During the first and / or third portions of the reset period 424, the second LOFIC gate 322 may be opened (e.g., fully opened) to couple the FD node 306 to the voltage source 338 via the second reset gate 324 and the second LOFIC gate 322. This may facilitate resetting the FD node 306 during the reset phase of a given image frame.

[0063] During the readout phase of each of a series of image frames, the image sensor pixel 300 may be configured to read out charge collected on the FD node 306, as well as on the photodiode 302 and any LOFIC capacitors used to collect charge during the integration phase of that image frame. In one or more embodiments, at the end of the integration period 412 of the first LOFIC capacitor 310, the charge accumulated by the image sensor pixel 300 may be read out in a first sampling operation. As part of the first sampling operation, the charge accumulated on the photodiode 302, the FD node 306, and the first LOFIC capacitor 310 may be read out via one or more individual measurements. This may occur during the readout phase 418 of the first set of image frames (e.g., during the readout phases 418 of the first image frame 401 and the third image frame 403). During each individual measurement, the read select gate 332 is opened, thereby allowing the source follower transistor 330 to drive the select line 334 according to the charge stored by the FD node 306 (and any additional components coupled to the FD node 306). If the read phase 418 of an image frame overlaps with the reset period 424 of the second LOFIC capacitor 320, the second LOFIC gate 322 is closed during that read phase 418.

[0064] In one or more embodiments, at the end of the integration period 422 of the second LOFIC capacitor 320, the charge accumulated by the image sensor pixel 300 may be read out in a first sampling operation. As part of the first sampling operation, the charge accumulated in the photodiode 302, the FD node 306, and the second LOFIC capacitor 320 may be read out via one or more individual measurements. This may occur during the readout phase 418 of the second set of image frames (e.g., during the readout phases 418 of the second image frame 402 and the fourth image frame 404). During each individual measurement, the readout select gate 332 is open, allowing the source follower transistor 330 to drive the select line 334 according to the charge accumulated by the FD node 306 (and any additional components coupled to the FD node 306). If the readout phase 418 of an image frame overlaps with the reset period 414 of the second LOFIC capacitor 320, the second LOFIC gate 322 is closed during that readout phase 418.

[0065] During other modes of operation, multiple LOFIC capacitors of an image sensor pixel may be used simultaneously to accumulate charge. FIG. 5 illustrates an example timing diagram 500 in accordance with some aspects of the present disclosure. In one or more embodiments, timing diagram 500 supports one or more aspects of an image sensor pixel having multiple LOFIC capacitors during a second mode of operation, as described further herein. For example, timing diagram 500 illustrates the timing of the integration, readout, and reset phases of an image sensor pixel utilizing a first LOFIC capacitor and a second LOFIC capacitor in parallel. In this manner, photocurrent generated by a photodiode may be accumulated in multiple charge overflow paths during the same integration phase. In one or more embodiments, one or more aspects of device 100 (e.g., an image sensor in a camera system) or image sensing device 200 may operate according to timing diagram 500. In some embodiments, the image sensor pixel operating according to timing diagram 500 may be image sensor pixel 300. For clarity, features not specifically described with reference to timing diagram 500 may have a corresponding description with respect to timing diagram 400.

[0066] Timing diagram 500 illustrates the functional operation of an image sensor pixel using at least two LOFIC capacitors. For illustrative purposes, the operation of timing diagram 400 will be described with reference to image sensor pixel 300 of FIG. 3. Timing diagram 500 illustrates the operation of the image sensor pixel during a series of image frames captured during a second mode of operation. The series of image frames illustrated in FIG. 4 includes four consecutive image frames: first image frame 501, second image frame 502, third image frame 503, and fourth image frame 504. It should be understood that the series of image frames can include any suitable number of image frames, and that image sensing device 200 can continue to capture image frames until image sensing device 200 stops operating to change to a different mode of operation. Each image frame includes three phases: a reset phase 506, an integration phase 508, and a readout phase 518.

[0067] A series of image frames may be divided into several repeating frame periods 530. In the variation shown in FIG. 5, each frame period 530 includes a single image frame, but it should be understood that in other examples, each frame period 530 may include one or more additional image frames utilizing different selections of charge overflow paths. Each frame period 530 includes an image frame having a corresponding integration phase 508, during which the first LOFIC capacitor 310 and the second LOFIC capacitor 320 are simultaneously coupled to the FD node 306 to collect charge along both the first charge overflow path 316 and the second charge overflow path 326.

[0068] 5 , during acquisition of a series of image frames, the first LOFIC capacitor 310 may be operated according to a first LOFIC operation 510, and the second LOFIC capacitor 320 may be operated according to a second LOFIC operation 520. Specifically, the first LOFIC operation 510 may include a series of integration periods 512 and reset periods 514 for the first LOFIC capacitor 310. Similarly, the second LOFIC operation 520 may include a series of integration periods 522 and reset periods 524 for the second LOFIC capacitor 320. Within a single frame period 530, the first LOFIC operation 510 includes at least the reset period 514 and integration period 512 for the first LOFIC capacitor 310, and the second LOFIC operation 520 includes at least the reset period 524 and integration period 522 for the second LOFIC capacitor 320.

[0069] For at least one image frame of each frame period 530, the image frame includes an integration phase 508 that includes both an integration period 512 of the first LOFIC capacitor 310 and an integration period 522 of the second LOFIC capacitor 320. Thus, the integration phase 508 uses both the first LOFIC capacitor 310 and the second LOFIC capacitor 320 in parallel, and thus charge is collected along the first charge overflow path 316 and the second charge overflow path 326 during a common duration. When the integration period 512 of the first LOFIC capacitor 310 and the integration period 522 of the second LOFIC capacitor 320 overlap during the integration phase 508, the transfer gate 304 opens to allow the FD node 306 to be coupled to and receive charge from the photodiode 302, the first LOFIC gate 312 opens to allow the first LOFIC capacitor 310 to be coupled to and receive charge from the FD node 306, and the second LOFIC gate 322 opens to allow the second LOFIC capacitor 320 to be coupled to and receive charge from the FD node 306. Additionally, both the first reset gate 314 and the second reset gate 324 are closed (resulting in the first LOFIC capacitor 310 and the second LOFIC capacitor 320 being electrically isolated from the voltage source 338). Overall, during the integration phase 508 of an image frame (e.g., any of the first image frame 501, the second image frame 502, the third image frame 503, or the fourth image frame 504), at least a portion of the charge generated in the photodiode 302 can flow to the first LOFIC capacitor 310 via the first charge overflow path 316, and at least a portion of the charge generated in the photodiode 302 can flow to the second LOFIC capacitor 320 via the second charge overflow path 326.

[0070] The image frame may further include a reset phase 506 that includes both a reset period 514 of the first LOFIC capacitor 310 and a reset period 524 of the second LOFIC capacitor 320. Thus, during the reset phase 506, both the first LOFIC capacitor 310 and the second LOFIC capacitor 320 are connected to a first voltage source (e.g., VDD) to reset the LOFIC capacitors. The reset phase 506 may be characterized by the first LOFIC capacitor 310 being coupled to the first voltage source with its first reset gate 314 open (as part of the reset period 514 of the first LOFIC capacitor 310) and the second LOFIC capacitor 320 being coupled to the first voltage source with its second reset gate 324 open (as part of the reset period 524 of the second LOFIC capacitor 320). One or both of the first LOFIC gate 312 or the second LOFIC gate 322 may be open to couple the FD node 306 during the reset phase 506, which may reset the FD node 306. Additionally, the transfer gate 304 may be closed during the reset phase 506 so that the FD node 306 does not collect photocurrent from the photodiode 302.

[0071] A readout phase 518 follows the integration phase 508 and allows the charge collectively stored on the FD node 306, the first LOFIC capacitor 310, and the second LOFIC capacitor 320 to be read out. Specifically, during the readout phase 518, a sampling operation may allow measurement of the charge stored by the photodiode 302, the first LOFIC capacitor 310, and the second LOFIC capacitor 320 via one or more individual measurements.

[0072] While the image sensor pixel 300 of FIG. 3 is shown as having two LOFIC capacitors defining two charge overflow paths, it should be understood that the image sensors described herein may include image sensor pixels having three or more charge overflow paths, each associated with a corresponding LOFIC capacitor. For example, FIG. 6 shows an exemplary image sensor pixel 600 according to some aspects of the present disclosure. The image sensor pixel 600 is configured and labeled similarly to the image sensor pixel 300 of FIG. 3 , except that the image sensor pixel 600 includes additional LOFIC capacitors beyond the first LOFIC capacitor 310 and the second LOFIC capacitor 320. Specifically, the image sensor pixel 600 includes a number N of LOFIC capacitors, where N is greater than 2. Only the first LOFIC capacitor 310, the second LOFIC capacitor 320, and the Nth LOFIC capacitor 610 are shown in FIG. 6 .

[0073] The Nth LOFIC capacitor 610 may have a first terminal selectively coupled to the FD node 306 via an Nth LOFIC gate 612, forming an Nth charge overflow path 626. Charge may further be stored in the Nth LOFIC capacitor 610 (e.g., in addition to the charge at the FD node 306) while both the transfer gate 304 and the Nth LOFIC gate 612 are open. The first terminal of the Nth LOFIC capacitor 610 is further selectively coupled to a voltage source 338 via an Nth reset gate 624. The second terminal of the Nth LOFIC capacitor 610 may be coupled to an Nth bias voltage source 606. In some embodiments, the bias voltage source may have a value in the range from ground to VDD. In some embodiments, the Nth LOFIC capacitor 610 may be an MIM capacitor, as described further herein.

[0074] In some embodiments, the image sensor pixel 600 uses different bias voltages for different LOFIC capacitors. For example, the image sensor pixel 600 may use a first bias voltage source 602 for the first LOFIC capacitor 310, a second bias voltage source 604 for the second LOFIC capacitor 320, and an Nth bias voltage source 606 for the Nth LOFIC capacitor 610.

[0075] The image sensor pixel 600 can be operated in several different modes to capture image frames. Because the image sensor pixel 600 has at least three different charge overflow paths, there can be different selections of charge overflow paths that can be used during the integration phase of a given image frame. For example, during the integration phase of certain image frames, none of the charge overflow paths are used to collect charge (e.g., each of the LOFIC capacitors is in its respective reset period and electrically isolated from the FD node 306), and as a result, charge is collected only within the FD node 306 during those image frames. During the integration phase of other image frames, a single charge overflow path can be used to collect charge (as described herein with respect to FIG. 7 ). For still other image frames, multiple charge overflow paths (e.g., a subset of the overflow paths or all of the overflow paths) can be used to collect charge during the integration phase of a given image frame.

[0076] FIG. 7 shows an example timing diagram 700 in accordance with some aspects of the present disclosure. In one or more embodiments, timing diagram 700 supports one or more aspects of an image sensor pixel having three or more LOFIC capacitors, as described further herein. For example, timing diagram 700 illustrates the timing of the integration, reset, and readout phases of an image frame, during which the image sensor pixel sequentially alternates between charge overflow paths defined by N LOFIC capacitors. In one or more embodiments, one or more aspects of device 100 (e.g., an image sensor of a camera system) or image sensing device 200 may operate according to timing diagram 700. For purposes of explanation, the operation of timing diagram 400 is described with respect to image sensor pixel 600 of FIG. 6. For clarity, features not specifically described with reference to timing diagram 700 may have a corresponding description with respect to timing diagram 400 and / or timing diagram 500.

[0077] Timing diagram 700 illustrates the operation of image sensor pixel 600 during four image frames: first image frame 701, second image frame 702, third image frame 703, and fourth image frame 704. A series of image frames includes N different sets of images, each associated with a different LOFIC capacitor. For example, if N is 3, the series of image frames includes a first set of image frames (e.g., including first image frame 701 and fourth image frame 704), a second set of image frames (e.g., including second image frame 702), and a third set of image frames (e.g., including third image frame 703). The series of image frames may be divided into several repeating frame periods 740, each of which includes a corresponding image frame from each of the N sets of images. Each image frame includes three phases: a reset phase 706, an integration phase 708, and a readout phase 718. As shown with respect to timing diagram 700, a single frame period 740 may be repeated. That is, the frames of the first set of frames (e.g., including the first image frame 701 and the fourth image frame 704) rotate with the frames of the second set of frames (e.g., including the second image frame 702), and so on, rotating with the frames of the Nth set of frames (e.g., including the third image frame 703).

[0078] Each of the N LOFIC capacitors is associated with a corresponding LOFIC operation (e.g., a first LOFIC operation 710 for the first LOFIC capacitor 310, a second LOFIC operation 720 for the second LOFIC capacitor 320, and an Nth LOFIC operation 730 for the Nth LOFIC capacitor). Each LOFIC operation includes an integration period and a reset period as described above with respect to timing diagram 400 of FIG. 4. Each image frame of a frame period 740 includes a corresponding integration phase 708 associated with an integration period for a single LOFIC capacitor and reset periods for the remaining LOFIC capacitors. For example, during the integration phase 708 of the first image frame 701, the first LOFIC capacitor 310 may be in an integration period 712 (e.g., the first LOFIC gate 312 is open and the first reset gate 314 is closed), the second LOFIC capacitor 320 may be in a reset period 724 (e.g., the second LOFIC gate 322 is closed and the second reset gate 324 is open), and the Nth LOFIC capacitor 610 may be in a reset period 734 (e.g., the Nth LOFIC gate 622 is closed and the Nth reset gate 624 is open). During the integration phase 708 of the second image frame 702, the second LOFIC capacitor 320 may be in the integration period 722 (e.g., the second LOFIC gate 322 is open and the second reset gate 324 is closed), the first LOFIC capacitor 310 may be in the reset period 714 (e.g., the first LOFIC gate 312 is closed and the first reset gate 314 is open), and the Nth LOFIC capacitor 610 may be in the reset period 734. During the integration phase 708 of the third image frame 703 (which may represent the Nth image frame of the frame period 740), the Nth LOFIC capacitor 610 may be in the integration period 732 (e.g., the Nth LOFIC gate 622 is open and the Nth reset gate 624 is closed), the first LOFIC capacitor 310 may be in the reset period 714, and the second LOFIC capacitor 320 may be in the reset period 724.

[0079] During the reset phase of these image frames, all of the LOFIC capacitors may be in their respective reset periods. It should be understood that some or all of the LOFIC gates may be open during the reset phase, connecting the FD node 306 to the voltage source 338, thereby resetting the FD node 306.

[0080] By alternating the use of the first LOFIC capacitor, the second LOFIC capacitor, and so on up to the Nth LOFIC capacitor, the periodicity of operation of the image sensor pixels may remain the same, but the length of the reset period is further increased for each individual LOFIC capacitor (e.g., for two LOFIC image sensor pixels, the duration is further extended relative to timing diagram 400 or timing diagram 500). In some examples, the frame duration may thereby be shortened, resulting in a higher frame rate while allowing for an appropriate reset duration for each LOFIC in pixels that utilize LOFIC.

[0081] FIG. 8 illustrates an example method 800 for controlling image sensor pixels of an image sensing device according to some aspects of the present disclosure. In some cases, one or more aspects of method 800 may be performed by device 100, or one or more components thereof, such as a processor (e.g., component processor 136), or a combination thereof. In some embodiments, processor (e.g., component processor 136) may include or be coupled to memory (e.g., memory 138) that may store instructions that, when executed by the processor, cause the processor to perform operations of method 800. When the processor performs operations of method 800, the processor may also cause device 100 or one or more components thereof to perform or cancel various operations. In some cases, one or more aspects of method 800 may be performed by or using image sensing device 200, image sensor pixel 300, image sensor pixel 600, or one or more components thereof. In some cases, method 800 may be performed in accordance with one or more of timing diagram 400, timing diagram 500, or timing diagram 700.

[0082] At 802, the method 800 includes collecting charge during a first integration period at a first LOFIC capacitor. In some embodiments, the method 800 includes collecting a first charge from a photodiode during the first integration period at a floating diffusion node of a plurality of LOFIC capacitors and a first lateral overflow capacitor of an image sensor pixel.

[0083] At 804, the method 800 includes reading the first charge. In some embodiments, the method 800 includes reading the first charge from the floating diffusion node and the first LOFIC capacitor at a first time.

[0084] At 806, the method 800 includes resetting the first LOFIC capacitor. In some embodiments, the method 800 includes resetting the first LOFIC capacitor by coupling the first LOFIC capacitor to a voltage source during a first reset period.

[0085] At 808, the method 800 includes collecting charge at a second LOFIC during a second integration period while resetting the first LOFIC. In some embodiments, the method 800 includes collecting a second charge at the floating diffusion node and a second LOFIC capacitor of the plurality of LOFIC capacitors from the photodiode during a second integration period that at least partially overlaps with the first reset period.

[0086] In one or more embodiments, the method further includes reading a second charge from the floating diffusion node and the second lateral overflow capacitor at a second time during the first reset period.

[0087] In one or more embodiments, the method further includes resetting the second lateral overflow capacitor by coupling the second lateral overflow capacitor to a voltage source during a second reset period, the second reset period including at least the first integration period.

[0088] In one or more embodiments, the method further includes detecting a light condition that does not meet a brightness threshold, and disabling one or more of the first LOFIC capacitor or the second LOFIC capacitor for charge collection at least in part in response to the detecting.

[0089] In one or more embodiments, the method further includes detecting a light condition that meets or exceeds a brightness threshold and enabling one or more of the first LOFIC capacitor or the second LOFIC capacitor for charge collection at least in part in response to the detection. In other words, the image sensor can change its operational mode in response to the brightness level present in the scene being imaged. For example, when the light level is sufficiently low, the image sensor may operate in an operational mode in which a charge overflow path of a given image sensor pixel is not utilized during the integration phase of an image frame captured by the image sensor. Above a certain light level, the image sensor may operate in a different operational mode in which successive image frames alternate between multiple charge overflow paths during the integration phase for a given image sensor pixel (as described herein with respect to FIGS. 4 and 7). At even higher light levels, the image sensor may operate in an operational mode in which multiple charge overflow paths of an image sensor pixel are used during the integration phase of a given image frame (as described herein with respect to FIG. 5). The image sensor can dynamically switch between different operational modes as needed.

[0090] In some embodiments, the first reset periods alternate with the second reset periods, and the first integration periods alternate with the second integration periods.

[0091] The method 800 may be variously embodied, extended, or adapted, as described in the following paragraphs and elsewhere in this description.

[0092] FIG. 9 shows an example method 900 for controlling an image sensing device according to some aspects of the present disclosure. In some cases, one or more aspects of method 900 may be performed by device 100, or one or more components thereof, such as a processor (e.g., component processor 136), or a combination thereof. In some embodiments, the processor (e.g., component processor 136) may include or be coupled to a memory (e.g., memory 138) that may store instructions that, when executed by the processor, cause the processor to perform operations of method 900. When the processor performs operations of method 900, the processor may also cause device 100 or one or more components thereof to perform or cancel various operations. In some cases, one or more aspects of method 900 may be performed by or using image sensing device 200, image sensor pixel 300, image sensor pixel 600, or one or more components thereof. In some cases, method 900 may be performed in accordance with one or more of timing diagram 400, timing diagram 500, or timing diagram 700.

[0093] At 902, method 900 includes controlling a first LOFIC to collect charge during a first integration period. In some embodiments, method 900 includes causing, by a control circuit coupled to the array of image sensor pixels, at least one of the floating diffusion node and the plurality of LOFIC capacitors to collect charge from the photodiode during at least one integration period.

[0094] At 904, method 900 includes resetting at least one of the LOFIC capacitors during a first LOFIC integration period. In some embodiments, method 900 includes: coupling, by a control circuit, at least one of the plurality of LOFIC capacitors to a voltage source during at least one reset period to reset the plurality of LOFIC capacitors, wherein the at least one reset period overlaps with the at least one integration period; and selectively coupling the plurality of LOFIC capacitors to the voltage source by a plurality of reset gates, wherein each LOFIC capacitor is associated with at least one of the plurality of reset gates.

[0095] In one or more embodiments, the method further includes coupling, by the control circuit, a first LOFIC capacitor of the plurality of LOFIC capacitors to a voltage source during a first reset period to reset the first LOFIC capacitor, and coupling, by the control circuit, a second LOFIC capacitor of the plurality of LOFIC capacitors to the voltage source during a second reset period to reset a second LOFIC capacitor of the plurality of LOFIC capacitors, the second reset period being different from the first reset period.

[0096] In one or more embodiments, the method further includes coupling, by the control circuit, a first LOFIC capacitor of the plurality of LOFIC capacitors and a second LOFIC capacitor of the plurality of LOFIC capacitors to a voltage source during a same reset period of the at least one reset period to reset the first LOFIC capacitor and the second LOFIC capacitor.

[0097] In one or more embodiments, the method further includes causing, by the control circuitry, the floating diffusion node and a first LOFIC capacitor of the plurality of LOFIC capacitors to collect a first charge from the photodiode during a first integration period of the at least one integration period, and causing, by the control circuitry, the floating diffusion node and a second LOFIC capacitor of the plurality of LOFIC capacitors to collect a second charge from the photodiode during a second integration period of the at least one integration period, wherein the second integration period is different from the first integration period.

[0098] In one or more embodiments, the method further includes causing, by the control circuit, the floating diffusion node, the first LOFIC capacitor of the plurality of LOFIC capacitors, and the second LOFIC capacitor of the plurality of LOFIC capacitors to collect charge from the photodiode during the same integration period of the at least one integration period.

[0099] In one or more embodiments, the method further includes causing the control circuit to cause a select gate to couple the source follower transistor to a select line of the image sensing device to read out charge stored in at least one of the floating diffusion node and the plurality of LOFIC capacitors, and each image sensor pixel of the array further includes a source follower transistor and a select gate.

[0100] In one or more embodiments, the method further includes causing, by the control circuit, the plurality of LOFIC capacitors to collect charge for a first light condition, and disabling, by the control circuit, the collection of charge in the plurality of LOFIC capacitors for a second light condition that is a relatively lower light condition than the first light condition.

[0101] The method 900 may be variously embodied, extended, or adapted, as described in the following paragraphs and elsewhere in this description.

[0102] Embodiments contemplated herein may include one or more non-transitory computer-readable media that store instructions that, when executed by one or more processors of the electronic device, cause the electronic device to perform one or more elements of method 800 or 900. In the context of method 800 or 900, this non-transitory computer-readable medium may be, for example, memory of device 100 (e.g., memory 138 as described herein).

[0103] The foregoing description, for purposes of explanation, uses specific terminology to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art after reading this description that specific details are not required to practice the described embodiments. Thus, the foregoing descriptions of the specific embodiments described herein are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. It will be apparent to those skilled in the art after reading this description that many modifications and variations are possible in light of the above teachings.

Claims

1. 1. An image sensor pixel, comprising: A photodiode; a floating diffusion node selectively coupled to the photodiode; a first lateral overflow capacitor selectively coupled to the floating diffusion node; a second lateral overflow capacitor selectively coupled to the floating diffusion node; a first reset gate operable to selectively couple the first lateral overflow capacitor to a voltage source during a first reset period to reset the first lateral overflow capacitor; a second reset gate operable to selectively couple the second lateral overflow capacitor to the voltage source during a second reset period to reset the second lateral overflow capacitor.

2. a readout circuit coupled to the floating diffusion node; The image sensor pixel of claim 1 further comprising:

3. a third lateral overflow capacitor selectively coupled to the floating diffusion node; The image sensor pixel of claim 1 further comprising:

4. a first terminal of the first lateral overflow capacitor selectively coupled to the floating diffusion node and a second terminal of the first lateral overflow capacitor coupled to a bias voltage source; a first terminal of the second lateral overflow capacitor selectively coupled to the floating diffusion node, and a second terminal of the second lateral overflow capacitor coupled to the bias voltage source; The image sensor pixel of claim 1 .

5. a first terminal of the first lateral overflow capacitor selectively coupled to the floating diffusion node and a second terminal of the first lateral overflow capacitor coupled to a first bias voltage source; a first terminal of the second lateral overflow capacitor selectively coupled to the floating diffusion node, and a second terminal of the second lateral overflow capacitor coupled to a second bias voltage source different from the first bias voltage source; The image sensor pixel of claim 1 .

6. 2. The image sensor pixel of claim 1, wherein the first lateral overflow capacitor and the second lateral overflow capacitor are each metal-insulator-metal (MIM) capacitors.

7. 1. An image sensing device, comprising: an array of image sensor pixels, a first pixel of the array comprising: A photodiode; a floating diffusion node selectively coupled to the photodiode; a plurality of lateral overflow capacitors selectively coupled to the floating diffusion nodes; a plurality of reset gates, each reset gate of the plurality of reset gates selectively coupling a corresponding one of the plurality of lateral overflow capacitors to a voltage source; a control circuit, wherein the control circuit controlling the floating diffusion node and at least one of the plurality of lateral overflow capacitors to collect charge from the photodiode during at least one integration period; and controlling the at least one of the plurality of lateral overflow capacitors to be coupled to the voltage source during at least one reset period to reset the plurality of lateral overflow capacitors.

8. The control circuit configured to reset the plurality of lateral overflow capacitors comprises: coupling a first horizontal overflow capacitor of the plurality of horizontal overflow capacitors to the voltage source during a first reset period to reset the first horizontal overflow capacitor; 8. The image sensing device of claim 7, configured to couple a second lateral overflow capacitor of the plurality of lateral overflow capacitors to the voltage source during a second reset period different from the first reset period to reset the second lateral overflow capacitor.

9. coupling a first horizontal overflow capacitor of the plurality of horizontal overflow capacitors and a second horizontal overflow capacitor of the plurality of horizontal overflow capacitors to the voltage source during a same reset period of the at least one reset period to reset the first horizontal overflow capacitor and the second horizontal overflow capacitor; The image sensing device of claim 7 further comprising:

10. controlling the floating diffusion node and the at least one of the plurality of lateral overflow capacitors to collect the charge from the photodiode during the at least one integration period; controlling the floating diffusion node and a first lateral overflow capacitor of the plurality of lateral overflow capacitors to collect a first charge from the photodiode during a first integration period of the at least one integration period; and controlling the floating diffusion node and a second lateral overflow capacitor of the plurality of lateral overflow capacitors to collect a second charge from the photodiode during a second integration period of the at least one integration period, wherein the second integration period is different from the first integration period.

11. controlling the floating diffusion node and the at least one of the plurality of lateral overflow capacitors to collect the charge from the photodiode during the at least one integration period; 8. The image sensing device of claim 7, further comprising: controlling the floating diffusion node, a first lateral overflow capacitor of the plurality of lateral overflow capacitors, and a second lateral overflow capacitor of the plurality of lateral overflow capacitors to collect the charge from the photodiode during a same integration period of the at least one integration period.

12. the first pixel further comprises a source follower transistor and a select gate; the control circuit is further configured to cause the select gate to couple the source follower transistor to a select line of the image sensing device to read out the charge stored in the floating diffusion node and the at least one of the plurality of lateral overflow capacitors. The image sensing device of claim 7 .

13. The control circuit collecting charge in the plurality of lateral overflow capacitors under a first light condition; 8. The image sensing device of claim 7, configured to disable the charge collection in the plurality of lateral overflow capacitors for a second light condition that is a relatively lower light condition than the first light condition.

14. 1. A method for controlling image sensor pixels of an image sensing device, comprising: collecting a first charge from a photodiode at a floating diffusion node of the image sensor pixel and at a first lateral overflow capacitor of a plurality of lateral overflow capacitors during a first integration period; reading the first charge from the floating diffusion node and the first lateral overflow capacitor at a first time; resetting the first lateral overflow capacitor by coupling the first lateral overflow capacitor to a voltage source during a first reset period; and collecting a second charge from the photodiode at the floating diffusion node and at a second lateral overflow capacitor of the plurality of lateral overflow capacitors during a second integration period that at least partially overlaps with the first reset period.

15. reading the second charge from the floating diffusion node and the second lateral overflow capacitor at a second time during the first reset period; The method of claim 14 further comprising:

16. and resetting the second lateral overflow capacitor by coupling the second lateral overflow capacitor to the voltage source during a second reset period, the second reset period including at least the first integration period.

15. The method of claim 14.

17. detecting a light condition prior to a third integration period that at least partially overlaps the second reset period; disabling the first lateral overflow capacitor during the third integration period in response to the light condition not meeting a threshold brightness value; collecting a third charge from the photodiode during the third integration period from the floating diffusion node while the first lateral overflow capacitor is disabled; 17. The method of claim 16, further comprising:

18. detecting a light condition prior to the first integration period, wherein the first charge is collected during the first integration period in response to the light condition not meeting a threshold brightness value.

15. The method of claim 14.

19. a first set of frames including the first integration period, a first portion of the first reset period, and a first portion of the second reset period; a second set of frames including the second integration period, a second portion of the first reset period, a second portion of the second reset period, and 15. The method of claim 14, comprising:

20. 20. The method of claim 19, wherein frames of the first set of frames alternate with frames of the second set of frames.

Images