Self-aligned via structure and method of forming the same

Abstract

To provide a method and a structure for ensuring accurate alignment between a via and a metal line.SOLUTION: The method includes forming a first metal line 26, forming a dielectric layer 24 with the first metal line in the dielectric layer, and etching back the first metal line to form a trench in the dielectric layer. A lower portion of the first metal line remains below the trench. The method also includes filling the trench with a photosensitive material and performing a photolithography process to pattern the photosensitive material. A via opening is formed in the dielectric layer and in the photosensitive material. A second metal line and a via are formed, wherein the via is formed in the via opening, and wherein the second metal line is over and joined with the via.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Priority claims and cross-references This application claims the benefit of provisional U.S. patent application Ser. No. 63 / 675,885, filed Jul. 26, 2024, entitled "Self-Aligned Via Structure for Fine-Pitch RDL," which is incorporated herein by reference. [Background technology]

[0002] In the formation of integrated circuits, redistribution structures are often used to connect device dies and reroute electrical signals. Redistribution structures often include multiple layers of redistribution lines. The multiple layers of redistribution lines are interconnected through vias formed below the redistribution lines. For example, the lower redistribution lines may include metal pads. A dielectric layer is formed over the metal pads. The upper redistribution lines include vias in the dielectric layer and line portions above the dielectric layer. The vias have lengths and widths that are smaller than the lengths and widths of the metal pads to allow them to fit within the metal pads. Summary of the Invention [Problem to be solved by the invention]

[0003] In conventional semiconductor packaging processes, vias can be misaligned with underlying metal lines, which can degrade electrical performance and limit design flexibility. Furthermore, such misalignment limits the pattern density of redistribution lines, thereby limiting integration capabilities and circuit miniaturization. Therefore, a need exists for a technique that ensures precise alignment of vias with metal lines while enabling increased density of redistribution lines. [Means for solving the problem]

[0004] According to some embodiments of the present disclosure, a method includes forming a first metal line; forming a first dielectric layer, wherein the first metal line is within the first dielectric layer; etching back the first metal line to form a trench in the first dielectric layer, wherein a lower portion of the first metal line remains below the trench; filling the trench with a photosensitive material; and performing a photolithography process to pattern the photosensitive material, wherein a via opening is formed in the first dielectric layer and in the photosensitive material; and forming a second metal line and a via, wherein the via is formed in the via opening and the second metal line is above and joined to the via.

[0005] According to some embodiments of the present disclosure, a structure includes: a first metal line having a first sidewall and a second sidewall parallel to the first sidewall; a via covering and contacting the first metal line, the via having a third sidewall aligned perpendicular to the first sidewall and a fourth sidewall aligned perpendicular to the second sidewall; a first dielectric layer, the first metal line and the via being within the first dielectric layer; a second metal line spanning and joined to the via, the second metal line having a bottom surface that contacts a top surface of the first dielectric layer; and a second dielectric layer, the top surface of the second dielectric layer and the top surface of the second metal line being coplanar.

[0006] According to some embodiments of the present disclosure, a structure includes: a first metal line having a first sidewall and a second sidewall parallel to the first sidewall; a via covering and contacting the first metal line, the via including a third sidewall, where in a cross-section of the structure, the third sidewall and the first sidewall are aligned with a same first straight line; and a fourth sidewall, where in a cross-section of the structure, the fourth sidewall and the second sidewall are aligned with a same second straight line; and a second metal line spanning the via and connected to the via. [Effects of the Invention]

[0007] Embodiments of the present disclosure have several advantageous features: By employing a recessing process for metal lines to leave a recess / trench in the dielectric layer and forming a via defined by the trench, the via is self-aligned to the metal line; the misalignment of the via relative to the underlying metal line is estimated; and the pattern density of redistribution lines can be increased.

[0008] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, various features have not been drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Brief explanation of the drawings]

[0009] [Figure 1] 1 illustrates the formation of a redistribution structure, according to some embodiments. [Figure 2] 1 illustrates the formation of a redistribution structure, according to some embodiments. [Figure 3] 1A-C illustrate the formation of a lower redistribution line and a via opening offset from the line end of the underlying metal line, according to some embodiments. [Figure 4]1A-C illustrate the formation of a lower redistribution line and a via opening offset from the line end of the underlying metal line, according to some embodiments. [Figure 5] 1A-C illustrate the formation of a lower redistribution line and a via opening offset from the line end of the underlying metal line, according to some embodiments. [Figure 6] 1A-C illustrate the formation of a lower redistribution line and a via opening offset from the line end of the underlying metal line, according to some embodiments. [Figure 7] 1A-C illustrate the formation of a lower redistribution line and a via opening offset from the line end of the underlying metal line, according to some embodiments. [Figure 8] 1A-C illustrate the formation of a lower redistribution line and a via opening offset from the line end of the underlying metal line, according to some embodiments. [Figure 9] 1A-C illustrate the formation of a lower redistribution line and a via opening aligned to the line end of an underlying metal line, according to some embodiments. [Figure 10] 1A-C illustrate the formation of a lower redistribution line and a via opening aligned to the line end of an underlying metal line, according to some embodiments. [Figure 11] 1A-C illustrate the formation of a lower redistribution line and a via opening aligned to the line end of an underlying metal line, according to some embodiments. [Figure 12] 1A-C illustrate the formation of a lower redistribution line and a via opening aligned to the line end of an underlying metal line, according to some embodiments. [Figure 13] 1A-C illustrate the formation of a lower redistribution line and a via opening aligned to the line end of an underlying metal line, according to some embodiments. [Figure 14] 1A-C illustrate the formation of a lower redistribution line and a via opening aligned to the line end of an underlying metal line, according to some embodiments. [Figure 15] 1A-C illustrate the formation of upper redistribution lines having a vertical direction different from that of the lower redistribution lines, according to some embodiments. [Figure 16] 1A-C illustrate the formation of upper redistribution lines having a vertical direction different from that of the lower redistribution lines, according to some embodiments. [Figure 17] 1A-C illustrate the formation of upper redistribution lines having a vertical direction different from that of the lower redistribution lines, according to some embodiments. [Figure 18] 1A-C illustrate the formation of upper redistribution lines having a vertical direction different from that of the lower redistribution lines, according to some embodiments. [Figure 19] 1A-C illustrate the formation of upper redistribution lines having a longitudinal direction parallel to that of the lower redistribution lines, according to some embodiments. [Figure 20] 1A-C illustrate the formation of upper redistribution lines having a longitudinal direction parallel to that of the lower redistribution lines, according to some embodiments. [Figure 21] 1A-C illustrate the formation of upper redistribution lines having a longitudinal direction parallel to that of the lower redistribution lines, according to some embodiments. [Figure 22] 1A-C illustrate the formation of upper redistribution lines having a longitudinal direction parallel to that of the lower redistribution lines, according to some embodiments. [Figure 23] 1 illustrates the formation of a package based on a redistribution structure, according to some embodiments. [Figure 24] 1 illustrates the formation of a package based on a redistribution structure, according to some embodiments. [Figure 25] 1 illustrates the formation of a package based on a redistribution structure, according to some embodiments. [Figure 26] 1 illustrates the formation of a package based on a redistribution structure, according to some embodiments. [Figure 27] 1A-C show cross-sectional views of several metal lines and overlapping vias according to some embodiments. [Figure 28] 1 illustrates a process flow for forming redistribution lines, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] The following disclosure provides many different embodiments, or examples, for implementing various features of the present invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature across or on a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features may be formed between the first and second features and in which the first and second features may not be in direct contact. Furthermore, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various disclosed embodiments and / or structures.

[0011] Additionally, for ease of description herein, spatially relative terms such as "below," "below," "under," "overlapping / covering," "above," etc. may be used to describe the relationship of one element or feature to another element or feature, as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may likewise be interpreted accordingly.

[0012] Redistribution structures and methods for forming redistribution structures are provided. According to some embodiments of the present disclosure, metal lines are formed, and the metal lines are located in a first dielectric layer. The metal lines are recessed to form trenches in the first dielectric layer. A dielectric material is filled into the trenches and patterned to form via openings. The dielectric material can be formed of a photosensitive material. Redistribution lines are then formed, and vias in the redistribution lines are formed in the via openings. The vias defined by the trenches thus have edges that are vertically aligned with the corresponding edges of the underlying recessed metal lines. Therefore, the vias are self-aligned to the metal lines, and the metal lines do not need larger pads to accommodate the vias above the metal lines. Therefore, the minimum pitch of the redistribution lines can be reduced, and the density of the redistribution lines is increased.

[0013] The embodiments discussed herein provide enabling examples for making or using the subject matter of the present disclosure, and those skilled in the art will readily appreciate modifications that can be made while remaining within the scope of the different embodiments. Like reference numerals are used to refer to like components throughout the various figures and exemplary embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] 1 and 2 show cross-sectional views of intermediate stages in the formation of a redistribution structure according to some embodiments of the present disclosure. Details of the formation of redistribution lines and dielectric layers within the redistribution structure are shown in FIGS. 3A, 3B, and 3C through to FIGS. 22A, 22B, and 22C. The corresponding processes for some of the embodiments are also reflected generally in process flow 200, as shown in FIG. 28.

[0015] 1 shows a carrier 20 and a release film 22 formed on the carrier 20. The carrier 20 may be a glass carrier, a silicon wafer, an organic carrier, or the like. The release film 22 may be made of a polymer-based material and / or an epoxy-based thermal release material (such as a light-to-heat conversion (LTHC) material), which can be decomposed under irradiation, such as with a laser beam, thereby debonding the carrier 20 from the overlapping structure formed in a subsequent process. According to some embodiments, the release film 22 is applied to the carrier 20 by spin coating or adhesive bonding.

[0016] 1, a portion of a redistribution structure 28 including a plurality of dielectric layers 24 and a plurality of redistribution lines (RDLs) 26 is formed on the release film 22. The redistribution structure 28 is alternatively referred to as an interposer 28. The interposer 28 can be an organic interposer including organic dielectric layers and redistribution lines.

[0017] According to some embodiments, the redistribution structure 28 is formed layer-by-layer starting with the release film 22. The formation process of the lower RDL and the upper RDL is detailed in Figures 3A, 3B, and 3C through Figures 22A, 22B, and 22C, which are described in later paragraphs.

[0018] 2 illustrates the formation of additional dielectric layers 24 and additional RDLs 26 to extend the redistribution structure. Throughout the specification, subsequently formed dielectric layers 24A, 24B, 24C, and 24D (shown in FIGS. 18B and 18C or FIGS. 22B and 22C) are individually and collectively referred to as dielectric layers 24, and RDL 26A is referred to as RDL 26.

[0019] After forming the top dielectric layer in the redistribution structure 28, the electrical connectors 32 can be formed. The electrical connectors 32 can be formed with or can include microbumps, metal pads, metal pillars, under-bump metallurgy (UBM), solder areas, etc. Formation of the electrical connectors 32 can be similar to forming the RDL, and the formation process can include patterning the top dielectric layer 24 to expose the underlying RDL 26, depositing a metal seed layer, forming a patterned plating mask, performing one or more plating processes to form the electrical connectors 32, removing the plating mask, and etching the metal seed layer. The electrical connectors 32 can include copper, aluminum, cobalt, nickel, gold, silver, tungsten, solder, alloys thereof, and / or multiple layers thereof.

[0020] 3A, 3B, and 3C through 8A, 8B, and 8C illustrate the formation of lower redistribution lines and via openings in redistribution structure 28, according to some embodiments. The via openings are vertically aligned with the middle portions of the lower redistribution lines (and offset from the line ends).

[0021] 9A, 9B, and 9C through 14A, 14B, and 14C illustrate the formation of lower redistribution lines and via openings in a redistribution structure according to an alternative embodiment, where the via openings are vertically aligned with the line ends of the lower redistribution lines.

[0022] 3A, 3B, and 3C, it can be understood that the embodiments shown in Figures 8A, 8B, and 8C can be implemented simultaneously with the embodiments shown in Figures 9A, 9B, and 9C, and Figures 14A, 14B, and 14C. Thus, within the same device die, some via openings are aligned with the middle portions of corresponding lower redistribution lines, while other openings are aligned with the line ends of corresponding lower redistribution lines.

[0023] 15A, 15B, and 15C through 18A, 18B, and 18C illustrate the formation of upper redistribution lines, according to some embodiments, having a vertical direction different from the vertical direction of the lower redistribution lines, with vias in via openings as shown in FIGS. 8B and 8C, or vias in via openings as shown in FIGS. 14B and 14C.

[0024] 19A, 19B, and 19C, and to Figures 22A, 22B, and 22C illustrate the formation of upper redistribution lines according to alternative embodiments. The upper redistribution lines have a longitudinal direction parallel to the longitudinal direction of the lower redistribution lines. The upper redistribution lines may also comprise vias in via openings, as shown in Figures 8B and 8C, or vias in via openings, as shown in Figures 14B and 14C.

[0025] Alternatively, each of the embodiments shown in Figures 3A, 3B, and 3C to Figures 8A, 8B, and 8C, and the embodiments shown in Figures 9A, 9B, and 9C to Figures 14A, 14B, and 14C, can be combined with any of the embodiments shown in Figures 15A, 15B, and 15C to Figures 18A, 18C, and 18C, or with any of the embodiments shown in Figures 19A, 19B, and 19C to Figures 22A, 22B, and 22C.

[0026] It is understood that the embodiments shown in Figures 15A, 15B, and 15C through 18A, 18B, and 18C can be implemented simultaneously with the embodiments shown in Figures 19A, 19B, and 19C through 22A, 22B, and 22C. Thus, within the same device die, some vias are aligned with the middle portions of corresponding lower redistribution lines, while other vias are aligned with the line ends of corresponding lower redistribution lines.

[0027] Subsequent drawings may be designated by a number followed by the letter A, B, or C. Figures with a designation containing the letter A represent a plan view of the structure. Figures with a designation containing the letter B represent a cross-section of the structure, which cross-section represents section A-A' of the corresponding plan view. Figures with a designation containing the letter C represent a cross-section of the structure, which cross-section represents section B-B' of the corresponding plan view.

[0028] 3A, 3B, and 3C show plan and cross-sectional views of an initial structure during formation, according to some embodiments. Dielectric layer 24A is formed, and RDLs 26A1 and 26A2 (also called metal lines) are formed on dielectric layer 24A. Dielectric layer 24A in FIGS. 3A, 3B, and 3C can be any of dielectric layers 24 (FIG. 2) with redistribution lines formed on it.

[0029] According to some embodiments, dielectric layer 24A can be formed of or include a photosensitive material such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), etc. When RDLs 26A1 and 26A2 are formed, dielectric layer 24A is cured and therefore is no longer photosensitive. This means that an exposure process and subsequent development process performed on dielectric layer 24A cannot pattern dielectric layer 24A.

[0030] According to some embodiments, RDLs 26A1 and 26A2, individually and collectively referred to as RDL 26A, are formed on dielectric layer 24A. The corresponding process is shown as process 202 in process flow 200 illustrated in FIG. 28. The longitudinal directions of RDLs 26A1 and 26A2 are parallel to each other. Although not shown in FIGS. 3B and 3C, RDLs 26A1 and 26A2 may (or may not) include vias in dielectric layer 24A. The heights (thicknesses) of RDLs 26A1 and 26A2 are intentionally formed to be greater than the intended thickness of RDL 26 in the final structure ( FIG. 2 ). For example, the thicknesses of RDLs 26A1 and 26A2 can be equal to or greater than the sum of the thicknesses of RDLs 26A1 and 26A2 and the heights (thicknesses) of the overlying vias in the final structure.

[0031] RDLs 26A1 and 26A2 can be formed of or include copper, nickel, titanium, tungsten, or the like. For example, RDLs 26A1 and 26A2 can include a titanium seed layer and a copper layer on the titanium seed layer. The formation process for RDLs 26A1 and 26A2 can include forming a metal seed layer (not shown), which includes portions on dielectric layer 24A. Dielectric layer 24A may (or may not) include an opening therein. When a via opening is formed in dielectric layer 24A, the metal seed layer can extend into dielectric layer 24A. The metal seed layer can be formed, for example, using physical vapor deposition (PVD) or a similar process.

[0032] A patterned plating mask (not shown), such as photoresist, can then be formed over the metal seed layer, followed by a metal plating process that deposits a metal material onto the exposed metal seed layer. The patterned plating mask and the portions of the metal seed layer covered by the patterned plating mask are then removed, leaving RDL 26A, as shown in Figures 3A, 3B, and 3C. The plated material can include copper, aluminum, cobalt, nickel, gold, silver, tungsten, or alloys thereof. The plating process can be performed using, for example, an electrochemical plating process.

[0033] 4A, 4B, and 4C, dielectric layer 24B is formed. The corresponding process is shown as process 204 in process flow 200 illustrated in FIG. 28. According to some embodiments, dielectric layer 24B can be formed of the same material as dielectric layer 24A. In the resulting structure, dielectric layers 24A and 24B may be distinguishable from one another (e.g., by a discernible interface therebetween), or may not be distinguishable from one another. Alternatively, dielectric layer 24B may be formed of a material different from that of dielectric layer 24A. Thus, in the resulting structure, dielectric layers 24A and 24B are distinguishable from one another.

[0034] According to some embodiments, dielectric layer 24B is formed of or includes an organic material, which may be a photosensitive polymer such as polyimide, PBO, BCB, or the like. Forming dielectric layer 24B may include providing dielectric layer 24B in a flowable form and curing dielectric layer 24B to a solid state. A planarization process, such as a chemical-mechanical polishing (CMP) process or a mechanical polishing process, is then performed to make the top surface of dielectric layer 24B flush with RDL 26A1 and RDL 26A2. The corresponding process is shown as process 206 in process flow 200 illustrated in FIG. 28. Once cured, dielectric layer 24B is no longer photosensitive.

[0035] According to an alternative embodiment, the dielectric layer 24B may be formed of a non-photosensitive material, such as a non-photosensitive organic material (such as a polymer) or an inorganic dielectric material. For example, the dielectric layer 24B may be formed of or include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like, or a combination thereof.

[0036] 5A, 5B, and 5C illustrate plan and cross-sectional views of recessing RDLs 26A1 and 26A2, according to some embodiments. As shown in FIGS. 5B and 5C, RDLs 26A1 and 26A2 are etched back (recessed) using an etching process to form trenches 36A and 36B. The corresponding process is shown as process 208 in process flow 200 illustrated in FIG. 28. According to some embodiments, the recess depth ranges from about 30% to about 70% of the height of RDLs 36A1 and 36A2.

[0037] The recess formation is performed using an etchant that chemically attacks RDLs 26A1 and 26A2 but not dielectric layer 24B. Thus, trenches 36A and 36B are formed self-aligned to RDLs 36A1 and 36A2, with the sidewall edges of dielectric layer 24B exposed in trenches 36A and 36B vertically aligned with the corresponding underlying edges of RDLs 36A1 and 36A2. While the edges of RDLs 36A1 and 36A2 shown in FIG. 4B are sloped and straight (e.g., have the same contours as those shown in FIGS. 27A and 27C), the sidewalls of dielectric layer 24B exposed in trenches 36A and 36B shown in FIG. 5B are also sloped and straight.

[0038] 6A, 6B, and 6C show plan and cross-sectional views of trenches 36A and 36B during filling, according to some embodiments. According to some embodiments, a photosensitive material (which may include a polymer), such as polyimide, PBO, or the like, is dispensed into trenches 36A and 36B in a flowable form. A corresponding process is shown as process 210 in process flow 200 shown in FIG. 28. The photosensitive material is baked to solidify. However, because the baked photosensitive material is not cured, the photosensitive material remains photosensitive.

[0039] A planarization process, such as a CMP process or a mechanical polishing process, is then performed to make the top surface of the photosensitive material flush with the top surface of the dielectric layer 24B. The remaining portions of the photosensitive material are photosensitive strips 24C1 and 24C2.

[0040] In the above process, the dielectric layer 24B acts as a mold to define the shape and size of the photosensitive strips 24C1 and 24C2. The upper portions of the RDLs 36A1 and 36A2, which were etched in the previous process, define the shape and size of the photosensitive strips 24C1 and 24C2.

[0041] Next, as also shown in Figures 6B and 6C, a photolithography mask 42 is placed over the previously formed structure, including dielectric layer 24B and photosensitive strips 24C1 and 24C2. Photolithography mask 42 includes opaque portions for blocking light and transparent portions for transmitting light. In the following description, it will be assumed that photosensitive strips 24C1 and 24C2 include positive photoresist, such that portions 42B are transparent portions, while portions 42A are opaque portions. It will be understood that photosensitive strips 24C1 and 24C2 could also include negative photoresist, in which case the pattern of opaque and transparent portions of lithography mask 42 would be reversed.

[0042] According to some embodiments, as shown in Figures 6B and 6C, opaque portion 42A directly overlies and overlaps photosensitive strip 24C1 and some portion of photosensitive strip 24C2, a portion of which is directly below and covered by transparent portion 42B.

[0043] An exposure process is then performed to expose the portion of the photosensitive strip 24C2 directly beneath the transparent portion 42B. In the cross-sectional view shown in FIG. 6B, the transparent portion 42B is larger in size and width than the edge of the underlying photosensitive strip 24C2, extending horizontally beyond it. This ensures that the underlying portion of the photosensitive strip 24C2 is exposed edge-by-edge, even in the event of lithographic misalignment. Because the dielectric layer 24B (if initially formed of a photosensitive material) is hardened, even if some portions of the dielectric layer 24B are exposed, the exposed portions of the dielectric layer 24B will not be removed in a subsequent development process.

[0044] In the cross-sectional view shown in FIG. 6C, transparent portion 42B overlaps a middle portion of RDL 26A2, and RDL 26A2 extends horizontally beyond the opposite edge of transparent portion 42B.

[0045] 7A, 7B, and 7C show plan and cross-sectional views of photosensitive strips 24C1 and 24C2 after development. Removal of the exposed portions of photosensitive strip 24C2 forms via opening 44. The corresponding process is shown as process 212 in process flow 200 illustrated in FIG. 28. As shown in FIG. 7B, via opening 44 is self-aligned to the underlying RDL 26A2. As shown in FIG. 7C, via opening 44 is aligned to the middle portion of RDL 26A2 and vertically offset from the line ends of RDL 26A2.

[0046] In a subsequent process, as shown in FIGS. 8A, 8B, and 8C, a curing process is performed on the photosensitive strips 24C1 and 24C2, so that the photosensitive strips 24C1 and 24C2 are no longer photosensitive and are converted into dielectric layers in the resulting structure. The corresponding process is shown as process 214 in the process flow 200 shown in FIG. 28. Throughout the specification, the photosensitive strips 24C1 and 24C2 are alternatively referred to as dielectric strips 24C1 and 24C2. The resulting dielectric strips 24C1 and 24C2 may comprise the same or a different dielectric material as the material of the dielectric layer 24B. The resulting dielectric strips 24C1 and 24C2 may be distinguishable (or indistinguishable) from the dielectric layer 24B. Accordingly, the interfaces between the dielectric layer 24B and the dielectric strips 24C1 and 24C2 are shown with dashed lines.

[0047] In the above-discussed embodiment shown in FIGS. 3A, 3B, and 3C through FIGS. 8A, 8B, and 8C, a via opening 44 is formed (that is aligned perpendicular to the mid-portion (rather than aligned with the line end) of the underlying RDL 26A2). FIGS. 9A, 9B, and 9C through FIGS. 14A, 14B, and 14C show several alternative embodiments for forming a via opening 44 aligned perpendicular to the line end of the underlying RDL 26A2. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are essentially the same as the same components indicated by the same reference numbers in the above embodiments. Details regarding materials, structures, and formation processes provided in each of the embodiments throughout this specification can be applied to any other embodiment, where applicable.

[0048] 9A, 9B, and 9C show plan and cross-sectional views of the initial structure in which dielectric layer 24A has been formed and RDLs 26A1 and 26A2 (individually and collectively referred to as RDLs 26A) have been formed on dielectric layer 24A. Details of the materials, structures, and methods of formation of dielectric layer 24A and RDLs 26A1 and 26A2 can be found by reference to those discussed in the above embodiments and will not be repeated here.

[0049] 10A, 10B, and 10C show plan and cross-sectional views of the dielectric layer 24B during its formation. The material and method of forming the dielectric layer 24B have been discussed in the above embodiment and will not be repeated here. For example, the dielectric layer 24B can include a photosensitive material that is applied, cured, and polished. The dielectric layer 24B is therefore no longer photosensitive. Alternatively, the dielectric layer 24B can be formed of an inorganic dielectric material.

[0050] 11A, 11B, and 11C show plan and cross-sectional views, respectively, of recessing RDLs 26A1 and 26A2 to form trenches 36A and 36B.

[0051] 12A, 12B, and 12C show plan and cross-sectional views, respectively, of photosensitive strips 24C1 and 24C2 in trenches 36A and 36B during their formation. For example, a planarization process can make the top surfaces of photosensitive strips 24C1 and 24C2 coplanar with the top surface of dielectric layer 24B. In the structures shown in FIGS. 12A, 12B, and 12C, photosensitive strips 24C1 and 24C2 are still photosensitive.

[0052] 12B and 12C further illustrate an exposure process 40 performed on photosensitive strips 24C1 and 24C2, according to some embodiments. Exposure process 40 is performed using a photolithography mask 42 to define a pattern. Exposure process 40 and photolithography mask 42 are essentially the same as those shown in FIGS. 6B and 6C, except that transparent portions 42B of photolithography mask 42 are aligned to the line ends of RDL 26A2 rather than to the middle portions of RDL 26A2.

[0053] According to some embodiments, in the cross-sectional view shown in Figure 12B, the transparent portions 42B are oversized and extend horizontally beyond the opposite edge of the photosensitive strip 24C2. In the cross-sectional view shown in Figure 12C, the transparent portions 42B are again oversized and extend horizontally beyond one end of the photosensitive strip 24C2. Because the dielectric layer 24B (if initially formed of a photosensitive material) is hardened, even if some portions of the dielectric layer 24B are exposed to light, the exposed portions of the dielectric layer 24B will not be removed in a subsequent development process.

[0054] 13A, 13B, and 13C show plan and cross-sectional views of photosensitive strips 24C1 and 24C2 during development, according to some embodiments. Via opening 44 is thus formed. The exposed portion of photosensitive strip 24C2 is removed, exposing underlying RDL 26A2. Because the exposed portion of photosensitive strip 24C2 is self-aligned to the end sidewall (the left sidewall as shown) of RDL 26A1, the corresponding via opening 44 has its left edge vertically aligned with the left end sidewall of RDL 26A2.

[0055] 14A, 14B, and 14C, a curing process is performed on the photosensitive strips 24C1 and 24C2, so that the photosensitive strips 24C1 and 24C2 are no longer photosensitive and are instead referred to as dielectric strips 24C1 and 24C2. The resulting dielectric strips 24C1 and 24C2 may comprise the same or a different dielectric material as that of the dielectric layer 24B. The resulting dielectric strips 24C1 and 24C2 may be distinguishable (or indistinguishable) from the dielectric layer 24B.

[0056] 15A, 15B, and 15C, through Figures 18A, 18B, and 18C, illustrate the formation of upper redistribution lines according to some embodiments. The upper redistribution lines have a vertical direction different from the vertical direction of the lower redistribution lines 26A1 and 26A2. While the process shown in Figures 15A, 15B, and 15C can be based on the structure shown in Figures 8A, 8B, and 8C in the illustrated embodiment, the process can also be based on the structure shown in Figures 14A, 14B, and 14C according to alternative embodiments.

[0057] 15A, 15B, and 15C illustrate the formation of a metal seed layer 50 formed on the structure shown in FIGS. 8A, 8B, and 8C. According to some embodiments, the metal seed layer 50 may include a titanium layer and a copper layer on the titanium layer. The metal seed layer 50 may be formed by conformal deposition, such as physical vapor deposition (PVD).

[0058] 15C further illustrates the formation of a mask 52, which may include patterned photoresist, with trenches 54A and 54B therein, according to some embodiments. Mask 52 is also referred to as a plating mask when a plating process is performed. A corresponding process is shown as process 216 in process flow 200 illustrated in FIG. 28. Trench 54A is for forming a metal line therein. Trench 54B is for forming a metal line therein and an underlying via.

[0059] 16A, 16B, and 16C, a metal material 57 is then provided in trenches 54A and 54B. The provision of metal material 57 can be performed by electrochemical vapor deposition (ECD), which, according to some embodiments, can include electrochemical plating (ECP). A corresponding process is shown as process 218 in process flow 200 shown in FIG. 28.

[0060] 17A, 17B, and 17C illustrate the removal of plating mask 52, thereby exposing the underlying portions of metal seed layer 50. The corresponding process is shown as process 220 in process flow 200, illustrated in FIG. 28. The exposed portions of metal seed layer 50 that are not directly under metal lines 58A and 58B are then etched away. Plated metal material 57 and the underlying metal seed layer 50 collectively form metal lines 58A and 58B and via 54. Metal lines 58A and 58B are elevated above dielectric layer 24B. Because via 54 is formed below and joined to metal line 58B, the interface between via 54 and metal line 58B is indistinguishable.

[0061] 16C and 17C, some portions of metal seed layer 50 are directly above RDL 26A1. Because the properties of RDL 26A2 are closer to those of metal seed layer 50 than to those of dielectric layer 24B, recesses can be formed in RDL 26A1 by over-etching metal seed layer 50. Dashed line 60 schematically indicates the upper surface of recessed RDL 26A2.

[0062] 18A, 18B, and 18C illustrate the formation of dielectric layer 24D. The corresponding process is shown as process 222 in process flow 200 illustrated in FIG. 28. According to some embodiments, dielectric layer 24D can be formed of a material selected from the same group of candidate materials for forming dielectric layers 24A, 24B, and / or 24C. The material of dielectric layer 24D can be the same as or different from the material of dielectric layers 24A, 24B, and / or 24C.

[0063] Dielectric layer 24D can be formed of an organic dielectric material (such as a photosensitive polymer) or an inorganic dielectric material. Dielectric layers 24A, 24B, and 24D and dielectric strips 24C1 and 24C2 (individually and collectively referred to as dielectric layers 24C) are collectively referred to as dielectric layer 24, as shown in FIG. 2. Some lower portions of dielectric layer 24D are within dielectric strip 24C2 and may contact vias 54.

[0064] According to embodiments of the present application, a high degree of alignment can be achieved to align the sidewalls of via 54 with the respective sidewalls of the corresponding underlying metal line. For example, in the cross-sectional view shown in FIG. 18B, sidewall 54SW of via 54 is vertically aligned with sidewall 26A2SW of metal line 26A2. This is due to the process in which metal line 26A2 (FIGS. 10B and 10C) is etched back (FIGS. 11B and 11C) to define the size of via 54. Dielectric layer 24B therefore maintains the size of the top of metal line 26A2. This process allows overlapping vias formed in subsequent processes to have the same width as underlying metal line 26A2 without the risk of misalignment.

[0065] 22A, 22B, and 22C, from Figures 19A, 19B, and 19C, illustrate the formation of upper redistribution lines according to alternative embodiments, in which the upper redistribution lines have a longitudinal direction that is parallel (rather than perpendicular) to the longitudinal direction of the lower redistribution lines 26A1 and 26A2.

[0066] 19A, 19B, and 19C, a metal seed layer 50 is formed on the structure shown in FIGS. 8A, 8B, and 8C. According to some embodiments, the metal seed layer 50 may include a titanium layer and a copper layer on the titanium layer. The metal seed layer 50 is formed by conformal deposition, such as physical vapor deposition (PVD). A mask 52 is then formed, and trenches 54A and 54B are formed therein. The mask 52 is also referred to as a plating mask when a plating process is performed.

[0067] 19A and 19B, in cross section A-A', trench 54B is wider than the underlying via opening 44. This allows for increased process margins when trench 54B is formed offset from via opening 44.

[0068] 20A, 20B, and 20C, a metal material 57 is then dispensed into trenches 54A and 54B. Metal lines 58A and 58B are thus formed at a height higher than dielectric layer 24B.

[0069] 21A, 21B, and 21C illustrate the removal of mask 52 and subsequent etching to remove the exposed portions of metal seed layer 50. The remaining portions of metal seed layer 50 are considered part of metal lines 58A and 58B and via 54. Via 54 is formed below and joins metal line 58B, so that their interfaces are indistinguishable.

[0070] 22A, 22B, and 22C illustrate the formation of dielectric layer 24D. According to some embodiments, dielectric layer 24D can be formed of a material selected from the same group of candidate materials for forming dielectric layers 24A, 24B, and / or 24C. The material of dielectric layer 24D can also be the same as or different from the material of dielectric layers 24A, 24B, and / or 24C. Dielectric layers 24A, 24B, 24C (including 24C1 and 24C2), and 24D are individually and collectively referred to as dielectric layer 24, which is also shown in FIG. 2.

[0071] According to embodiments of the present application, a high degree of alignment can be achieved to align the sidewalls of a via with the respective sidewalls of the corresponding underlying metal lines. For example, in the cross-sectional view shown in FIG. 22B, the sidewall 54SW of the via 54 is vertically aligned with the sidewall 26A2SW of the metal line 26A2. Furthermore, the sidewall 54SW and the respective underlying sidewall 26A2SW are collinearly aligned in the cross-sectional view shown in FIG. 18C (see also FIGS. 27A and 27C).

[0072] 15A, 15B, and 15C through 22A, 22B, and 22C depict the formation of via 54 and upper metal line 58B from the middle portion of underlying metal line 26A2 (as shown in FIGS. 8A, 8B, and 8C). According to an alternative embodiment, the same process can also be performed to form via 54 and upper metal line 58B from the end portion of underlying metal line 26A2 (as shown in FIGS. 14A, 14B, and 14C). In the corresponding final structure, via opening 44 (and thus via 54 filling via opening 44) would have three sidewalls (the first two sidewalls shown in FIG. 14B and the third shown in FIG. 14C) vertically aligned with the sidewalls of the corresponding underlying metal line 26A2, without misalignment concerns. Corresponding structures can be realized.

[0073] 23-26 illustrate the remaining process for forming a package according to some embodiments. The process continues from the structure shown in FIG. 2. As shown in FIG. 23, a package component 70 is bonded to interconnect structure 28. Package component 70 may include a device die, a package, a die stack, etc. An encapsulant 72 is formed to encapsulate package component 70 therein. Encapsulant 72 may include a molding compound, an underfill, a molded underfill, etc. In this manner, package 76 is formed.

[0074] 24, carrier 74 is then attached to package 76 via release film 75, after which carrier 20 is removed. Electrical connectors 78, which may include solder areas, are then formed as surface features of package 76. Figures 25 and 26 depict the bonding of package 76 to package component 80 to form package 82.

[0075] Figures 27A, 27B, and 27C show sidewall profiles of a via and an underlying metal line, according to some embodiments. Figure 27A shows that the via 54 and metal line 26A2 have an inverted trapezoidal shape in cross-section. Figure 27B shows that the via 54 and metal line 26A2 have a rectangular shape in cross-section. Figure 27C shows that the via 54 and metal line 26A2 have a trapezoidal shape in cross-section. The sidewall 54SW of the via 54 is aligned with and has the same slope angle θ as the sidewall 26A2SW of the corresponding underlying metal line 26A2. Furthermore, the sidewall 54SW is joined to the sidewall 26A2SW. The sidewall 54SW and the corresponding underlying sidewall 26A2SW are also aligned with a line in cross-section, where the line can be vertical or sloped.

[0076] 27A, 27B, and 27C may be formed in the same dielectric layer 24A, 24B, 24C, and 24D, and the sidewalls of the vias and the sidewalls of the underlying corresponding metal lines may be aligned to the same straight line, but the tilt angles θ of the different redistribution lines may be different from each other, as shown in FIGS.

[0077] Furthermore, due to the etch-back process, as shown in Figure 18C, the left end sidewall of metal line 26A2 and the left end sidewall of left dielectric strip 24C2 are aligned to the same straight line, which may be vertical or slanted, as in Figures 27A or 27C. Also, when via 54 is formed aligned to the line end (not shown) of metal line 26A2, the end sidewall of metal line 26A2 and the end sidewall of via 54 are aligned to the same straight line, which may be vertical or slanted, as in Figures 27A or 27C.

[0078] In the above embodiments, several processes and features are discussed according to some embodiments of the present disclosure for forming a three-dimensional (3D) package. Other features and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packaging or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of the 3D packaging or 3DIC, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein may be used in combination with test methods that incorporate intermediate verification of known good die to increase yield and reduce costs.

[0079] Embodiments of the present disclosure have several advantageous features: By employing a recessing process for metal lines to leave a recess / trench in the dielectric layer and forming a via defined by the trench, the via is self-aligned to the metal line; the misalignment of the via relative to the underlying metal line is estimated; and the pattern density of redistribution lines can be increased.

[0080] According to some embodiments of the present disclosure, a method includes forming a first metal line; forming a first dielectric layer, wherein the first metal line is within the first dielectric layer; etching back the first metal line to form a trench in the first dielectric layer, wherein a lower portion of the first metal line remains below the trench; filling the trench with a photosensitive material; and performing a photolithography process to pattern the photosensitive material, wherein a via opening is formed in the first dielectric layer and in the photosensitive material; and forming a second metal line and a via, wherein the via is formed in the via opening and the second metal line is above and joined to the via.

[0081] In one embodiment, the method further includes performing a planarization process prior to the photolithography process to make the first top surface of the photosensitive material flush with the second top surface of the first dielectric layer. In one embodiment, the method further includes performing a planarization process prior to etching back the first metal line to make the top surface of the first dielectric layer flush with the top surface of the first metal line. In one embodiment, the trench and the lower portion of the first metal line have the same length and width.

[0082] In one embodiment, the via opening has an edge that is vertically aligned with the line edge of the first metal line. In one embodiment, the via opening overlaps a middle portion of a lower portion of the first metal line. In one embodiment, the method further includes curing the photosensitive material before the second metal line and via are formed. In one embodiment, the method further includes forming a plating mask over the cured photosensitive material, and the second metal line and via are plated from the plating mask.

[0083] In one embodiment, the method further includes removing the plating mask and forming a second dielectric layer over and in contact with the photosensitive material, the second metal line being in the second dielectric layer. In one embodiment, etching back the first metal line exposes opposing sidewalls of the first dielectric layer down to the trench, where after forming the via opening, the opposing sidewalls of the first dielectric layer are exposed down to the via opening.

[0084] According to some embodiments of the present disclosure, a structure includes: a first metal line having a first sidewall and a second sidewall parallel to the first sidewall; a via covering and contacting the first metal line, the via having a third sidewall aligned perpendicular to the first sidewall and a fourth sidewall aligned perpendicular to the second sidewall; a first dielectric layer, the first metal line and the via being within the first dielectric layer; a second metal line spanning and joined to the via, the second metal line having a bottom surface that contacts a top surface of the first dielectric layer; and a second dielectric layer, the top surface of the second dielectric layer and the top surface of the second metal line being coplanar.

[0085] In one embodiment, the via overlaps an intermediate portion of the first metal line. In one embodiment, the via overlaps a line end of the first metal line, the via further comprising a first end sidewall aligned with a second end sidewall of the first metal line. In one embodiment, the structure further comprises a third dielectric layer overlapping the first metal line, wherein the third dielectric layer comprises a fifth sidewall vertically aligned to the first sidewall and a sixth sidewall vertically aligned to the second sidewall.

[0086] In one embodiment, the third dielectric layer comprises a photosensitive material. In one embodiment, the second dielectric layer comprises a first lower portion in the first dielectric layer that contacts a third sidewall of the via. In one embodiment, the second dielectric layer further comprises a second lower portion in the first dielectric layer that contacts a fourth sidewall of the via. In one embodiment, both the first and second dielectric layers comprise organic materials.

[0087] According to some embodiments of the present disclosure, a structure includes: a first metal line having a first sidewall and a second sidewall parallel to the first sidewall; a via covering and contacting the first metal line, the via including a third sidewall, where in a cross-section of the structure, the third sidewall and the first sidewall are aligned with a same first straight line; and a fourth sidewall, where in a cross-section of the structure, the fourth sidewall and the second sidewall are aligned with a same second straight line; and a second metal line spanning the via and connected to the via.

[0088] In one embodiment, the first metal line further includes a first end sidewall and the via further includes a second end sidewall, and in a cross-section of the structure, the first end sidewall and the second end sidewall are aligned to the same third straight line.

[0089] The foregoing has outlined features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures which carry out the same purposes and / or achieve the same advantages as the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art should also recognize that various changes, substitutions, and alterations can be made thereto by those skilled in the art without departing from the spirit and scope of the present disclosure.

Claims

1. forming a first metal line; forming a first dielectric layer, the first metal line being in the first dielectric layer; etching back the first metal line to form a trench in the first dielectric layer, wherein a lower portion of the first metal line remains below the trench; filling the trench with a photosensitive material; performing a photolithography process to pattern the photosensitive material, wherein a via opening is formed in the first dielectric layer and in the photosensitive material; forming a second metal line and a via, the via being formed in the via opening and the second metal line being over and bonded to the via; A method comprising:

2. 10. The method of claim 1, further comprising, prior to the photolithography process, performing a planarization process to make the first top surface of the photosensitive material coplanar with the second top surface of the first dielectric layer.

3. 2. The method of claim 1, further comprising, before etching back the first metal line, performing a planarization process to make the top surface of the first dielectric layer coplanar with the top surface of the first metal line.

4. curing the photosensitive material before the second metal line and the via are formed; forming a plating mask over the cured photosensitive material, the second metal lines and the vias being plated from the plating mask; removing the plating mask; forming a second dielectric layer over and in contact with the photosensitive material, the second metal line being in the second dielectric layer; The method of claim 1 further comprising:

5. 2. The method of claim 1, wherein the etching back of the first metal line exposes opposing sidewalls of the first dielectric layer down to the trench, and after forming the via opening, the opposing sidewalls of the first dielectric layer are exposed down to the via opening.

6. a first metal line having a first sidewall and a second sidewall parallel to the first sidewall; a via overlying and contacting the first metal line, the via having a third sidewall vertically aligned with the first sidewall and a fourth sidewall vertically aligned with the second sidewall; a first dielectric layer, the first metal line and the via being within the first dielectric layer; a second metal line spanning and bonded to the via, the second metal line having a bottom surface in contact with the top surface of the first dielectric layer; a second dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the second metal line are coplanar; Including, structure.

7. The structure of claim 6 , wherein the via overlaps a middle portion of the first metal line.

8. 7. The structure of claim 6, wherein the via overlaps a line end of the first metal line, the via further comprising a first end sidewall aligned with a second end sidewall of the first metal line.

9. a first metal line having a first sidewall and a second sidewall parallel to the first sidewall; a via covering the first metal line and contacting the first metal line, the via comprising: a third sidewall, wherein in a cross section of the structure, the third sidewall and the first sidewall are aligned with the same first straight line; a fourth sidewall, wherein in a cross section of the structure, the fourth sidewall and the second sidewall are aligned with the same second straight line; a via, a second metal line spanning and bonded to the via; Including, structure.

10. 10. The structure of claim 9, wherein the first metal line further includes a first end sidewall and the via further includes a second end sidewall, and in a cross section of the structure, the first end sidewall and the second end sidewall are aligned to the same third straight line.

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