Circuit board and method of manufacturing the same

Abstract

To provide a highly reliable circuit board.SOLUTION: A circuit board includes a ceramic substrate formed of a sintered body of silicon nitride, a circuit pattern bonded to a surface of the ceramic substrate and formed of a metal material, and a semiconductor chip mounted on the circuit pattern via a conductive layer formed of a conductive paste, in which a surface roughness Rz of the circuit pattern is 2.0 μm or more and 6.5 μm or less, and a glossiness (60 °) of the circuit pattern is 10 or more and 120 or less.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to a circuit board and a manufacturing method thereof, and more particularly to a circuit board having a circuit pattern on a ceramic substrate and a manufacturing method thereof. [Background technology]

[0002] Conventionally, semiconductor modules have been produced in which multiple semiconductor chips are mounted on a circuit board. In a typical circuit board, a circuit pattern made of a metal material is bonded to the front surface of a ceramic substrate, and a heat sink is bonded to the rear surface of the ceramic substrate. A portion of the circuit pattern is covered with solder resist, and a semiconductor chip and wire bonding are provided in the area of ​​the circuit pattern exposed by the solder resist. For example, when a semiconductor chip is provided on the front surface of the circuit pattern, the rear electrode of the semiconductor chip and the circuit pattern are electrically connected using a conductive paste such as solder. Furthermore, various wiring techniques are used on the circuit pattern, such as electrically connecting the front electrode of the semiconductor chip and the circuit pattern using wire bonding.

[0003] For example, Patent Document 1 discloses a circuit board in which the wettability and corrosion resistance of the surface of the circuit pattern are improved in consideration of contact with wire bonding using lead-free solder. The surface of this circuit pattern is subjected to chemical polishing and then treated with an anti-rust agent. Patent Document 1 also discloses that the surface roughness Ra of the circuit pattern treated in this way is 0.1 to 1.0 μm. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4760251 Summary of the Invention [Problem to be solved by the invention]

[0005] When mounting a semiconductor module, the circuit board is subjected to thermal loads due to various mounting processes. This thermal load and other factors can cause the solder resist to peel off from the circuit pattern. If the solder resist peels off, insulation between the circuit pattern, semiconductor chip, wire bonding, and conductive paste cannot be maintained, which can lead to short circuits. This can reduce the reliability of the semiconductor module.

[0006] Therefore, it is necessary to provide a highly reliable circuit board. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] In one embodiment, the circuit board comprises a ceramic substrate made of a sintered silicon nitride body, a circuit pattern made of a metal material and bonded to the surface of the ceramic substrate, and a semiconductor chip mounted on the circuit pattern via a conductive layer made of a conductive paste, wherein the surface roughness Rz of the circuit pattern is 2.0 μm or more and 6.5 μm or less, and the gloss (60°) of the circuit pattern is 10 or more and 120 or less.

[0008] In one embodiment, a method for manufacturing a circuit board includes: (a) preparing a ceramic substrate; (b) bonding a metal plate made of a metal material to a surface of the ceramic substrate after the step (a); (c) performing a pretreatment on the metal plate after the step (b) so that the polishing effect in the depth direction of the metal plate is smaller than the polishing effect in the planar direction; (d) performing a roughening treatment on the metal plate after the step (c) so that the polishing effect in the depth direction of the metal plate is larger than the polishing effect in the planar direction; and (e) patterning the metal plate after the step (d) to form a circuit pattern, wherein after the step (d), the surface roughness Rz of the metal plate is 2.0 μm or more and 6.5 μm or less, and the gloss (60°) of the metal plate is 10 or more and 120 or less. [Effects of the Invention]

[0009] According to one embodiment, a highly reliable circuit board can be provided. [Brief explanation of the drawings]

[0010] [Figure 1] 10A and 10B are cross-sectional views of a main part illustrating a manufacturing method of a circuit board in a study example. [Figure 2] 2 is a cross-sectional view of a main part illustrating the method of manufacturing the circuit board subsequent to FIG. 1. [Figure 3] 3 is a cross-sectional view of a main part illustrating the method of manufacturing the circuit board subsequent to FIG. 2. [Figure 4] FIG. 10 is a cross-sectional view of a main part showing a state in which a semiconductor chip is mounted on a circuit board of a study example. [Figure 5] 3 is a flowchart showing a method for manufacturing a circuit board according to the first embodiment. [Figure 6] 3 is a perspective view showing a method for manufacturing the circuit board according to the first embodiment. FIG. [Figure 7] 7 is a perspective view showing the method of manufacturing the circuit board subsequent to FIG. 6. FIG. [Figure 8] FIG. 8 is a cross-sectional view of a main part of FIG. 7. [Figure 9] 9 is a cross-sectional view of a main part illustrating the method of manufacturing the circuit board subsequent to FIG. 8. [Figure 10] 10 is a cross-sectional view of a main part illustrating the method of manufacturing the circuit board subsequent to FIG. 9. [Figure 11] 11 is a cross-sectional view of a main part illustrating the method of manufacturing the circuit board subsequent to FIG. 10. [Figure 12] 12 is a cross-sectional view of a main part illustrating the method of manufacturing the circuit board subsequent to FIG. 11. [Figure 13] 13 is a perspective view showing the method of manufacturing the circuit board subsequent to FIG. 12. FIG. [Figure 14] 14 is a cross-sectional view of a main part illustrating the method of manufacturing the circuit board subsequent to FIG. 13. [Figure 15] 15 is a perspective view showing the method of manufacturing the circuit board subsequent to FIG. 14. FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line AA in FIG. [Figure 17] 1 is a cross-sectional view showing a state in which a semiconductor chip is mounted on a circuit board according to a first embodiment. [Figure 18] FIG. 18 is a cross-sectional view of a main part of FIG. [Figure 19] 1 is an SEM image showing the surface of a metal plate in a study example. [Figure 20] 3 is an SEM image showing the surface of the metal plate in the first embodiment. [Figure 21] 3 is a table showing experimental data in the first embodiment. [Figure 22] 4 is a graph showing experimental data in the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0012] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a structure.

[0013] (Embodiment 1) <Considerations by the inventors of the present application> The present inventors have investigated a method for suppressing the above-described peeling of the solder resist by roughening the surface of the metal plate on which the circuit pattern is formed (roughening treatment) to improve the adhesion between the circuit pattern and the solder resist. As a result, it was found that this method also has advantages over the conventional techniques, but the present inventors have discovered that simply performing roughening treatment poses various problems. Below, an example of the study conducted by the present inventors will be described in detail using Figures 1 to 4.

[0014] Fig. 1 shows the state immediately after bonding a metal plate 4 to the surface of a ceramic substrate 2 via a brazing material layer 3, and before roughening treatment. Fig. 2 shows the state after roughening treatment has been performed on the metal plate 4. The metal plate 4 is, for example, a rolled copper foil formed by rolling treatment.

[0015] As shown in FIG. 1, there are multiple rolling marks 20 (multiple recesses) on the surface of the metal plate 4, and the depth of each rolling mark 20 is non-uniform. In this state, as shown in FIG. 2, the metal plate 4 is subjected to a roughening treatment. The roughening treatment is performed using, for example, an aqueous solution composed of water, hydrogen peroxide, sulfuric acid, and phosphoric acid. In this aqueous solution, the mass percent concentration of hydrogen peroxide is 3%, the mass percent concentration of sulfuric acid is 5%, and the mass percent concentration of phosphoric acid is 3%. This roughening treatment causes wet etching to proceed from the rolling marks 20 along the grain boundaries, deepening the recesses on the surface of the metal plate 4.

[0016] 3, an etching process is performed using the resist pattern as a mask to pattern the metal plate 4 and the brazing material layer 3, thereby forming a circuit pattern 4a. Next, a solder resist 6 is formed on the surface of the ceramic substrate 2 so as to cover a portion of the circuit pattern 4a. The solder resist 6 is formed so as to fill in the recesses in the surface of the circuit pattern 4a that have become deeper due to the roughening process, which improves the adhesion between the solder resist 6 and the circuit pattern 4a and makes the solder resist 6 less likely to peel off from the circuit pattern 4a.

[0017] Thereafter, a plurality of circuit boards are manufactured by dividing the ceramic substrate 2. When manufacturing a semiconductor module using the circuit board, for example, a semiconductor chip 11 is mounted via a conductive paste 10 on an area of ​​the circuit pattern 4a that is exposed from the solder resist 6, as shown in Fig. 4 .

[0018] Here, the surface of the circuit pattern 4a is roughened by the roughening treatment, and the recesses on the surface of the circuit pattern 4a are deep. Furthermore, the depths of the recesses are uneven. If the conductive paste 10 is applied to the surface of the circuit pattern 4a in this state, there is a risk that the conductive paste 10 will not be completely embedded in the recesses. In other words, there is a risk of voids 21 as shown in FIG. 4 being generated.

[0019] If such voids 21 occur, for example, there is a risk that the air trapped in the voids 21 will expand due to the thermal load when mounting the semiconductor module, and cracks will occur in the conductive paste 10 starting from the voids 21. That is, in the examined example, although the roughening treatment can improve peeling of the solder resist 6, there is a problem in that it makes the occurrence of voids 21 more likely to occur.

[0020] Therefore, there is a need for a technology that can prevent the peeling of the solder resist 6 and also prevent the occurrence of voids 21. The circuit board 1 described below was devised by the inventors of the present application in consideration of the problems in the study example.

[0021] <Circuit Board in First Embodiment> A method for manufacturing the circuit board 1 in the first embodiment will be described below with reference to Figures 5 to 16, and features of the circuit board 1 manufactured by this manufacturing method will be described with reference to Figures 17, 18, and 20 to 22. Figure 5 is a flowchart showing the method for manufacturing the circuit board 1. When describing steps S1 to S9 shown in Figure 5, Figures 6 to 16 will be used as necessary.

[0022] First, in step S1, a ceramic substrate 2 is prepared as shown in Fig. 6. The ceramic substrate 2 is made of a sintered body of a material that has high thermal conductivity and a high heat dissipation effect, such as a sintered body of silicon nitride.

[0023] 7, in step S2, a metal plate 4 is bonded to the front surface of the ceramic substrate 2 via a brazing material layer 3, and a heat sink (metal plate) 5 is bonded to the rear surface of the ceramic substrate 2 via the brazing material layer 3. The metal plate 4 and the heat sink 5 are, for example, rolled copper foil formed by a rolling process. More specifically, the metal material constituting the metal plate 4 and the heat sink 5 is, for example, copper (Cu) or a copper alloy mainly containing copper, such as Cu-Zr or Cu-Ni.

[0024] The brazing material that constitutes the brazing material layer 3 is made of a conductive material such as Ag-Cu containing Ti, Zr, or Hf. The metal plate 4 and heat sink 5 are joined to the ceramic substrate 2 by a brazing method. First, the brazing material is applied to the surface of the ceramic substrate 2, and then the metal plate 4 is adhered to the brazing material. Heat treatment is then performed at, for example, 700 to 900°C depending on the Ag / Cu composition ratio, thereby joining the metal plate 4 to the surface of the ceramic substrate 2 via the brazing material layer 3. A similar method is used for the heat sink 5, so that the heat sink 5 is joined to the back surface of the ceramic substrate 2 via the brazing material layer 3.

[0025] Fig. 8 is an enlarged cross-sectional view of a main part of the surface of the metal plate 4 of Fig. 7. As shown in Fig. 8, a plurality of rolling marks 20 are present on the surface of the metal plate 4.

[0026] In step S3, the metal plate 4 is subjected to a process (pre-processing) for uniforming the surface roughness of the metal plate 4. That is, since the depths of the plurality of rolling marks 20 (depths of the plurality of recesses) are non-uniform, the plurality of rolling marks 20 are removed as much as possible to uniform the depths of the plurality of recesses.

[0027] The pretreatment is performed using a first aqueous solution composed of, for example, water, hydrogen peroxide, and sulfuric acid. In this first aqueous solution, the mass percent concentration of hydrogen peroxide is 3%, and the mass percent concentration of sulfuric acid is 8%. The first aqueous solution may also contain phosphoric acid with a mass percent concentration of 0.3% or less. This first aqueous solution has a small effect of chemically polishing the metal plate 4 in the depth direction, but a large effect of chemically polishing the metal plate 4 in the planar direction. Therefore, it has a large effect of uniforming the surface roughness of the metal plate 4.

[0028] Fig. 9 shows the state of the metal plate 4 after pretreatment. By wet etching the metal plate 4 with the first aqueous solution for a predetermined time, the thickness of the metal plate 4 becomes slightly thinner than that of Fig. 8, and the surface roughness of the metal plate 4 becomes more uniform.

[0029] In step S4, the metal plate 4 is subjected to a roughening treatment to roughen the surface of the metal plate 4. In other words, the roughening treatment is a treatment to increase the surface roughness of the metal plate 4.

[0030] The roughening treatment is performed using a second aqueous solution composed of, for example, water, hydrogen peroxide, sulfuric acid, and phosphoric acid. In this second aqueous solution, the mass percent concentration of hydrogen peroxide is 3%, the mass percent concentration of sulfuric acid is 5%, and the mass percent concentration of phosphoric acid is 3%. The mass percent concentration of phosphoric acid contained in the second aqueous solution is preferably greater than the mass percent concentration of phosphoric acid contained in the second aqueous solution. Such a second aqueous solution has a strong effect of chemically polishing the metal plate 4 in the depth direction, thereby deepening the depth of the multiple recesses.

[0031] 10 shows the state of the metal plate 4 after the roughening treatment. The metal plate 4 is wet-etched with the second aqueous solution for a predetermined time, thereby increasing the surface roughness of the metal plate 4. Here, the roughening treatment was carried out until the surface roughness Rz of the metal plate 4 reached 2.0 μm or more and 6.5 μm or less.

[0032] The pretreatment makes the surface roughness of the metal plate 4 uniform, and the depths of the multiple recesses are uniform, and then the roughening treatment increases the surface roughness Rz of the metal plate 4. This makes it difficult for recesses to be extremely deep, and therefore makes it difficult for voids to occur when the conductive paste is applied.

[0033] In steps S5 and S6, the circuit pattern 4a is formed by patterning the metal plate 4. First, in step S5, as shown in Fig. 11, a resist pattern RP1 is formed by photolithography on the surface of the metal plate 4 so as to be in direct contact with the metal plate 4 and to cover a part of the metal plate 4.

[0034] 12, in step S6, the metal plate 4 exposed from the resist pattern RP1 is etched to form a circuit pattern 4a. Subsequently, the brazing material layer 3 formed under the etched metal plate 4 is also etched to remove the brazing material layer 3 and expose the ceramic substrate 2. Thereafter, the resist pattern RP1 is removed using a sodium hydroxide aqueous solution or the like.

[0035] Note that roughening the surface of the metal plate 4 by the roughening treatment in step S4 can improve adhesion between the resist pattern RP1 used in steps S5 and S6 and the metal plate 4. This can prevent problems such as the resist pattern RP1 being displaced or peeling off during the etching treatment.

[0036] In step S7, a laser scribing process is performed on the ceramic substrate 2. As shown in FIG. 13, a plurality of circuit patterns 4a are formed on the surface of the ceramic substrate 2. The ceramic substrate 2 will eventually be divided, but grooves are formed in the ceramic substrate 2 by irradiating the ceramic substrate 2 with a laser in advance along scribe lines SL, which are the locations to be divided. The formation of these grooves makes it easier to perform the division process in the subsequent step S9.

[0037] 14, in step S8, a solder resist 6 is formed on the surface of the ceramic substrate 2 so as to cover a portion of the circuit pattern 4a. First, the solder resist 6 is formed by, for example, screen printing or coating so as to cover the entire surface of the ceramic substrate 2. Next, an exposure process and a development process are performed to remove a portion of the solder resist 6.

[0038] The solder resist 6 may also be formed as follows. For example, a solder resist pattern may be formed using a printing plate corresponding to the area where the solder resist 6 is to be formed, and then the solder resist pattern may be subjected to an exposure process to form the solder resist 6. In this case, the development process can be omitted.

[0039] The solder resist 6 thus formed is in direct contact with the circuit pattern 4a. The surface roughness Rz of the circuit pattern 4a is set to 2.0 μm or more and 6.5 μm or less through pre-treatment and roughening treatment. Therefore, the solder resist 6 is in contact with the circuit pattern 4a with high adhesion, making it difficult for the solder resist 6 to peel off from the circuit pattern 4a.

[0040] In step S9, as shown in Fig. 15, the ceramic substrate 2 is divided along the scribe lines SL to manufacture a plurality of circuit boards 1. Fig. 16 is a cross-sectional view taken along line AA in Fig. 15, showing one circuit board 1. The area of ​​the circuit pattern 4a exposed from the solder resist 6 includes, for example, an area for forming a semiconductor chip via a conductive paste.

[0041] Thereafter, in step S10, a visual inspection and the like are performed on the plurality of circuit boards 1. The circuit boards 1 that are determined to be non-defective undergo packaging and the like, and the circuit boards 1 are shipped.

[0042] <Main features of circuit board 1> FIG. 17 shows a semiconductor chip 11 and a heat sink 12 mounted on the circuit board 1 of FIG. 16, and FIG. 18 is an enlarged cross-sectional view of the semiconductor chip 11 and its periphery in FIG. 17. As shown in FIGS. 17 and 18, the semiconductor chip 11 is mounted on the area of ​​the circuit pattern 4a that is exposed from the solder resist 6 via a conductive paste 10. The conductive paste 10 is made of, for example, lead-free solder. The heat sink 12 is bonded to the heat sink 5. Although not shown, other wiring configurations may also be used on the circuit pattern 4a, such as electrically connecting the surface electrodes of the semiconductor chip 11 to the circuit pattern 4a using external connection terminals such as wire bonding.

[0043] 4 in the above-mentioned study example, it is required that the circuit board 1 not only suppress peeling of the solder resist 6 but also suppress the occurrence of voids 21. The inventors of the present application focused on the surface roughness Rz and glossiness (60°) as indices for dealing with these, and conducted experiments on the relationship between the surface roughness Rz and glossiness (60°) and the peeling of the solder resist 6 and the occurrence of voids 21.

[0044] 19 and 20 are SEM images showing the surface of metal plate 4 after the roughening treatment of step S4, with FIG. 19 showing a study example and FIG. 20 showing embodiment 1. Note that FIGS. 19 and 20 show an SEM image at a magnification of 250x (with a scale where one division is 200 μm) and an SEM image at a magnification of 2500x (with a scale where one division is 20.0 μm), respectively. FIGS. 21 and 22 are a table and a graph showing experimental data for embodiment 1.

[0045] Comparing Figures 19 and 20, it was confirmed that in embodiment 1, the surface roughness of the metal plate 4 was made uniform by performing the pretreatment of step S3 before the roughening treatment of step S4.

[0046] 21 and 22, it was found that if the gloss (60°) is 120 or less, peeling of the solder resist 6 can be suppressed, and if the surface roughness Rz is 6.5 μm or less, the occurrence of voids 21 can be suppressed. If the surface roughness Rz is too small, peeling of the solder resist 6 is more likely to occur. To ensure adhesion between the solder resist 6 and the circuit pattern 4a, the surface roughness Rz is preferably 2.0 μm or more. If the gloss (60°) is 10 or more, it is possible to suppress the surface roughness Rz from becoming too large.

[0047] The surface roughness Rz described in this application is in accordance with JIS B0601:2001, and the gloss (60°) described in this application is in accordance with JIS B0601:2001. Z 8741. The surface roughness Rz was measured using a surface roughness meter (TOUCH50, manufactured by Tokyo Seimitsu Co., Ltd.), and the gloss was measured using a handheld gloss meter (PG-IIM, manufactured by Nippon Denshoku Industries Co., Ltd.). The surface roughness Rz and gloss (60°) of the metal plate 4 were measured at five locations: one location at the center and four locations at the edges. The center is the location where diagonal lines from the four corners on the surface of the metal plate 4 intersect, and the edges are locations 15 mm inward from each corner of the metal plate 4 in the direction toward the center. The values ​​of the surface roughness Rz and gloss (60°) described in this application are the average values ​​of the five locations.

[0048] In summary, after the pretreatment in step S3 and the roughening treatment in step S4, it is preferable that the surface roughness Rz of the metal plate 4 is 2.0 μm or more and 6.5 μm or less, and it is preferable that the gloss (60°) of the metal plate is 10 or more and 120 or less.

[0049] The formation of the solder resist 6 in step S8 is performed in a state where the surface roughness Rz of the circuit pattern 4a is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the circuit pattern 4a is 10 or more and 120 or less. Furthermore, when the semiconductor chip 11 is mounted on the circuit pattern 4a via the conductive paste 10, the surface roughness Rz and glossiness (60°) of the circuit pattern 4a are also within the above ranges.

[0050] As described above, by using the circuit pattern 4a formed by performing the pretreatment in step S3 and the roughening treatment in step S4 on the metal plate 4 and then patterning the metal plate 4, peeling of the solder resist 6 can be suppressed, and the occurrence of voids 21 can be suppressed when forming the conductive paste 10. Therefore, according to the first embodiment, a highly reliable circuit board 1 can be provided.

[0051] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0052] 1 Circuit board 2 Ceramic substrate 3 Brazing layer 4 metal plate 4a Circuit Pattern 5 Heat sink (metal plate) 6 Solder Resist 10 Conductive Paste 11 Semiconductor chip 12 Heatsink 20 Rolling marks 21 Void RP1 Resist pattern SL Scribe Line

Claims

1. a ceramic substrate made of a sintered body of silicon nitride; a circuit pattern bonded to a surface of the ceramic substrate and made of a metal material; a semiconductor chip mounted on the circuit pattern via a conductive layer made of a conductive paste; Equipped with the surface roughness Rz of the circuit pattern is 2.0 μm or more and 6.5 μm or less; The circuit board, wherein the glossiness (60°) of the circuit pattern is 10 or more and 120 or less.

2. 2. The circuit board according to claim 1, The circuit board, wherein the metal material is copper or a copper-based alloy.

3. 3. The circuit board according to claim 1, The conductive paste is made of lead-free solder.

4. 4. The circuit board according to claim 1, The semiconductor chip has surface electrodes electrically connected to the circuit pattern by wire bonding.

5. (a) providing a ceramic substrate; (b) after the step (a), a step of joining a metal plate made of a metal material to the surface of the ceramic substrate; (c) After the step (b), the action of polishing the metal plate in the depth direction is pre-treating the metal plate so that the effect of polishing is less than that of polishing; (d) after the step (c), performing a roughening treatment on the metal plate so that the polishing effect in the depth direction of the metal plate is greater than the polishing effect in the planar direction; (e) after the step (d), a step of patterning the metal plate to form a circuit pattern; Equipped with After the step (d), the surface roughness Rz of the metal plate is 2.0 μm or more and 6.5 μm or less, and the gloss (60°) of the metal plate is 10 or more and 120 or less.

Images